DISPLAY DEVICE

Abstract

A display device (100) according to embodiments of the disclosure comprises a substrate (111) and a transistor (TR) on the substrate (111). The transistor (TR) has an active layer (ACT) on the substrate (111), a first gate-insulating layer (631) on the active layer (ACT), a second gate-insulating layer (632) on the active layer (ACT) arranged at a distance in a first direction from the first gate-insulating layer (631), a first gate electrode (G1) on the first gate-insulating layer (631), a second gate electrode (G2) on the second gate-insulating layer (632) arranged at a distance from the first gate electrode (G1), a drain electrode (D) connected to a section of the active layer (ACT), and a source electrode (S) connected to another section of the active layer (ACT).The active layer (ACT) has a first channel section (CH1) that overlaps at least one section of the first gate electrode (G1), a second channel section (CH2) that overlaps at least one section of the second gate electrode (G2), a first conductive section (621) positioned in the first direction from the second channel section (CH2), a second conductive section (622) positioned between the first channel section (CH1) and the second channel section (CH2), and a third conductive section (623) positioned in a second direction opposite to the first direction from the first channel section (CH1).

Description

AREA The embodiments of the disclosure relate to a display device. BACKGROUND Display devices are used in various electronic devices, such as TVs, mobile phones, laptops, and tablets. Display devices include organic light-emitting diodes (OLEDs), which are self-emitting, and liquid crystal displays (LCDs), which require a separate light source. For an image display, a display device can have a display panel in which a plurality of data lines and a plurality of gate lines are arranged, a data control circuit that outputs data signals to the plurality of data lines, and a gate control circuit that outputs gate signals to the plurality of gate lines. Transistors are widely used in electronic devices as switching or control elements. Thin-film transistors can be classified, based on the material forming the active layer, into amorphous silicon thin-film transistors, in which amorphous silicon is used as the active layer; polycrystalline silicon thin-film transistors, in which polycrystalline silicon is used as the active layer; and oxide semiconductor thin-film transistors, in which an oxide semiconductor is used as the active layer. OVERVIEW Embodiments of the disclosure can provide a display device comprising a transistor capable of improving short-channel element characteristics and preventing deterioration due to hydrogen ingress. Embodiments of the disclosure may provide a display device that includes a transistor capable of preventing deterioration due to lateral stress. Embodiments of the disclosure may provide a display device comprising a transistor capable of improving an inrush current reduction phenomenon. The functions of embodiments of the disclosure are not limited to those set forth herein, and other unmentioned functions would be obvious to a person skilled in the art from the following description. In accordance with one aspect of the present disclosure, a display device according to claim 1 is provided. Further embodiments are described in the dependent claims. An indicator device according to embodiments of the disclosure can comprise a substrate and a transistor arranged on the substrate. The transistor can comprise an active layer on the substrate, a first gate-insulating layer arranged on the active layer, a second gate-insulating layer arranged on the active layer and positioned at a distance from the first gate-insulating layer in a first direction, a first gate electrode arranged on the first gate-insulating layer, a second gate electrode arranged on the second gate-insulating layer and positioned at a distance from the first gate electrode, a drain electrode connected to a section of the active layer, and a source electrode connected to another section of the active layer.The active layer can have a first channel section that overlaps at least one section of the first gate electrode, a second channel section that overlaps at least one section of the second gate electrode, a first conductive section positioned in the first direction from the second channel section, a second conductive section positioned between the first channel section and the second channel section, and a third conductive section positioned in a second direction opposite to the first direction from the first channel section. According to embodiments of the disclosure, a display device can be provided which includes a transistor that is able to improve short-channel element properties and prevent deterioration due to hydrogen ingress. According to embodiments of the disclosure, a display device can be provided which includes a transistor that is able to prevent deterioration due to lateral stress. According to embodiments of the disclosure, a display device can be provided which includes a transistor that is capable of improving an inrush current reduction phenomenon. According to embodiments of the disclosure, a display device can be provided that includes a transistor capable of preventing deterioration of element properties. This can increase the efficiency and lifespan of the display device, thereby reducing unnecessary power consumption and enabling lower power consumption. The effects of the disclosure are not limited to the aforementioned tasks, and further effects will become obvious to an average person skilled in the field from the following detailed description. DESCRIPTION OF THE DRAWINGS The disclosure will be more fully understood from the following detailed description and the accompanying drawings, which are provided for illustrative purposes only and are not intended to limit the disclosure: Fig. 1 represents a display device according to embodiments of the disclosure; Fig. 2 is an equivalent circuit representing a subpixel of a display device according to embodiments of the disclosure; Fig. 3 is a cross-sectional view representing a display panel according to embodiments of the disclosure; Fig. 4 represents a gate-in-panel circuit of a display device according to embodiments of the disclosure; Fig. 5 represents a transistor comprising a first transistor and a second transistor in a display device according to embodiments of the disclosure; Fig.Figure 6 is a cross-sectional view and a top view showing a transistor comprising a first transistor and a second transistor in a display device according to embodiments of the disclosure; Figure 7 shows a transistor comprising a first transistor through a third transistor in a display device according to embodiments of the disclosure; Figure 8 is a cross-sectional view and a top view showing a transistor comprising a first transistor through a third transistor in a display device according to embodiments of the disclosure; Figure 9 is an enlarged cross-sectional view showing a transistor in a display device according to embodiments of the disclosure; Figure 10 shows a transistor comprising a first transistor and a second transistor in a display device according to embodiments of the disclosure; FigureFigure 11 is a cross-sectional view showing a transistor comprising a first transistor and a second transistor in a display device according to embodiments of the disclosure; Figure 12 shows a transistor comprising a first transistor through a third transistor in a display device according to embodiments of the disclosure; Figures 13, 14 to 15 are cross-sectional views showing a transistor comprising a first transistor through a third transistor in a display device according to embodiments of the disclosure; Figure 16 shows a transistor comprising a first transistor through a third transistor in a display device according to embodiments of the disclosure; Figures 17 and 18 are cross-sectional views showing a transistor comprising a first transistor through a third transistor in a display device according to embodiments of the disclosure; FigureFigure 19 represents a transistor comprising a first to third transistor in a display device according to embodiments of the disclosure; Figures 20 and 21 are cross-sectional views representing a transistor comprising a first to third transistor in a display device according to embodiments of the disclosure; Figure 22 represents a transistor comprising a first to fifth transistor in a display device according to embodiments of the disclosure; Figure 23 is a cross-sectional view representing a transistor comprising a first to fifth transistor in a display device according to embodiments of the disclosure; and Figure 24 is a top view representing a transistor comprising a first to fifth transistor in a display device according to embodiments of the disclosure. DETAILED DESCRIPTION In the following description of examples or embodiments of the disclosure, reference is made to the accompanying drawings, which show specific examples or embodiments that can be implemented for illustrative purposes and in which the same reference numerals and symbols can be used to denote the same or similar components, even if they are shown in different accompanying drawings. Furthermore, in the following description of examples or embodiments of the disclosure, detailed descriptions of well-known functions and components included herein will be omitted if it is determined that such a description may make the subject matter rather unclear in some embodiments of the disclosure.The terms used here, such as "exhibiting," "having," "containing," "forming," "producing from," and "formed from," are generally intended to allow the addition of further components, unless the terms are used with the term "only." As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise. Terms such as “first”, “second”, “A”, “B”, “(A)”, or “(B)” may be used herein to describe elements of the revelation. Each of these terms is not used to define the essence, an order, a sequence, or a number of elements, etc., but is used merely to distinguish the corresponding element from other elements. When it is mentioned that a first element is "connected or coupled" to a second element, "contacts or overlaps" it, etc., this should be interpreted to mean not only that the first element is "directly connected or coupled" to the second element, or that the second element is "directly contacted or overlapped," but also that a third element may be "inserted" between the first and second elements, or that the first and second elements may be "connected or coupled" to each other, "contact or overlap" each other, etc., via a fourth element. In this context, the second element may be contained within at least one of two or more elements that are "connected or coupled" to each other, "contact or overlap" each other, etc. When time-related terms such as "after", "subsequent", "next", "before", and the like are used to describe processes or operations of elements or configurations or flows or steps in operation, further processing, or manufacturing processes, these terms may be used to describe non-consecutive or non-sequential processes or operations, unless the term "direct" or "immediate" is used together. Furthermore, if any dimensions, relative sizes, etc., are mentioned, it should be noted that numerical values ​​for elements or features, or corresponding information (e.g., level, range, etc.), have a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if a relevant description is not specified. Moreover, the term "may" fully encompasses all meanings of the term "can." Various embodiments of the disclosure are described in detail below with reference to the accompanying drawings. Fig. 1 is a view showing a configuration of a display device 100 according to embodiments of the disclosure. Referring to Fig. 1, a display device 100 according to embodiments of the disclosure can comprise a display panel 110 and display control circuits as components for displaying images. The display control circuit can be a circuit for controlling the display panel 110. The display control circuits can comprise a data control circuit 120, a gate control circuit 130, and a controller 140 that outputs a gate control signal GCS and a data control signal DCS for controlling the gate control circuit 130 and the data control circuit 120, respectively; however, embodiments of the disclosure are not limited to these. The display panel 110 can have a substrate 111 and a plurality of subpixels SP arranged on the substrate 111. Substrate 111 can have a display area (DA) and a non-display area (NDA). The display area (DA) is an area where images can be displayed and can also be referred to as an active area. A plurality of subpixels (SP) for image display can be arranged within the display area (DA). The non-display area (NDA) is an area where no image is displayed and can be an area outside the display area (DA). The non-display area (NDA) can be referred to as a border. The non-display area (NDA) can include a pad area. The display device 100 according to embodiments of the disclosure can be a self-emitting display device in which the display panel 110 itself emits light, however embodiments of the disclosure are not limited to this. For example, the display device 100 can be an organic light-emitting diode display in which the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 can be an inorganic light-emitting display in which the light-emitting element is implemented as a light-emitting diode based on an inorganic material. As yet another example, the display device 100 can be a quantum dot display in which the light-emitting element is implemented as a quantum dot, which is a self-emitting semiconductor crystal. As yet another example, the display device 100 can be a micro-LED display or a mini-LED display. The structure of each of the plurality of subpixels SP can vary according to the type of display device 100. For example, if the display panel 110 is a self-illuminating display device, each subpixel SP can have a light-emitting element that emits light, one or more transistors, and one or more capacitors. However, embodiments of the disclosure are not limited to this. Different types of signal lines for controlling a plurality of subpixels SP can be arranged on the substrate 111 of the display panel 110. For example, different types of signal lines can include a plurality of data lines DL, which transmit data signals (also called data voltages or image signals) to a plurality of subpixels SP, and a plurality of gate lines GL, which transmit gate signals (also called sampling signals) to the plurality of subpixels SP. The plurality of data lines DL and the plurality of gate lines GL can intersect. Each of the plurality of gate lines GL can be arranged to extend in the row direction. Each of the plurality of data lines DL can be arranged to extend in a column direction that is different from the row direction. The row direction and the column direction can be relative directions. For example, the angle between the row direction and the column direction can be 90 degrees or an angle other than 90 degrees. The data control circuit 120 can receive digital image data DATA from the controller 140 and can convert the received image data DATA into analog data signals (also called data voltages) and output them to the majority of data lines DL. The gate control circuit 130 is a circuit for controlling the majority of gate lines GL and can output gate signals to the majority of gate lines GL. The gate driver circuit 130 can be embedded in the display panel 110 in a gate-in-panel (GIP) configuration. In this case, the gate driver circuit 130 can be formed on the substrate 111 of the display panel 110 during the manufacturing process. If the gate driver circuit 130 is of a gate-in-panel type, it can be referred to as a gate-in-panel circuit (GIPC). For example, the gate drive circuit 130 can be located in the non-display area (NDA) of the display panel 110. For example, the gate drive circuit 130 can be located on one side or the other side of the display area (DA) in the non-display area (NDA). As another example, gate drive circuits 130 can be located on two opposite sides of the display area (DA) in the non-display area (NDA). As another example, the gate control circuit 130 can be located in the display area DA of the display panel 110. For example, the gate control circuit 130 can be located in the left area or the right area within the display area DA. As yet another example, the gate control circuit 130 can be located across the entire display area DA. Referring to Fig. 1, the non-display area NDA of the display panel 110 can have a gate border area GBZ in which the gate control circuit 130 and associated lines are arranged. The gate drive circuit 130 can have a plurality of transistors. Each of the plurality of transistors contained in the gate drive circuit 130 can have an active layer comprising a first semiconductor material, and each of the plurality of transistors contained in the subpixels SP can have an active layer comprising a second semiconductor material. For example, the first semiconductor material and the second semiconductor material can be identical. Alternatively, the first semiconductor material and the second semiconductor material can be different. For example, the first semiconductor material can be a silicon-based semiconductor (e.g., low-temperature polysilicon), and the second semiconductor material can be an oxide semiconductor. The active layer can also be a semiconductor layer. For example, the active layer can be a single layer. Alternatively, the active layer can consist of multiple layers. Fig. 2 is an equivalent circuit diagram representing a subpixel SP of a display device 100 according to embodiments of the disclosure. Referring to Fig. 2, if the display device 100 is a self-illuminating display device, each of the plurality of subpixels SP arranged on the substrate 111 can have a light-emitting element ED and a subpixel circuit SPC for controlling the light-emitting element ED. The subpixel circuit (SPC) can comprise a plurality of transistors and at least one capacitor for controlling the light-emitting element (ED). The SPC can control the light-emitting element (ED) by supplying a control current to the ED at a predetermined time. The light-emitting element (ED) can be controlled by this current in such a way that it emits light. Most transistors can have a control transistor DT for controlling the light-emitting element ED and a sampling transistor ST, which is switched on or off according to the sampling signal SC. The control transistor DT can supply a control current to the light-emitting element ED. The sampling transistor ST can be configured to control the electrical state of a corresponding node in the subpixel circuit SPC or to control the state or operation of the control transistor DT. The at least one capacitor can include a storage capacitor Cst to maintain a constant voltage during a frame. To control subpixel SP, a data signal VDATA (an image signal) and a sampling signal SC (a type of gate signal) can be applied to subpixel SP. Furthermore, a common control signal, comprising the control voltage VDD and the base voltage VSS, can be applied to subpixel SP. The light-emitting element ED can comprise a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL can be positioned between the pixel electrode PE and the common electrode CE. For example, the pixel electrode PE can be an electrode located in each subpixel SP, and the common electrode CE can be an electrode located in all subpixels SP. For example, the pixel electrode PE can be an anode, and the common electrode CE can be a cathode. If the light-emitting element ED is an organic light-emitting element, the intermediate layer EL can comprise a light-emitting layer EML and a common intermediate layer EL_COM. The common layer EL_COM can include a first common intermediate layer COM1 between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 between the light-emitting layer EML and the common electrode CE. The common electrode CE can be electrically connected to the base voltage line VSSL. The base voltage VSS, which is a type of common voltage, can be applied to the common electrode CE through the base voltage line VSSL. The pixel electrode PE can be electrically connected directly or indirectly (through another transistor) to the first node N1 of the drive transistor DT of each subpixel SP. In this disclosure, “base voltage VSS” can also be referred to as a first common voltage, a low-potential power voltage, or a low-potential voltage, and “base voltage line VSSL” can also be referred to as a first common voltage line, a low-potential power voltage line, or a low-potential voltage line. Each light-emitting element (ED) can have sections where the pixel electrode (PE), the intermediate layer (EL), and the common electrode (CE) overlap. A predefined light-emitting area can be formed by each light-emitting element (ED). For example, the light-emitting element ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot light-emitting element, a micro-LED or a mini-LED, but embodiments of the disclosure are not limited to these. The control transistor DT can be used to supply a control current to the light-emitting element ED. The control transistor DT can be connected between a control voltage line VDDL and the light-emitting element ED. The control transistor DT can have a first node N1, a second node N2, and a third node N3. The first node N1 can be electrically connected to the light-emitting element ED, the second node N2 can receive a data signal VDATA, and the third node N3 can receive a control voltage VDD, which is another type of common voltage, from the control voltage line VDDL. The control transistor DT can be connected between the first node N1 and the third node N3. In the control transistor DT, the second node N2 can be a gate node, the first node N1 can be a source node or a drain node, and the third node N3 can be a drain node or a source node. For the sake of simplicity, an example is described below in which, in the control transistor DT, the second node N2 can be a gate node, the first node N1 can be a source node, and the third node N3 can be a drain node; however, embodiments of the disclosure are not limited to this. The sampling transistor ST, which is included in the subpixel circuit SPC shown in Fig. 2, can be a switching transistor for transmitting the data signal VDATA, which is an image signal, to the second node N2, which is the gate node of the control transistor DT. The sampling transistor ST can be controlled in such a way that it is switched on and off by the sampling signal SC, which is a type of gate signal, applied by the sampling line SCL, which is a type of gate line GL, in such a way that an electrical connection between the second node N2 of the control transistor DT and the data line DL is controlled. The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the control transistor DT. As shown in Fig. 2, the subpixel circuit SPC can have a 2T(transistor)1C(capacitor) structure, comprising two transistors DT and ST and one capacitor Cst. In some cases, the subpixel circuit SPC may further include one or more transistors or may further include one or more capacitors. Since the circuit elements (e.g., the light-emitting element ED, implemented as an organic light-emitting diode (OLED) comprising an organic material) in each subpixel SP are sensitive to external moisture or oxygen, the encapsulation layer can be located on the display panel 110. The encapsulation layer can prevent external moisture or oxygen from penetrating the circuit elements (e.g., the light-emitting element ED). Fig. 3 is a cross-sectional view showing a display panel according to embodiments of the disclosure. However, Fig. 3 is a cross-sectional view showing an area 150 that includes a gate-enclosing area GBZ and a section of the display area DA of Fig. 1. Referring to Fig. 3, a display panel according to embodiments of the disclosure can have a gate-in-panel circuit GIPC, at least one first gate voltage line GVDDL arranged outside the gate-in-panel circuit GIPC, at least one second gate voltage line GVSSL arranged inside the gate-in-panel circuit GIPC, and a plurality of gate timing lines GCLKL arranged outside the at least one first gate voltage line GVDDL. The gate-in-panel circuit GIPC, at least one first gate voltage line GVDDL, at least one second gate voltage line GVSSL and the majority of gate timing lines GCLKL can be arranged on the substrate 111 and can be located in the non-display area NDA in the gate enclosure area GBZ. Referring to Fig. 3, the display panel according to embodiments of the disclosure may further have a ground line GND which is arranged outside the plurality of gate timing lines GCLKL. Referring to Fig. 3, the display panel according to embodiments of the disclosure can have a pixel area PA in the display area DA, and the pixel area PA can further have pixel electrodes PE which are contained in the light-emitting elements ED. Referring to Fig. 3, the display panel according to embodiments of the disclosure can further comprise a passivation layer 310 arranged on the gate-in-panel circuit GIPC and the plurality of gate timing lines GCLKL, a coating layer 320 arranged on the passivation layer 310, and a dam 330 arranged on the coating layer 320. Referring to Fig. 3, the display panel according to embodiments of the disclosure can further comprise an intermediate layer EL arranged in the pixel area PA on the dam 330 and the pixel electrodes PE, and a common electrode CE arranged on the intermediate layer EL. Referring to Fig. 3, the display panel according to embodiments of the disclosure can further comprise a cover layer 340 which is arranged on the common electrode CE. Referring to Fig. 3, the display panel according to embodiments of the disclosure can further comprise an encapsulation layer 350 on the cover layer 340. The encapsulation layer 350 can comprise an adhesive layer 351 on the cover layer 340 and a metal encapsulation layer 352 on the adhesive layer 351. Referring to Fig. 3, the common electrode CE can be located in the display area DA and can extend in the non-display area NDA to the gate enclosure area GBZ. Referring to Fig. 3, in the display panel according to embodiments of the disclosure, the passivation layer 310 can be arranged on the gate-in-panel circuit GIPC. The passivation layer 310 can protect a plurality of transistors that may be arranged in the gate-in-panel circuit GIPC, such that it insulates between the plurality of transistors or between the plurality of transistors and the light-emitting elements ED. The passivation layer 310 can be an inorganic layer comprising an inorganic insulating material. For example, the intermediate insulating layer can comprise at least one of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy), but the disclosure is not limited thereto. For example, if the passivation layer 310 consists of silicon nitride (SiNx), special gases, such as monosilane (SiH4) and ammonia (NH3), which contain a large amount of hydrogen, can be used during the process of forming the passivation layer 310. For this reason, the passivation layer 310 contains a large amount of hydrogen, and the hydrogen can diffuse out of the passivation layer 310 in a gaseous or ionic state. The diffused hydrogen can reduce the conductivity of the transistor, which may be located in the gate-in-panel circuit (GIPC), and accelerate its deterioration. Furthermore, if the transistor's threshold voltage (Vth) shifts in the negative direction, the image quality of the display panel can deteriorate due to low luminance from the light-emitting element. The following describes in detail a transistor which has a structure capable of improving short-channel element properties due to hydrogen penetration, preventing degradation, and preventing deterioration from lateral stress, which may additionally occur in the transistor from a number of transistors that may be arranged in the gate-in-panel circuit (GIPC). Fig. 4 schematically represents a gate-in-panel circuit (GIPC) of a display device according to embodiments of the disclosure. Referring to Fig. 4, a gate-in-panel circuit (GIPC) according to embodiments of the disclosure can have a plurality of gate output buffers 410 for outputting a plurality of gate signals and a control circuit 430 for controlling the plurality of gate output buffers 410. Here, each of the plurality of gate signals can be a scanning signal (SCAN) or a detection signal (SENSE). Each of the majority of gate output buffers 410 can be configured to receive a gate timing signal GCLK and a low-level gate voltage VGL and output a gate signal to the gate output node Ngout. The gate output buffer 410 can have a pull-up transistor Tu, into which the gate timing signal GCLK is input, and a pull-down transistor Td, into which the low-level gate voltage VGL is input. The gate output buffer 410 can output a gate signal to the gate output node Ngout, to which the pull-up transistor Tu and the pull-down transistor Td are connected. The pull-up transistor Tu can be connected between the gate timing node Ngclk and the gate output node Ngout and can switch a connection between the gate timing node Ngclk and the gate output node Ngout. The pull-down transistor Td can be connected between the low-level gate voltage node Nvgl and the gate output node Ngout, and can connect the low-level gate voltage node Nvgl and the gate output node Ngout. In the pull-up transistor Tu, a capacitor CAP can be electrically connected between the Q node, which is a gate node, and the gate output node Ngout. The capacitor CAP can serve to boost the voltage of the Q node according to a voltage variation of the gate output node Ngout. The control circuit 430 can control the voltage of the Q node, which is electrically connected to the gate node of the pull-up transistor Tu, and the voltage of the QB node, which is electrically connected to the gate node of the pull-down transistor Td. The QB node can receive either a DC or an AC voltage signal from the control circuit 430. The control circuit 430 controls the voltage of each of the Q nodes and the QB node and can include a control transistor Tc, which has a drain node to which a high-potential voltage is applied. The high-potential power voltage GVDD can be input into the control transistor Tc via the high-potential power node Ngvdd. The control transistor Tc can have multiple transistors. For example, the control transistor Tc can have one or more transistors for charging the Q node, one or more transistors for discharging the Q node, one or more transistors for charging the QB node, and one or more transistors for discharging the QB node. For example, one or more transistors of the control transistor Tc have a source node Ns, a gate node Ng, and a drain node Nd. To control the voltage of each of the Q node and the QB node, the control circuit 430 can receive a start signal, a reset signal or the like, and can also receive a carry signal according to a gate control method. Referring to Fig. 4, the gate-in-panel circuit GIPC can further include a carry-out buffer 420 comprising a carry-up transistor Tuc, into which the gate timing signal GCLK is input, and a carry-down transistor Tdc, into which the low-potential power supply voltage GVSS is input. The carry output buffer 420 can output a carry signal to a circuit of a previous stage and / or a circuit of a next stage via a carry output node Ncout, to which the carry pull-up transistor Tuc and the carry pull-down transistor Tdc are connected. The carry-pull-up transistor Tuc can be connected between the gate timing node Ngclk and the carry output node Ncout. The carry-pull-down transistor Tdc can be connected between the carry output node Ncout and the low-potential power supply node Ngvss. The gate node of the pull-up transistor Tu and the gate node of the carry-up transistor Tuc can be connected to the Q node. The gate node of the pull-down transistor Td and the gate node of the carry-down transistor Tdc can be connected to the QB node. In the display panel according to embodiments of the disclosure, at least one of the pull-up transistor Tu, the carry-pull-up transistor Tuc, and the control transistor Tc can have a structure capable of improving short-channel element characteristics due to hydrogen ingress, preventing degradation, and mitigating degradation from lateral stress that may additionally occur in the transistor. However, it can also be applied, without limitation, to other types of transistors that may be arranged throughout the interior and exterior of the gate-in-panel circuit GIPC. Below, with reference to a circuit diagram and a cross-sectional view representing a transistor with a structure according to embodiments of the disclosure, embodiments classified according to control methods are described in detail. Fig. 5 shows a transistor TR comprising a first transistor TR1 and a second transistor TR2 in a display device according to embodiments of the disclosure. Referring to Fig. 5, the transistor TR contained in the display device can have a source node S, a drain node D, and a gate node G. A gate voltage Vg can be applied to the gate node G. Referring to Fig. 5, the transistor TR contained in the display device can have a first transistor TR1 and a second transistor TR2. The first transistor TR1 can have a first source node S1, a first drain node D1, and a first gate node G1. The second transistor TR2 can have a second source node S2, a second drain node D2, and a second gate node G2. The first transistor TR1 and the second transistor TR2 can be connected in series. The first drain node D1 of the first transistor TR1 can be electrically connected to the second source node S2 of the second transistor. The first source node S1 of the first transistor TR1 can be the source node S of transistor TR, and the second drain node D2 of the second transistor TR2 can be the drain node D of transistor TR. The following describes a cross-sectional structure and a planar structure of the transistor TR from Fig. 5 with reference to Fig. 6. Fig. 6 is a cross-sectional view and a top view showing a transistor TR comprising a first transistor TR1 and a second transistor TR2 in a display device according to embodiments of the disclosure. Referring to the cross-sectional view shown in Fig. 6, a display panel according to embodiments of the disclosure can comprise a substrate 111 and a transistor TR arranged on the substrate 111. No duplicate description is given for essentially the same configuration as the configuration of Fig. 3. The transistor TR can have an active layer ACT on the substrate 111, a first gate-insulating layer 631 arranged on the active layer ACT, and a second gate-insulating layer 632 arranged on the active layer ACT and in a first direction at a distance from the first gate-insulating layer 631. The transistor TR can have a first gate electrode G1, which is located on the first gate insulating layer 631, and a second gate electrode G2, which is located on the second gate insulating layer 632 and at a distance from the first gate electrode G1. In other words, the second gate electrode G2 can be located at a distance from the first gate electrode G1. The active layer ACT may comprise an oxide semiconductor material, but the disclosure is not limited to this. For example, the active layer ACT may comprise amorphous silicon, polysilicon, or low-temperature polysilicon (LTPS). A portion of the active layer (ACT) may contain a dopant. This dopant may consist of foreign ions introduced into the active layer (ACT) via a doping process. A portion of the active layer (ACT) containing the dopant may function as a source region and / or a drain region, while the remaining portion of the active layer (ACT) without the dopant may function as a channel region. Referring to Fig. 6, the active layer ACT can have a first channel section CH1 that overlaps at least one section of the first gate electrode G1, a second channel section CH2 that overlaps at least one section of the second gate electrode G2, a first conductive section 621 that is positioned in the first direction from the second channel section CH2, a second conductive section 622 that is positioned between the first channel section CH1 and the second channel section CH2, and a third conductive section 623 that is positioned in the second direction from the first channel section CH1, which is opposite to the first direction. In other words, the first channel section CH1 and the second channel section CH2 may not contain a dopant, and the first conductive section to the third conductive section 621, 622 and 623 may contain a dopant. Referring to Fig. 6, the display panel according to embodiments of the disclosure can further comprise an intermediate insulating layer 640 arranged on the first gate electrode G1 and the second gate electrode G2. For example, the intermediate insulating layer 640 can be arranged such that it covers the active layer ACT, the first gate insulating layer 631, the second gate insulating layer 632, the first gate electrode G1 and the second gate electrode G2. Referring to Fig. 6, the intermediate insulating layer 640 can be inserted in an intermediate space in which the first gate electrode G1 and the second gate electrode G2 are arranged at a distance from each other, and in an intermediate space in which the first gate insulating layer 631 and the second gate insulating layer 632 are arranged at a distance from each other, such that it touches an upper surface of the second conductive section 622. The intermediate insulating layer 640 can be an inorganic layer comprising an inorganic insulating material. For example, the intermediate insulating layer 640 can comprise at least one of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy), but the disclosure is not limited thereto. Referring to Fig. 6, the drain electrode D is arranged on the intermediate insulation layer 640 and is connected through a hole in the intermediate insulation layer 640 to a section of the active layer ACT, and the source electrode S is arranged on the intermediate insulation layer 640 and is connected through a hole in the intermediate insulation layer 640 to a section of the active layer ACT. The drain electrode D can be connected to the first conductive section 621, and the source electrode S can be connected to the third conductive section 623. Referring to Fig. 6, the display panel according to embodiments of the disclosure can further comprise a buffer layer 610 between the substrate 111 and the active layer ACT, and a metal structure LS arranged between the substrate 111 and the buffer layer 610, overlapping the first channel section CH1 and the second channel section CH2. For example, the metal structure LS can overlap the entire active layer ACT. The buffer layer 610 can be arranged to cover the metal structure LS. The thickness of the buffer layer 610, which is arranged between the metal structure LS and the active layer ACT, can be greater than or equal to the thickness of the first gate insulating layer 631 and the thickness of the second gate insulating layer 632. For example, the thickness of the buffer layer 610, which is arranged between the metal structure LS and the active layer ACT, can be three times or more than the thickness of the first gate insulating layer 631 and the thickness of the second gate insulating layer 632. In the display panel according to embodiments of the disclosure, the metal structure LS can comprise at least one of a light-blocking layer, a conductor, and an electrode. Accordingly, the metal structure LS can have a state in which it is not connected to the transistor TR, a state in which the gate voltage applied to the first gate electrode G1 is applied, a state in which the ground voltage is applied, and an electrically potential-free state. The top view shown in Fig. 6 can depict an upper surface of transistor TR, which includes the first transistor TR1 and the second transistor TR2. The source electrode S and the drain electrode D can be arranged at two opposite ends of transistor TR. The first gate insulating layer 631 and the second gate insulating layer 632, and the first gate electrode G1 and the second gate electrode G2, can be arranged between the source electrode S and the drain electrode D. A third conductive section 623 can be arranged between the source electrode S and the first gate insulating layer 631, a second conductive section 622 can be arranged between the first gate insulating layer 631 and the second gate insulating layer 632, and a first conductive section 621 can be arranged between the second gate insulating layer 632 and the drain electrode D. Referring to the top view shown in Fig. 6, the distance D1 at which the second gate electrode G2 is located from the first gate electrode G1 can be equal to or greater than the distance D2 at which the second gate insulating layer 632 is located from the first gate insulating layer 631, and the length D2 of the upper surface of the second conductive section 622. The separation distance D1 between the first gate electrode G1 and the second gate electrode G2, the separation distance D2 between the first gate insulating layer 631 and the second gate insulating layer 632, and the length D2 of the upper surface of the second conductive section 622 can be described by the process of forming the structure of the transistor TR described above. Although not shown, the active layer ACT of the transistor TR can be formed in the display panel according to embodiments of the disclosure, and the gate-insulating layer material and the gate electrode material can be stacked sequentially. A first gate electrode G1 and a second gate electrode G2 can be formed by a structuring process on the gate electrode material. A first photostructure and a second photostructure can be formed by applying a photoresist (PR) material to the upper portions of the first gate electrode G1 and the second gate electrode G2, respectively. The first photostructure and the second photostructure can be spaced apart and can have a separation distance that is shorter than the separation distance between the first gate electrode G1 and the second gate electrode G2.For example, the separation distance between the first photostructure and the second photostructure can be 2 µm. The first gate-insulating layer 631 and the second gate-insulating layer 632 can be formed by etching the gate-insulating layer material using the first and second photostructures as masks. The gate-insulating layer material can be etched by a dry etching process. A section of the active layer ACT exposed by the structured first gate-insulating layer 631 and second gate-insulating layer 632 can be made conductive by a dry etching process. In other words, a dopant can be injected into the first conductive section through the third conductive section 621, 622, and 623 of the active layer ACT by a dry etching process. As a result, since the gate-insulating layer material is etched taking into account the maximum process clearance between the first gate electrode G1 and the second gate electrode G2, the width of the upper surface of the second conductive section 622 can be minimized. Fig. 7 depicts a transistor TR comprising a first to third transistor TR1, TR2, and TR3 in a display device according to embodiments of the disclosure. No duplicate description is given for essentially the same configuration as the configuration of Fig. 5. Referring to Fig. 7, the transistor TR contained in the display device can comprise a first through third transistor TR1, TR2, and TR3. The first transistor TR1 can have a first source node S1, a first drain node D1, and a first gate node G1. The second transistor TR2 can have a second source node S2, a second drain node D2, and a second gate node G2. The third transistor TR3 can have a third source node S3, a third drain node D3, and a third gate node G3. The first three transistors, TR1, TR2, and TR3, can be connected in series. The first drain node D1 of the first transistor TR1 can be electrically connected to the second source node S2 of the second transistor, and the first source node S1 of the first transistor TR1 can be electrically connected to the third drain node D3 of the third transistor. The third source node S3 of the third transistor TR3 can be the source node S of transistor TR, and the second drain node D2 of the second transistor TR2 can be the drain node D of transistor TR. The following describes a cross-sectional structure of the transistor TR of Fig. 7 with reference to Fig. 8. Fig. 8 is a cross-sectional view and a top view of a display panel according to embodiments of the disclosure. A display panel according to embodiments of the disclosure can comprise a substrate 111 and a transistor TR arranged on the substrate 111. No duplicate description is given for essentially the same configuration as the configuration of Fig. 6. The transistor TR can further comprise a third gate-insulating layer 833, which is arranged on the active layer ACT and is positioned in the second direction at a distance from the first gate-insulating layer 831, and a third gate electrode G3, which is arranged on the third gate-insulating layer 833 and is positioned at a distance from the first gate electrode G1. The thickness of the buffer layer 610, which is arranged between the metal structure LS and the active layer ACT, can be greater than or equal to the thicknesses of the first gate insulating layer through the third gate insulating layer 831, 832, and 833. For example, the thickness of the buffer layer 610, which is arranged between the metal structure LS and the active layer ACT, can be three times or more the thicknesses of the first gate insulating layer through the third gate insulating layer 831, 832, and 833. Referring to Fig. 8, the active layer ACT can have a third channel section CH3, which is positioned in the second direction from the third conductive section 823 and overlaps at least one section of the third gate electrode G3, and a fourth conductive section 824, which is positioned in the second direction from the third channel section CH3. The third channel section CH3 may not contain a dopant, and the fourth conductive section 824 may contain a dopant. At least one section of the first conductive section 821 can overlap the second gate electrode G2, the second conductive section 822 cannot overlap the first gate electrode G1 and the second gate electrode G2, the third conductive section 823 cannot overlap the first gate electrode G1 and the third gate electrode G3, and at least one section of the fourth conductive section 824 can overlap the third gate electrode G3. Referring to Fig. 8, an intermediate insulating layer 640 can be arranged on the first gate electrode G1 and the third gate electrode G3. The intermediate insulating layer 640 can be arranged such that it covers the active layer ACT, the first gate insulating layer to the third gate insulating layer 831, 832 and 833, and the first gate electrode to the third gate electrode G1, G2 and G3. Referring to Fig. 8, the intermediate insulating layer 640 can be inserted in an intermediate space in which the first gate electrode G1 and the third gate electrode G3 are arranged at a distance from each other, and in an intermediate space in which the first gate insulating layer 831 and the third gate insulating layer 833 are arranged at a distance from each other, such that it touches an upper surface of the third conductive section 823. Referring to Fig. 8, the drain electrode D can be connected to the first conductive section 821 through a hole in the intermediate insulation layer 640, and the source electrode S can be connected to the fourth conductive section 824 through another hole in the intermediate insulation layer 640. Referring to Fig. 8, in the display device according to embodiments of the disclosure, the metal structure LS can have a state in which it is not connected to the transistor TR, a state in which the gate voltage applied to the first gate electrode G1 is applied, a state in which the ground voltage is applied, and a state in which the metal structure LS is electrically potential-free. The top view shown in Fig. 8 can depict the upper surface of transistor TR, which includes transistors TR1, TR2, and TR3. The first gate insulating layer to the third gate insulating layer 831, 832, and 833, and the first gate electrode to the third gate electrode G1, G2, and G3, can be arranged between the source electrode S and the drain electrode D.A fourth conductive section 824 can be arranged between the source electrode S and the third gate insulating layer 833, a third conductive section 823 can be arranged between the third gate insulating layer 833 and the first gate insulating layer 831, a second conductive section 822 can be arranged between the first gate insulating layer 831 and the second gate insulating layer 832, and a first conductive section 821 can be arranged between the second gate insulating layer 832 and the drain electrode D. In the display device according to embodiments of the disclosure, since the gate-insulating layer material is etched taking into account the maximum value of the process clearance between the first gate electrode G1 and the third gate electrode G3, the length of the upper surface of the third conductive section 823 can be minimized. Accordingly, the distance D1, at which the third gate electrode G3 is arranged at a distance from the first gate electrode G1, can be greater than or equal to the distance D2, at which the third gate insulating layer 833 is arranged at a distance from the first gate insulating layer 831, and the width D2 of the upper surface of the third conductive section 823. Fig. 9 is an enlarged cross-sectional view showing a transistor TR in a display device according to embodiments of the disclosure. Area A is an enlarged cross-sectional view that provides a comparative example of a transistor TR which, in contrast to a display device according to embodiments of the disclosure, has only the first gate electrode G1, the first gate insulating layer 930 and the active layer ACT. Referring to Fig. 9, the active layer ACT of region A can have a first channel section CH1, a first connecting section 921 and a second connecting section 922, and the first connecting section 921 and the second connecting section 922 can contain a dopant. At least one section of the first interconnection section 921 may overlap the first gate electrode G1, and at least one section of the second interconnection section 922 may overlap the first gate electrode G1. The first conductive main section 921a of the first interconnection section 921 may be a region that does not overlap the first gate electrode G1, and the first conductive subsection 921b of the first interconnection section 921 may have a region that does overlap the first gate electrode G1. Similarly, the second conductive main section 922a of the second interconnection section 922 may be a region that does not overlap the first gate electrode G1, and the second conductive subsection 922b of the second interconnection section 922 may have a region that overlaps the first gate electrode G1. The first conductive main section 921a and the second conductive main section 922a can be regions into which a dopant is injected by a dry-etching process of the first gate-insulating layer 930. The first conductive subsection 921b and the second conductive subsection 922b can be regions into which dopants have diffused from the first conductive main section 921a and the second conductive main section 922a and which extend to the first channel section CH1. Since the first conductive subsection 921b and the second conductive subsection 922b are formed, the length of the first channel section CH1, i.e., the channel length of transistor TR, may be shorter than a predetermined value (hereinafter, the length by which the channel length of transistor TR was shortened from the intended value is referred to as "2ΔL"). For this reason, it may be difficult to control the drive of transistor TR, or the element's characteristics may deteriorate. Furthermore, in the display panel according to embodiments of the disclosure, the intermediate insulating layer 640 can contain hydrogen. For example, if the intermediate insulating layer 640 comprises silicon nitride (SiNx), special gases, such as monosilane (SiH4) and ammonia (NH3), which contain a large amount of hydrogen, can be used during the process of forming the intermediate insulating layer 640. For this reason, the intermediate insulating layer 640 contains a large amount of hydrogen, and hydrogen can be spread outside the intermediate insulating layer 640 by diffusion in a gaseous or ionic state. Since the diffused hydrogen increases the conductivity of the active layer ACT, 2ΔL in transistor TR can be increased. In other words, the length of the first channel segment CH1 can be further reduced, and the degradation of transistor TR can be accelerated. Furthermore, as the threshold voltage Vth of transistor TR shifts in the negative direction, a luminance defect of the light-emitting element can occur, leading to a reduction in the image quality of the display panel. Area A1 is an enlarged cross-sectional view showing the first transistor TR1 and the second transistor TR2 of Fig. 6 according to embodiments of the disclosure. In the display panel according to embodiments of the disclosure, the intermediate insulating layer 640 may contain hydrogen, and the first conductive section 621, the second conductive section 622 and the third conductive section 623 may contain hydrogen that diffuses from and penetrates the intermediate insulating layer 640. Referring to Fig. 9, the second conductive section 622 of region A1 cannot overlap the first gate electrode G1 and the second gate electrode G2. At least one section of the third conductive section 623 can overlap the first gate electrode G1. The third conductive main section 623a of the third conductive section 623 is a region that does not overlap the first gate electrode G1, and the third conductive subsection 623b of the third conductive section 623 may have a region that overlaps the first gate electrode G1. The length of the first channel section CH1 may be reduced due to the third conductive subsection 623b, which is formed by diffusion of the dopant from the third conductive main section 623a. However, since the second conductive section 622, which does not overlap the first gate electrode G1, does not reduce the length of the first channel section CH1, degradation of the transistor TR in region A1 is less likely than in region A. Area A2 is an enlarged cross-sectional view showing the first to third transistors TR1, TR2 and TR3 of Fig. 8, according to embodiments of the disclosure. In the display panel according to embodiments of the disclosure, the intermediate insulating layer 640 may contain hydrogen, and the first conductive section 821, the second conductive section 822 and the third conductive section 823 may contain hydrogen that diffuses from and penetrates the intermediate insulating layer 640. Referring to Fig. 9, the second conductive section 822 of region A2 cannot overlap the first gate electrode G1 and the second gate electrode G2. The third conductive section 823 also cannot overlap the first gate electrode G1 and the third gate electrode G3. Since the second conductive section 822 and the third conductive section 823 do not reduce the length of the first channel section CH1, deterioration of the transistor TR in the area A2 is least likely. As a result, in the display panel according to embodiments of the disclosure, deterioration of the transistor TR can be prevented, and reliability can be improved by ensuring a conductive area, i.e., a channel area, that does not overlap the first gate electrode G1 of the transistor TR. On the other hand, although the length of the first channel section CH1 cannot be reduced, since the second conductive section 822 and the third conductive section 823 do not overlap the first gate electrode G1, the lateral stress of the transistor TR may increase. For example, if transistor TR is driven in region A, the charge carrier can move through the first channel section CH1 and then sequentially through the first conductive subsection and the first conductive main section. If transistor TR is driven in region A2, the charge carrier can move directly to the second conductive section 822 after passing through the first channel section CH1. Accordingly, lateral stress can increase as the charge carrier concentration rapidly increases, and thus transistor TR can degrade. To improve the lateral stress of transistor TR, the resistance of the first channel section CH1 can be increased. For example, since the length of the first channel section CH1 in region A2 is not reduced by the second conductive section 822 and the third conductive section 823, it can have a resistance value greater than that of the first channel section CH1 in region A and region A1. Accordingly, the lateral stress generated in transistor TR can be partially mitigated. To mitigate the lateral stress on transistor TR, the first three transistors, TR1, TR2, and TR3, can be connected in series to form transistor TR. The resistance of the first channel section, CH1, can be increased by placing the second transistor, TR2, and the third transistor, TR3, which can act as a type of resistor, at opposite ends of the first transistor, TR1. In the display device according to embodiments of the disclosure, the transistor TR can correspond to at least one of the pull-up transistor Tu, the carry-up transistor Tuc, Tdc and the control transistor Tc of Fig. 4. The three types of transistors described above can be transistors that exhibit a high probability of deterioration due to lateral stress in the gate-in-panel circuit. For example, when a high-potential voltage is applied to the drain node, as in a control transistor, the electric field in the active layer (ACT) is concentrated on the side of the drain electrode (D), accelerating the charge carrier and causing impact ionization. This increases the probability of defects in the active layer (ACT), and the transistor can degrade. Accordingly, deterioration due to lateral stress of the transistor TR can be prevented by making a change to the drive of each of the first to third transistors TR1, TR2 and TR3, such as applying a different voltage to at least one of the first to third gate electrodes G1, G2 and G3 and the metal structure LS than those of the rest. The following describes in detail, with reference to Figs. 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 to 24, a method for driving the first to third transistors TR1, TR2 and TR3, which can mitigate deterioration due to lateral stress while preventing deterioration of the element properties by reducing 2ΔL. Fig. 10 depicts a transistor TR comprising a first transistor and a second transistor TR1 and TR2, in a display device according to embodiments of the disclosure. No duplicate description is given for essentially the same configuration as the configuration of Fig. 5. Referring to Fig. 10, a gate voltage Vg can be applied to the first gate node G1 and the second gate node G2. The first gate node G1 and the second gate node G2 can be electrically connected to each other. Fig. 11 is a cross-sectional view showing a transistor TR comprising a first transistor TR1 and a second transistor TR2 in a display device according to embodiments of the disclosure. Fig. 11 is a cross-sectional view showing a transistor TR corresponding to the circuit diagram shown in Fig. 10, and no duplicate description is given for essentially the same configuration as the configuration of Fig. 6. The display panel according to embodiments of the disclosure can further comprise a first metal structure LS1, which is arranged between the substrate 111 and the buffer layer 610 and overlaps the first channel section CH1, and a second metal structure LS2, which is arranged between the substrate 111 and the buffer layer 610, is arranged at a distance from the first metal structure LS1 and overlaps the second channel section CH2. Referring to Fig. 11, the same gate voltage Vg can be applied to the first gate electrode G1 and the second gate electrode G2, the gate voltage Vg applied to the first gate electrode G1 can be applied to the first metal structure LS1, and the ground voltage GND can be applied to the second metal structure LS2. Accordingly, the first transistor TR1 can have a double-gate structure, and the second transistor TR2 can have a top-gate structure. The second transistor TR2 can be positioned in a drain section relative to the first transistor TR1, receiving the charge carriers. Therefore, it can be a major factor in the lateral stress generated in transistor TR1. For example, if the second transistor TR2 has a dual-gate structure, the second channel section CH2 of the second transistor TR2 can have an electric field, i.e., a channel, formed on both the top and bottom surfaces, thus increasing the number of channels. Consequently, the number of charge carriers supplied to the drain section can also increase, and thus the lateral stress can increase. In the example of Fig. 11, since the second transistor TR2 is driven in a top-gate structure while preventing the formation of the bottom channel, deterioration due to lateral stress can be mitigated. Fig. 12 depicts a transistor TR comprising a first to third transistor TR1, TR2, and TR3 in a display device according to embodiments of the disclosure. No duplicate description is given for essentially the same configuration as that of Fig. 7. Referring to Fig. 12, a gate voltage Vg can be applied to the first gate node through the third gate node G1, G2, and G3. The first gate node through the third gate node G1, G2, and G3 can be electrically connected to each other. Figures 13, 14 to 15 are cross-sectional views showing a transistor TR comprising a first to third transistor TR1, TR2 and TR3, in a display device according to embodiments of the disclosure. Figures 13, 14 to 15 are cross-sectional views showing a transistor TR corresponding to the circuit diagram shown in Figure 12, and no duplicate description is given for essentially the same configuration as the configuration of Figure 8. Referring to Fig. 13, the display panel according to embodiments of the disclosure can further comprise a third metal structure LS3, which is arranged between the substrate 111 and the buffer layer 610, is arranged at a distance from the first metal structure LS1 and overlaps the third channel section. In the display panel according to embodiments of the disclosure, each of the first metal structure LS1, the second metal structure LS2 and the third metal structure LS3 can have a state of: a state in which it is not connected to the transistor TR, a state in which it is electrically connected to the source electrode S, a state in which the gate voltage Vg applied to the first gate electrode G1 is applied, a state in which the ground voltage GND is applied, and an electrically potential-free state. In the example of Fig. 13, the same gate voltage Vg can be applied to the first gate electrode up to the third gate electrode G1, G2 and G3, the ground voltage GND can be applied to the first metal structure LS1, and the gate voltage Vg applied to the first gate electrode G1 can be applied to the second metal structure LS2 and the third metal structure LS3. Accordingly, the first transistor TR1 can have a top-gate structure, and the second transistor TR2 and the third transistor TR3 can have a double-gate structure. Since the second transistor TR2 has a double-gate structure, the second channel section CH2 of the second transistor TR2 has channels formed on an upper section and a lower section thereof, thereby increasing the number of channels and the number of charge carriers received by the drain section. Therefore, in the example of Fig. 13, to reduce 2ΔL of the first transistor TR1, the second conductive section 822 and the third conductive section 823 are formed to prevent deterioration of the element properties, however, deterioration may increase due to lateral stress. Referring to Fig. 14, the same gate voltage Vg can be applied to the first gate electrode up to the third gate electrode G1, G2 and G3, the gate voltage Vg applied to the first gate electrode G1 can be applied to the first metal structure LS1, and the ground voltage GND can be applied to the second metal structure LS2 and the third metal structure LS3. Accordingly, in the example of Fig. 14, the first transistor TR1 can have a double-gate structure, and the second transistor TR2 and the third transistor TR3 can have a top-gate structure. Since the second transistor TR2 is driven in a top-gate structure while preventing the formation of a bottom channel, the number of charge carriers received from the drain section is reduced compared to the example in Fig. 13, thus mitigating degradation due to lateral stress. However, since only the first transistor TR1 is driven in a double-gate structure, the inrush current Ion of transistor TR may be reduced due to a lack of the total number of channels formed compared to the example in Fig. 13. Referring to Fig. 15, the same gate voltage Vg can be applied to the first gate electrode up to the third gate electrode G1, G2 and G3, the gate voltage Vg applied to the first gate electrode G1 can be applied to the first metal structure LS1 and the third metal structure LS3, and the ground voltage GND can be applied to the second metal structure LS2. Accordingly, in the example of Fig. 15, the first transistor TR1 and the third transistor TR3 can have a double-gate structure, and the second transistor TR2 can have a top-gate structure. Since the second transistor TR2 is driven in a top-gate structure while preventing the formation of a bottom channel, the number of charge carriers received from the drain section is reduced compared to the example in Fig. 13, thus mitigating degradation due to lateral stress. Since the first transistor TR1 and the third transistor TR3 are driven in a double-gate structure, the total number of channels formed is increased compared to the example in Fig. 14, thereby mitigating the reduction of the inrush current Ion of transistor TR. Fig. 16 depicts a transistor TR comprising a first to third transistor TR1, TR2, and TR3 in a display device according to embodiments of the disclosure. No duplicate description is given for essentially the same configuration as that of Fig. 7. Referring to Fig. 16, a gate voltage Vg can be applied to the first gate node G1, and a ground voltage GND can be applied to the second gate node G2 and the third gate node G3. Figures 17 and 18 are cross-sectional views showing a transistor TR comprising a first through third transistor TR1, TR2, and TR3 in a display device according to embodiments of the disclosure. Figures 17 and 18 are cross-sectional views showing a transistor TR corresponding to the circuit diagram shown in Figure 16, and no duplicate description is given for essentially the same configuration as the configuration of Figure 8. Referring to Fig. 17, a gate voltage Vg can be applied to the first gate electrode G1, a ground voltage GND can be applied to the second gate electrode G2 and the third gate electrode G3, a ground voltage GND can be applied to the first metal structure LS1, and a gate voltage Vg applied to the first gate electrode G1 can be applied to the second metal structure and third metal structure LS3. Accordingly, in the example of Fig. 17, the first transistor TR1 can have a top-gate structure, and the second transistor TR2 and the third transistor TR3 can have a bottom-gate structure. The first transistor TR1, which is driven in the top-gate structure, can have a first gate-insulating layer 831, and the second transistor TR2 and the third transistor TR3, which are driven in the bottom-gate structure, can have a buffer layer 610. Since the thickness of the buffer layer 610 in the display device according to embodiments of the disclosure is equal to or greater than the thicknesses of the first gate-insulating layer through the third gate-insulating layer 831, 832, and 833, the second transistor TR2 and the third transistor TR3 have a weaker channel than that of the first transistor TR1, so that less current can flow. Accordingly, the number of charge carriers received by the second transistor TR2, i.e., the drain section of the second transistor TR, can be reduced, thereby mitigating degradation due to lateral stress. However, since only the first transistor TR1 is driven in a top-gate structure, the inrush current Ion of transistor TR may be reduced. Referring to Fig. 18, a gate voltage Vg can be applied to the first gate electrode G1, a ground voltage GND can be applied to the second gate electrode G2 and the third gate electrode G3, and a gate voltage Vg applied to the first gate electrode G1 can be applied to the first metal structure to the third metal structure LS1, LS2 and LS3. Accordingly, in the example of Fig. 18, the first transistor TR1 can have a double-gate structure, and the second transistor TR2 and the third transistor TR3 can have a bottom-gate structure. The number of charge carriers received by the second transistor TR2, i.e., the drain section of the second transistor TR, can be reduced, thus mitigating degradation due to lateral stress. Since the first transistor TR1 is driven in a dual-gate configuration, the total number of channels formed is increased compared to the example in Fig. 17, thereby mitigating the reduction in the inrush current ion of transistor TR. Fig. 19 depicts a transistor TR comprising a first to third transistor TR1, TR2, and TR3 in a display device according to embodiments of the disclosure. No duplicate description is given for essentially the same configuration as that of Fig. 7. Referring to Fig. 19, a gate voltage Vg can be applied to the first gate node G1, and the second gate node G2 and the third gate node G3 can be electrically floating. Figures 20 and 21 are cross-sectional views showing a transistor TR comprising first through third transistors TR1, TR2, and TR3 in a display device according to embodiments of the disclosure. Figures 20 and 21 are cross-sectional views showing a transistor TR corresponding to the circuit diagram shown in Figure 19, and no duplicate description is given for essentially the same configuration as the configuration of Figure 8. Referring to Fig. 20, the gate voltage Vg can be applied to the first gate electrode G1, the second gate electrode G2 and the third gate electrode G3 can be electrically floating, and the ground voltage GND can be applied to the metal structure LS. Accordingly, in the example of Fig. 20, the first to third transistors TR1, TR2 and TR3 can have a top-gate structure. Since the second gate electrode G2 and the third gate electrode G3 are in an electrically potential-free state, a voltage that is very weak compared to the gate voltage Vg applied to the first gate electrode G1 can be applied to the second gate electrode G2 and the third gate electrode G3 by means of a boundary effect. Therefore, the number of charge carriers received by the second transistor TR2, i.e., the drain section of transistor TR, may be reduced, thus mitigating degradation due to lateral stress. However, since a very weak voltage is applied to the second gate electrode G2 and the third gate electrode G3, the total gate voltage Vg, i.e. the gate voltage Vg of the entire transistor TR, may be reduced, and thus the inrush current Ion of the transistor TR may be reduced. Referring to Fig. 21, the gate voltage Vg can be applied to the first gate electrode G1, the second gate electrode G2 and the third gate electrode G3 can be electrically floating, the ground voltage GND can be applied to the first metal structure LS1, and the gate voltage Vg applied to the first gate electrode G1 can be applied to the second metal structure LS2 and the third metal structure LS3. Accordingly, in the example of Fig. 21, the first transistor TR1 can have a top-gate structure, and the second transistor TR2 and the third transistor TR3 can have a double-gate structure. Since the second transistor TR2 has a double-gate structure, the second channel section CH2 of the second transistor TR2 has channels formed on an upper section and a lower section thereof, thereby increasing the number of channels and causing deterioration due to lateral stress. Since a very weak voltage is applied to the second gate electrode G2 and the third gate electrode G3, the gate voltage Vg of the entire transistor TR may be reduced compared to degradation due to lateral stress, thus increasing the risk of a reduction in the inrush current Ion of transistor TR. Therefore, if the second gate electrode G2 and the third gate electrode G3 are electrically floating, a sufficient current can be ensured by driving the second transistor TR2 and the third transistor TR3 in the dual-gate structure. Fig. 22 depicts a transistor TR comprising transistors TR1, TR2, TR3, TR4, and TR5, in a display device according to embodiments of the disclosure. No duplicate description is given for essentially the same configuration as that of Fig. 19. Referring to Fig. 22, the transistor TR contained in the display device can further comprise a fourth transistor TR4 and a fifth transistor TR5. The fourth transistor TR4 can comprise a fourth source node S4, a fourth drain node D4, and a fourth gate node G4. The fifth transistor TR5 can comprise a fifth source node S5, a fifth drain node D5, and a fifth gate node G5. The first through fifth transistors TR1, TR2, TR3, TR4, and TR5 can be connected in series. The second drain node D2 of the second transistor TR2 can be electrically connected to the fourth source node S4 of the fourth transistor TR4, and the third source node S3 of the third transistor TR3 can be electrically connected to the fifth drain node D5 of the fifth transistor TR5. The fifth source node S5 of the fifth transistor TR5 can be the source node S of transistor TR, and the fourth drain node D4 of the fourth transistor TR4 can be the drain node D of transistor TR. Referring to Fig. 22, the gate voltage Vg can be applied to the first gate node G1, the fourth gate node G4, and the fifth gate node G5, while the second gate node G2 and the third gate node G3 can be electrically isolated. The first gate node G1, the fourth gate node G4, and the fifth gate node G5 can be electrically connected to each other. Fig. 23 is a cross-sectional view showing a transistor TR comprising transistors TR1, TR2, TR3, TR4, and TR5 in a display device according to embodiments of the disclosure. Fig. 23 is a cross-sectional view showing a transistor TR corresponding to the circuit diagram shown in Fig. 22, and no duplicate description is given for essentially the same configuration as the configuration of Fig. 8. The transistor TR can further comprise a fourth gate insulating layer 2334, which is arranged in the first direction at a distance from the second gate insulating layer 2332, a fifth gate insulating layer 2335, which is arranged in the second direction at a distance from the third gate insulating layer 2333, a fourth gate electrode G4, which is arranged on the fourth gate insulating layer 2334 and is arranged at a distance from the second gate electrode G2, and a fifth gate electrode G5, which is arranged on the fifth gate insulating layer 2335 and is arranged at a distance from the third gate electrode G3. Referring to Fig. 23, the active layer ACT can have a fourth channel section CH4 that overlaps at least one section of the fourth gate electrode G4, a fifth channel section CH5 that overlaps at least one section of the fifth gate electrode G5, a fifth conductive section 2325 positioned in the first direction from the fourth channel section CH4, and a sixth conductive section 2326 positioned in the second direction from the fifth channel section CH5. The first conductive section 2321 can be positioned without overlapping the second gate electrode G2 and the fourth gate electrode G4, and the fourth conductive section 2324 can be positioned without overlapping the third gate electrode G3 and the fifth gate electrode G5. For example, the active layer ACT can further have a second conductive section 2322 and a third conductive section 2323. The drain electrode D can be connected to the fifth conductive section 2325 through a hole in the intermediate insulation layer 640, and the source electrode S can be connected to the sixth conductive section 2326 through another hole in the intermediate insulation layer 640. The display panel according to embodiments of the disclosure can further comprise a fourth metal structure LS4, which is arranged between the substrate 111 and the buffer layer 610 and overlaps the fourth channel section CH4, and a fifth metal structure LS5, which is arranged between the substrate 111 and the buffer layer 610 and overlaps the fifth channel section CH5. Referring to Fig. 23, the same gate voltage Vg can be applied to the first gate electrode G1, the fourth gate electrode G4, and the fifth gate electrode G5, while the second gate electrode G2 and the third gate electrode G3 can be electrically floating. The gate voltage Vg applied to the first gate electrode G1 can be applied to the first three metal structures LS1, LS2, and LS3, and the ground voltage GND can be applied to the fourth metal structure LS4 and the fifth metal structure LS5. Accordingly, in the example of Fig. 23, the first to third transistors TR1, TR2 and TR3 can have a double-gate structure, and the fourth transistor TR4 and the fifth transistor TR5 can have a top-gate structure. Since the fourth transistor TR4 and the fifth transistor TR5 are driven in a top-gate structure, while preventing the formation of a bottom channel, the number of charge carriers received from the drain section of the first transistor TR1 can be reduced compared to the example in Fig. 13, thus mitigating degradation due to lateral stress. If only the first transistor TR1 is driven in a dual-gate configuration, the number of channels formed in the entire transistor TR may be insufficient, and thus the inrush current Ion of transistor TR may be reduced. Since the second transistor TR2 and the third transistor TR3 are also driven in the dual-gate configuration, a sufficient current can be ensured, thereby mitigating the reduction in the inrush current Ion of transistor TR. Although the second transistor TR2 and the third transistor TR3 have a double-gate structure, the tendency to increase lateral stress can be reduced because a very weak voltage is applied to the second gate electrode G2 and the third gate electrode G3. Fig. 24 is a top view showing a transistor TR comprising transistors TR1, TR2, TR3, TR4, and TR5 in a display device according to embodiments of the disclosure. Fig. 24 may be a top view of a transistor TR corresponding to the cross-sectional structure of Fig. 23, and it may not be a duplicate description for essentially the same configuration as the configuration of Fig. 8. Fig. 24 can represent the top surface of a transistor TR, which has transistors TR1, TR2, TR3, TR4, and TR5. The first gate insulating layer to the fifth gate insulating layer 2331, 2332, 2333, 2334, and 2335, and the first gate electrode to the fifth gate electrode G1, G2, G3, G4, and G5, can be arranged between the source electrode S and the drain electrode D.A sixth conductive section 2326 can be arranged between the source electrode S and the fifth gate insulating layer 2335, a fourth conductive section 2324 can be arranged between the fifth gate insulating layer 2335 and the third gate insulating layer 2333, a first conductive section 2321 can be arranged between the second gate insulating layer 2332 and the fourth gate insulating layer 2334, and a fifth conductive section 2325 can be arranged between the fourth gate insulating layer 2334 and the drain electrode D. In the display device according to embodiments of the disclosure, since the gate-insulating layer material is etched taking into account the maximum value of the process clearance between the second gate electrode G2 and the fourth gate electrode G4, the length of the upper surface of the first conductive section 2321 can be minimized. For the same reason, the length of the upper surface of the fourth conductive section 2324 can be minimized. A display device according to one embodiment of the disclosure can be described as follows. In one aspect of the present disclosure, a display device is provided which has a substrate and a transistor arranged on the substrate. In accordance with one or more embodiments of the present disclosure, the transistor may have an active layer on the substrate, a first gate-insulating layer arranged on the active layer, a second gate-insulating layer arranged on the active layer and positioned at a first distance from the first gate-insulating layer, a first gate electrode arranged on the first gate-insulating layer, a second gate electrode arranged on the second gate-insulating layer and positioned at a distance from the first gate electrode, a drain electrode connected to a section of the active layer, and a source electrode connected to another section of the active layer. In accordance with one or more embodiments of the present disclosure, the active layer may have a first channel section overlapping at least one section of the first gate electrode, a second channel section overlapping at least one section of the second gate electrode, a first conductive section positioned in the first direction from the second channel section, a second conductive section positioned between the first channel section and the second channel section, and a third conductive section positioned in a second direction opposite to the first direction from the first channel section. In accordance with one or more embodiments of the present disclosure, at least one section of the first conductive section can overlap the second gate electrode, and the second conductive section can be non-overlapping the first gate electrode and the second gate electrode. In accordance with one or more embodiments of the present disclosure, the drain electrode can be connected to the first conductive section, the source electrode can be connected to the third conductive section, and at least one section of the third conductive section can overlap the first gate electrode. In accordance with one or more embodiments of the present disclosure, the active layer may comprise an oxide semiconductor material. In accordance with one or more embodiments of the present disclosure, the display device may further comprise an intermediate insulating layer arranged on the first gate electrode and the second gate electrode. In accordance with one or more embodiments of the present disclosure, the intermediate insulating layer can be inserted in an intermediate space in which the first gate electrode and the second gate electrode may be arranged at a distance from each other, and in an intermediate space in which the first gate insulating layer and the second gate insulating layer may be arranged at a distance from each other, such that it touches an upper surface of the second conductive section. In accordance with one or more embodiments of the present disclosure, the intermediate insulating layer may contain hydrogen, and the first conductive section, the second conductive section and the third conductive section may contain hydrogen. In accordance with one or more embodiments of the present disclosure, the display device can be configured to apply the same gate voltage to the first gate electrode and the second gate electrode. In accordance with one or more embodiments of the present disclosure, the display device can be configured to apply a gate voltage to the first gate electrode and to apply a ground voltage to the second gate electrode. In accordance with one or more embodiments of the present disclosure, the display device can be configured to apply a gate voltage to the first gate electrode and to make the second gate electrode electrically potential-free. In accordance with one or more embodiments of the present disclosure, the display device may further comprise a buffer layer between the substrate and the active layer and a metal structure arranged between the substrate and the buffer layer, overlapping the first channel section and the second channel section. In accordance with one or more embodiments of the present disclosure, the metal structure can be configured to have one of a state in which it is electrically connected to the source electrode, a state in which a gate voltage can be applied to the first gate electrode, a state in which a ground voltage can be applied, and an electrically potential-free state. In accordance with one or more embodiments of the present disclosure, the display device may further comprise a buffer layer between the substrate and the active layer, a first metal structure arranged between the substrate and the buffer layer and overlapping the first channel section, and a second metal structure arranged between the substrate and the buffer layer at a distance from the first metal structure and overlapping the second channel section. In accordance with one or more embodiments of the present disclosure, each of the first metal structure and the second metal structure can be configured to have one of a state in which it is electrically connected to the source electrode, a state in which a gate voltage applied to the first gate electrode can be applied, a state in which a ground voltage can be applied, and an electrically potential-free state. In accordance with one or more embodiments of the present disclosure, the display device may further comprise a gate line arranged on the substrate and supplying a gate signal to a subpixel, and a gate-in-panel circuit arranged on the substrate and configured to output the gate signal to the gate line. The transistor may be included in the gate-in-panel circuit. In accordance with one or more embodiments of the present disclosure, the gate-in-panel circuit may comprise a gate output buffer configured to output the gate signal and comprising a pull-up transistor and a pull-down transistor, a carry output buffer configured to output a carry signal and comprising a carry-pull-up transistor and a carry-pull-down transistor, and a control circuit that controls a voltage state of a Q node corresponding to a gate node of the pull-up transistor and a gate node of the carry-pull-up transistor, and a voltage state of a QB node corresponding to a gate node of the pull-down transistor and a gate node of the carry-pull-down transistor. In accordance with one or more embodiments of the present disclosure, the control circuit can include a control transistor having a drain node to which a high potential voltage can be applied, and wherein at least one of the pull-up transistor, the carry-pull-up transistor and the control transistor corresponds to the transistor of the display device according to embodiments of the disclosure. In accordance with one or more embodiments of the present disclosure, the display device may further comprise a third gate-insulating layer arranged on the active layer and positioned at a distance from the first gate-insulating layer in the second direction, and a third gate electrode arranged on the third gate-insulating layer and positioned at a distance from the first gate electrode. In accordance with one or more embodiments of the present disclosure, the active layer may have a third channel section positioned in the second direction from the third conductive section and overlapping at least one section of the third gate electrode, and a fourth conductive section positioned in the second direction from the third channel section. In accordance with one or more embodiments of the present disclosure, the display device may further comprise an intermediate insulating layer arranged on the first gate electrode and the third gate electrode. In accordance with one or more embodiments of the present disclosure, the intermediate insulating layer can be inserted in an intermediate space in which the first gate electrode and the third gate electrode can be arranged at a distance from each other, and in an intermediate space in which the first gate insulating layer and the third gate insulating layer can be arranged at a distance from each other, such that it touches an upper surface of the third conductive section. In accordance with one or more embodiments of the present disclosure, at least one section of the first conductive section can overlap the second gate electrode, the second conductive section can not overlap the first gate electrode and the second gate electrode, the third conductive section can not overlap the first gate electrode and the third gate electrode, and at least one section of the fourth conductive section can overlap the third gate electrode. In accordance with one or more embodiments of the present disclosure, the drain electrode can be connected to the first conductive section, and the source electrode can be connected to the fourth conductive section. In accordance with one or more embodiments of the present disclosure, when a gate voltage is applied to the first gate electrode, each of the second gate electrode and the third gate electrode can be configured to have one of a state in which the gate voltage can be applied, a state in which a ground voltage can be applied, and an electrically potential-free state. In accordance with one or more embodiments of the present disclosure, the display device may further comprise a buffer layer between the substrate and the active layer and a metal structure between the substrate and the buffer layer. In accordance with one or more embodiments of the present disclosure, the metal structure can be configured to have one of a state in which it is electrically connected to the source electrode, a state in which a gate voltage can be applied to the first gate electrode, a state in which a ground voltage can be applied, and an electrically potential-free state. In accordance with one or more embodiments of the present disclosure, the display device may further comprise a buffer layer between the substrate and the active layer, a first metal structure arranged between the substrate and the buffer layer and overlapping the first channel section, a second metal structure arranged between the substrate and the buffer layer at a distance from the first metal structure and overlapping the second channel section, and a third metal structure arranged between the substrate and the buffer layer at a distance from the first metal structure and overlapping the third channel section. In accordance with one or more embodiments of the present disclosure, each of the first metal structure, the second metal structure and the third metal structure can be configured to have one of a state in which it is electrically connected to the source electrode, a state in which a gate voltage applied to the first gate electrode can be applied, a state in which a ground voltage can be applied and an electrically potential-free state. In accordance with one or more embodiments of the present disclosure, a distance at which the second gate electrode is arranged at a distance from the first gate electrode may be greater than or equal to any distance at which the second gate insulating layer is arranged at a distance from the first gate insulating layer and a width of an upper surface of the second conductive section. In accordance with one or more embodiments of the present disclosure, the transistor can be formed by connecting a first transistor, a second transistor and a third transistor in series, and the resistance of the first channel section can be increased by arranging the second transistor and the third transistor, acting as a type of resistor, at two opposite ends of the first transistor.

Claims

A display device (100) comprising: a substrate (111); and a transistor (TR) arranged on the substrate (111), the transistor (TR) comprising: an active layer (ACT) on the substrate (111); a first gate-insulating layer (631) arranged on the active layer (ACT); a second gate-insulating layer (632) arranged on the active layer (ACT) and positioned at a distance from the first gate-insulating layer (631) in a first direction; a first gate electrode (G1) arranged on the first gate-insulating layer (631); a second gate electrode (G2) arranged on the second gate-insulating layer (632) and positioned at a distance from the first gate electrode (G1); and a drain electrode (D) connected to a section of the active layer (ACT).and a source electrode (S) connected to another section of the active layer (ACT), the active layer (ACT) comprising: a first channel section (CH1) overlapping at least one section of the first gate electrode (G1); a second channel section (CH2) overlapping at least one section of the second gate electrode (G2); a first conductive section (621) positioned in the first direction from the second channel section (CH2); a second conductive section (622) positioned between the first channel section (CH1) and the second channel section (CH2); and a third conductive section (623) positioned in a second direction opposite to the first direction from the first channel section (CH1). The display device (100) according to claim 1, wherein at least one section of the first conductive section (621) overlaps the second gate electrode (G2), and wherein the second conductive section (622) does not overlap the first gate electrode (G1) and the second gate electrode (G2). The display device (100) according to claim 1 or 2, wherein the drain electrode (D) is connected to the first conductive section (621), wherein the source electrode (S) is connected to the third conductive section (623), and wherein at least one section of the third conductive section (623) overlaps the first gate electrode (G1). The display device (100) according to one of claims 1 to 3, wherein the active layer (ACT) comprises an oxide semiconductor material. The display device (100) according to one of claims 1 to 4, further comprising an intermediate insulating layer (640) arranged on the first gate electrode (G1) and the second gate electrode (G2), wherein the intermediate insulating layer (640) is inserted in an intermediate space in which the first gate electrode (G1) and the second gate electrode (G2) are arranged at a distance from each other, and an intermediate space in which the first gate insulating layer (631) and the second gate insulating layer (632) are arranged at a distance from each other, such that it contacts an upper surface of the second conductive section (622). The display device (100) according to claim 5, wherein the intermediate insulating layer (640) comprises hydrogen, and wherein the first conductive section (621), the second conductive section (622) and the third conductive section (623) comprise hydrogen. The display device (100) according to one of claims 1 to 6, wherein the display device is configured to apply the same gate voltage (Vg) to the first gate electrode (G1) and the second gate electrode (G2). The display device (100) according to one of claims 1 to 7, wherein the display device is configured to apply a gate voltage (Vg) to the first gate electrode (G1) and to apply a ground voltage (GND) to the second gate electrode (G2). The display device (100) according to one of claims 1 to 8, wherein the display device is configured to apply a gate voltage (Vg) to the first gate electrode (G1) and to make the second gate electrode (G2) electrically potential-free. The display device (100) according to any one of claims 1 to 9, further comprising: a buffer layer (610) between the substrate (111) and the active layer (ACT); and a metal structure (LS) arranged between the substrate (111) and the buffer layer (610) and overlapping the first channel section (CH1) and the second channel section (CH2), wherein the metal structure (LS) is configured to have one of the following: a state of being electrically connected to the source electrode (S); a state in which a gate voltage (Vg) applied to the first gate electrode (G1) is applied; a state in which a ground voltage (GND) is applied; and an electrically potential-free state. The display device (100) according to any one of claims 1 to 9, further comprising: a buffer layer (610) between the substrate (111) and the active layer (ACT); a first metal structure (LS1) arranged between the substrate (111) and the buffer layer (610) and overlapping the first channel section (CH1); and a second metal structure (LS2) arranged between the substrate (111) and the buffer layer (610), spaced apart from the first metal structure (LS1) and overlapping the second channel section (CH2), each of the first metal structure (LS1) and the second metal structure (LS2) being configured to have one of the following: a state of being electrically connected to the source electrode (S); a state in which a gate voltage (Vg) applied to the first gate electrode (G1) is applied; a state in which a ground voltage (GND) is applied; and an electrically potential-free state. The display device (100) according to one of claims 1 to 11, further comprising: a gate line (GL) arranged on the substrate (111) and supplying a gate signal to a subpixel (SP); and a gate-in-panel circuit (GIPC) arranged on the substrate (111) and configured to output the gate signal to the gate line (GL), wherein the transistor (TR) is included in the gate-in-panel circuit (GIPC). The display device (100) according to claim 12, wherein the gate-in-panel circuit (GIPC) comprises: a gate output buffer (410) configured to output the gate signal and comprising a pull-up transistor (Tu) and a pull-down transistor (Td); a carry output buffer (420) configured to output a carry signal and comprising a carry pull-up transistor (Tuc) and a carry pull-down transistor (Tdc);and a control circuit (430) that controls a voltage state of a Q node corresponding to a gate node of the pull-up transistor (Tu) and a gate node of the carry-pull-up transistor (Tuc), and a voltage state of a QB node corresponding to a gate node of the pull-down transistor (Td) and a gate node of the carry-pull-down transistor (Tdc), wherein the control circuit (430) includes a control transistor (Tc) having a drain node to which a high-potential voltage is applied, and wherein at least one of the pull-up transistor (Tu), the carry-pull-up transistor (Tuc), and the control transistor (Tc) corresponds to the transistor (TR) contained in the gate-in-panel (GIPC) circuit. The display device (100) according to claim 1, further comprising: a third gate-insulating layer (833) arranged on the active layer (ACT) and positioned at a distance in the second direction from the first gate-insulating layer (631); and a third gate electrode (G3) arranged on the third gate-insulating layer (833) and positioned at a distance from the first gate electrode (G1), wherein the active layer (ACT) comprises: a third channel section (CH3) positioned in the second direction from the third conductive section (623) and overlapping at least one section of the third gate electrode (G3); and a fourth conductive section (824) positioned in the second direction from the third channel section (CH3). The display device (100) according to claim 14, further comprising an intermediate insulating layer (640) arranged on the first gate electrode (G1) and the third gate electrode (G3), wherein the intermediate insulating layer (640) is inserted in an intermediate space in which the first gate electrode (G1) and the third gate electrode (G3) are arranged at a distance from each other, and an intermediate space in which the first gate insulating layer (631) and the third gate insulating layer (833) are arranged at a distance from each other, such that it contacts an upper surface of the third conductive section (623). The display device (100) according to claim 14 or 15, wherein at least one section of the first conductive section (621) overlaps the second gate electrode (G2), wherein the second conductive section (622) does not overlap the first gate electrode (G1) and the second gate electrode (G2), wherein the third conductive section (623) does not overlap the first gate electrode (G1) and the third gate electrode (G3), wherein at least one section of the fourth conductive section (824) overlaps the third gate electrode (G3), wherein the drain electrode (D) is connected to the first conductive section (621), and wherein the source electrode (S) is connected to the fourth conductive section (824). The display device (100) according to one of claims 14 to 16, wherein, when a gate voltage (Vg) is applied to the first gate electrode (G1), each of the second gate electrode (G2) and the third gate electrode (G3) is configured to have one of the following: a state in which the gate voltage (Vg) is applied; a state in which a ground voltage (GND) is applied; and an electrically potential-free state. The display device (100) according to any one of claims 14 to 17, further comprising: a buffer layer (610) between the substrate (111) and the active layer (ACT); and a metal structure (LS) between the substrate (111) and the buffer layer (610), wherein the metal structure (LS) is configured to have one of the following: a state of being electrically connected to the source electrode (S); a state in which a gate voltage (Vg) applied to the first gate electrode (G1) is applied; a state in which a ground voltage (GND) is applied; and an electrically potential-free state. The display device (100) according to one of claims 14 to 17, further comprising: a buffer layer (610) between the substrate (111) and the active layer (ACT); a first metal structure (LS1) arranged between the substrate (111) and the buffer layer (610) and overlapping the first channel section (CH1); a second metal structure (LS2) arranged between the substrate (111) and the buffer layer (610), at a distance from the first metal structure (LS1) and overlapping the second channel section (CH2);and a third metal structure (LS3) arranged between the substrate (111) and the buffer layer (610), at a distance from the first metal structure (LS1) and overlapping the third channel section (CH3), each of the first metal structure (LS1), the second metal structure (LS2) and the third metal structure (LS3) being configured to have one of the following: a state of being electrically connected to the source electrode (S); a state in which a gate voltage (Vg) applied to the first gate electrode (G1) is applied; a state in which a ground voltage (GND) is applied; and an electrically potential-free state. The display device (100) according to any one of claims 1 to 19, wherein a distance at which the second gate electrode (G2) is arranged at a distance from the first gate electrode (G1) is greater than or equal to any distance at which the second gate insulating layer (632) is arranged at a distance from the first gate insulating layer (631), and a length of an upper surface of the second conductive section (622).

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