DISPLAY DEVICE

Abstract

A display device comprises a substrate containing a display area and a non-display area, wherein the display area includes a first display area and a second display area, the first display area containing a first pixel region and the second display area containing a second pixel region comprising a first emission area and a transparent area; a first light-emitting diode in the first pixel region comprising a first cathode; a second light-emitting diode in the first emission area comprising a second cathode; a cathode separation pattern between the first and second pixel regions; a deposition prevention pattern in the transparent area; and a first and a second low-potential voltage line in the non-display area, wherein the first and second cathodes are separated by the cathode separation pattern and the first and second cathodes are connected to the first and second low-potential voltage lines, respectively.

Description

The application claims priority over Korean patent application No. 10-2024-0195956, filed in the Republic of Korea on December 24, 2024. TECHNICAL AREA The disclosure relates to a display device and, in particular, to a display device that can provide high luminance in a detection pixel area. BACKGROUND As large-area display devices are developed, the demand for flat, space-saving display devices is increasing. Liquid crystal display devices, organic light-emitting displays (OLEDs), and inorganic light-emitting displays (ILEDs) are rapidly being developed as types of flat display devices. For example, in an organic light-emitting display (OLED), holes from an anode and electrons from a cathode are combined to generate an exciton in an organic light-emitting layer, and the exciton is converted from an excited state to a ground state. As a result, light is emitted from the OLED. SUMMARY The disclosure relates to a display device which substantially avoids one or more of the problems associated with the limitations and disadvantages of the conventional related technique. One task is to provide a display device that can prevent the reduction in luminance in a detection pixel area that contains an emission area and a transmittance area. Additional features and advantages of the disclosure are set forth in the following description and will be apparent from the description or through practical application of the present disclosure. The functions and further advantages of the disclosure are realized and achieved through the features described here and in the accompanying drawings. The problem is solved by the features of the independent claims; preferred embodiments are specified in the dependent claims. To achieve these and further advantages in accordance with the purpose of the embodiments of the disclosure described herein, one aspect of the disclosure is a display device comprising a substrate containing a display area and a non-display area outside the display area, wherein the display area comprises a first display area and a second display area, the first display area comprising a first pixel region and the second display area comprising a second pixel region comprising a first emission area and a transmittable area; a first light-emitting diode in the first pixel region;comprising a second light-emitting diode in the first emission area and a first and a second low-potential voltage line in the non-display area, wherein a cathode of the first light-emitting diode is connected to the first low-potential voltage line and a cathode of the second light-emitting diode is connected to the second low-potential voltage line in order to control the luminance of the first light-emitting diode in the first pixel area and of the second light-emitting diode independently. In a further aspect, a display device is provided comprising a substrate containing a display area and a non-display area outside the display area, wherein the display area includes a first display area and a second display area, the first display area containing a first pixel region and the second display area containing a second pixel region comprising a first emission area and a transparent area; a first light-emitting diode in the first pixel region comprising a first anode, a first light-emitting layer and a first cathode; a second light-emitting diode in the first emission area comprising a second anode, a second light-emitting layer and a second cathode; a cathode separation pattern between the first pixel region and the second pixel region; and a deposition prevention pattern in the transparent area.comprising a first low-voltage line in the non-display area and a second low-potential voltage line in the non-display area. Preferably, the first cathode and the second cathode can be separated by the cathode separation pattern. Preferably, the first cathode can be connected to the first low-potential voltage line. Preferably, the second cathode can be connected to the second low-potential voltage line. The following optional feature can be added to the general aspect mentioned above, either alone, in combination, or as a sub-combination. In one or more embodiments, the deposition prevention pattern can extend from the cathode separation pattern. In one or more embodiments, the cathode separation pattern can be located over a space between the first and second display areas. In one or more embodiments, the first cathode in one of the first pixel areas and the first cathode in another of the first pixel areas can be connected to each other. In one or more embodiments, the second cathode in one of the second pixel areas and the second cathode in another of the second pixel areas can be connected to each other. In one or more embodiments, the second cathode may include a cathode extension section that extends into the non-display area to be connected to the second low-potential voltage line. In one or more embodiments, the cathode separation pattern can surround the second cathode and the cathode extension section. In one or more embodiments, the cathode extension section in one of the second pixel area is connected to the cathode extension section in the further part of the second pixel area. In one or more embodiments, the first low-potential voltage line can include a first line on one side of the second low-potential voltage line and a second line on the far side of the second low-potential voltage line. In one or more embodiments, the display device may further comprise a first bank between the first line and the second low-potential voltage line and a second bank between the second line and the second low-potential voltage line. In one or more embodiments, the cathode separation pattern can be arranged on the first and second banks. In one or more embodiments, the cathode separation pattern can surround the second pixel area. In one or more embodiments, the second cathode can be connected to the second low-potential voltage line in the second pixel area. In one or more embodiments, the first pixel area can contain a second emission area. In one or more embodiments, the area of ​​the second emission surface can be larger than the area of ​​the first emission surface. In one or more embodiments, an area of ​​the second emission surface can be equal to a summation of an area of ​​the first emission surface and an area of ​​the permeable surface. In one or more embodiments, an area of ​​the first cathode can be larger than an area of ​​the second cathode. In one or more embodiments, the first and second low-potential voltage lines can be arranged on the same layer. In one or more embodiments, a first voltage can be applied to the first low-potential voltage line. In one or more embodiments, a second voltage can be applied to the second low-potential voltage line. In one or more embodiments, the second voltage can be lower than the first voltage. In one or more embodiments, the display device may include a sensor arranged in the permeable area. In one or more embodiments, the cathode separation pattern and the deposition prevention pattern can be formed from the same material. In one or more embodiments, a side face of the cathode separation pattern can touch a side face of the first cathode and a side face of the second cathode. In one or more embodiments, a side surface of the deposition prevention pattern can touch a side surface of the first cathode and a side surface of the second cathode. In one or more embodiments, the luminance of the first light-emitting diode and the luminance of the second light-emitting diode can be uniform. In one or more embodiments, the second cathode need not be located in the permeable area. In one or more embodiments, the second display area may also contain a third pixel area. In one or more embodiments, a third light-emitting diode can be arranged in the third pixel area. In one or more embodiments, a cathode of the third light-emitting diode can be connected to a first low-potential voltage line. In one or more embodiments, the cathode separation pattern may include a first pattern surrounding three sides of the second cathode and having an open section corresponding to the cathode extension section, and a second and a third pattern each extending from the first pattern along both sides of the cathode extension section. In one or more embodiments, the display device may further comprise a bank containing a first and a third contact hole exposing the first and second conductors respectively, and a second contact hole exposing the second low-potential voltage conductor. In one or more embodiments, the bank can be formed on a planarization layer. In one or more embodiments, a section of the bank and the planarization layer can be arranged in the third contact hole. In one or more embodiments, the cathode separation pattern can completely surround every second pixel area. In one or more embodiments, the second low-potential voltage line can extend into the second pixel area. It should be understood that both the preceding general description and the following detailed description are exemplary and explanatory and are intended to further explain the present invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a better understanding of the disclosure and are incorporated into the application text as a part thereof, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. Fig. 1 is a schematic top view of a display device according to a first embodiment of the disclosure. Fig. 2 is a schematic circuit diagram of a pixel area of ​​a display device according to an embodiment of the disclosure. Fig. 3 is a schematic cross-sectional view of a pixel area of ​​a display device according to the first embodiment of the disclosure. Fig. 4 is a schematic cross-sectional view of an emission pixel area and a detection pixel area of ​​a display device according to the first embodiment of the present disclosure.Figure 5 is a schematic cross-sectional view illustrating a connection between an emission pixel area and a first low-potential voltage line and a connection between a detection pixel area and a second low-potential voltage line in a display device according to the first embodiment of the disclosure. Figure 6 is a schematic cross-sectional view illustrating an emission pixel area and a connection between the emission pixel area and a first low-potential voltage line in a display device according to the first embodiment of the present disclosure. Figure 7 is a schematic top view of a display device according to a second embodiment of the present disclosure.Figure 8 is a schematic cross-sectional view illustrating a connection between an emission pixel area and a first low-potential voltage line, and a connection between a detection pixel area and a second low-potential voltage line in a display device according to the second embodiment of the present disclosure. Figure 9 is a schematic top view of a display device according to a third embodiment of the present disclosure. Figure 10 is a schematic cross-sectional view illustrating a detection pixel area and a connection between the detection pixel area and a second low-potential voltage line in a display device according to the third embodiment of the present disclosure. DETAILED DESCRIPTION Reference is now made to specific aspects of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, if it is determined that a detailed description of known functions or configurations relating to this document would unnecessarily obscure a key aspect of the inventive concept, their detailed description will be omitted. The sequence of processing steps and / or operations described is an example; however, the sequence of steps and / or operations is not limited to that presented here and, with the exception of steps and / or operations that necessarily occur in a specific order, may be modified as is known in the prior art. Similar reference numerals denote similar elements throughout.The names of the respective elements used in the following explanations are chosen solely to simplify the writing of the application text and may therefore differ from those used in actual products. The advantages and features of the present disclosure and methods for achieving them will become clear with reference to the aspects described in detail below and the accompanying drawings. However, the present disclosure is not limited to the aspects disclosed below, but can be implemented in a variety of different forms, and only these aspects make the disclosure of the present invention complete. The present disclosure is provided to fully inform a person skilled in the field of the present disclosure about its scope. The shapes, sizes, proportions, angles, numbers, and the like disclosed in the drawings to illustrate aspects of the present disclosure are for illustrative purposes only, and the present disclosure is not limited to the illustrated content. The same reference numerals refer to the same elements throughout the description. Furthermore, when describing the present disclosure, if it is determined that a precise description of the related known technology would unnecessarily obscure the subject matter of the present disclosure, its precise description may be omitted. When terms such as 'contain,' 'exhibit,' 'consist of,' and the like are used in this application, additional parts may be added unless 'merely' is used. When a component is expressed in the singular, cases containing the plural are included unless a specific statement is being described. The expression “at least one of a, b and c”, which is described in the application text, can include ‘a alone’, ‘b alone’, ‘c alone’, ‘a and b’, ‘a and c’, ‘b and c’, or ‘all of a, b and c’. The advantages and features of the present invention and the methods for achieving them will become apparent with reference to the embodiments described in detail below, in conjunction with the accompanying drawings. When designing an element, the element is designed as if it contains a fault area or a tolerance area, even though there is no explicit description of such a fault area or tolerance area. When describing a positional relationship, for example, if a positional relationship between two parts is described as "on", "above", "under" and "next to", one or more other parts may be positioned between the two parts, unless a more restrictive term such as "exactly" or "directly" is used. When describing a temporal relationship, for example, if the temporal sequence is described as "after", "subsequently", "next" and "before", there may be a case that is not continuous, unless a more restrictive term such as "exactly", "immediately" or "directly" is used. The area, length or thickness of each component described in the application text is illustrated for the sake of simplicity, and the present invention is not necessarily limited to the area, length and thickness of the illustrated component. It will be understood that, although the terms "first," "second," etc., may be used here to describe different elements, the elements are not meant to be limited by these terms. These terms are used merely to distinguish one element from another. For example, a first element could be called a second element, and correspondingly a second element could be called a first element, without deviating from the scope of the present revelation. Features of various aspects of this disclosure can be partially or completely coupled or combined and can interact and be technically controlled in different ways, as those skilled in the art can reasonably understand. The aspects of this disclosure can be implemented independently of one another or can be implemented together in a mutually dependent relationship. Without a specific description, a transistor forming the pixel circuit of the present disclosure may include at least one oxide thin-film transistor (oxide TFT), one amorphous silicon TFT (a-Si TFT) and one low-temperature polysilicon TFT (LTPS TFT). The following embodiments are described with reference to organic light-emitting display devices. However, the embodiment of the present disclosure is not limited to organic light-emitting display devices. For example, a display device according to one embodiment of the present disclosure may be an organic light-emitting display device using an organic light-emitting material or an inorganic light-emitting display device using an inorganic light-emitting material such as a quantum dot. In particular, the display device of the present disclosure may be an organic light-emitting display device or an inorganic light-emitting display device. Now, specific reference will be made to some of the examples and preferred embodiments illustrated in the accompanying drawings. Fig. 1 is a schematic top view of a display device according to a first embodiment of the present disclosure. Referring to Fig. 1, the display device according to the first embodiment of the present disclosure comprises a substrate 102 and several pixel areas P1, P2 and P3 arranged on the substrate 102. A display area DA, containing a first display area DA1 and a second display area DA2 outside the first display area DA1, and a non-display area NDA outside the display area DA are defined on substrate 102. The first pixel area P1 is arranged in the first display area DA. A first light-emitting diode D1 (from Fig. 2) is arranged in the first pixel area P1. Several first pixel areas P1 are arranged in the first display area DA1, and these multiple first pixel areas P1 can contain red, green, and blue pixel areas. A second pixel area P2 is arranged in the second display area DA2. A second LED D2 (from Fig. 2) is arranged in the second pixel area P2. The second pixel area P2 can be a red, a green, or a blue pixel area. Several second pixel areas P2 are arranged in the second display area DA2, and the multiple second pixel areas P1 can contain red, green, and blue pixel areas. The second pixel area P2 contains an emission surface EA and a transparent surface TA on one side of the emission surface EA, while the first pixel area P1 contains an emission surface without a transparent surface. For example, an area (e.g., a planar surface) of the emission surface of the first pixel area P1 can be essentially equal to the sum of an area of ​​the emission surface of the second pixel area P2 and an area of ​​the transparent surface of the second pixel area P2. A cathode separation pattern 182 is arranged between the first and second display areas DA1 and DA2. The cathode separation pattern 182 can extend from one side of the display device to the opposite side of the display device, e.g., from a non-display area NDA on the left side to the non-display area NDA on the right side, thereby completely separating the first display area from the second display area. A first cathode of the first LED D1 in the first display area DA1 and a second cathode of the second LED D2 in the second display area DA2 are separated by the cathode separation pattern 182. Specifically, the cathodes in the several first pixel areas P1 in the first display area DA1 are connected to each other, and the cathodes in the several second pixel areas P2 in the second display area DA2 are connected to each other. Thus, the cathode separation pattern 182 is located at the level of the first and second cathodes 158c and 160c. The cathode separation pattern 182 is arranged directly on bank 156. Therefore, the first cathode of the first pixel area P1 and the second cathode in the second pixel area P2 are separated by the cathode separation pattern 182. In the second pixel area P2, the second light-emitting diode D2 is arranged in the emission area EA, and a deposition prevention pattern 184 is arranged in the transmitting area TA. Specifically, in the second pixel area P2, the second cathode is arranged in the emission area EA, and the deposition prevention pattern 184 is arranged in the transmitting area TA without the second cathode. The cathode separation pattern 182 can run in one direction and the deposition prevention pattern 184 can run (or protrude) from the cathode separation pattern 182 to the second pixel area P2. Accordingly, the area of ​​the first light-emitting diode D1 in the first pixel area P1 can be larger than the area of ​​the second light-emitting diode D2 in the second pixel area P2. The first pixel area P1 can be an image-generating pixel area, and the second pixel area P2 can be a detection-generating pixel area. For example, the first pixel area P1 can be called an emission pixel area, and the second pixel area P2 can be called a detection pixel area. A sensor can be arranged in the transparent area TA. Furthermore, a third pixel area P3 can be arranged in the second display area DA2. A third light-emitting diode D3 (from Fig. 2) is arranged in the third pixel area P3. The third pixel area P3 can be the emission pixel area or the detection pixel area. Multiple third pixel areas P3 can be arranged within the second display area DA2, and these multiple third pixel areas P3 can include red, green, and blue pixel areas. For clarity, the display device is illustrated with the third pixel area P3 being the emission pixel area. Several (first) emission pixel areas (P1) are arranged in the first display area DA1 and several detection pixel areas (P2) or several detection pixel areas and several emission pixel areas are arranged in the second display area DA2. Fig. 2 is a schematic circuit diagram of a pixel area of ​​a display device according to an embodiment of the present disclosure. As shown in Fig. 2, the display device contains the first pixel area P1 in the first display area DA1 (from Fig. 1) and the second and third pixel areas P2 and P3 in the second display area DA2 (from Fig. 1). The first pixel area P1 is the emission pixel area, and the second pixel area P2 is the detection pixel area. The third pixel area P3 is either the emission pixel area or the detection pixel area. In Fig. 3, the third pixel area P3 is the emission pixel area. Specifically, the emission pixel area and the detection pixel area are arranged in the second display area DA2. The display device includes a gate line GL and a data line DL that intersect to define the first, second, and third pixel areas P1, P2, and P3. The first and third pixel areas P1 and P3 contain the emission area EA, and the second pixel area P2 contains the emission area EA and the transmit area TA. In the emission area EA of each of the first to third pixel areas P1, P2, and P3, a first thin-film transistor (TFT) T1, a second TFT T2, and a storage capacitor Cst are arranged. Additionally, the first, second, and third light-emitting diodes D1, D2, and D3 are arranged in the first, second, and third pixel areas P1, P2, and P3, respectively. The gate line GL extends in a first direction, and the data line DL extends in a second direction, perpendicular to the first direction. In Fig. 2, the first to third pixel areas P1, P2, and P3 share the gate line GL. In one embodiment of the present disclosure, the first to third pixel areas P1, P2, and P3 can be connected to different gate lines GL. In the first TFT T1, a gate electrode is connected to the gate line and a source electrode is connected to the data line DL. In the second TFT T2, a gate electrode is connected to a drain electrode of the first TFT T1 and a source electrode is connected to a high-potential voltage VDD. In each of the first to third LEDs D1, D2, and D3, an anode is connected to a drain electrode of the second TFT T2. A cathode of each of the first and third LEDs D1 and D3 is connected to a first low-potential line 192 (from Fig. 5) to receive a first low-potential voltage, and a cathode of the second LED D2 is connected to a second low-potential line 194 (from Fig. 5) to receive a second low-potential voltage. The storage capacitor Cst is connected to the gate electrode and the drain electrode of the second TFT T2. In the display device of the present disclosure, the first TFT T1 can be a switching TFT and the second TFT T2 can be a driving TFT. In the display device, when the first TFT T1 is switched on by a gate signal applied via the gate line GL, a data signal from the data line DL is applied to the gate electrode of the second TFT T2 and to an electrode of the storage capacitor Cst via the first TFT T1. When the second TFT T2 is switched on by the data signal, an electric current at a high potential voltage is supplied to each of the first, second, and third LEDs D1, D2, and D3. As a result, the first, second, and third LEDs D1, D2, and D3 emit light. Accordingly, the current to the first, second, and third LEDs D1, D2, and D3 is controlled such that an image can be displayed. Each of the first, second, and third LEDs D1, D2, and D3 emits light through the current of the high-potential voltage VDD applied by the second TFT T2. The storage capacitor Cst serves to maintain the voltage of the gate electrode of the driver TFT (the second TFT T2) when the switching TFT (the first TFT T1) is switched off. Accordingly, even when the switching TFT is switched off, a level of electrical current introduced by the power supply line PL into the OLED D is maintained for the next frame. As a result, the display device can show a desired image. Fig. 3 is a schematic cross-sectional view of a pixel area of ​​a display device according to the first embodiment of the present disclosure, and Fig. 4 is a schematic cross-sectional view of an emission pixel area and a detection pixel area of ​​a display device according to the first embodiment of the present disclosure. Fig. 5 is a schematic cross-sectional view illustrating a connection of an emission pixel area and a first low-potential voltage line and a connection of a detection pixel area and a second low-potential voltage line in a display device according to the first embodiment of the present disclosure, and Fig. 6 is a schematic cross-sectional view illustrating an emission pixel area and a connection of the emission pixel area and a first low-potential voltage line in a display device according to the first embodiment of the present disclosure. Fig. 3 is a cross-sectional view taken along line II' in Fig. 1, and Fig. 4 is a cross-sectional view taken along line II-II' in Fig. 1. Fig. 5 is a cross-sectional view taken along line III-III' in Fig. 1, and Fig. 6 is a cross-sectional view taken along line IV-IV' in Fig. 1. Referring to Fig. 3, Fig. 4, Fig. 5 to Fig. 6 with Fig. 1, the display device 100 according to the first embodiment of the present disclosure comprises a substrate 102, which includes the display area DA, which contains the first display area DA1, and the second display area DA2, and the non-display area NDA outside the display area DA, the first light-emitting diode D1 in the first display area DA1, the second light-emitting diode D2 in the second display area DA2, the cathode separation pattern 182, which is arranged between the first and the second display areas DA1 and DA2, the deposition prevention pattern 184, which is arranged in a section of the second display area DA2, and the first and the second low-potential voltage lines 192 and 194 in the non-display area NDA. The first pixel area P1, which contains the second emission surface, is arranged in the first display area DA1, and the second pixel area P2, which contains the first emission surface and the transparent surface TA, is arranged in the second display area DA2. The first light-emitting diode D1 is located in the first pixel area P1 and contains a first anode 158a, a first light-emitting layer 158b, and a first cathode 158c. The second light-emitting diode D2 is located in the first emission area of ​​the second pixel area P2 and contains a second anode 160a, a second light-emitting layer 160b, and a second cathode 160c. Substrate 102 can be a glass substrate or a plastic substrate. For example, substrate 102 can be a polyimide substrate (PI substrate), a polyethersulfone substrate (PES substrate), a polyethylene naphthalate substrate (PEN substrate), a polyethylene terephthalate substrate (PET substrate), and a polycarbonate substrate (PC substrate). In an exemplary embodiment of the present disclosure, the substrate 102 can have a three-layer structure comprising a first polyimide layer, a second polyimide layer, and an intermediate inorganic layer between the first and second polyimide layers. The intermediate inorganic layer can be formed from an inorganic insulating material, e.g., silicon dioxide or silicon nitride. A first light-shielding pattern 104 is arranged on the substrate 102. The light passing through the substrate 104 can be blocked by the first light-shielding pattern 104. For example, the first light-shielding pattern 104 can be made of a metallic material, e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or their alloys, and can have a single-layer or multi-layer structure. A buffer layer formed from an inorganic insulating material, e.g. silicon oxide or silicon nitride, can be arranged between the substrate 102 and the first light-shielding pattern 104. A first buffer layer 106, covering the first light-shielding pattern 104, is arranged over the substrate 102. Moisture and / or oxygen can be blocked by the first buffer layer 106. For example, the first buffer layer 106 can be formed from an inorganic insulating material, such as silicon dioxide or silicon nitride, and can have a single-layer or multi-layer structure. If the first light-shielding pattern 104 is omitted, the first buffer layer 106 can be formed directly on the substrate 102 and contact it. A first semiconductor layer 110, corresponding to the first light-shielding pattern 104, is arranged on the first buffer layer 106. The first semiconductor layer 110 can consist of a polysemiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. If the first light-shielding pattern 104 and the first buffer layer 106 are omitted, the first semiconductor layer 110 can be arranged directly on the substrate 102. In an exemplary embodiment of the present disclosure, the first semiconductor layer 110 can be formed from a polysemiconductor material, e.g., polycrystalline silicon. The first semiconductor layer 110 can include a first channel region 110a, a first source region 110b on one side of the first channel region 110a, and a first drain region 110c on the other side of the first channel region 110a. Impurities can be doped into the first source region and the first drain regions 110b and 110c. A first gate insulating layer 112, covering the first semiconductor layer 110, is arranged above the first buffer layer 106. The first gate insulating layer 112 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A first gate electrode 114, corresponding to the first channel region 110a of the first semiconductor layer 110, is arranged on the first gate insulating layer 112. Additionally, a first capacitor electrode 116, spaced apart from the first gate electrode 114, is arranged on the first gate insulating layer 112. The first gate electrode 114 and the first capacitor electrode 116 can be arranged on the same layer and made of the same material. For example, the first gate electrode 114 and the first capacitor electrode 116 can each be made of a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or their alloys, and can have a single-layer or a multi-layer structure. A first insulating layer 118, covering the first gate electrode 114 and the first capacitor electrode 116, is arranged on the first gate insulating layer 112. The first insulating layer 118 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A second capacitor electrode 130, corresponding to the first capacitor electrode 116, and a second light shielding pattern 132, spaced apart from the second capacitor electrode 130, are arranged on the first insulating intermediate layer 118. The second capacitor electrode 130 and the second light-shielding pattern 132 can be arranged in the same layer and made of the same material. For example, the second capacitor electrode 130 and the second light-shielding pattern 132 can each be made of a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or their alloys, and can have a single-layer or a multi-layer structure. A second insulating layer 134, covering the second capacitor electrode 130 and the second light-shielding pattern 132, is arranged on top of the first insulating layer 118. External moisture and / or external oxygen can be blocked by the second insulating layer 134. For example, the second insulating layer 134 can be made of an inorganic insulating material, such as silicon oxide or silicon nitride, or an organic insulating material, such as photoacrylic or benzocyclobutene (BCB), and can have a single-layer or multi-layer structure. A second semiconductor layer 136, corresponding to the second light-shielding pattern 132, is arranged on the second insulating intermediate layer 134. The second semiconductor layer 136 can contain a polysemiconductor material, an amorphous semiconductor material, or an oxide semiconductor material. In an exemplary embodiment of the present disclosure, the second semiconductor layer 136 can be formed from an oxide semiconductor material, e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), or indium aluminum zinc oxide (IAZO). The second semiconductor layer 136 can include a second channel region 136a, a second source region 136b on one side of the second channel region 136a, and a second drain region 136c on the far side of the second channel region 136a. Impurities can be doped into the second source and drain regions 136b and 136c, respectively. A second gate insulating layer 138, covering the second semiconductor layer 136, is arranged above the second insulating intermediate layer 134. The second gate insulating layer 138 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A second gate electrode 140, corresponding to the second channel region 136a of the second semiconductor layer 136, is arranged on the second gate insulating layer 136. For example, the second gate electrode 140 can be made of a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or their alloys, and can have a single-layer or multi-layer structure. A third insulating layer 142, covering the second gate electrode 140, is arranged on the second gate insulating layer 138. The third insulating layer 142 can be made of an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A first source electrode 144a, a first drain electrode 144b, a second source electrode 146a and a second drain electrode 146b are arranged on the third insulating intermediate layer 142. The first source electrode 144a and the first drain electrode 144b are connected to the first source region 110b and the first drain region 110c, respectively, via contact holes through the third insulating layer 142, the second gate insulating layer 138, the second insulating layer 134, the first insulating layer 118, and the first gate insulating layer 112. The first source electrode 144a is connected to the first capacitor electrode 116 via a contact hole through the third insulating layer 142, the second gate insulating layer 138, the second insulating layer 134, and the first insulating layer 118. The second source electrode 146a and the second drain electrode 146b are connected to the second source region 136b and the second drain region 136c, respectively, via contact holes through the third insulating layer 142 and the second gate insulating layer 138. The second source electrode 146a is connected to the second capacitor electrode 130 via a contact hole through the third insulating layer 142, the second gate insulating layer 138, and the second insulating layer 134. The first source and drain electrodes 144a and 144b and the second source and drain electrodes 146a and 146b can be arranged on the same layer and made of the same material. For example, the first source and drain electrodes 144a and 144b and the second source and drain electrodes 146a and 146b can each be made of a metallic material, e.g., Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or their alloy, and can have a single-layer or multi-layer structure. The first semiconductor layer 110, the first gate electrode 114, the first source electrode 144a, and the first drain electrode 144b form a first TFT T1, and the second semiconductor layer 136, the second gate electrode 140, the second source electrode 146a, and the second drain electrode 146b form a second TFT T2. For example, the first TFT T1 can be a switching TFT, and the second TFT can be a driver TFT. Additionally, the first and second capacitor electrodes 116 and 130 form a storage capacitor. The display device 100 of the present disclosure comprises the first and the second TFT T1 and T2. Each of the first semiconductor layer 110 of the first TFT T1 and the second semiconductor layer 136 of the second TFT T2 can comprise a polysemiconductor material, an amorphous semiconductor material, and an oxide semiconductor material, and at least one of the first semiconductor layer 110 of the first TFT T1 and the second semiconductor layer 136 of the second TFT T2 can comprise the oxide semiconductor material. In an exemplary embodiment of the present disclosure, the first semiconductor layer 110 of the first TFT T1 can be formed from the polysemiconductor material, e.g., polycrystalline silicon, and the second semiconductor layer 136 of the second TFT T2 can be formed from the oxide semiconductor material. In Fig. 3, the first gate electrode 114, the first source electrode 144a, and the first drain electrode 146a are arranged above the first semiconductor layer 110, and the second gate electrode 140, the second source electrode 146a, and the second drain electrode 146b are arranged above the second semiconductor layer 136. Specifically, each of the first and second TFTs T1 and T2 has a coplanar structure. Alternatively, in each of the first and second TFTs T1 and T2, a gate electrode can be arranged below a semiconductor layer, and a source and a drain electrode can be arranged above the semiconductor layer. Specifically, each of the TFTs T1 and T2 can have an inverted staggered structure. A third TFT, which can be a switching TFT, and a fourth TFT, which can be a driver TFT, are arranged in the second pixel area P2. For example, the third TFT can contain a third semiconductor layer, a third gate electrode, a third source electrode, and a third drain electrode, and can have the same structure as the first TFT T1. The fourth TFT can contain a fourth semiconductor layer, a fourth gate electrode, a fourth source electrode, and a fourth drain electrode, and can have the same structure as the second TFT T2. In the third pixel area P3, which is the emission pixel area, the first TFT T1 is arranged as a switching TFT and the second TFT T2 as a driving TFT, just as in the first pixel area P1. A planarization layer 150, covering the first source and drain electrodes 144a and 144b and the second source and drain electrodes 146a and 146b, is arranged on the third insulating intermediate layer 142. The planarization layer 150 can be formed from an organic insulating material, e.g., photoacrylic or BCB. The planarization layer 150 can include a first planarization layer 152 on the first source and drain electrodes 144a and 144b and the second source and drain electrodes 146a and 146b, and a second planarization layer 154 on the first planarization layer 152. A first connecting electrode 148, corresponding to the second source electrode 146a, is arranged on the first planarization layer 152. The first connecting electrode 148 can be connected to the second source electrode 146a through a contact hole in the first planarization layer 152. A second connecting electrode, corresponding to the fourth source electrode, is arranged on the first planarization layer 152. The second connecting electrode can be connected to the fourth source electrode through a contact hole in the first planarization layer 152. Additionally, the first and second low-potential voltage lines 192 and 194 are arranged on the first planarization layer 150a. The first and second low-potential voltage lines 192 and 194 are located in the non-indicating area NDA and are spaced apart from each other. For example, each of the first connecting electrode 148, the second connecting electrode and the first and second low-potential voltage lines 192 and 194 can be made of a metallic material, e.g. Mo, Al, Cr, Au, Ti, Ni, Nd, Cu or their alloy, and can have a single-layer structure or a multi-layer structure. The second planarization layer 154 is arranged on top of the first planarization layer 152 to cover the first connecting electrode 148, the second connecting electrode, and the first and second low-potential voltage lines 192 and 194. The second planarization layer 154 includes a first connecting contact hole exposing the first connecting electrode 148, a second connecting contact hole exposing the second connecting electrode, a first and a third contact hole CH1 and CH3 exposing the first low-potential voltage line 192, and a second contact hole CH2 exposing the second low-potential voltage line 194. In Fig. 1, the first and third contact holes CH1 and CH3, which expose the first low-potential line 192, are spaced apart from each other. In one embodiment of the present disclosure, the first and third contact holes CH1 and CH3 can be integrated as a single body. A first anode 158a and a second anode 160a are arranged on the second planarization layer 154. The first anode 158a corresponds to the first connecting electrode 148 and is connected to the first connecting electrode 148 through the first connecting contact hole in the second planarization layer 154. The second anode 160a corresponds to the second connecting electrode and is connected to the second connecting electrode through the second connecting contact hole in the second planarization layer 154. The first anode 158a is formed separately in each first pixel area P1, and the second anode 160a is formed separately in each second pixel area P2. Each of the first and second anodes 158a and 160a can contain a transparent conductive oxide layer (TCO layer) formed from a conductive material, e.g., a transparent conductive oxide material exhibiting a relatively high work function. Each of the first and second anodes 158a and 160a can further contain a reflective layer. For example, the transparent conductive oxide material may contain at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), tin oxide (SnO2), zinc oxide (ZnO), indium copper oxide (ICO) and aluminum zinc oxide (Al:ZnO, AZO), and the reflective layer may contain at least one of silver (Ag), an alloy of Ag and one of palladium (Pd), Cu, In and Nd and an aluminum palladium copper alloy (APC). In one embodiment of the present disclosure, the first and second anodes 158a and 160a can each have a double-layer structure of Ag / ITO or APC / ITO or a three-layer structure of ITO / Ag / ITO or ITO / APC / ITO. A bank 156 is formed on the second planarization layer 154 at a boundary of the pixel area. The bank 156 covers one edge of each of the first and second anodes 158a and 160a and has an opening to expose one center of each of the first and second anodes 158a and 160a. The bank 156 may also contain an opening corresponding to the transparent area TA of the second pixel area P2. In the first and third pixel areas P1 and P3, the first anode 158a and the third anode are exposed through the opening of bank 156. The second anode 160a in the emission surface EA of the second pixel area P2 is exposed through the opening of bank 156, and the second planarization layer 154 in the transparent surface TA is exposed through the opening of bank 156. The bank 156 can extend into a section of the non-display area (NDA). The bank 156 can be formed from a transparent organic insulating material, e.g., photoacrylic, benzocyclobutene, or polyimide, to be transparent. In one embodiment of the present disclosure, the bank 156 can further contain a light-absorbing particle, e.g., a black particle, to exhibit a light-absorbing property. In the non-display area (NDA), bank 156 is partially removed to expose the first, second, and third contact holes CH1, CH2, and CH3. In other words, bank 156 and the second planarization layer 154, corresponding to the first low-potential line 192, are removed to form the first and third contact holes CH1 and CH3, and bank 156 and the second planarization layer 154, corresponding to the second low-potential line 194, are removed to form the second contact hole CH2. In Fig. 6, a section of bank 156 and the second planarization layer 154 are arranged in the third contact hole CH3, such that the third contact hole CH3 is divided into two parts by the section of bank 156 and the second planarization layer 154. Alternatively, bank 156 and the second planarization layer 154 can be omitted in the third contact hole CH3, such that a single third contact hole CH3 is present. A spacer 159 is arranged on the bench 156. For example, the spacer 159 can contain an organic insulating material, e.g., photoacrylic, benzocyclobutene (BCB), or polyimide, and can have a single-layer or multi-layer structure. The spacer 159 can be omitted. A first light-emitting layer 158b is arranged on the first anode 158a, and a second light-emitting layer 160b is arranged on the second anode 160a. The first light-emitting layer 158b contacts the first anode 158a in the opening of the bench 156, and the second light-emitting layer 160b contacts the second anode 160a in the opening of the bench 156. One end of each of the first and second light-emitting layers 158b and 160b can be arranged on the bench 156. For example, each of the first and second light-emitting layers 158b and 160b can contain an organic layer of emitting material comprising a host and a dopant. Each of the first and second light-emitting layers 158b and 160b can further contain at least one hole injection layer, one hole transport layer, one electron barrier layer, one hole barrier layer, one electron transport layer, and one electron injection layer to exhibit a multilayer structure. In one embodiment of the present disclosure, each of the first and second light-emitting layers 158b and 160b can contain an inorganic layer of emitting material which contains an inorganic emitting material, e.g. a quantum dot. The cathode separation pattern 182, which corresponds to a space between the first and second display areas DA1 and DA2, is arranged on the bank 156 and the deposition prevention pattern 184, which corresponds to the transparent area TA of the second pixel area P2, is arranged on the second planarization layer 154. The cathode separation pattern 182 extends into a section of the non-indicating area NDA to be positioned between the first and second low-potential voltage lines 192 and 194. Each of the cathode separation pattern 182 and the deposition prevention pattern 184 contains a compound represented by formula 1. In formula 1, each of L1 and L2 is chosen independently from the group consisting of a substituted or unsubstituted C6 to C30 arylene group and a substituted or unsubstituted C3 to C30 heteroarylene group, each of m and n is chosen independently 0 or 1, and each of X1 to X6 is chosen independently from hydrogen and halogen. In one embodiment of the present disclosure, a C6 to C30 arylene group can be selected from the group consisting of phenylene, biphenylene, terphenylene, naphthylene, anthracene, pentanenylene, indenylene, indenoindenylene, heptalenylene, biphenylenylene, indacene, phenanthrenylene, benzophenanthrenylene, dibenzophenanthrenylene, azulenylene, pyrenylene, fluoranthenylene, triphenylenylene, chrysenylene, tetraphenylene, tetrasenylene, picenylene, pentaphenylene, pentacene, fluorenylene, indenofluorenylene and spirofluorenylene. In one embodiment of the present disclosure, a C3 to C30 heteroarylene group can be selected from the group consisting of pyrrolylenes, pyridinylenes, pyrimidinylenes, pyrazinylenes, pyridazinylenes, triazinylenes, tetrazinylenes, imidazolylenes, pyrazolylenes, indolylenes, isoindolylenes, indazolylenes, indolizinylenes, pyrrololizinylenes, carbazolylenes, benzocarbazolylenes, dibenzocarbazolylenes, indolocarbazolylenes, indenocarbazolylenes, benzofurocarbazolylenes, benzothienocarbazolylenes, quinolinylenes, isoquinolinylenes, phthalazinylenes, quinoxalinylenes, cinnolinylenes, quinazolinylenes, quinozolinylenes, quinolinylenes, purinylenes, phthalazinylenes, quinoxalinylenes, benzoquinolinylenes, Benzoisoquinolinylene, benzoquinazolinylene, benzoquinoxalinylene, acridinylene, phenanthrolinylene, perimidinylene, phenanthridinylene, pteridinylene, cinnolinylene, naphtharidinylene, furanylene, oxazinylene, oxazolylene, oxadiazolylene, triazolylene, dioxynylene, benzofuranyenel, Dibenzofuranylene, thiopyranylene, xanthenylene, chromanylene, isochromanylene,Thioazinylene, thiophenylene, benzothiophenylene, dibenzothiophenylene, difuropyrazinylene, benzofurodibenzofuranylene, benzothienobenzothiophenylene, benzothienodibenzothiophenylene, benzothienobenzofuranylene and benzothienodibenzofuranylene. In one embodiment of the present disclosure, the substituent of a C6 to C30 aryl group and a C3 to C30 heteroarylene group can be selected from the group consisting of a substituted or unsubstituted C1 to C10 alkyl group, a substituted or unsubstituted C3 to C30 cycloalkyl group, a substituted or unsubstituted C6 to C30 aryl group and a substituted or unsubstituted C3 to C30 heteroarylene group. Halogen can be chosen from F, Cl, Br and I. In one embodiment of the present disclosure, each of m and n can be 0 and each of X1 to X6 can be H or F. In one embodiment of the present disclosure, each of m and n can be 1, each of L1 and L2 can be phenylene or thiophenylene, and each of X1 to X6 can be H or F. For example, each of the cathode separation pattern 182 and the deposition prevention pattern 184 independently contains a compound chosen from formula 2. In Fig. 4, the deposition prevention pattern 184 is arranged on the second planarization layer 154 to correspond to the permeable area TA of the second pixel area P2. In one embodiment of the present disclosure, the second planarization layer 154 in the transparent area TA of the second pixel region P2 can be removed, and the deposition prevention pattern 184 can be arranged on the first planarization layer 152. In another embodiment of the disclosure, the first and second planarization layers 152 and 154 in the transparent area TA of the second pixel region P2 can be removed, and the deposition prevention pattern 184 can be arranged on the third insulating intermediate layer 142. In Fig. 4, the second light-emitting layer 160b is shown in the emission area EA and not in the transparent area TA. In one embodiment, the second light-emitting layer 160b can be shown in both the emission area EA and the transparent area TA. In this embodiment, the deposition prevention pattern 184 can be arranged on the second light-emitting layer 160b in the transparent area TA. The first cathode 158c and the second cathode 160c are formed by depositing a conductor material over the substrate 102, which contains the first and second light-emitting layers 158b and 160b, the cathode separation pattern 182, and the deposition prevention pattern 184. For example, the conductor material can be one of ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti, and their alloys. Each of the first and second cathodes 158c and 160c can have a small thickness to be a transparent or semi-transparent electrode. The first cathode 158c is arranged on the entire surface of the first display area DA1. Specifically, the first cathodes 158c, which are arranged in the several first pixel areas P1 in the first display area DA1, are connected to each other in such a way that the entire surface of the first display area DA1 is covered by the first cathode 158c. Additionally, the first cathode 158c extends into a section of the non-indicating area NDA to contact the first low-potential line 192 through the first and third contact holes CH1 and CH3. The extension section of the first cathode 158c into the non-indicating area NDA can be referred to as a first cathode extension section 158d. The second cathode 160c is located in the second display area DA2. The second cathodes 160c, located in the emission areas EA of the several second pixel areas P2 in the second display area DA2, are interconnected such that the surface of the second display area DA2, except for the transparent area TA, is covered by the second cathode 160c. Specifically, in the second pixel area P2, the second cathode 160c is shown in the emission area EA and is not shown in the transparent area TA. As a result, the deposition prevention pattern 184 is not covered by the second cathode 160c and is exposed. Additionally, the second cathode 160c extends into a section of the non-indicating area NDA to contact the second low-potential line 194 through the second contact hole CH2. The extension section of the second cathode 160c into the non-indicating area NDA can be referred to as a second cathode extension section 160d. The metal layer for forming the first and second cathodes 158c and 160c is patterned by the cathode separation pattern 182 and the deposition prevention pattern 184. A metal material is selectively deposited by the cathode separation pattern 182 and the deposition prevention pattern 184. Specifically, when a metal material is deposited onto an entire surface of the display area DA using an open mask, the metal material is not deposited in an area where the cathode separation pattern 182 and the deposition prevention pattern 184 are shown, and is deposited in an area where the cathode separation pattern 182 and the deposition prevention pattern 184 are not shown. As a result, the first and second cathodes 158c and 160c are formed. In other words, the first cathode 158c in the first display area DA1 and the second cathode 160c in the second display area DA2 are separated by the cathode separation pattern 182, and metal deposition into the transparent area TA of the second pixel area P2 is prevented by the deposition prevention pattern 184. Since the compound (e.g., a material) represented by equation 1 is transparent to the deposition prevention pattern 184, the transmission measure in the transparent area TA can be maintained. Since the first and second cathodes 158c and 160c are patterned with the cathode separation pattern 182, a side face of each of the first and second cathodes 158c and 160c can touch a side face of the cathode separation pattern 182. Additionally, since the first and second cathodes 158c and 160c are patterned with the deposition prevention pattern 184, a side face of each of the first and second cathodes 158c and 160c can touch a side face of the deposition prevention pattern 184. The first anode 158a, the first light-emitting layer 158b and the first cathode 158c form the first light-emitting diode D1 and the second anode 160a, the second light-emitting layer 160b and the second cathode 160c form the second light-emitting diode D2. In the display device 100 of the present disclosure, the light from the first light-emitting layer 158b or the second light-emitting layer 160b passes through the first cathode 158c and the second cathode 160c to display an image. Specifically, the display device 100 is a top-emitting display device. The first cathode 158c in the first display area DA1 and the second cathode 160c in the second display area DA2 are separated by the cathode separation pattern 182. The first cathode 158c is electrically connected to the first low-potential voltage line 192 via the first cathode extension section 158d, and the second cathode 160c is electrically connected to the second low-potential voltage line 194 via the second cathode extension section 160d. In one embodiment of the present disclosure, a first voltage can be applied to the first low-potential voltage line 192, and a second voltage, which is lower than the first voltage, can be applied to the second low-potential voltage line 194. Similarly, the first voltage can be applied to the first cathode 158c through the first cathode extension section 158d, and the second voltage, which is lower than the first voltage, can be applied to the second cathode 160c through the second cathode extension section 160d. As described above, the emission area (excluding the transmitting area) is located in the first pixel area P1, which is the emission pixel area, and the emission area EA and the transmitting area are located in the second pixel area P2, which is the detection pixel area. Therefore, the luminance of the light emitted by the second LED D2 in the second pixel area P2 is lower than the luminance of the light from the first LED D1 in the first pixel area P1. However, in the display device 100, the first cathode 158c in the first display area DA1, which contains the first pixel area P1, and the second cathode 160c in the second display area DA2, which contains the second pixel area P2, are separated by the cathode separation pattern 182, and the first and second cathodes 158c and 160c are connected to the first and second low-potential voltage lines 192 and 194, respectively. The relatively low voltage is applied to the second cathode 160c of the second LED D2 in the second pixel area P2, such that the luminance of the light from the second LED D2 is increased. Accordingly, the luminance of the first LED D1 and the luminance of the second LED D2 can be uniform, or the luminance difference between the first and second LEDs D1 and D2 can be reduced.In short, the voltage applied to the second LED D2 can be controlled independently of the voltage applied to the first LED D1, and thus the luminance of both D1 and D2 can be controlled. Referring to Fig. 1 and Fig. 5, the first and second low-potential voltage lines 192 and 194 are arranged in the non-display area NDA on one side of the display area DA, and the first and second cathode extension sections 158d and 160d extend from the first and second cathodes 158c and 160c in the same direction. In one embodiment of the present disclosure, the first and second low-potential voltage lines 192 and 194 can be arranged in different areas of the non-indicating area NDA, and the first and second cathode extension sections 158d and 160d extend from the first and second cathode 158c and 160c in different directions. For example, the first low-potential voltage line 192 can be located in the non-display area NDA on one side of the display area DA, and the first cathode extension section 158d can extend from the first cathode 158c in a first direction to contact the first low-potential voltage line 192. The second low-potential voltage line 194 can be located in the non-display area NDA on the far side of the display area DA, and the second cathode extension section 160d can extend from the second cathode 160c in a second direction opposite to the first direction to contact the second low-potential voltage line 194. The first and second low-potential voltage lines 192 and 194 are arranged on the same layer, i.e., on the first planarization layer 152, and are formed on the same material. In one embodiment of the present disclosure, the first and second low-potential voltage lines 192 and 194 can be arranged on different layers. For example, one of the first and second low-potential voltage lines 192 and 194 can be arranged on the first planarization layer 152, and the other of the first and second low-potential voltage lines 192 and 194 can be arranged between the substrate 102 and the first planarization layer 152. An encapsulation layer (or thin encapsulation layer) 162 is arranged over the entire surface of the substrate 102, which contains the first cathode 158c, the first cathode extension section 158d, the second cathode 160c, the second cathode extension section 160d, the cathode separation pattern 182, and the deposition prevention pattern 184, to prevent moisture ingress. The encapsulation layer 162 comprises a first inorganic insulating layer 162a, an organic insulating layer 162b, and a second inorganic insulating layer 162c, which are stacked sequentially, but there is no restriction on this arrangement. Each of the first and second inorganic insulating layers 162a and 162c can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride. The organic insulating layer 162b can be formed from an organic insulating material, e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. A bridge pattern 166 is arranged on the encapsulation layer 162. The bridge pattern 166 can correspond to a boundary of each of the first to third pixel areas P1, P2, and P3. For example, the bridge pattern 166 can be formed from ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti, and their alloys, and can have a single-layer or multi-layer structure. A second buffer layer can be arranged between the encapsulation layer 162 and the bridge pattern 166. For example, the second buffer layer can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or multi-layer structure. A fourth insulating layer 168 is arranged over the entire surface of the substrate 102 to cover the bridging pattern 166. The fourth insulating layer 168 can be formed from an inorganic insulating material, e.g., silicon oxide or silicon nitride, and can have a single-layer or a multi-layer structure. A contact electrode 170 is arranged on the fourth insulating layer 168. The contact electrode 170 is connected to the bridge pattern 166 by a contact hole in the fourth insulating layer 168. For example, the contact electrode 170 can be made of ITO, IZO, Al, Ag, Cu, Pb, Mg, Mo, Ti and their alloys, and can have a single-layer or multi-layer structure. A first protective layer 172 is arranged over the entire surface of the substrate 102 to cover the contact electrode 170. The first protective layer 172 can be formed from an organic insulating material, e.g., photoacrylic or benzocyclobutene, or an inorganic insulating material, e.g., silicon dioxide or silicon nitride, and can have a single-layer or a multi-layer structure. A black matrix 174 is arranged on the first protective layer 172. The black matrix 174 is positioned at the boundary of the first to third pixel areas P1, P2 and P3 and contains an opening corresponding to the first to third LEDs D1, D2 and D3 and the transparent area TA of the second pixel area P2. The opening of the black matrix 174 corresponds to the opening of the bank 156. For the wide viewing angle, the size (e.g., a flat surface) of the opening in the black matrix 174 can be larger than that of the opening in the bank 156. Specifically, bank 156 can have a first width, and black matrix 174 can have a second width that is smaller than the first width. The black matrix 174 can be arranged in at least one section of the non-display area NDA. For example, the black matrix 174 can be arranged such that it corresponds to an entire surface of the non-display area NDA. A color filter layer 176, corresponding to the black matrix 174, is arranged on the first protective layer 172. The color filter layer 176 can contain a red color filter corresponding to the red pixel area, a green color filter corresponding to the green pixel area, and a blue color filter corresponding to the blue pixel area. The color filter layer 176 can contain an organic material and a color particle (e.g., a color pigment or a color dye). For example, the organic material can be selected from polymethyl methacrylate, polycarbonate, polyacrylate, polyurethane, epoxy, polyester, and polyimide, but there is no restriction on this. A second protective layer 178 is arranged on the black matrix 174 and the color filter layer 176 and over the entire substrate 102. The second protective layer 178 can be formed from an organic insulating material, e.g., photoacrylic or benzocyclobutene, or an inorganic insulating material, e.g., silicon dioxide or silicon nitride, and can have a single-layer or a multi-layer structure. In the display device 100 according to the first embodiment of the present disclosure, the cathode separation pattern 182 is arranged between the first display area DA1, which contains the first pixel area P1 as an emission pixel area, and the second display area DA2, which contains the second pixel area P2 as a detection pixel area, and the first cathode 158c of the first light-emitting diode D1 in the first pixel area P1 and the second cathode 160c of the second light-emitting diode D2 in the second pixel area P2 are connected to the first and second low-potential voltage lines 192 and 194, respectively. Accordingly, the reduction in luminance in the second pixel area P2, which contains the transmitting area TA and the emission area TA, can be prevented from having an emission area that is smaller than that of the first pixel area P1, so that the display device 100 can provide an image with high luminance. In the display device 100, the first and second cathodes 158c and 160c are selectively deposited (or formed) in desired areas using the cathode separation pattern 182 and the deposition prevention pattern 184, which are formed by the same process and the same material, and the display device 100, which has a detection function and high luminance, can be provided without an additional process. Fig. 7 is a schematic top view of a second embodiment of the disclosure. With reference to Fig. 7 and Fig. 2, the display device of the second embodiment of the disclosure comprises a substrate 102 and several pixel areas P1, P2 and P3 arranged on the substrate 102. A display area DA, containing a first display area DA1 and a second display area DA2 outside the first display area DA1, and a non-display area NDA outside the display area DA are defined on substrate 102. The first pixel area P1 is located in the first display area DA. A first LED D1 is located in the first pixel area P1. A second pixel area P2 is located in the second display area DA2. A second LED D2 is located in the second pixel area P2. The second pixel area P2 can be red, green, or blue. The second pixel area P2 contains an emission surface EA and a transparent surface TA on one side of the emission surface EA, and the first pixel area P1 contains an emission surface without a transparent surface. For example, an area (e.g., a planar surface) of the emission surface of the first pixel area P1 can be essentially equal to the sum of an area of ​​the emission surface of the second pixel area P2 and an area of ​​the transparent surface of the second pixel area P2. The first pixel area P1 can be a pixel area that provides an image, and the second pixel area P2 can be a pixel area that provides a capture function. For example, the first pixel area P1 can be called an emission pixel area, and the second pixel area P2 can be called a capture pixel area. A third pixel area P3 can also be arranged in the second display area DA2. A third LED D3 is arranged in the third pixel area P3. The third pixel area P3 can be the emission pixel area or the detection pixel area. Multiple third pixel areas P3 can be arranged within the second display area DA2, and these multiple third pixel areas P3 can include red, green, and blue pixel areas. For clarity, the display device is illustrated with the third pixel area P3 being the emission pixel area. Several emission pixel areas are arranged in the first display area DA1, and several detection pixel areas or several detection pixel areas and several emission pixel areas are arranged in the second display area DA2. A cathode separation pattern 280 for separating the second cathode 260c of the second LED D2 in the second pixel area P2 from the first cathode 258c of the first LED D1 in the first pixel area P1 and the third cathode of the third LED D3 in the third pixel area P3 is arranged in the second display area DA2. The second cathode 260c includes a second cathode extension section 260d that extends into the non-display area NDA. The cathode separation pattern 280 surrounds the second cathode 260c, which contains the second cathode extension section 260d, to separate the second cathode 260c from the first cathode 258c and the third cathode. The cathode separation pattern 280 can include a first pattern 282 surrounding the second cathode 260c, and a second and a third pattern 286 and 288 extending from the first pattern 282 along both sides of the second cathode extension section 260d. In each of the first to third LEDs D1, D2, and D3, the anode is connected to the drain electrode of the driver TFT T2. The cathode 258c of the first LED D1 and the cathode of the third LED D3 are connected to the first low-potential line 192 (from Fig. 8) to receive a first low-potential voltage VSS1, and the cathode 260c of the second LED D2 is connected to the second low-potential line 194 (from Fig. 8) to receive a second low-potential voltage VSS2. In Fig. 7, the cathode separation pattern 280 is arranged such that it surrounds the second cathode 260c in the second pixel area P2 and the second cathode extension section 260d. Alternatively, the cathode separation pattern 280 can also include a pattern that is located over a space between the first and second display areas DA1 and DA2 in order to separate the cathode in the first display area DA1 and the cathode in the second display area DA2. Fig. 8 is a schematic cross-sectional view illustrating a connection between an emission pixel area and a first low-potential voltage line, and a connection between a detection pixel area and a second low-potential voltage line in a display device according to the second embodiment of the present disclosure. Fig. 8 is a cross-sectional view taken along line VV' in Fig. 7. Fig. 8 shows the display device 200 without elements between the substrate 102 and the first planarization layer 152 and above the light-emitting diode. Referring to Fig. 8 with Fig. 2 and Fig. 7, the display device 200 of the second embodiment comprises a substrate 102 comprising the display area DA, which includes the first display area DA1 and the second display area DA2, and the non-display area NDA outside the display area DA, the first light-emitting diode D1 in the first display area DA1, the second light-emitting diode D2 in the second display area DA2, a cathode separation pattern 280 arranged between the first and second display areas DA1 and DA2, a deposition prevention pattern 284 arranged in a section of the second display area DA2, and the first and second low-potential voltage lines 192 and 194 in the non-display area NDA. The display device 200 of the second embodiment exhibits a key difference in the cathode separation pattern 280 compared to the display device 100 of the first embodiment. The explanation of the display device 200 focuses on the cathode separation pattern 280. The first and second low-potential voltage lines 192 and 194 are located in the non-indication area NDA and on the first planarization layer 152. The first to third light-emitting diodes D1, D2 and D3 are arranged in the display area DA and above the first planarization layer 152, e.g. on the second planarization layer 154. A bank 256 is arranged between two adjacent first to third pixel areas P1, P2 and P3 in the display area DA and between the first and second low potential voltage lines 192 and 194 in the non-display area and on the first planarization layer 152. In one embodiment of the disclosure, the first low-potential voltage line 192 can include a first line positioned on one side of the second low-potential voltage line 194 and a second line positioned on the far side of the second low-potential voltage line 194. This can be achieved by a bank 256 which includes a first bank positioned between the first line and the second low potential voltage line 194, and a second bank positioned between the second line and the second low potential voltage line 194. Bank 256 contains an opening corresponding to each of the first to third pixel areas P1, P2 and P3. In addition, bank 256 further contains a first and a third contact hole CH1 and CH3, which expose a first and a second conductor of the first low-potential voltage line 192 respectively, and a second contact hole CH2, which exposes the second low-potential voltage line 194. Although not shown, the second planarization layer 154 (from Fig. 4) can be arranged between the first planarization layer 152 and the bank 256 in the non-display area (NDA). For example, the second planarization layer 154 can have the same shape as the bank 256. Specifically, in the non-display area (NDA), the first and third contact holes CH1 and CH3, which expose a first and a second conductor of the first low-potential line 192 respectively, and the second contact hole CH2, which exposes the second low-potential line 194, can be formed by the bank 256 and the second planarization layer 154. Each of the first light-emitting diode D1 in the first pixel area P1 and the third light-emitting diode D3 in the third pixel area P3 contains a first anode 158a (from Fig. 4), a first light-emitting layer 158b (from Fig. 4), and a first cathode 258c, and the first cathode 258c contains a first cathode extension section 258d that extends into the non-display area NDA. The second light-emitting diode D2 in the second pixel area P2 contains a second anode 160a (from Fig. 4), a second light-emitting layer 160b (from Fig. 4), and a second cathode 260c, and the second cathode 260c contains a second cathode extension section 260d that extends into the non-display area NDA. The second cathode extension section 260d is spaced apart from the first cathode extension section 258d. The second cathode extension section 260d can be positioned between the first cathode extension section 258d of the first LED D1 and the first cathode extension section 258d of the third LED D3. The cathode separation pattern 280 surrounds the second cathode 260c and the second cathode extension section 260d. The cathode separation pattern 280 contains the first pattern 282, which surrounds the second cathode 260c, and the second and third patterns 286 and 288, respectively, which extend from the first pattern 282 along both sides of the second cathode extension section 260d. In particular, the cathode separation pattern 280 can have substantially the same shape as the second cathode 260c, which contains the second cathode extension section 260d. In other words, the first pattern 282 can surround three sides of the second cathode 260c or second pixel area P2 and have an open section corresponding to the second cathode extension section 260d, and each of the second and third patterns 286 and 288 extends from the first pattern 282 along the second cathode extension section 260d. The first pattern 282 is located on bank 256 and at the boundary of the second pixel area P2, and the second and third patterns 286 and 288 are located on bank 256 and between the first and second low-potential voltage lines 192 and 194. The deposition prevention pattern 284 is located in the transparent area TA of the second pixel area P2. The deposition prevention pattern 284 can extend from the cathode separation pattern 280. Each of the cathode separation pattern 280 and the deposition prevention pattern 284 can contain the compound represented by Formula 1. For example, each of the cathode separation pattern 280 and the deposition prevention pattern 284 can independently contain a compound chosen from the compounds in Formula 2. In one embodiment of the present disclosure, if several second pixel areas P2 are arranged in the second display area DA2, the second cathode extension section 260d in one of the second pixel areas P2 can be connected to the second cathode extension section 260d in the further of the second pixel areas P2. In one embodiment of the present disclosure, each of the second cathode extension section 260d in one of the second pixel areas P2 and of the second cathode extension section 260d in the further of the second pixel areas P2 extends into the non-display area NDA in order to be connected to the second low potential voltage line 194. In the display device 200 according to the second embodiment of the present disclosure, the first and second low-potential voltage lines 192 and 194 are arranged in the non-display area NDA on one side of the display area DA, and the first and second cathode extension sections 258d and 260d extend from the first and second cathode 258c and 260c in the same direction. In one embodiment of the present disclosure, the first and second low-potential voltage lines 192 and 194 can be arranged in different areas of the non-indicating area NDA, and the first and second cathode extension sections 258d and 260d extend from the first and second cathode 258c and 260c in different directions. For example, the first low-potential voltage line 192 can be located in the non-display area NDA on one side of the display area DA, and the first cathode extension section 258d can extend from the first cathode 258c in a first direction to contact the first low-potential voltage line 192. The second low-potential voltage line 194 can be located in the non-display area NDA on the far side of the display area DA, and the second cathode extension section 260d can extend from the second cathode 260c in a second direction opposite to the first direction to contact the second low-potential voltage line 194. In the display device 200 according to the second embodiment of the present disclosure, the cathode separation pattern 280 is arranged between the first pixel area P1 as an emission pixel area and the second pixel area P2 as a detection pixel area, and the first cathode 258c of the first light-emitting diode D1 in the first pixel area P1 and the second cathode 260c of the second light-emitting diode D2 in the second pixel area P2 are connected to the first and second low-potential voltage lines 192 and 194, respectively. Accordingly, the luminance decrease of the second pixel area P2, which contains the transmitting area TA and the emission area TA, can be prevented in order to have an emission area that is smaller than that of the first pixel area P1, such that the display device 200 can provide an image with high luminance. In the display device 200, the first and second cathodes 258c and 260c are selectively deposited (or formed) in desired areas using the cathode separation pattern 280 and the deposition prevention pattern 284, which are formed by the same process and the same material, wherein the display device 200, which has a detection function and high luminance, can be provided without an additional process. Furthermore, in the display device 200, when the third pixel area P3 is arranged as an emission pixel area in the second display area DA2, the cathode in the third pixel area P3 is separated from the cathode 260c in the second pixel area P2, which is a detection pixel area, and is connected to the first low-potential voltage line 192. As a result, luminance inconsistency in the first and third pixel areas P1 and P3, the emission pixel area, can be prevented. Fig. 9 is a schematic top view of a display device of a third embodiment of the disclosure. Referring to Fig. 9 with Fig. 2, the display device 300 of the third embodiment includes a substrate 102 and several pixel areas P1, P2 and P3 arranged on the substrate 102. A display area DA, containing a first display area DA1 and a second display area DA2 outside the first display area DA1, and a non-display area NDA outside the display area DA are defined on substrate 102. The first pixel area P1 is located in the first display area DA. A first LED D1 is located in the first pixel area P1. A second pixel area P2 is located in the second display area DA2. A second LED D2 is located in the second pixel area P2. The second pixel area P2 can be red, green, or blue. The second pixel area P2 contains an emission surface EA and a transparent surface TA on one side of the emission surface EA, and the first pixel area P1 contains an emission surface without a transparent surface. For example, an area (e.g., a planar surface) of the emission surface of the first pixel area P1 can be essentially equal to the sum of an area of ​​the emission surface of the second pixel area P2 and an area of ​​the transparent surface of the second pixel area P2. The first pixel area P1 can be a pixel area that provides an image, and the second pixel area P2 can be a pixel area that provides a capture function. For example, the first pixel area P1 can be called an emission pixel area, and the second pixel area P2 can be called a capture pixel area. A third pixel area P3 can also be arranged in the second display area DA2. A third LED D3 is arranged in the third pixel area P3. The third pixel area P3 can be the emission pixel area or the detection pixel area. Multiple third pixel areas P3 can be arranged within the second display area DA2, and these multiple third pixel areas P3 can include red, green, and blue pixel areas. For clarity, the display device is illustrated with the third pixel area P3 being the emission pixel area. Several emission pixel areas are arranged in the first display area DA1, and several detection pixel areas or several detection pixel areas and several emission pixel areas are arranged in the second display area DA2. A cathode separation pattern 380 for separating the second cathode 360c of the second LED D2 in the second pixel area P2 from the first cathode 358c of the first LED D1 in the first pixel area P1 and the third cathode of the third LED D3 in the third pixel area P3 is arranged in the second display area DA2. The cathode separation pattern 380 surrounds the second cathode 360c, which is to be separated from the first cathode 358c and the third cathode. In each of the first to third LEDs D1, D2, and D3, the anode is connected to the drain electrode of the driver TFT T2. The cathode 258c of the first LED D1 and the cathode of the third LED D3 are connected to the first low-potential line 192 (from Fig. 5) to receive a first low-potential voltage VSS1, and the cathode 260c of the second LED D2 is connected to the second low-potential line 394 (from Fig. 10) to receive a second low-potential voltage VSS2. The second low-potential line 394 extends into the second pixel area P2, and the second cathode 360c and the second low-potential line 394 in the second pixel area P2 are connected to each other. Specifically, the cathode separation pattern 380 completely surrounds every second pixel area P2, and the second cathode 360c in the second pixel area P2 is separated from the first cathode 358c in the first pixel area P2 and the third cathode in the third pixel area P3. Additionally, the second cathode 360c in one of the second pixel areas P2 is separated from the second cathode 360c in the other of the second pixel areas P2. In one embodiment, the second cathode 360c in one of the second pixel areas P2 and the second cathode 360c in the other of the second pixel areas P2 can be connected to each other. In Fig. 9, the cathode separation pattern 380 is arranged to surround the second pixel area P2. Alternatively, the cathode separation pattern 380 can also include a pattern that extends over a space between the first and second display areas DA1 and DA2 to separate the cathode in the first display area DA1 and the cathode in the second display area DA2. Fig. 10 is a schematic cross-sectional view of a detection pixel area and a connection between the detection pixel area and a second low-potential voltage line in a display device of the third embodiment. Fig. 10 is a cross-sectional view taken along line VI-VI' in Fig. 9. Fig. 8 shows the display device 200 without elements between the substrate 102 and the third insulating intermediate layer 142 and above the light-emitting diode. Referring to Fig. 10 with Fig. 2 and Fig. 9, the display device 300 of the second embodiment comprises a substrate 102, which includes the display area DA, which contains the first display area DA1 and the second display area DA2, and the non-display area NDA outside the display area DA, the first light-emitting diode D1 in the first display area DA1, the second light-emitting diode D2 in the second display area DA2, a cathode separation pattern 280 arranged between the first and the second display areas DA1 and DA2, a deposition prevention pattern 284 arranged in a section of the second display area DA2, and the first low-potential voltage line 192 (from Fig. 5) and the second low-potential voltage line 194 in the non-display area NDA. The display device 300 of the third embodiment exhibits a key difference in the cathode separation pattern 380 compared to the display device 100 of the first embodiment. The explanation of the display device 300 focuses on the cathode separation pattern 380. The third insulating layer 142 is arranged on the substrate 102, and the first planarization layer 152 is arranged on the third insulating layer 142. The second low-potential voltage line 394 is arranged on the first planarization layer 152. In one embodiment, the second low-potential voltage line 394 can be arranged between the substrate 102 and the first planarization layer 152. The second planarization layer 154, which covers the second low-potential line 394, is arranged on the first planarization layer 152. The first and second planarization layers 152 and 154 in the transparent area TA of the second pixel area P2 can be removed, such that the third insulating intermediate layer 142 is exposed. The second anode 360a, corresponding to the emission area EA, is located on the second planarization layer 154 and in the second pixel area P2. Additionally, an auxiliary electrode 361 is located on the second planarization layer 154 and between the emission area EA and the transparent area TA. The auxiliary electrode 361 is connected to the second low-potential voltage line 394 via a contact hole in the second planarization layer 154. The auxiliary electrode 361 can be made of the same material as the second anode 360a. Alternatively, the auxiliary electrode 361 can be made of the same material as the second low-potential voltage line 394. Bank 356 is located at the boundary of the second pixel area P2 and between the transparent area TA and the emission area EA. Bank 356 covers one edge of the second anode 360a and contains an opening corresponding to the transparent area TA and the emission area EA. The second anode 360a is exposed through the opening in the emission area EA, and the third insulating intermediate layer 142 is exposed through the opening in the transparent area TA. In addition, bank 356 also contains an auxiliary contact hole CH, which exposes the auxiliary electrode 361. The second light-emitting layer 360b is arranged on the second anode 360a in the emission area EA of the second pixel area P2. The second light-emitting layer 360b does not need to be represented in the transparent area TA, such that the third insulating intermediate layer 142 is exposed. The cathode separation pattern 380 is arranged to surround the second pixel area P2, and the deposition prevention pattern 384 is arranged in the transparent area TA of the second pixel area P2. The cathode separation pattern 380 can be positioned on the bed 356 that surrounds the second pixel area P2, and the deposition prevention pattern 384 can be positioned on the third insulating intermediate layer 142 in the transparent area TA. In one embodiment, at least one of the first and second planarization layers 152 and 154 can be formed on the third insulating intermediate layer 142 in the permeable area TA. In this case, the deposition prevention pattern 384 can be positioned on the first planarization layer 152 or the second planarization layer 154 in the permeable area TA. In Fig. 10, the second light-emitting layer 360b is shown in the emission area EA and is not shown in the transparent area TA. In one embodiment, the second light-emitting layer 360b can be shown in both the emission area EA and the transparent area TA. In this embodiment, the deposition prevention pattern 384 can be positioned on the second light-emitting layer 360b in the transparent area TA. Each of the cathode separation pattern 380 and the deposition prevention pattern 384 can contain the compound represented by Formula 1. For example, each of the cathode separation pattern 380 and the deposition prevention pattern 384 can independently contain a compound chosen from the compounds in Formula 2. The second cathode 360c is located on the second light-emitting layer 360b in the emission surface EA. The second cathode 360c extends into the auxiliary contact hole CH in bank 356 to be connected to the auxiliary electrode 361 through the auxiliary contact hole CH. Accordingly, the second cathode 360c is electrically connected to the second low-potential voltage line 394 through the auxiliary electrode 361. The first light-emitting diode D1 is arranged in the first pixel area P1, and the third light-emitting diode D3 is arranged in the third pixel area P3. For example, the first cathode 358c of the first light-emitting diode D1 can extend into the non-display area NDA in the first pixel area P1 to be connected to the first low-potential voltage line 192 (from Fig. 5). In one embodiment of the present disclosure, the first cathode 358c can be connected to the first low-potential voltage line 192 in the first pixel area P1. In the display device 300 of the third embodiment, the cathode separation pattern 380 is arranged between the first pixel area P1 as an emission pixel area and the second pixel area P2 as a detection pixel area, and the first cathode 358c of the first light-emitting diode D1 in the first pixel area P1 and the second cathode 360c of the second light-emitting diode D2 in the second pixel area P2 are connected to the first low-potential voltage line 192 and the second low-potential voltage line 394, respectively. Accordingly, the reduction in luminance in the second pixel area P2, which contains the transparent area TA and the emission area TA, can be prevented in order to have an emission area that is smaller than that of the first pixel area P1, such that the display device 300 can provide an image with high luminance. In addition, in the display device 300, the first and second cathodes 358c and 360c are selectively deposited (or formed) in desired areas using the cathode separation pattern 380 and the deposition prevention pattern 384, which are formed by the same process and from the same material, and the display device 300, which has a detection function and high luminance, can be provided without an additional process. Furthermore, in the display device 300, when the third pixel area P3 is arranged as an emission pixel area in the second display area DA2, the cathode in the third pixel area P3 is separated from the second cathode 360c in the second pixel area P2 as a detection pixel area and is connected to the first low-potential voltage line 192. Thus, luminance inconsistency in the first and third pixel areas P1 and P3, the emission pixel area, can be prevented. It will be apparent to those skilled in the art that various modifications and variants of the embodiments of the present disclosure can be made without deviating from the scope of the present disclosure. Thus, it is intended that the modifications and variants cover this disclosure, provided they fall within the scope of the appended claims and their equivalents. QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature KR 10-2024-0195956

[0001]

Claims

Display device comprising: a substrate (102) containing a display area (DA) and a non-display area (NDA) outside the display area (DA), wherein the display area (DA) comprises a first display area (DA1) and a second display area (DA2), the first display area (DA1) comprising a first pixel area (P1) and the second display area (DA2) comprising a second pixel area (P2) comprising a first emission area (EA) and a transmittable area (TA); a first light-emitting diode (D1) in the first pixel area (P1); a second light-emitting diode (D2) in the first emission area (EA) and a first and a second low-potential voltage line (192, 194) in the non-display area (NDA);wherein a cathode (158c) of the first light-emitting diode (D1) is connected to the first low-potential voltage line (192) and a cathode (160c) of the second light-emitting diode (D2) is connected to the second low-potential voltage line (194) in order to control the luminance of the first light-emitting diode (D1) in the first pixel area (P1) and of the second light-emitting diode (D2) independently. Display device according to claim 1, which further comprises a cathode separation pattern (182) between the first pixel area (P1) and the second pixel area (P2), wherein a cathode (158c) of the first light-emitting diode (D1) and a cathode (160c) of the second light-emitting diode (D2) are separated by the cathode separation pattern (182). Display device according to claim 1 or 2, which further comprises a separation prevention pattern (184) in the permeable area (TA). Display device according to one of the preceding claims, wherein the deposition prevention pattern (184) extends from the cathode separation pattern (182) and / or the cathode separation pattern (182) is over a space between the first and the second display area (DA1, DA2). Display device according to one of the preceding claims, wherein the cathode (160c) of the second light-emitting diode (D2) includes a cathode extension section (160d) which extends into the non-display area (NDA) to be connected to the second low-potential voltage line (194), and the cathode separation pattern (182) surrounds the cathode (160c) and the cathode extension section (160d), wherein preferably the cathode extension section (160d) in one of the second pixel area (P2) is connected to the cathode extension section (160d) in the further part of the second pixel area (P2). Display device according to one of the preceding claims 2 - 5, wherein the first low potential voltage line (192) comprises a first line on one side of the second low potential voltage line (194) and a second line on the far side of the second low potential voltage line (192). Display device according to claim 6, further comprising: a first bank (256) between the first line (192) and the second low-potential voltage line (194) and a second bank (256) between the second line (192) and the second low-potential voltage line (194), wherein the cathode separation pattern (280) is preferably arranged on the first and the second bank (256). Display device according to one of the preceding claims, wherein the cathode separation pattern (182) and the deposition prevention pattern (184) are formed from the same material and / or side surfaces of the cathode separation pattern (182) contact side surfaces of the first and second cathode (158c, 160c) and / or side surfaces of the deposition prevention pattern (184) contact side surfaces of the first and second cathode (158c, 160c). Display device according to one of the preceding claims, wherein the cathode separation pattern (280) surrounds the second pixel area (P2) and preferably the second cathode (260c) is connected to the second low potential voltage line (194) in the second pixel area (P2). Display device according to one of the preceding claims, wherein the first pixel area (P1) contains a second emission surface (EA), preferably an area of ​​the second emission surface is larger than an area of ​​the first emission surface (EA) and / or an area of ​​the second emission surface (EA) is equal to a summation of an area of ​​the first emission surface (EA) and an area of ​​the transparent surface (TA). Display device according to one of the preceding claims, wherein an area of ​​the first cathode (158c) is larger than an area of ​​the second cathode (160c). Display device according to one of the preceding claims, wherein the first and the second low-potential voltage lines (192, 194) are arranged on the same layer. Display device according to one of the preceding claims, wherein a first voltage (VSS1) is applied to the first low potential voltage line (192) and a second voltage (VSS2) is applied to the second low potential voltage line (194) and preferably the second voltage (VSS2) is smaller than the first voltage (VSS1). Display device according to one of the preceding claims, further comprising a sensor arranged in the transparent area (TA), wherein preferably the second cathode (160c) is not arranged in the transparent area (TA). Display device according to one of the preceding claims, wherein the second display area (DA2) further comprises a third pixel area (P3) and a third light-emitting diode (D3) is arranged in the third pixel area (P3), wherein preferably a cathode of the third light-emitting diode (D3) is connected to a first low-potential voltage line (192). Display device according to one of the preceding claims, wherein the cathode separation pattern (280) comprises a first pattern (282) surrounding three sides of the second cathode (260c) and having an open section corresponding to the cathode extension section (260d), and a second and a third pattern (286, 288) extending from the first pattern (282) along both sides of the cathode extension section (260d). Display device according to one of the preceding claims 2-16, further comprising a bank (156) comprising a first and a third contact hole (CH1, CH3) exposing the first and second lines (192, 194) respectively, and a second contact hole (CH2) exposing the second low-potential voltage line (194), wherein preferably the bank (156) is formed on a planarization layer (152, 154) and a section of the bank (156) and the planarization layer (152, 154) is arranged in the third contact hole (CH3). Display device according to one of the preceding claims, wherein the cathode separation pattern (380) completely surrounds every second pixel area (P2) and / or the second low-potential voltage line (194) extends into the second pixel area (P2).

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