Separate microchannel voltage domains in stacked memory architecture

Abstract

Storage device (100, 200, 300, 400, 500, 600), comprising: a memory stack (220, 420, 520, 610, 620, 630, 640) with multiple coupled memory chips, wherein the memory stack (220, 420, 520, 610, 620, 630, 640) contains a plurality of microchannels, and a logic chip (210, 410, 510) coupled to the memory stack (220, 420, 520, 610, 620, 630, 640), wherein the logic chip (210, 410, 510) contains a memory controller (530), where each of the multiple microchannels contains a separate voltage domain, wherein the memory controller (530) separately controls a voltage for each of the multitude of microchannels, wherein the memory controller (530) includes a traffic tracker (532), and the memory controller (530) detects a change in the voltage of one of the microchannels, which is based at least in part on a traffic pattern for data, wherein the memory controller (530) determines a performance advantage in connection with the change in the voltage of one microchannel, and wherein the logic chip (210, 410, 510) includes a dynamic voltage engine (546) for providing instructions to control the voltage level in each of the multitude of microchannels.

Description

TECHNICAL AREA

[0001] Embodiments of the invention generally relate to the field of electronic devices and in particular to separate microchannel voltage domains in a stacked memory architecture. BACKGROUND

[0002] To provide memory with higher density for computing operations, concepts are being developed that include storage devices with multiple tightly coupled memory elements (which can be referred to as 3D stacked memory or stacked memory). A 3D stacked memory can comprise coupled layers or units of DRAM (dynamic random-access memory) memory elements, which can be described as a memory stack. Stacked memory can be used to provide a large amount of main memory in a single component or unit, which can also include certain system components, such as a memory controller and a CPU (central processing unit).

[0003] In conventional implementations of stacked multi-channel 3D DRAM architectures like WidelO, the voltage domain (which can also be called the voltage Vint) for data paths, codecs, and clocking is the same across each of the architecture's multiple microchannels. For this reason, it is not possible to change the voltage level for effective operation in each microchannel of the memory device.

[0004] US 2011 / 0 121 811 A1 relates to a power supply in a heterogeneous 3D stacking device. US 2009 / 0 103 345 A1 discloses three-dimensional memory module architectures. US 2009 / 0 103 854 A1 discloses photonic interconnects for computer system devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments of the invention are shown by way of example and in no way limiting in the figures of the accompanying drawings, whereby the same reference numbers refer to similar elements. Fig. Figure 1 illustrates an embodiment of a stack storage device. Fig. Figure 2 illustrates an embodiment of a 3D stack storage system. Fig. Figure 3 illustrates an embodiment of a memory chip with multiple voltage domains. Fig. Figure 4A illustrates an embodiment of a stacked storage device that provides a separate power domain for each microchannel disk of the storage stack. Fig. Figure 4B illustrated an embodiment of a stacked storage device that provides a separate power domain for each microchannel chip of the storage stack. Fig. 5A illustrates an embodiment of a storage device or storage system that provides power control of the microchannels. Fig. Figure 5B illustrates a memory controller of an embodiment of a memory device. Fig. 5C is a flowchart illustrating the interaction of the memory controller with the dynamic voltage engine in one embodiment of a device or system. Fig. Figure 6 illustrates an architecture of an embodiment of a stack storage device. Fig. Figure 7 is a block diagram illustrating an embodiment of a mobile computing device including a stack storage device, and Fig. Figure 8 illustrates an embodiment of a computer system including a stack memory. DETAILED DESCRIPTION

[0006] The invention is defined in the independent claims. Dependent claims describe preferred embodiments.

[0007] Embodiments of the invention are generally directed towards separate microchannel storage domains in a stacked storage architecture.

[0008] As used here: "3D stack memory" (where 3D indicates three-dimensional) or "stack memory" means main memory comprising one or more coupled memory layers, memory units, or other memory elements. The memory (referred to as stack memory) may be stacked vertically or horizontally (such as side by side), or it may otherwise comprise interconnected memory elements. In particular, a DRAM stack memory device or system may contain a memory device with multiple DRAM layers. A stack memory device may also include system elements (which may be referred to as a logic chip) within the device, the logic chip being a CPU (central processing unit), a memory controller, and other associated system elements, which may include a power host chip, with the memory stack being stacked with the power host chip.In some embodiments, the logic chip can be an application processor or a graphics processing unit (GPU). A 3D stack can include, but is not limited to, a WideIO storage device.

[0009] A "microchannel" is a logical, independent memory channel in a 3D memory stack. Generally, a memory channel is referred to as a microchannel if a 3D memory stack contains more than one memory channel. Otherwise, the memory stack is a single-channel 3D memory stack.

[0010] In stacked multi-channel 3D DRAM architectures like WidelO, the voltage domain (also known as voltage vint) for data paths, codecs, and clocking is the same across the architecture's multiple channels. A separate voltage domain per microchannel is not available, and therefore, per-microchannel energy efficiency optimizations by adjusting the local vint are not possible.

[0011] In some embodiments, a memory controller includes the ability to control the DRAM stack power consumption more efficiently. In some embodiments, platforms with higher energy efficiency can be provided with multi-channel DRAM stacks. In some embodiments, the voltage control function is enabled via the memory controller and CPU of a device.

[0012] In some embodiments, a device, system, or method ensures that each microchannel of a stack storage device has a separate local vint and that the vint is adjustable for each microchannel. In some embodiments, the vint for each microchannel is provided by on-chip power generators, which may be part of a separate, dedicated power generation chip (a power host chip), or the power generators may be integrated into a logic chip element (e.g., a system-on-chip containing the CPU) that is part of the 3D stack storage.

[0013] In some embodiments, each Vint domain rail of a stacked memory device is connected via a Power Through Silicon Via (TSV) of the specific microchannel. In other embodiments, there are no connections between multiple Vint domains of each memory chip containing the tiles of different microchannels.

[0014] In some embodiments, an alternative implementation integrates the Vint generators into each DRAM chip. In some embodiments, each DRAM chip in a memory stack contains as many Vint domains and generators as the DRAM chip contains microchannels. In such an implementation, a DVS (Dynamic Voltage Scaling) engine in the logic chip generates a control word that controls each of the Vint voltage generators, thus enabling individual scaling of Vint domains.

[0015] In some embodiments, a DVS engine assigns an activity factor to each of the individual microchannels of the stack storage device. In some embodiments, the DVS engine scales the Vint domains for each of the microchannels of a stack storage device up or down, at least partially, based on the activity factor, thus enabling an improved power-saving policy compared to a conventional device with a single voltage domain.

[0016] In some embodiments, the conventional Vint domain of a memory chip in a memory stack is divided into separate Vint domains for each tile disk (or other part of the memory chip) of the respective microchannel (each tile of a chip having a Vint domain separate from the other tiles of the chip), or can be divided, with each chip being a microchannel (each chip with a Vint domain separate from the other chips of the memory stack). In some embodiments, the Vint domains of the tiles belonging to the same microchannel (with a particular disk of the memory stack) are connected via TSV columns. In some embodiments, the Vint domains are connected to their associated Vint generators or are freely adjustable via a word sent by the memory controller or another controller to effectively control all DRAM tiles.In some embodiments, CPU control word control of Vint provides an implementation approach that can be used when Vint generators reside on the DRAM chip. In some embodiments, each DRAM supports a mode for adjusting its local Vint voltage domain values ​​by changing specific bits in a mode register.

[0017] In some embodiments, a storage device includes a memory stack with one or more coupled memory chips, wherein a first memory chip of the memory stack contains multiple microchannels, and a logic chip coupled to the memory stack, the logic chip containing a memory controller. Each of the microchannels contains a separate voltage domain, and the voltage level is controlled for each of the multiple microchannels.

[0018] In some embodiments, traffic tracking for a first microchannel of a storage device, wherein the storage device contains a logic chip coupled to a memory stack of one or more coupled memory chips, wherein the storage device contains a plurality of microchannels and each microchannel has a voltage domain, involves detecting a traffic pattern for the first microchannel, determining an advantage associated with a change in the voltage of the microchannel, and requesting a change in the voltage of the microchannel.

[0019] Fig. Figure 1 illustrates one embodiment of a stack storage device. In some embodiments, a stack storage device 100 comprises a memory stack comprising one or more DRAM chip layers 120 and tightly coupled to a system element such as a logic chip 110, which may be a SoC or another system element.

[0020] In some embodiments, the logic chip 110 can include the control of voltage domains for each microchannel of the memory stack 120. In some embodiments, the memory stack or the logic chip 110 can include multiple separate voltage generators for each microchannel of the memory stack. In some embodiments, the logic chip 110 can use the control of the microchannel voltage domains to control the power consumption of the memory device 100.

[0021] Fig. Figure 2 represents an embodiment of a 3D stacked memory. In this representation, a 3D stacked memory device 200 comprises a system element, e.g., a logic chip 210, coupled to one or more DRAM memory chip layers 220, also referred to here as a memory stack. In some embodiments, the memory stack 220 may comprise multiple microchannels. In some embodiments, the system element 210 may be a system-on-a-chip (SoC) or another similar element. The elements of this figure and the following figures are shown for illustrative purposes and are not drawn to scale.Each chip layer can include a temperature-compensated self-refresh (TCSR) circuit to address thermal aspects, where the TCSR and a mode register (MR) can be part of the device's management logic, and where the mode register (MC) can include thermal offset bit(s) for setting the refresh rate by the TCSR. The chip layers and the system element can be thermally coupled.

[0022] Although Fig. Figure 2 illustrates an implementation in which the logic chip 210 is coupled below the memory stack consisting of one or more memory chip layers 220; however, embodiments are not limited to this arrangement. For example, in some embodiments, a system element 210 may be arranged adjacent to the memory stack 220 and may therefore be coupled to the memory stack 220 in a side-by-side arrangement. In some embodiments, the system element 210 may include a power host chip, wherein the power host chip can supply power to separate Vint domains of the memory device's microchannels.

[0023] In this representation, the DRAM memory chip layers comprise four memory chip layers, namely a first memory chip layer 230, a second memory chip layer 240, a third memory chip layer 250, and a fourth memory chip layer 260. However, embodiments are not limited to a specific number of memory chip layers in the memory stack 220 and may include a larger or smaller number of memory chip layers. Among other elements, the system element 210 may include a memory controller 212 for the memory stack 220. In some embodiments, each memory chip layer (with the possible exception of the top or outermost memory chip layer, such as the fourth memory chip layer 260 in this representation, which may or may not contain TSVs) includes a plurality of through silicon vias (TSVs) 205 to provide paths through the silicon substrate of the memory chip layers.In some embodiments, the DRAM memory stack can provide 220 Vint power pins / microbumps for each Vint domain.

[0024] In some embodiments, the memory stack 220 includes a plurality of microchannels, wherein each tile disk of the memory stack is a microchannel (e.g., the illustrated disks of tiles 290 of the memory stack 220), or wherein each chip is a separate microchannel. In some embodiments, each of the microchannels includes a separate voltage domain with a voltage vint. In some embodiments, the vint for each microchannel can be generated on each chip. In some embodiments, vint generators 280 for each microchannel are generated in the system element 210, e.g., a power host chip, and in some embodiments, vint generators 282 for each microchannel are located in each memory chip 230-260.

[0025] Fig. Figure 3 illustrates an embodiment of a memory chip with multiple voltage domains. In this illustration, a DRAM chip 300 comprises four tiles (or other parts of a chip). In some embodiments, each of the tiles comprises a separate voltage domain with a voltage Vint that can be set independently of the Vint of any other tile. In this example, the DRAM chip comprises a Domain_0 305 with voltage Vint0, a Domain_1 310 with voltage Vint1, a Domain_2 315 with voltage Vint2, and a Domain_3 320 with voltage Vint3. In some embodiments, each domain can be controlled independently of the other Vint values. In some embodiments, other DRAM chips in a memory stack have the same tile layout, with the tiles in a vertical stack forming a disk that represents a specific microchannel. Fig. 4A and Fig. Figure 4B illustrates two different microchannel implementations:

[0026] Fig. Figure 4A illustrates an embodiment of a stacked storage device that provides a separate current domain for each microchannel disk of the storage stack. In the Fig. In the implementation illustrated in Figure 4A, each disk or column of tiles is a microchannel, and thus the number of tiles per DRAM memory chip is equal to the number of microchannels. In some embodiments, a stack memory device 400 includes a logic chip 410 and a memory stack with one or more memory chips 420 coupled to the logic chip 410. In this particular representation, the memory stack includes four chips, each chip containing four microchannels (µCH0, µCH1, µCH2, and µCH3), and the microchannels are coupled to the system chip by a plurality of TSVs. In this representation, there are separate Vint domains across each chip (Vint0, Vint1, Vint2, and Vint3), with the same separation of Vint domains present in each chip of the memory stack to form disks of chips, and the Vint domains are connected via TSVs.In some embodiments, the stack storage device 400 includes a separate power domain for each microchannel, with a power supply or control unit for each microchannel.

[0027] In this embodiment, a power supply for each microchannel is located in the logic chip 410, thus between the substrate and the DRAM 3D stack. The logic chip 410 may include a power host chip that has a local power supply and control unit for each microchannel. In some embodiments, the tiles or other parts of chips located in the same column (and thus on the same disk) share a common Vint domain, which is supplied or controlled by the respective Vint control unit in the controller or CPU of the logic chip 410. In some embodiments, the chip tiles in a column are connected by TSVs that traverse the memory stack. In some embodiments, the power for the voltage domain of the microchannels is supplied by, for example, a power supply unit.the Vint0 supply or control unit 422 for a first voltage domain, the Vint1 supply or control unit 424 for a second voltage domain, the Vint2 supply or control unit 426 for a third voltage domain and the Vint3 supply or control unit 428 for a fourth voltage domain are supplied and controlled.

[0028] Fig. Figure 4B illustrated an embodiment of a stacked memory device that provides a separate power domain for each microchannel chip of the memory stack. In the Fig. In the implementation illustrated in Figure 4B, each DRAM memory chip is a separate microchannel, and therefore the number of chips corresponds to the number of microchannels. In some embodiments, the stack memory device 401 includes a logic chip 411 and a memory stack consisting of one or more memory chips 421 coupled to the logic chip 411. In this particular representation, the memory stack includes four chips, each containing a single microchannel (µCH0, µCH1, µCH2, and µCH3), and the microchannels are coupled to the system chip by a plurality of TSVs. In this representation, there is a single Vint domain over each chip (Vint0, Vint1, Vint2, or Vint3), with the Vint domains interconnected by TSVs. In some embodiments, the stack memory device 401 includes a separate power domain for each microchannel, with a power supply or control unit for each microchannel.

[0029] In this embodiment, a power supply for each microchannel is located in the logic chip 411, thus between the substrate and the DRAM 3D stack, wherein the logic chip 411 may contain a power host chip that has a local power supply and control unit for each microchannel. In some embodiments, each chip has a Vint domain that is supplied or controlled by the respective Vint supply or control unit of the system element 411. In some embodiments, each chip is connected to specific TSVs that traverse the memory stack. In some embodiments, the energy for the voltage domain of the microchannels is supplied by, for example, a power supply unit.the Vint0 supply or control unit 423 for a first voltage domain, the Vint1 supply or control unit 425 for a second voltage domain, the Vint2 supply or control unit 427 for a third voltage domain and the Vint3 supply or control unit 429 for a fourth voltage domain are supplied and controlled.

[0030] Fig. Figure 5A illustrates an embodiment of a storage device or storage system that provides power control of the microchannels. In some embodiments, a storage stack device 500 may include a storage stack 520 with a plurality of microchannels and a logic chip 510, wherein the logic chip 510 includes a storage controller 530, and a steering block 512 provides the logic for power control of the plurality of microchannels of the storage stack 520. In some embodiments, the steering block 512 includes a dynamic voltage scaling engine 516, wherein the dynamic voltage scaling engine includes the ability to generate control words 514 for controlling the voltages of the microchannel voltage domains.

[0031] In some embodiments, the dynamic voltage scaling engine 516 includes logic for determining the voltage level for each of the voltage domains of the memory stack 520. In some embodiments, the operation of the dynamic voltage scaling engine 516 is based at least partially on feedback information received from DRAM chips of the memory stack 520. In some embodiments, the operation of the dynamic voltage scaling engine 516 is based at least partially on a lookup table that receives data from a traffic monitor that monitors traffic for each microchannel. In some embodiments, the dynamic voltage scaling engine generates a control word 514 or similar instruction that is issued to Vint supply generators, the supply generators 580 being located together in the logic chip (the supply is then provided via the TSVs).In some embodiments, the control word is fed directly into the stack, with the stack containing the Vint supply generators 580 locally on the memory chips.

[0032] Fig. Figure 5B illustrates a memory controller of an embodiment of a storage device. In some embodiments, a memory controller 530 may include a traffic tracker 532 for tracking data traffic to the stack storage device 500, the use of the traffic tracker in a particular implementation being described in Figure 5B. Fig. 5C is illustrated.

[0033] Fig. Figure 5C is a flowchart illustrating the interaction of the memory controller with the dynamic voltage engine in one embodiment of a device or system. In some embodiments, traffic to a particular microchannel n is monitored by a memory controller traffic tracker 540, e.g., the traffic tracker 532 of the memory controller 530, which is located in Fig. 5B is illustrated.

[0034] In some embodiments, when the memory controller detects a specific traffic flow pattern, where such a pattern indicates a long idle phase 542, a memory controller-based traffic prediction algorithm can detect a performance benefit in changing the vint, e.g., reducing the vint of microchannel n because of the long idle state indicated for microchannel 544. In some embodiments, the memory controller transmits a request requesting a vint change for microchannel n to the dynamic voltage engine 546, which can change the vint of microchannel 548.

[0035] Fig. Figure 6 illustrates the architecture of one embodiment of a stacked memory device. In some embodiments, each microchannel of a stacked memory device is driven by a DRAM chip in the memory stack. Fig. Figure 6 illustrates architectures for memory devices containing two chips and four chips. In some embodiments, a memory stack may contain a separate command and address (C / A) bus for each channel. In other embodiments, a memory stack may contain a common C / A bus for all channels.

[0036] In this illustration, a first architecture 610 illustrates a stack of two chips with a separate C / A bus for each channel, a second architecture 620 illustrates a stack of two chips with a common C / A bus for each channel, a third architecture 630 illustrates a stack of four chips with a separate C / A bus for each channel, and a fourth architecture 640 illustrates a stack of four chips with a common C / A bus for all channels.

[0037] Fig. Figure 6 illustrates various forms of C / A bus topologies and the distribution of I / Os across the DRAM chips as the stack grows. In some embodiments, a Vint domain partitioning and control can be used for each such implementation, as shown in Fig. 4A illustrates how it can be applied.

[0038] Fig. Figure 7 is a block diagram illustrating an embodiment of a mobile computing device, including a stack storage device. Computing Device 700 represents a computing device, including a mobile computing device, such as a laptop or notebook computer, a netbook, a tablet computer (including a device having a touchscreen without a separate keyboard, a device having both a touchscreen and a keyboard, a device with fast initiation, referred to as "instant on" operation, and a device generally connected to a network in operation, referred to as "always connected"), a mobile phone or smartphone, a wireless-enabled e-reader, or any other wireless mobile device. It is evident that certain components are represented in a general way and not all components of such a device are shown in Device 700.The components can be connected by one or more buses or other connections 705.

[0039] Device 700 includes Processor 710, which performs the primary processing operations of Device 700. Processor 710 may comprise one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by Processor 710 include the execution of an operating platform or operating system on which applications or device functions, or both, run. The processing operations include I / O (input / output) operations with a human user or with other devices, power management operations, operations, or both, related to connecting Device 700 to another device. The processing operations may also include operations related to audio I / O, display I / O, or both.In one embodiment, the device 700 comprises the audio subsystem 720, which represents hardware (such as audio hardware and audio circuitry), and software components (such as drivers and codecs) associated with providing audio functionality to the computer device. Audio functionality may include a speaker output, a headphone output, or both types of audio output, as well as a microphone input. The devices for such functionality may be integrated into or connected to the device 700. In one embodiment, a user interacts with the device 700 by providing audio commands, which are received and processed by the processor 710.

[0040] The display subsystem 730 represents hardware (such as display devices) and software components (such as drivers) that include a display providing visual elements, tactile elements, or both for a user to interact with the computer device. Display subsystem 730 includes the display interface 732, which comprises the specific screen or hardware device used to provide a display to a user. In one embodiment, the display interface 732 includes logic that is separate from the processor 710 to perform at least some processing associated with the display. In another embodiment, the display subsystem 730 includes a touchscreen device that provides both output and input to a user.

[0041] The I / O Controller 740 represents hardware devices and software components associated with user interaction. The I / O Controller 740 can manage hardware that is part of the Audio Subsystem 720, the Display Subsystem 730, or both. Additionally, the I / O Controller 740 illustrates a connection point for additional devices connected to the Device 700 through which a user could interact with the system. For example, devices that could connect to the Device 700 might include microphones, speakers or stereo systems, video systems or other display devices, a keyboard or keyboard devices, or other I / O devices for use with specific applications, such as card readers or other devices.

[0042] As mentioned above, I / O Controller 740 can interact with Audio Subsystem 720, Display Subsystem 730, or both. For example, input via a microphone or other audio device can provide inputs or commands for one or more applications or functions of Device 700. Audio output can also be provided instead of, or in addition to, display output. In another example, the display device also acts as an input device that can be managed, at least partially, by I / O Controller 740 if the Display Subsystem includes a touchscreen. There can also be additional buttons or switches on Device 700 to provide I / O functions that can be managed by I / O Controller 740. In one embodiment, I / O Controller 740 manages devices such as accelerometers, cameras, light sensors, or other sensors or hardware that may be included in Device 700.The input can be part of direct user interaction as well as providing an environment-based input to the device to influence its operations (such as filtering noise, adjusting displays with respect to brightness detection, applying a camera flash, or other functions). In one embodiment, Device 700 includes Power Management 750, which manages battery power usage, battery charging, and functions associated with power-saving operation.

[0043] In some embodiments, the memory subsystem 760 includes memory devices for storing information in the device 700. The processor 710 can read data from and write data to elements of the memory subsystem 760. Memory can include non-volatile memory devices (which have a state that does not change when power to the memory device is interrupted), volatile memory devices (which have an indeterminate state when power to the memory device is interrupted), or both. The memory 760 can store application data, user data, music, photos, documents, or other data, as well as device data (whether long-term or temporary) associated with the execution of the applications and the functions of the device 700.

[0044] In some embodiments, the memory subsystem 760 can include a stack storage device 762, wherein the stack storage device contains one or more memory chip layers and a plurality of microchannels with separate voltage domains. In some embodiments, the stack storage device 762 includes a power management subsystem for controlling the microchannel voltage domains 764, wherein the power management subsystem 764 includes a dynamic voltage scaling engine for generating signals or commands to adjust the voltage level in each of the microchannels.

[0045] Connectivity 770 includes hardware devices (e.g., connectors and transmission devices for wireless communication, wired communication, or both) and software components (e.g., drivers, protocol stacks) to enable Device 700 to communicate with peripheral devices. Device 700 could be separate devices, such as other computer equipment, wireless access points or base stations, as well as peripheral devices, such as headsets, printers, or other equipment. Connectivity 770 can encompass several different types of connectivity. Generally speaking, Device 700 is represented by cellular connectivity 772 and wireless connectivity 774.Mobile connectivity 772 generally refers to mobile network connectivity provided by mobile network operators, such as 4G / LTE (Long Term Evolution), GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiple Access) or variants or derivatives, or other mobile service standards. Wireless connectivity 774 refers to wireless connectivity that is not mobile. It may include personal networks (such as Bluetooth), local area networks (such as WiFi), wide area networks (such as WiMAX), and other wireless communications. Connectivity may include one or more omnidirectional or directional antennas 776.

[0046] The peripheral connections 780 include hardware interfaces and ports, as well as software components (e.g., drivers, protocol stacks) for establishing peripheral connections. However, it is evident that the Device 700 can be both a peripheral device (“to” 782) to other computer devices and connected to peripheral devices (“from” 784). The Device 700 generally has a “docking” connector to connect it to other computer devices for purposes such as managing (like downloading, uploading, changing, or synchronizing) content on the Device 700. Additionally, a docking connector may allow the Device 700 to connect to certain peripheral devices that enable the Device 700 to, for example, control content output to audiovisual or other systems.

[0047] In addition to a proprietary docking connector or other proprietary connection hardware, the device can establish 700 peripheral connections via common or standards-based connectors. Common types may include a USB port (which may encompass any of a number of different hardware interfaces), DisplayPort, including Mini DisplayPort (MDP), HDMI (High Definition Multimedia Interface), FireWire, or another type.

[0048] Fig. Figure 8 illustrates an embodiment of a computer system including a stack memory. Certain conventional and generally known components not relevant to the present invention are not shown in this illustration. The computer system may comprise a computer, a server, a game console, or another computing device. In some embodiments, the computer system 800 comprises a coupling structure or matrix switch 805 or another means of communication for transmitting data. The computer system 800 may include a processing means, such as one or more processors 810, which are coupled to the coupling structure 805 for processing information. The processors 810 may comprise one or more physical processors and one or more logical processors.For simplicity, coupling structure 805 is illustrated as a single coupling structure; however, it can represent multiple different coupling structures or buses, and the component connections to such coupling structures can vary. The following are shown in... Fig. The coupling structure 805 shown is a generalization in which one or more separate physical buses, point-to-point links, or both are connected by appropriate bridges, adapters, or controllers.

[0049] In some embodiments, the computer system 800 further comprises a random access memory (RAM) or other dynamic storage device or element as main memory 814 for storing information and instructions executed by the processors 810.

[0050] RAM memory comprises Dynamic Random Access Memory (DRAM), which requires updates to its contents, and Static Random Access Memory (SRAM), which does not require updates but is more expensive. In some embodiments, main memory may include the active storage of applications, such as a browser application for use during network browsing activities by a user of the computer system. The DRAM memory may include SDRAM (Synchronous Dynamic Random Access Memory), which has a clock signal for controlling signals, and EDO-DRAM (Extended Data-Out Dynamic Random Access Memory). In some embodiments, the system memory may include specific registers or other specialized memory.In some embodiments, the main memory 814 can comprise a stack memory 815, wherein the stack memory comprises a plurality of microchannels and each microchannel comprises a separate voltage domain that can be controlled by a controller in the stack memory. The stack memory 815 can contain memory as in . Fig. Figures 1-6 are shown.

[0051] The Computer System 800 may also include a Read Only Memory (ROM) 816 or other static storage device to store static information and instructions for the Processors 810. The Computer System 800 may include one or more Permanent Memory Elements 818 for storing specific items.

[0052] In some embodiments, the computer system 800 comprises one or more input devices 830, wherein the input devices may be one or more of the following: keyboard, mouse, touchpad, voice command recognition, gesture recognition or any other device for providing input to a computer system.

[0053] The computer system 800 can also be coupled to an output display 840 via the coupling structure 805. In some embodiments, the display 840 may include a liquid crystal display (LCD) or another display technology to show information or content to a user. In some environments, the display 840 may include a touchscreen that is used, at least in part, as an input device. In some environments, the display 840 may be or include an audio device, such as a loudspeaker, to provide audio information.

[0054] One or more transmitters or receivers 845 may also be coupled to the coupling structure 805. In some embodiments, the computer system 800 may include one or more ports 850 for receiving or transmitting data. The computer system 800 may further include one or more omnidirectional or directional antennas 855 for receiving data via radio signals.

[0055] The Computer System 800 may also include a Power Supply Unit or System 860, which comprises a power supply, battery, solar cell, fuel cell, or other system or device for providing or generating power. The power provided by the Power Supply Unit or System 860 may be distributed to elements of the Computer System 800 as needed.

[0056] The foregoing description includes numerous specific details for explanatory purposes, in order to facilitate a thorough understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be realized without some of these specific details. In other instances, generally known arrangements and devices are shown in the form of block diagrams. Intermediate structures may exist between the illustrated components. The components described or illustrated herein may have additional inputs or outputs that are not illustrated or described.

[0057] Different implementations can involve different processes. These processes can be executed by hardware components, or they can be embedded in a computer program or machine-executable instructions that can be used to instruct a general-purpose or specialized processor, or logic circuits programmed with the instructions, to execute the processes. Alternatively, the processes can be executed by a combination of hardware and software.

[0058] Parts of various embodiments may be provided as a computer program product, which may include a computer-readable medium on which instructions of a computer program are stored, which can be used to program a computer (or other electronic devices) for execution by one or more processors to carry out a process according to certain embodiments.The computer-readable medium may include, but is not limited to, floppy disks, optical discs, CD-ROMs (compact disk read-only memory) and magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or other types of computer-readable medium suitable for storing electronic instructions. Furthermore, embodiments may also be downloadable as a computer program product, wherein the program can be transferred from a remote computer to a requesting computer.

[0059] Many of the methods are described in their most basic form; however, processes can be added to or removed from each of the methods, and information can be added to or removed from any of the described processes without deviating from the basic scope of the present invention. It is obvious to those skilled in the art that many further modifications and adaptations can be implemented. The specific embodiments are not intended to limit the invention but to illustrate it. The scope of the embodiments of the present invention is not determined by the specific examples listed above but only by the following claims.

[0060] When it is stated that an element "A" is coupled with element "B", element A can be directly coupled to element B or indirectly coupled through, for example, element C. If the description or claims state that a component, feature, structure, process, or characteristic A "causes" a component, feature, structure, process, or characteristic B, this means that "A" is at least a partial cause of "B", but that there may also be at least one other component, feature, structure, process, or characteristic that contributes to the causation of "B".If the description states that a component, feature, arrangement, process, or property "may" or "could" be included, that specific component, feature, arrangement, process, or property is not necessarily included. Similarly, if the description or claim refers to "one" element, this does not mean that only one of the described elements is present.

[0061] An embodiment is an implementation or example of the present invention. Reference in the description to "an embodiment," "some embodiments," or "other embodiments" means that a particular feature, arrangement, or property described in connection with the embodiments is included in at least some, but not necessarily all, embodiments. The different occurrences of "an embodiment" or "some embodiments" do not necessarily refer to the same embodiments.It should be self-evident that in the preceding description of embodiments of the present invention, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of simplifying the disclosure and achieving a better understanding of one or more different inventive aspects. However, this method of disclosure should not be interpreted as an intention that the claimed invention requires more features than are expressly cited in each claim. Rather, the inventive aspects, as set forth in the following claims, are contained in fewer than all the features of a single disclosed embodiment. Thus, the claims are expressly an integral part of this description, with each claim standing independently as a separate embodiment of this invention.

Claims

Storage device (100, 200, 300, 400, 500, 600), comprising: a memory stack (220, 420, 520, 610, 620, 630, 640) with multiple coupled memory chips, wherein the memory stack (220, 420, 520, 610, 620, 630, 640) contains a plurality of microchannels, and a logic chip (210, 410, 510) coupled to the memory stack (220, 420, 520, 610, 620, 630, 640), wherein the logic chip (210, 410, 510) contains a memory controller (530), each of the plurality of microchannels containing a separate voltage domain, wherein the memory controller (530) separately controls a voltage for each of the plurality of microchannels, wherein the memory controller (530) includes a traffic tracker (532), and the memory controller (530) detects a change in the voltage of one of the microchannels, which is based at least in part on a traffic pattern for data,wherein the memory controller (530) determines a performance advantage in connection with the change in the voltage of one microchannel, and wherein the logic chip (210, 410, 510) includes a dynamic voltage engine (546) for providing instructions to control the voltage level in each of the plurality of microchannels. Storage device (100, 200, 300, 400, 500, 600) according to claim 1, wherein each of the multiple memory chips contains a plurality of tiles, and wherein each tile of a memory chip is a microchannel that is separate from the other tiles of the memory chip. Storage device (100, 200, 300, 400, 500, 600) according to claim 2, wherein a first tile of a first memory chip and a first tile of a second memory chip are connected via a Through Silicon Via, TSV, for a first channel. Storage device (100, 200, 300, 400, 500, 600) according to claim 1, wherein each memory chip is a microchannel separate from the other memory chips. Storage device (100, 200, 300, 400, 500, 600) according to claim 1, wherein the dynamic voltage engine (546) receives feedback from each microchannel. Storage device (100, 200, 300, 400, 500, 600) according to claim 1, further comprising a voltage generator for each of the microchannels. Storage device (100, 200, 300, 400, 500, 600) according to claim 6, wherein the voltage generators for the plurality of microchannels are located in the logic chip (210, 410, 510). Storage device (100, 200, 300, 400, 500, 600) according to claim 7, wherein the logic element is a power host chip. Storage device (100, 200, 300, 400, 500, 600) according to claim 6, wherein the voltage generators for the plurality of microchannels are located in one or more memory chips of the memory stack (220, 420, 520, 610, 620, 630, 640). Method comprising: tracking the traffic for a first microchannel of a storage device (100, 200, 300, 400, 500, 600), wherein the storage device (100, 200, 300, 400, 500, 600) includes a logic chip (210, 410, 510) coupled with a memory stack (220, 420, 520, 610, 620, 630, 640) of multiple coupled memory chips, and the storage device (100, 200, 300, 400, 500, 600) comprises a plurality of microchannels, each microchannel having a voltage domain and a voltage being controlled separately for each of the plurality of microchannels, detecting a traffic pattern for the first microchannel, and detecting a change in the voltage of the first microchannel, which at least partly based on the traffic pattern for the first microchannel, determining a performance advantage in connection with a change in the voltage of the microchannel, wherein the performance advantage is determined in connection with a change in the voltage of the microchannel,and request for a change in the voltage of the microchannel by a dynamic voltage engine (546) of the logic chip (210, 410, 510). Method according to claim 10, wherein the request for a change in the voltage of the microchannel comprises the generation of a control word directed to a supply generator for the microchannel. Method according to claim 11, wherein the supply generator for the microchannel is located in the logic chip (210, 410, 510). Method according to claim 12, wherein the logic element is a power host chip. Method according to claim 10, wherein the voltage generator for the microchannel is a memory chip of the memory stack (220, 420, 520, 610, 620, 630, 640). The method of claim 10, wherein each of the memory chips contains a plurality of tiles, and wherein each tile of a memory chip is a microchannel separate from the other tiles of the memory chip. System comprising: a processor for processing data of the system, a transmitter, a receiver or both coupled to an omnidirectional antenna for transmitting data, receiving data or both, and a memory for storing data, the memory comprising a stack storage device (100, 200, 300, 400, 500, 600), the stack storage device (100, 200, 300, 400, 500, 600) comprising: a memory stack (220, 420, 520, 610, 620, 630, 640) with multiple coupled memory chips, the memory stack (220, 420, 520, 610, 620, 630, 640) containing a plurality of microchannels, and a connection to the memory stack (220, 420, 520, 610, 620, 630, 640) coupled logic chip (210, 410, 510), wherein the logic chip (210, 410, 510) contains a memory controller (530), wherein each of the plurality of microchannels contains a separate voltage domain, and wherein the voltage level for each of the plurality of microchannels is controlled separately,wherein the memory controller (530) includes a traffic tracker (532), and the memory controller (530) detects a change in the voltage of one of the microchannels, which is based at least in part on a traffic pattern for data, wherein the memory controller (530) determines a performance advantage associated with the change in the voltage of one microchannel, and wherein the logic chip (210, 410, 510) includes a dynamic voltage engine (546) for providing instructions to control the voltage level in each of the plurality of microchannels. System according to claim 16, wherein each of the multiple memory chips contains a plurality of tiles, and wherein each tile of a memory chip is a microchannel that is separate from the other tiles of the memory chip. System according to claim 17, wherein a first tile of a first memory chip and a first tile of a second memory chip are connected via a Through Silicon Via, TSV, for a first channel. System according to claim 16, wherein each memory chip is a microchannel separate from the other memory chips. System according to claim 16, wherein the storage device (100, 200, 300, 400, 500, 600) further includes a voltage generator for each of the microchannels. System according to claim 20, wherein the voltage generators for the plurality of microchannels are located in the logic chip (210, 410, 510). System according to claim 21, wherein the logic chip (210, 410, 510) is a power host chip. System according to claim 20, wherein the voltage generators for the plurality of microchannels are located in one or more memory chips of the memory stack (220, 420, 520, 610, 620, 630, 640). Non-volatile, computer-readable storage medium containing data stored thereon that represents sequences of instructions which, when executed by a processor, cause the processor to perform operations, wherein the operations comprise: tracking traffic for a first microchannel of a storage device (100, 200, 300, 400, 500, 600), wherein the storage device (100, 200, 300, 400, 500, 600) includes a logic chip (210, 410, 510) which is coupled with a memory stack (220, 420, 520, 610, 620, 630, 640) of multiple coupled memory chips, and the storage device (100, 200, 300, 400, 500, 600) comprises a plurality of microchannels, each microchannel having a has a voltage domain and a voltage is controlled separately for each of the multitude of microchannels, detection of a traffic pattern for the first microchannel, detection of a change in the voltage of the first microchannel,which is based at least in part on the traffic pattern for the first microchannel, determining a performance advantage in connection with a change in the voltage of the microchannel, wherein the performance advantage is determined in connection with a change in the voltage of the microchannel, and requesting a change in the voltage of the microchannel by a dynamic voltage engine (546) of the logic chip (210, 410, 510).

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