Radiation-emitting semiconductor chip

Abstract

Radiation-emitting semiconductor chip (1), comprising - a semiconductor body (2) having an active region (20) designed to generate radiation; - a first contact layer (3) comprising a first contact surface (31) for external electrical contacting of the semiconductor chip and a first contact finger structure (35) connected to the first contact surface; - a second contact layer (4) comprising a second contact surface (41) for external electrical contacting of the semiconductor chip and a second contact finger structure (45) connected to the second contact surface, wherein the first contact finger structure and the second contact finger structure overlap in places in a top view of the semiconductor chip; - a current distribution layer (51) which is electrically connected to the first contact layer; - a connecting layer (52) which is electrically connected to the first contact layer via the current distribution layer; - an insulating layer (6) containing a dielectric material, wherein the insulating layer is arranged locally between the connection layer and the current distribution layer; - the insulation layer has at least one opening (60) in which the connection layer and the current distribution layer adjoin each other; and - the diameter of the openings is between inclusive 2 µm and inclusive 6 µm.

Description

[0001] The present application relates to a radiation-emitting semiconductor chip.

[0002] Document US 2012 / 0049234A1 describes a high-brightness light-emitting diode, document DE 102014114674A1 describes a radiation-emitting semiconductor chip, and document US 2010 / 0155752A1 describes a light-emitting semiconductor device.

[0003] For the efficient operation of radiation-emitting semiconductor devices such as LED chips, efficient lateral current distribution is desirable. Metallic contact structures or transparent conductive layers can be used for this purpose. However, this can lead to absorption losses, which reduces the efficiency of the semiconductor chip.

[0004] One task is to specify a radiation-emitting semiconductor chip that is characterized by high efficiency and low absorption losses.

[0005] This problem is solved, among other things, by a radiation-emitting semiconductor chip according to claim 1. Further embodiments and advantages are the subject of the dependent claims.

[0006] A radiation-emitting semiconductor chip comprising a semiconductor body is described. The semiconductor body includes an active region designed to generate radiation. For example, the active region is designed to generate radiation in the ultraviolet, visible, or infrared spectral range. The active region is specifically located between a first semiconductor layer and a second semiconductor layer, wherein the first and second semiconductor layers differ at least partially in their conduction type, such that the active region is situated within a pn junction. The first semiconductor layer, the second semiconductor layer, and the active region can each be single-layered or multi-layered.

[0007] The semiconductor chip has a first contact layer. This first contact layer has a first contact surface for external electrical contacting of the semiconductor chip. For example, the first contact surface is designed for electrical contacting the first semiconductor layer. Furthermore, the first contact layer can have a first contact finger structure connected to the first contact surface. The first contact finger structure is designed for the lateral distribution of charge carriers that are imprinted via the first contact surface during operation of the radiation-emitting semiconductor chip.

[0008] A lateral direction is understood to be a direction that runs parallel to a principal extension plane of the active area. Similarly, a vertical direction runs perpendicular to the principal extension plane of the active area.

[0009] The semiconductor chip has a second contact layer, which provides a second contact surface for external electrical contacting of the semiconductor chip. Specifically, the second contact layer is designed for electrical contacting the second semiconductor layer. For example, the second contact layer has a second contact finger structure connected to the second contact surface.

[0010] Advantageously, there is no direct electrical contact between the first and second contact layers. In particular, a current path between the first and second contact layers runs through the semiconductor body, especially through the active region.

[0011] The first and second contact finger structures overlap, at least partially, when viewed from above on the semiconductor chip. Areas where the first and second contact finger structures overlap can be used for lateral current distribution for contacting both the first and second semiconductor layers. For example, at least 10%, at least 30%, or at least 90% of the first contact finger structure, when viewed from above on the semiconductor chip, lies within the second contact finger structure. The larger this percentage, the more of the semiconductor chip's surface area, which is otherwise unavailable for radiation generation due to the second contact finger structure, can be additionally used for charge carrier distribution via the first contact finger structure.Compared to a radiation-emitting semiconductor chip where the first and second contact layers are arranged side by side without overlap, the area of ​​the active region covered by the contact layers can be reduced. However, one of the contact layers, for example, the first contact layer, can also have at least one contact finger that is formed without overlap with the other, for example, the second, contact layer. In contrast, the first and second contact surfaces are advantageously arranged without overlapping each other, so that both contact surfaces are accessible for external electrical contacting.

[0012] In particular, the first contact finger structure can have a number of contact fingers that is greater than or equal to the number of contact fingers of the second contact finger structure.

[0013] A contact finger structure is generally understood to be an area of ​​a contact layer which, compared to the contact surface intended for electrical contacting, has a comparatively small extent in at least one lateral direction.

[0014] The semiconductor chip has a current distribution layer. The current distribution layer is electrically connected to the first contact layer. For example, the current distribution layer is directly adjacent to the first contact layer. For example, in a top view of the semiconductor chip, the first contact layer is located entirely within the current distribution layer.

[0015] The semiconductor chip has a depletion layer. The depletion layer is electrically connected to the first contact layer, for example, via the current distribution layer. Specifically, the depletion layer is directly adjacent to the semiconductor body, particularly to the first semiconductor layer. For example, the depletion layer is not directly adjacent to the first contact layer at any point.

[0016] The semiconductor chip has an insulating layer. This insulating layer contains, for example, a dielectric material. The dielectric material is a weakly or non-conductive, non-metallic material whose charge carriers are generally not freely mobile – for example, at typical operating currents. The insulating layer contains, for example, at least one of the following materials: silicon nitride, silicon dioxide, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or niobium oxide.

[0017] The insulating layer covers, for example, at least 30%, at least 50%, at least 70%, or at least 90% of the total surface area of ​​the semiconductor chip in top view. For example, the insulating layer covers at most 99% of the total surface area of ​​the semiconductor chip in top view.

[0018] The insulation layer is positioned in certain areas between the connection layer and the current distribution layer, particularly in the vertical direction. Thus, the insulation layer prevents a direct vertical current path between the connection layer and the current distribution layer, at least in certain areas.

[0019] For example, the insulating layer is arranged vertically between the first contact layer and the second contact layer.

[0020] In at least one embodiment of the radiation-emitting semiconductor chip, the semiconductor chip comprises a semiconductor body having an active region for generating radiation. The semiconductor chip comprises a first contact layer having a first contact surface for electrical contacting the semiconductor chip and a first contact finger structure connected to the first contact surface. The semiconductor chip comprises a second contact layer having a second contact surface for external electrical contacting the semiconductor chip and a second contact finger structure connected to the second contact surface, wherein the first contact finger structure and the second contact finger structure overlap in a top view of the semiconductor chip. The semiconductor chip comprises a current distribution layer that is electrically conductively connected to the first contact layer.The semiconductor chip comprises a connection layer that is electrically connected to the first contact layer via the current distribution layer. The semiconductor chip also includes an insulating layer containing a dielectric material, with the insulating layer being positioned at certain points between the connection layer and the current distribution layer.

[0021] According to at least one embodiment of the radiation-emitting semiconductor chip, the insulating layer covers at least 30% of the area of ​​the connection layer. For example, the insulating layer covers at least 50%, at least 70%, or at least 90% of the connection layer. The insulating layer can therefore cover a large area of ​​the connection layer.

[0022] For example, the insulation layer covers the connection layer to a maximum of 95% or a maximum of 99%.

[0023] The insulating layer has at least one opening where the connection layer and the current distribution layer meet. In other words, the connection layer and the current distribution layer are electrically connected in the region of the opening. Specifically, the connection layer and the current distribution layer only meet in this one opening. For example, the opening is surrounded by the insulating layer material along its entire circumference. Alternatively, the opening may be at least partially filled with the current distribution layer material.

[0024] According to at least one embodiment of the radiation-emitting semiconductor chip, the insulating layer has a plurality of openings. The position of these openings allows for adjustment during the manufacturing process of the semiconductor chip, determining where the current distribution layer abuts the connection layer. For example, the openings are configured with respect to their distribution density and / or size such that a uniform current is introduced into the semiconductor chip in the lateral direction. The distance between two adjacent openings is, for example, between 5 µm and 60 µm (inclusive), or between 20 µm and 50 µm (inclusive). The diameter of the openings is, in particular, between 0.5 µm and 20 µm (inclusive). The diameter of the openings is between 2 µm and 6 µm (inclusive).The diameter of a non-circular opening refers to its longest lateral dimension. The openings can also differ in shape and / or size. For example, one or more openings may be provided at the edge of the semiconductor chip that are larger than openings in the center of the chip.

[0025] According to at least one embodiment of the radiation-emitting semiconductor chip, the insulating layer is designed as a filter layer that predominantly transmits incident radiation within a first angular range and predominantly reflects incident radiation within a second angular range. "Predominantly" means, in particular, that at least 60% of the radiation is transmitted or reflected.

[0026] In particular, the angles of the first angular range are smaller with respect to the vertical direction than the angles of the second angular range. Radiation striking the insulating layer at relatively steep angles is therefore predominantly transmitted, while radiation striking at a relatively shallow angle is predominantly reflected. Radiation components that, due to their relatively shallow angle of incidence, could not be coupled out of the semiconductor chip anyway are thus retained at the insulating layer. This reduces radiation absorption losses in downstream layers, such as the current distribution layer. For example, the boundary between the first and second angular ranges is determined by the critical angle of total internal reflection, which can be derived from the refractive index of the semiconductor and the refractive index of the surrounding medium.The first angle range includes angles smaller than this limit. The second angle range, on the other hand, includes angles larger than this limit.

[0027] The insulating layer, which is designed particularly as a filter layer, can consist of a single layer. This means, in particular, that the insulating layer is homogeneous and, for example, made of a single dielectric material. Advantageously, the dielectric material has a matching refractive index, where "matched" means that the refractive index of the dielectric material is greater than or equal to the refractive index of a medium surrounding the insulating layer. The surrounding medium is located downstream of the insulating layer, starting from the semiconductor body. The surrounding medium comprises elements that enclose the semiconductor body and, in particular, provide protection. For example, the semiconductor body can include a passivation layer and / or encapsulation as the surrounding medium.

[0028] In an alternative embodiment, the insulating layer, which is designed particularly as a filter layer, is multilayered and comprises at least two sublayers that differ in their refractive index. Preferably, the filter layer comprises a sequence of alternating sublayers with a higher and a lower refractive index. In particular, the sublayers with a higher refractive index have a smaller thickness than the sublayers with a lower refractive index.

[0029] Preferably, the insulating layer, which is designed particularly as a filter layer, has a thickness between 400 nm and 800 nm inclusive. When determining the thickness of the insulating layer, care must be taken, on the one hand, to keep the manufacturing effort, which is greater for a multilayer structure than for a single-layer structure, within reasonable limits, and on the other hand, to still achieve the desired filter characteristics, which in this case are better achieved with a multilayer structure than with a single-layer structure. A suitable compromise between manufacturing effort and filter characteristics can be achieved with a thickness between 400 nm and 800 nm inclusive.

[0030] According to at least one embodiment of the radiation-emitting semiconductor chip, the insulating layer borders the connection layer and the current distribution layer. Between the connection layer and the current distribution layer, there are therefore, at least in some areas, no other layers besides the insulating layer in the vertical direction. In other words, the insulating layer is, at least in some areas, the only layer located between the connection layer and the current distribution layer.

[0031] According to at least one embodiment of the radiation-emitting semiconductor chip, the depletion layer has a smaller thickness than the current distribution layer. For example, the current distribution layer is at least twice as thick as the depletion layer. For example, the thickness of the depletion layer is between 3 nm and 30 nm inclusive, or between 5 nm and 25 nm inclusive. The thickness of the current distribution layer is, for example, between 30 nm and 200 nm inclusive, or between 50 nm and 150 nm inclusive. Particularly due to its greater thickness, the current distribution layer exhibits higher transverse conductivity than the depletion layer. Conversely, the depletion layer, due to its smaller thickness, also exhibits lower absorption losses for the radiation passing through it.

[0032] Radiation absorption losses in the current distribution layer can be reduced by means of the insulating layer, which acts particularly as a filter layer. In other words, by combining a connection layer and a current distribution layer, and especially an insulating layer arranged vertically between them in certain areas, high transverse conductivity is achieved with simultaneously low absorption losses.

[0033] According to at least one embodiment of the radiation-emitting semiconductor chip, at least 50% of the total area of ​​the second contact finger structure overlaps with the first contact finger structure. In other words, at least half of the area covered by the second contact finger structure is also used for current distribution via the first contact finger structure.

[0034] According to at least one embodiment of the radiation-emitting semiconductor chip, the semiconductor body has at least one recess extending from the radiation-emitting surface through the active region. In particular, the second contact layer is electrically connected to the semiconductor body in the recess. For example, the second contact layer is directly adjacent to the semiconductor body, especially to the second semiconductor layer. For example, at least partially, material from the insulating layer and / or material from the current distribution layer is arranged in the recess.

[0035] However, the recess can also be completely filled with material from the second contact layer.

[0036] According to at least one embodiment of the radiation-emitting semiconductor chip, the insulating layer is arranged between the first contact layer and the second contact layer. The insulating layer thus also serves to electrically isolate the first and second contact layers, so that, in particular, there is no direct current path between these contact layers.

[0037] According to at least one embodiment of the radiation-emitting semiconductor chip, there is no direct vertical current path between the first contact layer and the semiconductor body at any point on the semiconductor chip. Charge carrier injection from the first contact layer into the semiconductor body therefore does not occur directly beneath the first contact layer, but rather at a lateral distance from it. This reduces the proportion of radiation that is generated directly beneath the first contact layer in the active region and is prevented from exiting by the first contact layer.

[0038] According to at least one embodiment of the radiation-emitting semiconductor chip, a dielectric mirror layer is arranged in a region between the semiconductor body and the current distribution layer. For example, the dielectric mirror layer comprises a plurality of layer pairs, wherein the layers of the layer pairs differ from one another with respect to their refractive indices. For example, the dielectric mirror layer has between three and ten sublayers, with adjacent sublayers differing from one another in their refractive index. Preferably, the dielectric mirror layer comprises a sequence of alternating sublayers with higher and lower refractive indices. In particular, the sublayers with higher refractive indices have a smaller thickness than the sublayers with lower refractive indices.

[0039] In particular, the dielectric mirror layer is provided to avoid absorption losses at the first and / or second contact layer.

[0040] The dielectric mirror layer covers, in particular, the side surfaces of the recesses in certain areas. For example, the dielectric mirror layer is arranged in the vertical direction in certain areas between the terminal layer and the current distribution layer, especially between the terminal layer and the insulating layer. This prevents radiation from escaping the semiconductor body at the side surface of the recess and subsequently causing absorption losses at the first and / or second contact layers.

[0041] According to at least one embodiment of the radiation-emitting semiconductor chip, the dielectric mirror layer overlaps the first and second contact layers in a top view of the semiconductor chip. Radiation absorption can thus be avoided or at least reduced at both the first and second contact layers.

[0042] According to at least one embodiment of the radiation-emitting semiconductor chip, the connection layer and / or the current distribution layer contains a TCO material.

[0043] Transparent conductive oxides (TCOs) are transparent, conductive materials, typically metal oxides such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, or indium tin oxide (ITO). Besides binary metal-oxygen compounds like ZnO, SnO₂, or In₂O₃, the TCO group also includes ternary metal-oxygen compounds such as Zn₂SnO₄, CdSnO₃, ZnSnO₃, MgIn₂O₄, GaInO₃, Zn₂In₂O₅, or In₄Sn₃O₁₂, as well as mixtures of different transparent conductive oxides. Furthermore, TCOs do not necessarily have a stoichiometric composition and can also be p- or n-doped.

[0044] The connection layer and the current distribution layer can be made of the same material. Alternatively, the connection layer and the current distribution layer can have different material compositions. For example, the contact layer can be chosen for good contact resistance to the semiconductor body and / or the current distribution layer for high transmission of radiation generated in the active region.

[0045] According to at least one embodiment of the radiation-emitting semiconductor chip, the dielectric mirror layer is arranged in certain areas between the semiconductor body and the second contact layer. For example, the dielectric mirror layer has a recess in which the second contact layer directly abuts the semiconductor body. The dielectric mirror layer prevents, at least in certain areas, the absorption of radiation generated in the active region by the second contact layer.

[0046] According to at least one embodiment of the radiation-emitting semiconductor chip, the second contact layer comprises a reflective layer. Silver or aluminum, for example, are suitable materials for this reflective layer. Silver allows for particularly high reflectivities in the visible spectral range. For example, the reflective layer has a thickness between 300 nm and 2 µm.

[0047] According to at least one embodiment of the radiation-emitting semiconductor chip, the second contact layer includes a contact layer. This contact layer is designed to establish good ohmic contact with the semiconductor body, particularly with the second semiconductor layer. For example, the contact layer has a thickness between 3 nm and 100 nm. The contact layer is specifically located between the mirror layer and the second semiconductor layer. This allows the mirror layer to be made of a material that would otherwise form a comparatively poor contact with the semiconductor body, such as silver to an n-type nitride compound semiconductor material. For example, the contact layer may contain a TCO material, such as ITO or ZnO.In particular, using a TCO material for the contact layer and silver for the mirror layer, a contact layer can be realized that is characterized by high reflectivity and at the same time good electrical contact to the second semiconductor layer.

[0048] According to at least one embodiment of the radiation-emitting semiconductor chip, the second contact layer comprises a barrier layer. In particular, the reflective layer is arranged between the contact layer and the barrier layer. A suitable barrier layer could be, for example, a metal such as Ti, Pt, Cu, or Au, or a TCO material such as ITO or ZnO. The barrier layer could, for example, have a thickness between 30 nm and 400 nm. The barrier layer can encapsulate the reflective layer. Therefore, a material susceptible to migration, for example due to moisture, is also suitable for the reflective layer.

[0049] The materials mentioned and / or at least one or all of the layers can also be used for the first contact layer.

[0050] The following effects, in particular, can be achieved with the described radiation-emitting semiconductor chip.

[0051] The areas where a metal layer, such as the first or second contact layer, is directly adjacent to the semiconductor chip are reduced. This increases the brightness of the radiation-emitting semiconductor chip at the same operating current.

[0052] The insulating layer reduces absorption losses, particularly in the current distribution layer. Even when using a relatively thick current distribution layer to achieve high transverse conductivity, absorption losses are reduced by the insulating layer. In particular, the insulating layer can function as an angle-selective filter layer.

[0053] The areas where the highest current density occurs during operation of the semiconductor chip can be adjusted by means of at least one opening in the insulating layer. In particular, these areas can be laterally spaced from the first contact layer. For example, the areas where the highest current density occurs can also be laterally spaced from the first contact finger structure.

[0054] As a result, the amount of light generated in the active area increases, and the efficiency loss at high operating currents (also known as "droop") is reduced. A higher current density distribution and the associated homogeneous light distribution on the radiation-emitting surface of the semiconductor chip also increases the efficiency of a downstream radiation conversion material, thereby further increasing the brightness of a component with such a radiation-emitting semiconductor chip.

[0055] Furthermore, absorption losses at the second contact layer can also be avoided, for example by means of a dielectric mirror layer. By arranging the dielectric mirror layer on a side surface of the semiconductor chip, for example on the side surface of the recess, absorption losses at the second contact layer can be further avoided or at least reduced.

[0056] The second contact layer itself can be characterized by particularly low absorption losses, especially through a multilayer structure with a contact layer and a mirror layer. Migration effects can be suppressed by the barrier layer, thus increasing the freedom in the choice of material for the mirror layer.

[0057] Further designs and advantages will become apparent from the following description of the exemplary embodiments in conjunction with the figures.

[0058] They show: The Fig. 1A, Fig. 1B and Fig. 1C a first embodiment of a radiation-emitting semiconductor chip in schematic sectional view ( Fig. 1A), in a schematic representation of a section in schematic sectional view ( Fig. 1B) and an enlarged representation of a section of the sectional view in Fig. 1B ( Fig. 1C); the Fig. 2A to 2C Simulation results of current density distributions for a radiation-emitting semiconductor chip according to the present invention ( Fig. 2A) and for comparison structures ( Fig. 2B and Fig. 2C); Fig. 3 a second embodiment of a radiation-emitting semiconductor chip in schematic sectional view; and Fig. 4 A third embodiment of a radiation-emitting semiconductor chip in schematic sectional view.

[0059] Identical, similar, or similarly effective elements in the figures are provided with the same reference symbols.

[0060] The figures are schematic representations and therefore not necessarily to scale. Rather, comparatively small elements and especially layer thicknesses may be exaggerated for clarity.

[0061] In the Fig. Figure 1A shows a first embodiment of a radiation-emitting semiconductor chip 1, wherein Fig. Figure 1B shows a section of this semiconductor chip in a cutaway view. In a top view, the radiation-emitting semiconductor chip can be seen, for example, as in Fig. 2A is shown as being formed.

[0062] The radiation-emitting semiconductor chip 1 comprises a semiconductor body 2 with a sequence of semiconductor layers. The semiconductor body 2 includes, in particular, an active region 20 designed for generating radiation, which is arranged between a first semiconductor layer 21 of a first conductor type (for example, p-type) and a second semiconductor layer 22 of a second conductor type different from the first (for example, n-type). The semiconductor body 2, and in particular the active region 20, is preferably based on a III-V compound semiconductor material, in particular on a nitride compound semiconductor material.

[0063] In this context, "based on nitride compound semiconductor material" means that at least one layer of the semiconductor regions is a nitride III / V compound semiconductor material, preferably Al n Ga m In 1-n-m N comprises, where 0 ≤ n ≤ 1, 0 ≤ m ≤ 1, and n+m ≤ 1. This material does not necessarily have to have a mathematically exact composition according to the formula above. Rather, it can contain one or more dopants as well as additional components that exhibit the characteristic physical properties of Al. n Ga m In 1-n-m The N-materials do not change in essence. For the sake of simplicity, however, the formula above only includes the essential components of the crystal lattice (Al, Ga, In, N), even though these may be partially replaced by small amounts of other substances.

[0064] The semiconductor body 2 is arranged on a support 29. In particular, the support is a growth substrate for the semiconductor layer sequence of the semiconductor body. For a semiconductor body based on nitride compound semiconductor material, for example, sapphire, silicon carbide or gallium nitride are suitable as growth substrates.

[0065] On a radiation emission surface 28 facing away from the support 29, a first contact layer 3 and a second contact layer 4 are arranged. The first contact layer 3 has a first contact surface 31 for the external electrical contacting of the first semiconductor layer 21. The second contact layer 4 has a second contact surface 41 provided for the external electrical contacting of the second semiconductor layer.

[0066] The first contact layer 3 further comprises a first contact finger structure 35, which is connected to the first contact surface 31. Similarly, the second contact layer 4 comprises a second contact finger structure 45, which is electrically connected to the second contact surface 41.

[0067] In the Fig. In the embodiment shown in Figure 2A, the contact finger structures 35, 45 each comprise two contact fingers extending from the respective contact surfaces 31, 41. Each contact finger has a bend, so that together the two contact fingers form a frame-shaped structure. However, other structures are also conceivable, for example, contact fingers that are curved in places, a comb-shaped configuration, or a configuration of the contact finger structures similar to the veining of a leaf. The number of contact fingers can also be varied within wide limits. The number of contact fingers of the first contact finger structure 35 and the second contact finger structure 45 can also differ from each other. For example, the number of contact fingers of the first contact finger structure is greater than the number of contact fingers of the second contact finger structure.

[0068] The first contact finger structure 35 and the second contact finger structure 45 overlap in a top view of the radiation-emitting semiconductor chip. In this way, areas of the semiconductor chip where the active region 20 is already removed for the formation of the second contact finger structure 45 can also be used for current distribution to electrically contact the first semiconductor layer 21.

[0069] In contrast to the described embodiment, the first contact finger structure 35 and the second contact finger structure 45 can also overlap to a smaller percentage. For example, the first contact finger structure 35 can have at least one contact finger that does not overlap with the second contact finger structure 45 over at least half of its main axis of extension.

[0070] The second contact layer 4, in particular the second contact finger structure 45, borders the second semiconductor layer 22 in a recess 25 of the semiconductor body. Thus, by means of the recess, the second semiconductor layer 22, which is covered by the first semiconductor layer 21, is partially exposed for contact with the second contact layer 4.

[0071] An insulating layer 6 is arranged vertically between the first contact layer 3 and the second contact layer 4. The insulating layer 6 partially covers the radiation emission surface 28 of the semiconductor body 2. In the illustrated embodiment, the insulating layer 6 also covers the side surfaces 250 of the recesses 25.

[0072] The semiconductor chip 1 further comprises a current distribution layer 51, which is electrically connected to the first contact layer 3. The radiation-emitting semiconductor chip 1 also comprises a connection layer 52. The connection layer 52 is electrically connected to the first contact layer via the current distribution layer 51. An insulating layer 6 is arranged between the current distribution layer 51 and the connection layer 52 in certain areas, particularly in the vertical direction.

[0073] The insulating layer 6 has a plurality of openings 60 where the current distribution layer 51 and the connection layer 52 adjoin each other. During operation of the radiation-emitting semiconductor chip, the current density injected into the semiconductor chip is highest in a region vertically below the openings 60. The openings in the insulating layer 6 thus define the regions where the current density is highest. Without an insulating layer between the current distribution layer 51 and the connection layer 52, the current density would be highest in the region around the first contact layer 3. In lateral regions further away from the contact layer 3, only a comparatively low charge carrier injection would occur.

[0074] The openings 60 are advantageously arranged laterally such that a current density distribution that is as homogeneous as possible results. In particular, the arrangement of the openings on the radiation emission surface 28 is also selected based on the respective material parameters of the current distribution layer 51 and the connection layer 52 to achieve the most homogeneous current density distribution possible.

[0075] For example, peripheral areas of the radiation emission surface 28 can have more openings than central areas of the radiation emission surface. The distances between the openings can be between 20 µm and 50 µm inclusive. A suitable diameter for the openings is, in particular, between 1 µm and 15 µm inclusive, or, for example, between 2 µm and 6 µm inclusive.

[0076] Despite the openings 60, the insulating layer 6 can cover a large area of ​​the connection layer, for example, at least 30%, at least 50%, or at least 70% of the area of ​​the connection layer as seen from above on the semiconductor chip. For example, the insulating layer covers the connection layer 52 to a maximum of 90% or at most 95%.

[0077] The connection layer 52 has a smaller thickness than the current distribution layer 51. Unlike the current distribution layer 51, the connection layer 52 does not need to have high transverse conductivity. Due to the comparatively small thickness of the connection layer 52, absorption losses in the connection layer can be reduced.

[0078] Viewed from the active region 20, the current distribution layer 51 is at least partially upstream of the insulation layer 6. The insulation layer 6 can, in particular, function as a filter layer, exhibiting a higher reflectivity for radiation traveling at relatively large angles to the normal to the principal plane of extension of the active region 20 than for radiation striking at a relatively small angle to the normal. This allows radiation components that would not be able to exit the semiconductor chip 1 anyway due to total internal reflection to be reflected largely without loss at the insulation layer 6. Absorption losses in the current distribution layer 51 can thus be reduced. The insulation layer can, for example, cover at least 50%, at least 70%, or at least 90% of the total surface area of ​​the semiconductor chip in plan view.Absorption losses can thus be avoided particularly efficiently by means of the insulating layer 6.

[0079] In particular, the transmission of radiation within a first angular range can be increased compared to a conventional semiconductor chip. Here, the first angular range is denoted by angle α, where 0° ≤ α ≤ α tot , where α tot This specifies the critical angle of total internal reflection. For angles α larger than the critical angle α tot , i.e., in a second angular range with α tot For angles < α ≤ 90°, absorption in the described semiconductor chip is significantly reduced compared to a conventional semiconductor chip. The first angular range represents a cone-shaped region with a principal axis parallel to the vertical direction. The critical angle of total internal reflection α totis determined from the refractive index of the semiconductor body 2 and the refractive index of the surrounding medium, where, for example, for a semiconductor body 2 made of GaN with a refractive index n = 2.5 and a surrounding medium with a refractive index n = 1.55, a critical angle α tot = arcsin(1.55 / 2.5) = 38.3° results.

[0080] A particularly efficient filtering effect can be achieved through a multi-layered design of the insulating layer with alternating layers of lower and higher refractive indices. However, a filtering effect can also be achieved with a single-layer insulating layer.

[0081] On the side facing away from the support 29, the radiation-emitting semiconductor chip 1 can be partially sealed by a passivation layer 7. The passivation layer serves in particular to protect the semiconductor body from external stresses such as moisture, dust, or mechanical stress.

[0082] The current distribution layer 51 and the connection layer 52 can each comprise the same material or different materials. Preferably, the current distribution layer and the connection layer contain a TCO material, for example ITO.

[0083] The first contact layer 3 and the second contact layer 4, or at least a sublayer thereof, can each be metallic. This simplifies external electrical contacting of the semiconductor chip 1.

[0084] One possible multi-layered design of the second contact layer 4 is in Fig. 1C shown schematically.

[0085] The second contact layer has a contact layer 42, a mirror layer 43 and a barrier layer 44.

[0086] For example, silver or aluminum are suitable for the reflective coating. Particularly high reflectivities in the visible spectral range can be achieved with silver. For example, the reflective coating has a thickness between 300 nm and 2 µm.

[0087] The contact layer 42 enables good ohmic contact with the semiconductor body, particularly when using a material for the mirror layer 43 that would otherwise provide comparatively poor contact with the semiconductor body, such as silver to an n-type nitride compound semiconductor material. For example, the contact layer has a thickness between 3 nm and 100 nm. The contact layer is specifically located between the mirror layer and the second semiconductor layer. For example, the contact layer contains a TCO material, such as ITO or ZnO. In particular, with a TCO material for the contact layer and silver for the mirror layer, the second contact layer 4 can exhibit high reflectivity and simultaneously provide good electrical contact with the second semiconductor layer.

[0088] For the barrier layer 44, a metal such as Ti, Pt, Cu, or Au, or a TCO material such as ITO or ZnO, is suitable. For example, the barrier layer has a thickness between 30 nm and 400 nm. The mirror layer 43 can be encapsulated by means of the barrier layer. Therefore, a material that is susceptible to migration, for example due to moisture, is also suitable for the mirror layer; silver is particularly suitable.

[0089] The first contact layer 3 can also be multilayered and contain at least one of the materials described in connection with the second contact layer.

[0090] Simulation results of the lateral current density distribution for a radiation-emitting semiconductor chip 1 described above are presented in Fig. Figure 2A shows areas of the semiconductor body with high current density in light and areas with low current density in dark. By laterally separating the direct charge carrier injection via the terminal layer 52 into the semiconductor body 2 from the position of the contact finger structure 35, the homogeneity of the charge carrier density in the lateral direction can be significantly increased.

[0091] This becomes clear based on simulation results for comparison structures, which are presented in the Fig. 2B and Fig. 2C are shown. In the Fig. In the semiconductor chips shown in Figure 2C, a first contact structure 91 and a second contact structure 92 are arranged next to each other without overlap. As a result, a comparatively large proportion of the surface area of ​​the semiconductor chip 1 is lost to radiation generation due to the large total area of ​​the contact structures 91 and 92.

[0092] At the in Fig. In the embodiment shown in Figure 2B, the first contact structure 91 and the second contact structure 92 overlap in a top view of the semiconductor chip. Due to the smaller metal-covered area, absorption losses are also reduced. However, a significantly increased current density results in the immediate vicinity of the superimposed contact bridges, since the charge carriers choose the shortest current path between the contact bridges and the structure of the semiconductor chip, unlike the present invention, does not provide any countermeasures for this. Therefore, a laterally homogeneous current induction does not occur.

[0093] In contrast, the described radiation-emitting semiconductor chip allows absorption losses to be significantly minimized compared to the state of the art, and furthermore, the homogeneity of the current density distribution in the lateral direction can also be increased.

[0094] The in Fig. The second embodiment shown in section 3 essentially corresponds to the one described in connection with the Fig. 1A, Fig. 1B and Fig. 1C described first embodiment.

[0095] In contrast, the radiation-emitting semiconductor chip 1 additionally features a dielectric mirror layer 65. The dielectric mirror layer 65 is arranged in certain areas between the semiconductor body 2 and the first contact layer 3. In particular, the dielectric mirror layer 65 overlaps the first contact layer 3 and the second contact layer 4. The dielectric mirror layer 65 has a recess 650 in which the second contact layer 4 abuts the semiconductor body 2, in particular the second semiconductor layer 22. The dielectric mirror layer 65 has, for example, a plurality of layer pairs, wherein the layers of each layer pair have different refractive indices. The materials specified for the insulating layer in the general part of the description are particularly suitable for the dielectric mirror layer.The individual sub-layers of the dielectric mirror layer are not explicitly shown in the figure for the sake of simplicity.

[0096] The dielectric mirror layer 65 prevents radiation absorption at the second contact layer 4. This is illustrated by an arrow 8, which indicates radiation reflected by the dielectric mirror layer 65. Furthermore, the dielectric mirror layer 65 also covers the side surface 250 of the recess 25. This prevents radiation exiting through this side surface from being absorbed at the first contact layer 3 or at the second contact layer 4.

[0097] The dielectric mirror layer is arranged, in particular, in certain areas between the insulating layer 6 and the semiconductor body 2. Furthermore, viewed vertically, the dielectric mirror layer 65 extends in certain areas between the current distribution layer 51 and the connection layer 52. Alternatively, the dielectric mirror layer 65 and the connection layer 52 can also be arranged without overlapping. The current distribution layer 51 can completely cover the dielectric mirror layer 65 when viewed from above on the semiconductor chip.

[0098] The in Fig. The third embodiment shown in section 4 essentially corresponds to the one described in connection with Fig. 3 described second embodiment.

[0099] In contrast, the recess 25 is completely or at least almost completely filled with material from the dielectric mirror layer 65 and the second contact layer 4. In this embodiment, the electrical contact of the second semiconductor layer 22 is achieved via adjacent recesses 650 in the dielectric mirror layer 65.

[0100] Preferably, the lateral extent of the recesses 650 is also limited along a lateral principal extension direction of the associated contact finger of the second contact finger structure 45. The recesses are thus surrounded along their entire circumference by material of the dielectric mirror layer. In other words, the second contact finger structure 45 can be completely covered with material of the dielectric mirror layer, at least at some points along the principal extension direction of the associated contact finger, in a lateral transverse direction to the principal extension direction of the contact finger. Radiation absorption losses at the second contact layer 4 can thus be further reduced.

[0101] Furthermore, in the Fig. 4 A passivation layer 7 is formed on the side of the semiconductor body 2 facing away from the support 29. This passivation layer can also be used in the Fig. The 3 shown embodiment can be used.

[0102] In the lateral direction, the contact finger of the first contact finger structure 35, which overlaps with the recess 25, has a smaller lateral extent than the associated contact finger of the second contact finger structure 45. Absorption losses at the second contact finger structure can thus be further reduced.

[0103] This patent application claims priority over German patent application DE 10 2016 112 587 A1. Reference symbol list 1 radiation-emitting semiconductor chip 2 Semiconductor bodies 20 active area 21 first semiconductor layer 22 second semiconductor layer 25 Exclusion 250 side area 28 Radiation emission surface 29 carriers 3 first contact layer 31 first contact surface 35 first contact finger structure 4 second contact layer 41 second contact surface 42 contact layer 43 Mirror layer 44 Barrier layer 45 second contact finger structure 51 Power distribution layer 52 Connection layer 6 Insulation layer 60 opening 65 dielectric mirror layer 650 recess 7 Passivation 8 Arrow 91 first contact structure 92 second contact structure

Claims

[1] Radiation-emitting semiconductor chip (1), comprising - a semiconductor body (2) having an active region (20) designed to generate radiation; - a first contact layer (3) comprising a first contact surface (31) for external electrical contacting of the semiconductor chip and a first contact finger structure (35) connected to the first contact surface; - a second contact layer (4) comprising a second contact surface (41) for external electrical contacting of the semiconductor chip and a second contact finger structure (45) connected to the second contact surface, wherein the first contact finger structure and the second contact finger structure overlap in places in a top view of the semiconductor chip; - a current distribution layer (51) which is electrically connected to the first contact layer; - a connecting layer (52) which is electrically connected to the first contact layer via the current distribution layer; - an insulating layer (6) containing a dielectric material, wherein the insulating layer is arranged locally between the connection layer and the current distribution layer; - the insulation layer has at least one opening (60) in which the connection layer and the current distribution layer adjoin each other; and - the diameter of the openings is between inclusive 2 µm and inclusive 6 µm. [2] Radiation-emitting semiconductor chip according to claim 1, wherein the insulating layer covers the connection layer to at least 30% of the area of ​​the connection layer. [3] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein the diameter of the openings is between 1 µm inclusive and 20 µm inclusive. [4] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein the insulating layer is designed as a filter layer which predominantly transmits radiation incident within a first angular range and predominantly reflects radiation incident within a second angular range. [5] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein the insulation layer is adjacent to the connection layer and the current distribution layer. [6] Radiation-emitting semiconductor chip according to any of the preceding claims, wherein the connection layer has a smaller thickness than the current distribution layer. [7] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein the first contact surface and the second contact surface are accessible for external electrical contacting from a radiation-emitting surface (28) of the semiconductor body. [8] Radiation-emitting semiconductor chip according to any of the preceding claims, wherein at least 50% of the total area of ​​the second contact finger structure overlaps with the first contact finger structure. [9] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein the semiconductor body has at least one recess (25) extending from the radiation-emitting surface through the active area and wherein the second contact layer is electrically connected to the semiconductor body in the recess. [10] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein the insulating layer is arranged between the first contact layer and the second contact layer. [11] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein there is no direct vertical current path between the first contact layer and the semiconductor body at any point in the semiconductor chip. [12] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein a dielectric mirror layer (65) is arranged in certain areas between the semiconductor body and the current distribution layer. [13] Radiation-emitting semiconductor chip according to claim 12, wherein the dielectric mirror layer overlaps the first contact layer and the second contact layer in a top view of the semiconductor chip. [14] Radiation-emitting semiconductor chip according to claim 12 or 13, wherein the dielectric mirror layer is arranged locally between the semiconductor body and the second contact layer. [15] Radiation-emitting semiconductor chip according to one of claims 12 to 14, wherein the dielectric mirror layer comprises a sequence of alternating sublayers with a higher refractive index and a lower refractive index. [16] Radiation-emitting semiconductor chip according to any of the preceding claims, wherein the connection layer and / or the current distribution layer contains a TCO material. [17] Radiation-emitting semiconductor chip according to one of the preceding claims, wherein the second contact layer comprises a contact layer (42), a mirror layer (43) and a barrier layer (44), wherein the mirror layer is arranged between the contact layer and the barrier layer. [18] Radiation-emitting semiconductor chip according to claim 17, wherein the contact layer contains a TCO material and the mirror layer contains silver.

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