Multiplier circuit

Abstract

Multiplier Circuit This description relates to a circuit configured to perform a multiplication operation between a first value and a second value, the first and second values ​​each comprising up to N pieces of bits respectively, the circuit comprising: - an NMUL number of multiplier subcircuits configured to generate first partial products, each first partial product corresponding to a multiplication between a piece from among the pieces of the first value and a piece from among the pieces of the second value; - an adding part configured to generate a first intermediate sum and first excess bit values, from the first partial products;and a parallel adder configured to generate a value corresponding to the product between the first and second values ​​from the first intermediate sum and the first integer bit generated by the first adder circuit and the second processing circuit. Figure for the abbreviation: Fig. 5;

Description

Title of the invention: Multiplier circuit technical field

[0001] This description relates generally to multiplier circuits and in particular to circuits configured to perform multiplications between high-precision data. Previous technique

[0002] The hardware constraints of multiplier circuits impose a limitation on the bit width of the data manipulated. This limitation on the bit width is due to the circuit's timing constraints. The larger the bit width of the multiplier inputs, the lower the maximum frequency that the hardware multiplier can achieve. For example, the maximum bit width can also be chosen from the bit widths supported by the host processor. For each frequency, there is a maximum bit width for each arithmetic unit.

[0003] There is a need to improve the architecture of the multiplier circuits in order to reduce the latency time in multiplications between data, and in particular between high-precision data. Summary of the invention

[0004] One embodiment provides a circuit configured to perform a multiplication operation between a first value and a second value, the first and second values ​​each comprising up to N pieces of n bits, 11 being an integer greater than or equal to 2, the circuit comprising: - an NMUL number of multiplying subcircuits, NMUL being an integer, configured to generate first partial products, each first partial product corresponding to a multiplication between a piece among the pieces of the first value and a piece among the pieces of the second value; - an adding part configured to generate a first intermediate sum and first excess bit values, from the first partial products; and - a parallel adder configured to generate a value corresponding to the product between the first and second values ​​from the first intermediate sum and the first integer bit generated by the first adding circuit and the second processing circuit.

[0005] According to one embodiment, the NMUL multiplying subcircuits are configured to generate the first partial NMUL products in response to the circuit's reception of a first significant edge of a clock signal, and wherein the adding portion is configured to generate the first intermediate sum in response upon receiving a second significant edge of the clock signal, subsequent to the first significant edge, the NMUL multiplier subcircuits are configured to generate second partial products in response to the reception of the second significant edge of the clock signal.

[0006] According to one embodiment, the above circuit further comprises: - a first transverse circuit configured to receive the first partial products generated by the NMUL multiplying sub-circuits and to supply them to the adding section; and - an intermediate memory configured to store the first intermediate sum and the first excess bits generated by the adding part and to provide them to the parallel adder.

[0007] According to one embodiment, the adding part is configured to generate 2N-1 intermediate sums and 2N-2 excess bit values ​​following the reception of a log2(NMUL) number of clock signals, the intermediate memory being configured to provide the 2N-1 intermediate sums and the 2N-2 excess bit values ​​to the parallel adder, the parallel adder being configured to deliver as output the product between the first and second values ​​by adding the 2N-1 intermediate sums and the 2N-2 excess bit values.

[0008] According to one embodiment, the intermediate memory comprises first, second and third regions, and the adding part is configured to store a maximum of N intermediate sums in the first region and a maximum of Nl intermediate sums in the second region, and to store the excess bit values ​​in the third region.

[0009] According to one embodiment: - the n least significant bits of a first intermediate sum, among the at most N intermediate sums, stored in the second region, are stored in the same memory column as the n most significant bits of a second intermediate sum stored in the first region; - the n most significant bits of the first intermediate sum stored in the second region are stored in the same memory column as the n least significant bits of a third intermediate sum stored in the first region.

[0010] According to one embodiment, the above circuit further comprises: - a second transverse circuit configured to receive at least one piece from among the pieces of the first value and at least one piece from among the pieces of the second value; and - a control unit configured to tell the second cross circuit which pieces to supply to which multiplier sub-circuit.

[0011] According to one embodiment, the control unit is clocked by the clock signal and is configured to: - upon receiving the first significant edge of the clock signal, control the second transverse circuit to supply a first piece of the first value and a first piece of the second value to a first multiplier sub-circuit; and - upon receiving the second significant edge of the clock signal, subsequent to the first significant edge, cause the supply of a first partial product, generated by the first multiplier sub-circuit, to the adding part and command the second transverse circuit to supply a second piece of the first value and a second piece of the second value to the first multiplier sub-circuit.

[0012] According to one embodiment, the control unit is configured to control the second transverse circuit directly or through the transmission of additional control bits included in the first chunks of the first and second values.

[0013] According to one embodiment, the control unit is further configured to, upon receiving the first and / or second significant edge of the clock signal, control the second transverse circuit to provide a third piece of the first value and a third piece of the second value to a second multiplier subcircuit.

[0014] According to one embodiment, n is equal to at least 2 and for example to 16 or 32 or 64 or 128.

[0015] According to one embodiment, the integer NMUL is equal to an integer between 2 and N2-

[0016] According to one embodiment, the adding part comprises one or more adding trees configured to perform addition operations in parallel.

[0017] One embodiment proposes a method for multiplying a first and a second value by a circuit, the first and second values ​​each comprising up to N pieces of n bits, N being an integer greater than or equal to 2 and 11 being an integer, the method comprising: - the generation of first partial products, by NMUL multiplying sub-circuits, NMUL being an integer, of the circuit, each partial product corresponding to a multiplication between a piece among the pieces of the first value and a piece among the pieces of the second value; - the generation of a first intermediate sum and a first value of excess bits, by an adding part of the circuit, from the first partial products; and - the generation of a value corresponding to the product between the first and second values, by a parallel adder of the circuit, from the first intermediate sum and the first integer bit.

[0018] According to one embodiment, the pieces of the first value and the pieces of the second value are supplied to a first transverse circuit coupled to the NMUL multiplier subcircuits and a control unit is configured to indicate to the first transverse circuit which pieces to supply to which multiplier subcircuits.

[0019] According to one embodiment, the control unit is controlled by a clock signal and the control unit is further configured to: - upon receiving the first significant edge of the clock signal, control the first transverse circuit to supply a first portion of the first value and a first portion of the second value to a first multiplier sub-circuit; and - upon receiving a second significant edge of the clock signal, subsequent to the first significant edge: trigger the supply of a first partial product, generated by the first multiplication circuit from the first pieces, to the first addition circuit and / or the second processing circuit; and command the first cross circuit to supply a second piece of the first value and a second piece of the second value to the first or second multiplier sub-circuit.

[0020] According to one embodiment, the above process further comprises: - the generation of 2N-1 intermediate sums and 2N-2 excess bit values ​​by the adding part in response to the reception of at least N clock signals, and their storage in an intermediate memory; and - the provision of the 2N-1 intermediate sums and the 2N-2 excess bit values ​​to a parallel adder, the parallel adder being configured to generate the product between the first and second values ​​by adding the 2N-1 intermediate sums and the 2N-2 excess bit values. Brief description of the figures

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0022] Figure [1] illustrates a multiplication between two input data values, according to one embodiment of the present description;

[0023] [Fig.2A] illustrates an example of ordering sub-multiplications of mantissa pieces, according to an embodiment of the present description;

[0024] [Fig.2B] illustrates an example of scheduling micro-instructions included in a control unit, according to an embodiment of the present description;

[0025] [Fig.2C] illustrates the latency time of a multiplication between two data values ​​comprising pieces, according to an embodiment of the present description;

[0026] Figure 3A illustrates an example of micro-instruction scheduling, according to a another way of implementing this description;

[0027] [Fig.3B] illustrates an example of the latency time of a multiplication between two data values ​​comprising pieces of mantissa, according to another embodiment of the present description;

[0028] [Fig. 4] is a diagram illustrating the addition, by an accumulator, of intermediate sums; and

[0029] [Fig.5] illustrates a circuit configured for the multiplication of two data values, according to an embodiment of the present description. Description of the implementation methods

[0030] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0032] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements, such as buffer memories.

[0033] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean at 10%, preferably at 5%.

[0035] Figure 1 illustrates a multiplication between two mantissas 100 and 102 of two operands A and B. In particular, Figure 1 illustrates the Comba multiplication algorithm. Both mantissas 100 and 102 are fixed-point values. By way of example, the mantissa 100 comprises one or more integer bits and the mantissa 102 comprises one or more integer bits Ib. The mantissa 100 further comprises, for example, 4 pieces a0, a1, a2, and a3, each comprising a plurality n of bits. For example, a0 comprises the n most significant bits of the decimal part of the mantissa 100, and a3 comprises the n least significant bits of the decimal part of the value of the mantissa 100. Similarly, the mantissa 102 further comprises 4 pieces b0, b1, b2, and b3, each comprising n bits. For example, b0 comprises the n most significant bits of the decimal part of the mantissa 102, and b3 comprises the n least significant bits of the decimal part of the value of the mantissa 102. In general, a mantissa as described here comprises an integer part, composed of a number of bits, and a number N of n-bit pieces, of which L pieces are valid. In particular, the integer N indicates the maximum number of n-bit pieces.Thus, a mantissa with fewer than N n-bit segments is still represented by the N n-bit segments, but only L of these segments are valid, corresponding, for example, to the segments with non-zero values. Furthermore, when multiplying two mantissas, for example, mantissas 100 and 102, even if they contain the same number N of available n-bit segments, these two mantissas do not necessarily have the same number of integer bits, or the same number L of valid n-bit segments. In what follows, the integers La and Lb refer respectively to the L n-bit segments that are valid for operands A and B, respectively. In the particular case illustrated in [Fig. 1], the number of valid segments for each of the two operands is 4.For example, for an operand C with N = 4 and having two valid n-bit chunks c0 and cl, i.e., L = 1, C is represented by an integer part and 4 chunks c0, cl, c2, and c3, among which chunks c2 and c3, for example, contain only bits equal to 0 or are ignored for multiplication. When multiplying operands A and C, partial products containing c2 and c3 are null by definition.

[0036] In addition, the integers Ja and refer respectively to the lengths of the integer parts la and Ib of the operands A and B.

[0037] In one embodiment, the number n of bits in each piece is equal to 16, 32, 64 or 128, but could more generally be equal to any integer value of 2 or more.

[0038] In one embodiment, the NMUL number of multipliers is equal to an integer between 2 and N2-

[0039] Multiplication between mantissas 100 and 102 produces a mantissa 104. The decimal part of the mantissa 104 comprises, for example, 8 pieces r0 to r7, each comprising, for example, n bits, and a piece rib corresponding to an integer part of the mantissa 104, depending, for example, on the ya bits of the integer part la and the yb bits of the integer part Ib.

[0040] By way of example, the multiplication of two mantissas involves the calculation of several partial products. Each partial product corresponds to the product between one piece of mantissa 100 and another piece of mantissa 102. In particular, for two mantissas comprising a number L of pieces, the multiplication involves the calculation of I? partial products. In the example in [Fig. 1], the 16 partial products correspond to the products involving the pieces a0 to a3 and b0 to b3 and the integer parts a1 and Ib.

[0041] By way of example, the partial products are grouped into groups 11 to 17, each comprising between 1 and 4 partial products. Groups 11 and 17 each comprise a single partial product ( / ^*2” + M) ) * ( la*?? + ) ct a3*b3 respectively. In particular, the partial product of group 17 is (la*?? + ) *\lb*2? + bO ) ■ Groups 12 and 16 each contain two partial products a3*b2, a2*b3, ekll*(lb*2n + bQ) > (Ia*2n + a())*b 1 respectively. Groups 13 and 15 each contain three partial products a3*bl, a2*b2, al*b3 and a2*( Ib*2n + a0) , al*bl and b2*(la*? + aQ) ■> respectively. Group 14 comprises the four partial products a²*(Ib*2n + bQ), a²*b₁, a₁*b₂, and #²*(la*?? + a&Y). In what follows, any integer bit la or Ib, denoted as separated by the " " sign, with a product of bits, refers to the concatenation as described above. In particular, multiplications involving the bit a₀ and / or the bit b₀ are further based on the corresponding integer bit la and / or Ib.The sizes of the groups that do not involve the integer parts la and Ib are 2n, the sizes of the groups involving only the integer part la are ya + 2n, the sizes of the groups involving only the integer part Ib are yb + 2n, and the sizes of the groups involving both integer parts la and Ib are {ya + yb^ + 2«. .

[0042] Referring again to the example in Figure 1, the intermediate sums s1 to s7 correspond to the 2n least significant bits of the resulting sum of the partial products of the same group. For example, the intermediate sum s1 corresponds to the 2n bits of the partial product a3*b3, and the intermediate sum s2 is equal to the 2n least significant bits of the sum of the partial products of group 12. For each group sum, the parts 2 to 11 are called excess bits and correspond respectively to the bits of the sum of each partial product that exceed the 2n bits of the intermediate sum s2 to s7. In other words, each sum of the partial products of the same group is a value encoded by 2n + 3 bits, where P is an integer representing the number of excess bits, possibly equal to 0, and dependent on the group. For example, P is always equal to zero for the sum of group 11.For the sums of the other groups, the integer P depends on the length of the parts. integers la and / or Ib and the number of elements in the group. In particular, P is equal to maxsize(la, Ib) + ceil(logl (K) ), where K is the size of groups 11 to 17.

[0043] In general, there are as many intermediate sums as there are groups of partial products, i.e., {La+ !)*(£ / > +1) - 1 in the case where the two mantissas comprise L pieces of n valid bits. Each intermediate sum sm, 1 < / « < (La + 1 )*(Lb +1)-1, corresponds to the 2n least significant bits of the sum of the elements of group 1m. One or more integer bits am correspond to the excess bits that exceed 2n bits. In particular, for each 1 <m< ( La + 1 ) * ( Lb + 1 ) -1, la concaténation de am avec sm correspond à la somme des produits partiels du groupe 1m.

[0044] By way of example, the n least significant bits of the intermediate sum si correspond to the piece r7 representing the n least significant bits of the multiplication of the two mantissas. The n most significant bits of the intermediate sum si are, for example, added to the n least significant bits of the intermediate sum s2 to generate the n-bit piece r6, taking into account the carry propagation in the addition. Indeed, when adding the n most significant bits of the intermediate sum si to the n least significant bits of the intermediate sum s2, a carry bit may appear. In particular, the pieces r0 to r7 are n-bit pieces, corresponding to the n least significant bits of an addition between the n most significant bits of one intermediate sum and the n least significant bits of another intermediate sum, and involving carry bits from the addition of the intermediate sums.The propagation of these carry bits is described in more detail in Figures 4 and 5.

[0045] Generally, for mantissas comprising L n-bit chunks, the n least significant bits of an intermediate sum s(i+1) are added to the n most significant bits of the intermediate sum si. Thus, each of these sums corresponds to an n-bit chunk r of the product of the two mantissas and to an integer bit to be taken into account for calculating the chunk from the sums s(i+1) and s(i+2). In the prior art, these intermediate sums are added iteratively, one after the other, propagating the carry among the accumulations.

[0046] Figure 2A illustrates an example of scheduling partial multiplications of mantissa chunks, according to an embodiment of the present description. In one embodiment, the multiplications between two mantissas are performed by a general circuit. In one embodiment, the general circuit comprises a number NMUL of multiplying circuits, NMUL being an integer greater than or equal to 2. In some examples, the integer NMUL is equal to the maximum number N of n-bit chunks in the mantissas. In another example, the integer NMUL is equal to <y2- Plus Generally, the NMUL number of multiplying circuits is an integer between 2 and ÿy2-

[0047] According to one embodiment, the NMUL multiplier circuits are configured to operate in parallel. For example, in the case where NMUL is equal to 4, four multiplier circuits x1, x2, x3 and x4 are configured to calculate the partial products of one or more groups 11 to 17, described in relation to [Fig.1] and with N = 4, in parallel and over several calculation cycles.

[0048] By way of example, the multipliers xl to x4 are configured to calculate, in a first cycle (CYCLE), the partial products of groups 11 and 13. For example, the multipliers xl, x2 and x3 are configured to calculate the partial products of group 13 and the multiplier x4 is configured to calculate the partial product of group 11. By way of example, during this first cycle, the multiplier circuits xl, x2, x3 and x4 are respectively configured to calculate the products a3*bl, a2*b2, al*b3 and al*b3.

[0049] By way of example, the multipliers xl to x4 are configured to calculate, in a second calculation cycle, for example following the first calculation cycle, the partial products of groups 12 and 16. By way of example, the multipliers xl and x2 are configured to calculate the partial products of group 12 and the multipliers x3 and x4 are configured to calculate the partial products of group 12. For example, the multipliers xl, x2, x3 and x4 are respectively configured to calculate the partial products a1*Ib b0, a1 a0*bl, a3*b2 and a2*b3.

[0050] By way of example, the multipliers xl to x4 are configured to calculate, in a third calculation cycle, for example following the second calculation cycle, the partial products of group 14. By way of example, the multipliers xl, x2, x3 and x4 are respectively configured to calculate the partial products a3*Ib bO, a2*bl, al*b2, and la a0*b3.

[0051] For example, the multipliers xl to x4 are configured to calculate, in a fourth calculation cycle, for example following the third calculation cycle, the partial products of groups 15 and 17. As an example, the multiplier xl is configured to calculate the partial product of group 17 and the multipliers x2, x3 and x4 are configured to calculate the partial products of group 15. As an example, the multipliers xl, x2, x3 and x4 are respectively configured to calculate the partial products la a0*Ib bO, a2*Ib bO, al*bl, and la a0*b2.

[0052] Groups 11 to 17 are thus reorganized so that the four multipliers xl to x4 all operate in parallel over a plurality of calculation cycles. Thus, the 16 partial products are calculated by the four multipliers xl to x4 over four calculation cycles, for example, a calculation cycle lasting one or more cycles. clock. In this example, no multiplier circuit is inactive during any of the calculation cycles.

[0053] In the example where the number of valid pieces LA and LB is equal to the number NMUL of multiplier circuits, the 2N-1 groups of partial products are grouped such that in each cycle, the NMUL multipliers each calculate a partial product within the same group. For example, one calculation cycle is reserved for calculating the NMUL partial products of the group containing NMUL partial products. For example, the partial product of one of the two groups, for example groups 11 and 1(2*NMUL-1), for example group 1(2*NMUL-1) is group 17 in the case where NMUL is equal to 4, is calculated by a multiplier during the same cycle as the calculation of Nl partial products belonging to one of the groups containing Nl partial products, for example groups 13 and 1(NMUL-3). For example, if N = 4 and NMUL = 8, in the first clock cycle, the partial products of groups 14, 13 and 11 are calculated.In a second clock cycle, the partial products of groups 15, 12, 16 and 17 are calculated.

[0054] By way of example, each calculation cycle is triggered by the general circuit receiving a significant edge of a clock signal. The term "significant edge" refers to one of the edges of the clock cycle configured to trigger the operations performed by the general circuit. These significant edges can be either rising edges, falling edges, or both rising and falling edges.

[0055] Figure 2B illustrates an example of instructions 200 stored in memory or logically encoded, for example by a finite state machine, of a control unit for the multiplier circuits, according to an embodiment of the present description. By way of example, the instructions 200 allow pieces of each of the mantissas to be supplied to the multiplier circuits.

[0056] For example, instructions 200 comprise a plurality of micro-instructions stored in read-only memory (ROM). The addresses of the micro-instructions are, for example, defined such that, knowing the number of valid chunks La and Lh, it is possible to deduce a first address to be executed. Each micro-instruction includes, for example, information indicating which chunks should be multiplied by each of the multiplier circuits. Each micro-instruction also includes, for example, other information associated with the addition of partial products. As an example, the address of a micro-instruction is in the form ^A^B-^^micro, where Nbmicro corresponds to the number of the micro-instruction. For example, in the case where N = NMUL = 4, La = 0, Lb = 3, the micro-instructions comprise, for example, a single micro-instruction.For example, in the case where N = NMUL = 4, La = 3, Lb = 3, the micro-instructions include, for example, only 4 micro-instructions.

[0057] In the example of operands A and B, each comprising 4 valid pieces, and in which the general circuit comprises 4 multiplier circuits, an instruction line 202, for example stored at an address (@) 4.4.0 of a memory, for example a read-only memory (ROM), of the general circuit, internal or external to the general circuit, directs the provision of the pieces involved in the calculation of the partial products of group 13 to the multipliers x1, x2 and x3 as well as the provision of the pieces involved in the partial products of group 11 to the multiplier x4. An instruction line 204, for example stored at an address 4.4.1 of the memory, directs the provision of the pieces involved in the calculation of the partial products of group 16 to the multipliers x1 and x2 as well as the provision of the pieces involved in the calculation of the partial products of group 12 to the multipliers x3 and x4. A line of instruction 206, for example stored at address 4.4.2 of memory, commands the provision of the pieces involved in the calculation of the partial products of group 14 to the multipliers xl, x2, x3 and x4. A line of instruction 208, for example stored at memory address 4.4.3, commands the provision of the pieces involved in the calculation of the partial product of group 17 to the multipliers xl as well as the provision of the pieces involved in the calculation of the partial products of group 15 to the multipliers x2, x3 and x4. .

[0058] By way of example, instructions 202 to 208 are transmitted to the multiplier circuits following the reception, for example by the main circuit, of consecutive significant edges of the clock signal. Furthermore, instructions 202 to 208 include additional information concerning the path of each digital data point through the main circuit.

[0059] Addresses 4.4.0 to 4.4.3 are given by way of example and are of course not exhaustive. Similarly, the order of instructions, as well as groupings, for example of group 13 with group 11, etc., are given by way of example and are of course not exhaustive.

[0060] Figure 2C illustrates an example of scheduling micro-instructions in the multiplier circuit pipeline using a Gantt chart, according to an embodiment of the present description. In particular, Figure 2C illustrates a calculation of the partial products and intermediate sums described in relation to Figure 1 and under partial control of instructions 200. In particular, the order of the partial products illustrated in relation to Figure 2C is the same as that described in relation to Figure 2A.

[0061] By way of example, during a first calculation cycle (CYCLE), the multipliers xl to x4 calculate the partial products (PPM) associated with groups 11 and 13. During a second calculation cycle, the multipliers xl to x4 then calculate the partial products (PPM) associated with groups 12 and 16. During this second cycle, The general circuit is further configured to calculate the sums (ADD1, ADD2) of the partial products. As an example, the general circuit also includes one or more adder trees configured to add the partial products, an example of which is described below in relation to Figure 5. For example, one adder tree is configured to generate the intermediate sum s1 during the second calculation cycle. The intermediate sum s1 is then stored in a memory location within the general circuit. Furthermore, during the second cycle, another adder tree is configured to receive as input the three partial products of group 13 and to generate a portion of the intermediate sum s3. For example, this other adder tree is configured to generate the intermediate sum s3 and the excess bits '3' over two calculation cycles.In other words, during a third calculation cycle, the other adding tree is configured to generate the intermediate sum s3 and the excess bits '3' from the sums obtained during the second calculation cycle. As an example, the intermediate sum s3 and the excess bits '3' are then stored in a memory of the general circuit.

[0062] By way of example, during the third calculation cycle, the multipliers x1 to x4 calculate the partial products associated with group 14. For example, during the third cycle, the adder trees are further configured to calculate the intermediate sums s2 and s6 and the excess bits a2 and a6, from the partial products generated during the second cycle. Since the intermediate sums s2 and s6 and their excess bits a2 and a6 are each generated from two partial products, a single cycle is sufficient to calculate them. By way of example, after the third cycle, the intermediate sums s1, s3, s2, and s6 and the excess bits a3, a2, and a6 are stored in memory.

[0063] By way of example, in a fourth calculation cycle, the multipliers xl to x4 calculate the partial products associated with groups 15 and 17. During the fourth calculation cycle, a first part of the intermediate sum s4 is, for example, calculated by one of the adding trees. Indeed, since the intermediate sum s4 is equal to the sum of four partial products, its calculation is performed over two calculation cycles. Thus, in a fifth calculation cycle, the intermediate sum s4 and the excess bits '4' are generated.

[0064] The fifth calculation cycle further includes, for example, the generation of the intermediate sum s₁ and the excess bits '₂', corresponding to the partial product a₀*I₁b₀, and its storage in memory. The fifth calculation cycle, for example, further includes the generation of a first part of the intermediate sum s₅, from three partial products. By way of example, the intermediate sum s₅ and the excess bits '₅' have finished being calculated by one of the trees adders during a sixth calculation cycle. Once generated, the intermediate sum s5 and the excess bits "5" are, for example, stored in memory.

[0065] In the example illustrated in Figure 2B, the intermediate sums s to s7 and the extra bits 2 to 7 are obtained in 6 calculation cycles. As an example, each calculation cycle corresponds to a time between two significant edges of a clock signal received by the main circuit.

[0066] The size of an ai is ceil(log2(K)) + max(size(Ia), size(Ib)), where K is the number of elements in the group, size(Ia) = ya is set to 0 if the element is not used in the group, and size(Ib) = yb is set to 0 if Ib is not used in the group. Then, for '7', the size is size(Ia) + size(Ib) = ya + yb, indeed, for dl the number of elements in the group is equal to 1, so log2 is equal to zero.

[0067] In other examples, for example when the general circuit includes more than MULN = 4 multiplying subcircuits, the addition of the partial products takes place over at most log2(N) clock cycles.

[0068] In general, depending on the number of partial products to be added, the latency introduced by the adder tree varies. For K partial products to be added, the latency for adding K partial products is equal to ceil(log2(K)). This is the only variable part of the latency in the overall circuit. Reordering the instructions so that all the additions with the longest latency occur at the beginning reduces the overall latency.

[0069] Fig. 3A illustrates another example of submultiplication of mantissa pieces for the calculation of partial products, according to an embodiment of the present description.

[0070] By way of example, the multipliers xl to x4 are configured to calculate, during a first calculation cycle (CYCLE), the partial products of groups 11 and 13, described in relation to [Fig. 1]. By way of example, the multipliers xl, x2 and x3 are configured to calculate the partial products of group 13 and the multiplier x4 is configured to calculate the partial product of group 11. By way of example, during this first calculation cycle, the multiplier circuits xl, x2, x3 and x4 are respectively configured to calculate the partial products a3*bl, a2*b2, al*b3 and al*b3.

[0071] By way of example, the multipliers xl to x4 are configured to, in a second calculation cycle, for example following the first calculation cycle, calculate the partial products of group 14. By way of example, the multipliers xl, x2, x3 and x4 are respectively configured to calculate the partial products a3*Ib bO, a2*bl, a3*b2 and a0*b3.

[0072] By way of example, the multipliers xl to x4 are configured to, in a third calculation cycle, for example following the second calculation cycle, calculate the partial products of groups 17 and 15. For example, the multiplier xl is configured to calculate the partial product of group 17 and the multipliers x2, x3 and x4 are configured to calculate the partial products of group 15. For example, the multipliers xl, x2, x3 and x4 are respectively configured to calculate the partial products la a0*Ib b0, a2*Ib b0, al*bl and la a0*b2.

[0073] By way of example, the multipliers xl to x4 are configured to calculate, in a fourth calculation cycle, for example following the third calculation cycle, the partial products of groups 16 and 12. For example, the multipliers xl and x2 are configured to calculate the partial products of group 16 and the multipliers x3 and x4 are configured to calculate the partial products of group 12. By way of example, the multipliers xl, x2, x3 and x4 are respectively configured to calculate the partial products Ib al*b0, la a0*bl, a3*b2 and a2*b3.

[0074] If the NMUL number of multiplier circuits is greater than the maximum number of chunks N, the remaining multiplier circuits are, for example, supplied with chunks to calculate the partial products of other groups. All instructions are then, for example, reordered. Indeed, several groups must be added together. Priority is given to the operation for which the log2 of the size of the groups concerned is maximum. For example, the log2 of the size of groups 12 and 16 is equal to 1 and the log2 of the size of groups 14 and 15 is equal to 2. [Fig. 3B] illustrates the reordering of instructions, in order to give priority to the sum of groups 14 and 15.

[0075] Figure 3B illustrates another example of performing the calculation of intermediate sums according to an embodiment of the present description. In particular, Figure 3B illustrates a calculation of intermediate sums described in relation to Figure 1, where the partial products are calculated in the manner described in relation to Figure 3A. Figure 3B illustrates a reordering algorithm for reducing the latency of the operation by switching the execution of certain microinstructions in memory so as to advance the execution of instructions that take a relatively long time to execute.

[0076] By way of example, during a first calculation cycle (CYCLE), the multipliers xl to x4 calculate the partial products (PPM) associated with groups 11 and 13. During a second calculation cycle, the multipliers xl to x4 then calculate the partial products (PPM) associated with group 14. During this second calculation cycle, the general circuit is further configured to calculate sums (ADD1, ADD2). By way of example, an adder tree is configured to generate the intermediate sum si during the second calculation cycle. For example, the sum The intermediate sum is then stored in a memory location within the main circuit. Furthermore, during the second calculation cycle, another adding tree is configured to take as input the three partial products of group 13 and to generate a portion of the intermediate sum s3. For example, this other adding tree is configured to generate the intermediate sum s3 and the excess bits '3' over two cycles. In other words, during a third calculation cycle, the other adding tree is configured to generate the intermediate sum s3 and the excess bits '3' from the portion of the sum obtained during the second calculation cycle. As an example, the intermediate sum s3 and the excess bits '3' are then stored in a memory location within the main circuit.

[0077] By way of example, during the third calculation cycle, the multipliers xl to x4 calculate the partial products associated with groups 15 and 17. For example, during the third calculation cycle, the adding trees are further configured to calculate a part of the intermediate sum s4, from the four partial products generated during the second calculation cycle.

[0078] By way of example, in a fourth calculation cycle, the multipliers xl to x4 calculate the partial products associated with groups 12 and 16. During the fourth cycle, the intermediate sum s4 and the excess bits "4" are calculated, for example, from the part generated during the third calculation cycle. Indeed, since the intermediate sum s4 is equal to the sum of four partial products, its calculation takes place over two cycles.

[0079] The fourth calculation cycle includes, for example, the generation of the intermediate sum s7 and the excess bits a7, corresponding to the partial product a0*b0, and their storage in memory. The fourth calculation cycle also includes, for example, the generation of a first part of the intermediate sum s5 from three partial products. By way of example, the intermediate sum s5 and the excess bits a7 have finished being calculated by one of the adding trees during a fifth calculation cycle. Once generated, the intermediate sum s5 and the excess bits a7 are, for example, stored in memory.

[0080] The fifth calculation cycle includes, for example, the generation of the intermediate sums s2 and s6 and their associated bits "2" and "6. Since each of these two intermediate sums is obtained from two partial products, a single calculation cycle is sufficient for their calculation.

[0081] In the example illustrated in Figure 3B, the intermediate sums si to s7 and the excess bits a2 to «7 are obtained in 5 calculation cycles. By way of example, each calculation cycle corresponds to a time between two significant edges of a clock signal received by the general circuit.

[0082] When the NMUL number of multipliers exceeds the maximum number of pieces N, the sum of the partial products of each group is performed by more than one adding tree. In this case, multiple groups are processed in parallel. For example, when NMUL = 8 and N = 4, in a first clock cycle, groups 14, 13, and 12 are processed, and in a second clock cycle, groups 15, 12, 16, and 1 are processed. In the case where the NMUL number of multipliers is less than the maximum number of pieces N, groups containing more than NMUL elements are calculated and processed by an additional accumulator. This accumulator is used iteratively to accumulate the partial sums of the same group until all the partial products have been processed by the partial multipliers.

[0083] Figure 4 is a diagram illustrating the addition, by a parallel adder 500, of the intermediate sums si to s7 taking into account the excess bits a2 to «7.

[0084] By way of example, after their calculation, the intermediate sums s1 to s7 and the associated excess bits "2 to "7 are stored in a 502 memory architecture of the general circuit.

[0085] In particular, the 502 architecture is such that the size of the internal operators is limited according to the maximum frequency of the general circuit.

[0086] In the particular example of n-bit multipliers and adders on R*n bits for partial sums, where R is an integer, the 502 architecture comprises three rows and an NMUL / R number of columns.

[0087] By way of example, for an NMUL number equal to four 64-bit multipliers and one 128-bit adder, the 502 memory architecture comprises rows A, B, and C divided into columns (col) 1 to 4. By way of example, columns 1 to 3 have a width of 128 bits, or more generally 2n bits, and column 4 has a width of ) bits. More generally, the last column has a width of 2n + ceil(log2(K)) bits, K being the number of elements in a group. Each intersection between a row A or B and a column (Col) k is a location denoted A[k] or B[k].

[0088] By way of example, the intermediate sums s1, s2, s3, s5, and s7 are stored in row A, the sums s2, s4, and s6 are stored in row B, and the excess bits '2 to '7 are stored in row C. In particular, the 2n bits of the intermediate sum s1 are stored at location A[1]. The 2n bits of the intermediate sums s3, s5, and s7 are stored at locations A[2], A[3], and A[4], respectively. In particular, the intermediate sum s7 is stored as the 2n least significant bits of location A[4]. By way of example, the intermediate sums s2, s4, and s6 are stored in row B spanning two columns. The n least significant bits of the intermediate sum s2 are stored in the n most significant bits of location B[1], while the n most significant bits are stored in the n most significant bits of location B[2]. The n least significant bits of the intermediate sum s4 are stored as the n most significant bits of location B[2], while the n most significant bits of the intermediate sum s4 are stored as the n least significant bits of location B[3]. The n least significant bits of the intermediate sum s6 are stored as the n most significant bits of location B[3], while the n most significant bits of the intermediate sum s6 are stored as the n least significant bits of location B[4]. Generally, the intermediate sums sj, where j is an odd integer, are located on row A, while the intermediate sums sk, where k is an even integer, are located on row B.The 2n bits of each intermediate sum located on row A are located in the same column, while the intermediate sums on row B have their n least significant bits in a column adjacent to the one containing their n most significant bits.

[0089] By way of example, the extra bits '2' through '7' are located on row C. The extra bits '2', 'a4', and '6' are located at locations C[2], C[3], and C[4], respectively. In particular, '2', and respectively 'a4' and 'a6', occupy bits n to n+size('2'), n to n+size('a4'), and n to n+size('a6') of locations C[2], C[4], and C[6]. The extra bits '3' and '5' are located in the least significant bit positions of locations C[3] and C[4], respectively. The integer bits '7', for example, occupy the most significant bits of size (a7)-th of location C[4].

[0090] For example, memory implementing the 502 architecture includes multiple read ports and multiple write ports. In another example, the 502 architecture is implemented by separate buffer memories. In yet another example, the 502 architecture is implemented by a single buffer memory or a single memory entity.

[0091] By way of example, before the programming of the excess bits, the bits of line C are all programmed to a default value, such as the value 0. In another example, after the programming of the excess bits, all other bits, not used by the excess bits, are set to 0.

[0092] The parallel adder 500 is then configured to generate the chunks r0 to r7 as well as the resulting integer bits rib.

[0093] The parallel adder 500 includes, for example, 7 adders 505, 506, 506', 507, 507', 508 and 508'. The accumulator 500 further includes 3 multiplexers 510, 512 and 514. Generally, when the mantissas comprise a number L of pieces, the parallel adder 500 includes 2N-1 adders and Nl multiplexers.

[0094] The parallel adder 500 is, for example, configured to generate the pieces r0 to r7, each being, for example, coded by n bits. The parallel adder 500 is by An example configured to generate piece r7 by selecting the value stored in the n least significant bits of location A[l]. Piece r7 then corresponds to the n least significant bits of the intermediate sum. Via the 505 adder, the 500 parallel adder is configured to generate piece r6 by adding the values ​​stored in the n most significant bits of locations A[l] and B[l]. For example, the 505 adder is configured to generate a value encoded by n+1 bits, where the n least significant bits correspond to piece r6 and the most significant bit is a carry bit provided as a control bit to the 510 multiplexer.

[0095] The values ​​stored at locations A[2], B[2] and C[2] are provided to adders 506 and 506'. As an example, adder 506 is configured to calculate the sum of the n most significant bits of the intermediate sum s2, the n least significant bits of the intermediate sum s4, the 2n bits of the intermediate sum s3 and the excess bits a2.

[0096] The 506' adder is configured to calculate the sum of the values ​​stored at locations A[2], B[2], C[2] and the value 1, corresponding to a carry-ahead bit.

[0097] To perform the addition steps in parallel, each pair of adders 506-506', 507-507', and 508-508' is configured to calculate the sums of the values ​​stored at locations A[k], B[k], and C[k], k = 2, 3, and 4, with and without carry-ahead bits. Each pair of adders is coupled to the same multiplexer 510, 512, or 514. The multiplexers 510, 512, and 514 are configured to propagate the carry bits into the result. For example, adder 505 is configured to generate n+1 bit values, with the most significant bit being either 0 or 1. The adder is configured to provide a control bit, with the value of the most significant bits of the output of adder 505, to multiplexer 510. Multiplexer 510 is then configured to select the result from adder 506'.The 510 multiplexer is configured to select the result of the 506 adder if its control bit is equal to 0, and to select the result of the 506' adder otherwise.

[0098] For example, adders 506 and 506' are configured to generate values ​​on 2n+1 bits, the most significant bit being equal to 0 or 1. Multiplexer 510 is then configured to provide a control bit equal to the value of the most significant bit of its selected value. Multiplexer 512 is then configured to select the output of adder 507 or 507', from the control bits provided by multiplexer 510, and so on.

[0099] By way of example, adders 506 and 506' are configured to generate values ​​encoded by 2n+l bits, the most significant bit being equal to 0 or 1. Multiplexer 510 is then configured to generate the piece r5 corresponding to the n least significant bits of the selected value. Multiplexer 510 is further configured to Generate the r4 segment corresponding to bits n+1 to 2n of the selected value. The most significant bit is propagated through multiplexers 512 and 514.

[0100] The 507 adder is configured to calculate the sum of the values ​​stored at locations A[3], B[3], and C[3]. The 507' adder is configured to calculate the sum of the values ​​stored at locations A[3], B[3], C[3], and the value 1, corresponding to a carry-ahead bit. The sum of the values ​​stored at locations A[3], B[3], and C[3] corresponds to the sum of the n most significant bits of the intermediate sum s4, the n least significant bits of the intermediate sum s6, the 2n bits of the intermediate sum s5, and the excess bits '3' and '4'. The 512 multiplexer is then configured to select the value provided by the 507 adder if the control bit transmitted by the 510 multiplexer is equal to 0, and to select the value provided by the 507' adder if the value of the control bit is equal to 1. The 507 and 507' adders are, for example, configured to generate values ​​on 2n+l bits, the most significant bit being equal to 0 or 1.

[0101] The 512 multiplexer is then configured to generate the piece r3 corresponding to the n least significant bits of the selected value. The 512 multiplexer is further configured to generate the piece r2 corresponding to bits n+1 to 2n of the selected value. The 512 multiplexer is further configured to provide the most significant bit of the selected value as a control bit to the 514 multiplexer. For example, the (2n+1)th bit of the value selected by the 512 multiplexer is used as the selection bit for the 514 multiplexer.

[0102] The 508 adder is configured to calculate the sum of the values ​​stored at locations A[4], B[4], and C[4]. The 508' adder is configured to calculate the sum of the values ​​stored at locations A[4], B[4], C[4], and the value 1, corresponding to a carry-ahead bit. The sum of the values ​​stored at locations A[4], B[4], and C[4] corresponds to the sum of the n most significant bits of the intermediate sum s6, the 2n bits of the intermediate sum s7, and the excess bits 5, a6, and a7. The 514 multiplexer is then configured to select the value supplied by the 508 adder if the control bit, transmitted by the 512 multiplexer, is equal to 0, and to select the value supplied by the 508' adder if the value of the control bit is equal to 1. As an example, the values ​​generated by the 508 and 508' adders are coded by 2n + ya + yh bits.

[0103] The 514 multiplexer is then configured to generate the rl piece corresponding to the n least significant bits of the selected value. The 514 multiplexer is also configured to generate the rO piece corresponding to bits n+1 to 2n of the selected value. The 514 multiplexer is further configured to generate resulting integer bits rib corresponding to the most significant bits, exceeding 2n bits of low weight, of the selected value. In particular, the resulting integer bits encode the output integer bits.

[0104] As an example, the pieces r0 to r7 and the additional value rib are stored, after their generation, in a memory 509. For example, memory 509 is a register.

[0105] By way of example, adders 505, 506, 506', 507, 507', 508, and 508' are configured to calculate sums in parallel. In another example, for instance, implemented to reduce the size of memory 502, the additions are performed through and through by a machine when the intermediate sums are provided from the previous step.

[0106] The implementation of the 502 memory architecture on three rows and several columns is given by way of example. In particular, the locations are not necessarily implemented on rows and columns of a memory. The locations are such that the parallel adder 500 calculates the appropriate intermediate sums.

[0107] Figure 5 represents a general circuit 600 configured for the multiplication of two mantissas, according to an embodiment of this description. In particular, the circuit 600 is configured to compute multiplications between two mantissas, each comprising N = 8 pieces 606 (PIECES) a0 to a7 and b0 to b7 and the integer bits la and Ib. The circuit 600 is also suitable for all possible permutations of La and each from 0 to N-1. However, more generally, a person skilled in the art will understand how to extend the circuit in [Fig. 5] so as to compute multiplications between two mantissas, each comprising a different number of pieces.

[0108] The 600 circuit includes, for example, a 602 control unit (CTRL UNIT). As an example, the 602 control unit includes a memory, for example, a ROM (Read Only Memory) type memory storing 604 instructions (INST.). The 604 instructions are, for example, similar to those described in relation to Figure 2B. The 602 control unit is further configured to receive a clock signal (CLK). In this example, the general 600 circuit includes NMUL = 8 multiplier circuits 610-1 to 610-8. However, more generally, a person skilled in the art will understand how to generalize the circuit in Figure 5 to a circuit with an NMUL number of multiplier circuits, NMUL being equal to or greater than 2. The 600 circuit is configured to receive a multiplication command, including for example 606 pieces, as input and to transmit it to the 602 control unit.The 602 control unit then retrieves the LA and LB fields from the 606 chunks. These fields are used to calculate the first address from which to read the 602 instructions into memory. The unit... The 602 control unit is, for example, configured to read memory line by line from the first calculated address by merging the number of valid chunks La and Lb, until it reaches a microinstruction displaying a "last instruction" flag. In another example, the 602 control unit is configured to calculate the number of microinstructions required for a given operation. Furthermore, each microinstruction includes, for example, several fields that apply to the entire pipeline. One or more fields are used to provide instructions to an input cross-circuit 608, which selects the correct chunks for the appropriate multiplier circuits. All control signals transmitted by the 602 control unit are, for example, copied to all the inputs of the multiplier circuits.Once the multiplier circuits 610-1 to 610-8 have finished executing, one or more control signals are generated to control a partial product (PP) transverse circuit 612. These control signals ensure that the valid partial product, calculated by the multiplier circuits 610-1 to 610-8, is routed to the correct input of the adder. Furthermore, all these control signals are copied to the inputs of an adding section 615 of the circuit 600. Specifically, the adding section 615 comprises a plurality of adders, forming a plurality of adding trees.

[0109] The adders of the adding section 615 are activated, for example, if a count value in the control signal is not zero. In particular, the count value indicates how many additions must be performed within a group before the adding section 615 is bypassed to reach a column sum transversal circuit 618. At each adding stage of the adding section 615, the count value within the intermediate addition results of the same group is decremented. If an addition is completed before reaching the end of the adding section 615, a bypass path is provided to supply the result directly to the cross circuit 618 without it being necessary to continue to the end of the adding section 615.The 618 cross circuit includes, for example, an accumulator configured to accumulate the partial sum in the case where the NMUL number of multiplier circuits is less than the maximum number of pieces N. In one example, several adder trees are instantiated in parallel, with additional branch ports in the case where NMUL is greater than N.

[0110] The column sum transverse circuit 618 is configured to receive all partial sums and to write them into a buffer 620 at a position specified by the control signals provided by the control unit 602. The buffer 620 includes, for example, a finite state machine configured to count how many intermediate sums and excess bits have been written, according to the architecture described in relation to [Fig. 4]. Once all the entries have been written, buffer memory 620 activates, for example, an adder circuit 622, which automatically performs a parallel addition over 2 clock cycles. The adder circuit 622 has, for example, the same architecture as the parallel adder 500, comprising adders and multiplexers configured to propagate the carry.

[0111] Once all the additions have been performed by the adder circuit 622, an output 634 (OUTPUT) of the circuit 600 is generated, corresponding to the multiplication between the two operands A and B. In some embodiments, the adder circuit 622 is configured to generate the output 634 with an output precision determined by one or more control bits generated by the control unit 602, the precision being defined at the bit level or at the chunk level. Furthermore, the control bit(s) are, for example, used to mask the output of the adder circuit 622 and / or to calculate a weighting bit and guard bits, for example, by means of shifts, masks, and / or AND-OR logic.

[0112] Generally, when the general circuit 600 includes NMUL multiplier circuits, these NMUL multiplier circuits are configured to generate, at each cycle, NMUL partial products, each comprising for example between 2n and 2n + ya + yb bits, and to supply them to the second cross-circuit 612.

[0113] The adding part 615 is configured to perform the addition in order to generate the intermediate sums and their excess bits, i.e. the additions of the partial products, taking into account the integer bits la and Ib of the same group.

[0114] In what follows, reference is made to "standard adders" and "intermediate adders". The term "standard" indicates that so-called standard adders form adder trees, while the term "intermediate" indicates that intermediate adders form an intermediate adder circuit between the standard adders.

[0115] The adding section 615 includes a first stage consisting of NMUL / 2 standard adders. In the example in [Fig. 5], the first stage of the adding section 615 comprises four standard adders 616-1 to 616-4. In particular, the adders in the first stage are grouped into pairs of standard adders. For example, standard adders 616-1 and 616-2 form a first pair, and standard adders 616-3 and 616-4 form a second pair. Each pair of standard adders is coupled to a standard adder in a second stage of the adding section 615. Each standard adder in a pair is then configured to provide its output to the standard adder in the second stage. For example, standard adders 616-1 and 616-2 are coupled to an adder standard 617-1 and standard adders 616-3 and 616-4 are coupled to a standard adder 617-2.

[0116] Furthermore, the input and output of each standard adder in the first stage, with the exception, for example, of the first and last standard adders 616-1 and 616-4 respectively in the first stage, are also supplied to a multiplexer. For example, the input of adder 616-2 is also supplied to multiplexer 617-3, and the input of adder 616-3 is also supplied to multiplexer 617-4. Two multiplexers receiving adder inputs from different pairs, for example, neighboring pairs, are coupled to intermediate adders in the second stage. For example, multiplexers 617-3 and 617-4 are coupled to an intermediate adder 617-5. The second stage comprises, for example, NMUL / 4 standard adders and NMUL / 4-1 intermediate adders, for a total of NMUL / 2-1 adders.In general, the first row of adders is formed of NMUL / 2 standard adders, the second row of adders is formed of NMUL / 4 standard adders plus (NMUL / 4)-1 intermediate adders, an i-th row of adders is formed of NMUL / 2 standard adders plus (NMUL / 1)-1 intermediate adders. In addition, the adder part 615 comprises a number equal to ceil(log2(NMUL)) of rows of adders.

[0117] The output of the intermediate adder 615=7-5 of the second stage is supplied to two multiplexers. For example, the intermediate adder 617-5 is configured to supply its output to multiplexers 617-6 and 617-8. In addition, each standard adder of the second stage is configured to supply its output to one of the multiplexers. For example, the standard adder 617-1 supplies its output to multiplexer 617-6, while the standard adder 617-2 supplies its output to multiplexer 617-7. Each pair of multiplexers is configured to supply its outputs to an adder of a third stage, for example, to a standard adder 617-8. In the particular example of [Fig. 5], the adding section 615 comprises three stages, with the standard adder forming standard adder trees.

[0118] In the example where NMUL is greater than 8, the third stage includes, for example, an alternation of standard and intermediate adders. The adding section 615 also includes other stages, based on the same construction. The last stage includes a single standard adder.

[0119] In addition, a corresponding time barrier, comprising for example flip-flops, is positioned at the inputs of each standard and intermediate adder, each flip-flop 619 being clocked by the CLK clock signal and ensuring a time barrier between two clock cycles of the CLK clock. in order to ensure pipeline operation of the adding part 615. In addition, the output of each standard and intermediate adder is directly coupled to the transverse circuit 618 via a bypass path, symbolized in [Fig.5] by a point at the output of each adder.

[0120] The adding part 615 is for example capable, by the use of additional multiplexers and adders, of adding any selected group of partial products.

[0121] Other embodiments of the adding section 615 are possible, depending on the NMUL number of multiplying circuits. For example, in some cases, the adding section 615 includes only standard adders.

[0122] Furthermore, the maximum number of clock cycles used by the adding part to perform an addition depends on the NMUL number of multiplying subcircuits, and is for example equal to ceil(log2(NMUL)).

[0123] In addition to the number of partial additions to be performed by the adding unit 615, each input of the adding unit 615 is associated with the group of partial products to which it belongs. This information is, for example, encoded by additional control bits that pass through the pipeline of circuit 600 in parallel with the digital data. These additional control bits are, for example, generated by the control unit 602 and are, for example, updated by the cross circuits 612 and 618.

[0124] In particular, when they pass through the adding part 615, these additional control bits indicate the path to be followed by the digital data through the stages, in particular whether or not a particular value is to be supplied by a bypass path to the cross circuit 618.

[0125] The architecture of the adder circuit 622 is similar to that described in relation to Figure 4. In the particular case of Figure 5, the adder section 615 produces the intermediate sums s0 to s15 and the associated excess bits a2 to a15. The intermediate sums and excess bits are stored in corresponding locations in the buffer memory 620 in the same manner as described in relation to [Fig. 4], i.e., in three rows and NMUL / R columns. The adder circuit 622 comprises an NMUL / R number of adders 624_1 to 624_NMUL / R. In the example in [Fig.5], NMUL / R = 8. Adders 624_1 to 624_NMUL / R are configured, for example, to add the contents of locations A[k] and B[K] in buffer 620, for each K.

[0126] The 622 adder circuit includes 625_1 to 625_NMUL / R flip-flops, each configured to receive, at each clock cycle, the output of a corresponding 624_1 to 624_NMUL / R adder. In particular, the 625j flip-flop, 1 < / < NMUL / R is configured to receive the output of the 624j adder. The 622 adder further includes the 626_2 to 626_NMUL / R flip-flops. Each 626j flip-flop, 2 < j < NMUL / R, is configured to receive the contents of location C[j] in buffer 620.

[0127] Each pair of 625j and 626j flip-flops, 2 < / < NMUL / R, has its outputs coupled to the 628_lj and 628_2j adders. The 628_lj adders are configured to add the contents of the 625j and 626j flip-flops, that is, to perform the addition of the values ​​at locations A[j]+B[j]+C[j] of the buffer, reusing the value of A[j]+B[j], which is already calculated by the 624-j adder. The 628_2j adders are configured to add the output values ​​of the 625j and 626j flip-flops with the value 1 corresponding to a carry-ahead bit, that is, to perform the addition of locations A[j]+B[j]+C[j]+1 of the buffer.

[0128] The 600 circuit further includes NMUL / R-1 multiplexers 630_2 to 630_NMUL / R. Each multiplexer 630j is configured to receive the output of adders 628_lj and 628_2j. Each multiplexer 630j is also configured to provide a control bit, equal to the most significant bit of its selected value, i.e., the 2n+1st bit, to multiplexer 630_(j+l). Multiplexer 630_2 is configured to receive, as its control bit, the most significant bit stored in flip-flop 625_1. If the received control value is 0, multiplexer 630j is configured to select the output of adder 628_lj. If the received command value is equal to 1, the 630j multiplexer is configured to select the output of the 628_2j adder.

[0129] Each 630j multiplexer is, for example, configured to provide the value selected to a 632 computing circuit (GB+UDF CALC), which is, for example, configured to calculate one or more guard bits and a balancing value from the selected values. In another example, only the guard bits or the offset value are calculated by the 632 circuit. In another example, only the guard bits or the offset value are calculated by the 632 circuit. In some examples, the guard bits and / or the offset value are equal to 0. The 632 calculation circuit, for example, provides selected output values ​​from adders 628-12 to 628_1NMUL / R, 628-22 to 628-2NMUL / R, along with the calculated guard bit and offset value, to a 634 memory that is part of an output interface of the 600 circuit. In another example, each 630j multiplexer is, for example, configured to directly provide the selected value to the 634 memory.In this case, no guard bit and no balancing value are calculated.

[0130] For example, memory 634 is a shift register, random access memory (RAM), flip-flop, etc., configured to receive the output of circuit 632, which calculates a final output, also producing the guard bits and / or the override bit, according to the indications provided by control unit 602. In another example, memory 634 is configured to directly receive the outputs of each 630-j multiplexer.

[0131] By way of example, memory 634 is configured to store the result and propagation path of the multiplication of the two mantissas supplied to the input of circuit 600. In particular, the result of the multiplication is stored as a sequence of chunks of size n. The n least significant bits of the intermediate sum if form the chunk corresponding to the n least significant bits of the result, the next n least significant bits of the intermediate sum if form the chunk corresponding to the next n least significant bits of the result, and so on for subsequent intermediate sums.

[0132] Although [Fig.5] illustrates a particular example of a general 600 circuit in which the mantissas to be multiplied each comprise 8 pieces of n bits, a person skilled in the art will be able to adapt the general 600 circuit, and in particular the structure of the adder trees 614-1 and 614-2 as well as the structure of the memory 620 and the parallel adder 622, to the general case in which the mantissas each comprise L pieces of n bits.

[0133] In one example, the multiplier subcircuits 610-1 to 610-8 exhibit an internal pipelined organization. In this case, the control signals for subsequent steps, which implicitly pass through the multipliers, are pipelined accordingly. In particular, the instructions 604 include, for example, additional information such as: the path on the adder portion 615 of each partial product and / or the number of additions in the adder portion 615 to be applied to each partial product before completing the calculation of the sum of the associated group; and / or the location in buffer 620 at which an intermediate sum is to be stored; and / or the number of partial sums to be stored in buffer 620; and / or the maximum output precision for calculating the guard bit and the weighting, if necessary.

[0134] In another example, the input cross circuit 608 is replaced by multiple read ports in the memory containing the chunks 606. The control unit 604 is configured to select the chunks to be used by the partial multipliers 610-1 to 610-8. In other words, the functionality of the cross circuit 608 is implemented by the combination of the memory containing the chunks and the control unit 604.

[0135] In another example, the output of the partial multipliers 610-1 to 610-8 is directly coupled to the input of the adding section 615, for example via flip-flops. In this case, the cross circuit 608 is omitted. Furthermore, in some embodiments, the cross circuit 612 is also omitted.

[0136] One advantage of the described embodiments is that the latency in the multiplication of two mantissas is reduced. Indeed, the cascading execution of the multiplier circuits and the stages of the adding trees, and the propagation of the carry during the addition of the results, make it possible to eliminate the latency in the generation of the intermediate sums and the integer bits.

[0137] Another advantage of the described embodiments, and in particular of the cascade execution of the different components of the circuit 600, is that they allow the surface area of ​​the circuit 600 to be relatively reduced due to the use of the different components in parallel, in particular the reuse of the sub-circuits of the multiplier and the adding part 615.

[0138] Another advantage of the described embodiments is that the 600 multiplier circuit is suitable for forming a subunit of a computing circuit configured to implement other multiplication algorithms such as, for example, the Karatsuba algorithm, the NNT (Number Needed to Treat) algorithm, the Toomcook algorithm, etc. Furthermore, it is suitable for other functional units such as floating-point units, graphics processing units (GPUs), coprocessors, accelerators, etc.

[0139] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the implementations described in relation to Figures 2A, 2C, 3A, and 3B are not limiting. Specifically, those skilled in the art may adapt the instructions 604 to other calculation sequences for intermediate sums. Similarly, those skilled in the art may adapt the instructions to the general case where the main circuit comprises a number NMUL, for example, NMUL = 2, 3, 4, 8, etc., of multiplier circuits. Likewise, the length of the adder trees depends on the number of multipliers. In particular, the number of cycles required for the calculation of intermediate sums by the adder section 615 is less than or equal to log2(NMUL).The number of multiplying circuits can also exceed the maximum number N of pieces. For example, if La = 0 and Lb = 7, 8 partial products must be calculated, i.e., one per group. In this case, no addition needs to be performed by the adding part 615. The partial products are, for example, bypassed directly after the flip-flops 619 to reach the transverse column sum circuit 618.

[0140] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional specifications given above. In particular, the NMUL number of multipliers being equal to the number N of pieces is a specific case. It is possible to have a number of multipliers less than or greater than the number of pieces. In this case, an additional stage is used. This additional stage allows the propagation of the sum after the adding section 615 and is implemented, for example, by an additional branch and certain logic control signals to properly control the data flow. Furthermore, it is possible to implement the multiplier subcircuits in a pipelined configuration. Moreover, it is also possible to merge the internal pipeline stages, for example, by removing the memory 620 and reducing the operating frequency of the circuit.Furthermore, the memory comprising the 604 instructions can be implemented by a read-only memory (ROM), or rather, instead of being a memory, it could be implemented by a combinational circuit, or a finite-state machine, which produces the appropriate control signals at its output. In addition, various implementations of the 620 buffer and / or the 622 parallel adder would be possible. Different implementations of the 615 adder portion are also possible. In particular, possible implementations of the 615 adder portion include one or more adder trees configured to perform addition operations, among one or more groups, in parallel. Furthermore, examples of memories implemented by a ROM have been described, but the same functionality could be implemented by a finite-state machine.Furthermore, in the case where NMUL < N, the 618 cross-circuit includes, for example, an accumulator configured to store the partial products of the same group, and the scheduling algorithm is adapted accordingly. This scheduling algorithm is determined, for example, by the 604 instructions, which are micro-instructions. Moreover, all the information used by the circuit to channel the data is indicated, for example, by control bits. These additional control bits are modified, for example, as they pass through the 600 circuit in parallel with the digital data.

Claims

Demands

1. A circuit (600) configured to perform a multiplication operation between a first value and a second value, the first and second values ​​each comprising up to N pieces of n bits, where N is an integer greater than or equal to 2, the circuit comprising: - an NMUL number of multiplying subcircuits (610-1,..., 610-8), where NMUL is an integer, configured to generate first partial products, each first partial product being a multiplication between a piece from among the pieces of the first value and a piece from among the pieces of the second value; - an adding part (615) configured to generate a first intermediate sum (s1,..., s7,..., s15) and first excess bit values ​​(s1,..., s17,..., s15), al 5), from the first partial products; and - a parallel adder (500, 622) configured to generate a value corresponding to the product between the first and second values ​​from the first intermediate sum and the first integer bit generated by the first adder circuit and the second processing circuit.

2. Circuit (600) according to claim 1, wherein the NMUL multiplying subcircuits (610-1,610-8) are configured to generate the first NMUL partial products in response to the reception, by the circuit (600), of a first significant edge of a clock signal (CLK), and wherein the adding portion (615) is configured to generate the first intermediate sum in response to the reception of a second significant edge of the clock signal (CLK), subsequent to the first significant edge, the NMUL multiplying subcircuits being configured to generate the second partial products in response to the reception of the second significant edge of the clock signal.

3. Circuit (600) according to claim 1 or 2, further comprising: - a first transverse circuit (612) configured to receive the first partial products generated by the NMUL multiplying sub-circuits (610-1, ..., 610-8) and to supply them to the adding part (615); and - an intermediate memory (620) configured to store the first intermediate sum and the first excess bits generated by the adding part and to provide them to the parallel adder (500, 622)

4. Circuit according to claim 3, wherein the adding part (615) is configured to generate 2N-1 intermediate sums (si,..., s7,..., sl5) and 2N-2 excess bit values ​​(a2, a7,..., al5) following the reception of a log2(NMUL) number of clock signals, the intermediate memory (620) being configured to provide the 2N-1 intermediate sums and the 2N-2 excess bit values ​​to the parallel adder, the parallel adder being configured to output the product between the first and second values ​​by adding the 2N-1 intermediate sums and the 2N-2 excess bit values.

5. Circuit (600) according to claim 4, wherein the intermediate memory (620) comprises first, second and third regions (A, B, C) and wherein the adding part (615) is configured to store at most N intermediate sums in the first region and at most Nl intermediate sums in the second region and to store the excess bit values ​​in the third region.

6. Circuit (600) according to claim 5, wherein: - the n least significant bits of a first intermediate sum, among the at most N intermediate sums, stored in the second region, are stored in the same memory column as the n most significant bits of a second intermediate sum stored in the first region; - the n most significant bits of the first intermediate sum stored in the second region are stored in the same memory column as the n least significant bits of a third intermediate sum stored in the first region.

7. Circuit (600) according to any one of claims 1 to 6, further comprising: - a second transverse circuit (608) configured to receive at least one piece from among the pieces of the first value and at least one piece from among the pieces of the second value; and - a control unit (602) configured to tell the second cross circuit which pieces to supply to which multiplier subcircuit.

8. Circuit (600) according to claim 7, in its dependence on claim 2, wherein the control unit (602) is clocked by the clock signal (CLK) and is configured to: - upon receiving the first significant edge of the clock signal, control the second transverse circuit (608) to supply a first piece of the first value and a first piece of the second value to a first multiplier subcircuit (610-1,..., 610-8); and - upon receiving the second significant edge of the clock signal (CLK), subsequent to the first significant edge, cause the supply of a first partial product, generated by the first multiplier subcircuit, to the adding part (615) and control the second transverse circuit to supply a second piece of the first value and a second piece of the second value to the first multiplier subcircuit.

9. Circuit (600) according to claim 8, wherein the control unit (602) is configured to control the second transverse circuit (608) directly or through the transmission of additional control bits included in the first chunks of the first and second values.

10. Circuit according to claim 8 or 9, wherein the control unit (602) is further configured to, upon receiving the first and / or second significant edge of the clock signal (CLK), command the second transverse circuit (608) to supply a third piece of the first value and a third piece of the second value to a second multiplier subcircuit (610-1,..., 610-8).

11. Circuit according to any one of claims 1 to 10, wherein “ is equal to at least 2 and for example to 16 or 32 or 64 or 128.

12. Circuit according to any one of claims 1 to 11, wherein the integer NMUL is equal to an integer between 2 and ^V2.

13. Circuit according to any one of claims 1 to 12, wherein the adding part (615) comprises one or more adding trees configured to perform addition operations in parallel.

14. A method for multiplying a first and a second value by a (600) circuit, the first and second values ​​each comprising up to N pieces of bits, N being an integer greater than or equal to 2 and μ being an integer, the method comprising: - the generation of first partial products by multiplying sub-circuits (610-1, ..., 610-8), μ being an integer, of the circuit, each partial product corresponding to a multiplication between a piece from among the pieces of the first value and a piece from among the pieces of the second value; - the generation of a first intermediate sum (i, ..., s7, ..., s 15) and a first excess bit value (“2,al5”), by an adding part (615) of the circuit, from the first partial products; and - the generation of a value corresponding to the product between the first and second values, by a parallel adder (622) of the circuit, from the first intermediate sum and the first integer bit.

15. A method according to claim 14, wherein the pieces of the first value and the pieces of the second value are supplied to a first cross circuit (608) coupled to the NMUL multiplying sub-circuits (610-1, ..., 610-8) and wherein a control unit (602) is configured to indicate to the first cross circuit which pieces to supply to which multiplying sub-circuits.

16. A method according to claim 15, wherein the control unit (602) is controlled by a clock signal (CLK) and wherein the control unit is further configured to: - upon receiving a first significant edge of the clock signal, control the first transverse circuit (608) to supply a first piece of the first value and a first piece of the second value to a first multiplier sub-circuit (610-1,...,610-8); and - upon receiving a second significant edge of the clock signal, subsequent to the first significant edge: cause the supply of a first partial product, generated by the first multiplier circuit from the first pieces, to the first adder circuit and / or the second processing circuit; and

17. command the first cross circuit to supply a second piece of the first value and a second piece of the second value to the first or second multiplier subcircuit (610-1,610-8). A method according to any one of claims 14 to 16, further comprising: - the generation of 2N-1 intermediate sums (si,..., s7,..., sl5) and 2N-2 excess bit values ​​(a2,al5) by the adding part (615) in response to the reception of at least N clock signals, and their storage in an intermediate memory (620); and - the provision of the 2N-1 intermediate sums and the 2N-2 excess bit values ​​to a parallel adder (622), the parallel adder being configured to generate the product between the first and second values ​​by adding the 2N-1 intermediate sums and the 2N-2 excess bit values.

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