Display substrate, method for manufacturing the same, and display device

Abstract

Provided are a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a plurality of sub-pixels. The first sub-pixel includes a first pixel circuit and a first effective light-emitting region. The second sub-pixel includes a second pixel circuit and a second effective light-emitting region. There is a first light-shielding layer between the first pixel circuit and the first base substrate, and the orthographic projection of the first light-shielding layer onto the first base substrate of the first pixel circuit at least partially overlaps. There is a second light-shielding layer between the second pixel circuit and the first base substrate, and the orthographic projection of the second light-shielding layer onto the first base substrate of the second pixel circuit at least partially overlaps. The wavelength of the light emitted from the first effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region. The ratio M1 of the ratio a of the area of the first light-shielding layer to the area of the first sub-pixel and the ratio b of the area of the second light-shielding layer to the area of the second sub-pixel is 1.020 to 1.120. By adjusting the aperture ratios corresponding to the first sub-pixel and the second sub-pixel, the entire process can be facilitated.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202210823111.7 filed on July 14, 2022, and all the contents disclosed in the above Chinese patent application are incorporated herein by reference as part of this application.

[0002] Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0003] Display devices include thin film transistor liquid crystal displays (TFT-LCDs) and active matrix organic light emitting diode (AMOLED) display devices. Active matrix organic light emitting diode (AMOLED) display devices have the advantages of long lifespan, high display brightness, high contrast, and wide color gamut. Organic light emitting diode display devices using active matrix organic light emitting diodes as light emitting elements have the characteristics of being thin and lightweight in addition to high-speed response, wide viewing angle, and low voltage driving compared with conventional liquid crystal display devices. Therefore, organic light emitting diode display devices can be widely applied to cellular phones, portable information terminals, televisions, and monitors.

[0004] An organic light emitting diode display device mainly includes a cathode, a light emitting layer, and an anode. In an active matrix organic light emitting diode display device, each sub-pixel has a switching transistor and a driving transistor, and by adjusting the switching transistor and the driving transistor, the light emitting layer of the organic light emitting diode display device emits light.

Summary of the Invention

Means for Solving the Problems

[0005] At least one embodiment of the present disclosure provides a display substrate and a method for manufacturing the same, and a display device. In the display substrate, the wavelength of light emitted from a first effective light-emitting region is greater than the wavelength of light emitted from a second effective light-emitting region. The ratio M1 of the ratio a of the area of a first light-shielding layer corresponding to the first effective light-emitting region to the area of a first sub-pixel and the ratio b of the area of a second light-shielding layer corresponding to the second effective light-emitting region to the area of a second sub-pixel is in the range of 1.020 to 1.120. That is, the area ratio of the light-shielding layer corresponding to the emitted long-wavelength light is larger. By satisfying the range of the ratio M1, the aperture ratio of the display substrate can be adjusted.

[0006] At least one embodiment of the present disclosure includes a first base substrate and a plurality of sub-pixels provided on the first base substrate and including a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first pixel circuit and a first effective light-emitting region. The second sub-pixel includes a second pixel circuit and a second effective light-emitting region. A first light-shielding layer is provided between the first pixel circuit and the first base substrate, and a positive projection of the first light-shielding layer onto the first base substrate at least partially overlaps a positive projection of the first pixel circuit onto the first base substrate. A second light-shielding layer is provided between the second pixel circuit and the first base substrate, and a positive projection of the second light-shielding layer onto the first base substrate at least partially overlaps a positive projection of the second pixel circuit onto the first base substrate. The wavelength of light emitted from the first effective light-emitting region is greater than the wavelength of light emitted from the second effective light-emitting region. The ratio of the area of the first light-shielding layer to the area of the first sub-pixel is a, and the ratio of the area of the second light-shielding layer to the area of the second sub-pixel is b. The range of the ratio M1 of a to b is 1.020 to 1.120. A display substrate is provided.

[0007] For example, in the display substrate according to at least one embodiment of the present disclosure, the area of the first sub-pixel is equal to the area of the second sub-pixel. In a plane parallel to the main surface of the first base substrate, the ratio of the area of the first light-shielding layer to the area of the second light-shielding layer is equal to the M1.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, the aperture ratio of the first sub-pixel is n1(1 - a), and the aperture ratio of the second sub-pixel is n2(1 - b).

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[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of sub-pixels further includes a third sub-pixel, the third sub-pixel includes a third pixel circuit and a third effective light-emitting region, a third light-shielding layer is provided between the third pixel circuit and the first base substrate, the orthographic projection of the third light-shielding layer onto the first base substrate at least partially overlaps the orthographic projection of the third pixel circuit onto the first base substrate, the wavelength of the light emitted from the third effective light-emitting region is smaller than the wavelength of the light emitted from the second effective light-emitting region, in a plane parallel to the main surface of the first base substrate, the area ratio c of the third light-shielding layer is equal to the ratio of the area of the third light-shielding layer to the area of the third sub-pixel, and the aperture ratio of the third sub-pixel is n3(1 - c).

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[0010] For example, in the display substrate according to at least one embodiment of the present disclosure, the plurality of sub-pixels further includes a fourth sub-pixel, the fourth sub-pixel includes a fourth pixel circuit and a fourth effective light-emitting region, a fourth light-shielding layer is provided between the fourth pixel circuit and the first base substrate, the orthographic projection of the fourth light-shielding layer on the first base substrate at least partially overlaps with the orthographic projection of the fourth pixel circuit on the first base substrate, the wavelength of the light emitted from the fourth effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region, in a plane parallel to the main surface of the first base substrate, the area ratio d of the fourth light-shielding layer is equal to the ratio of the area of the fourth light-shielding layer to the area of the fourth sub-pixel, and the value range of the aperture ratio n4(1 - d) of the fourth sub-pixel is 0.230 to 0.950, where n4 is the ratio of the area of the opening region of the fourth sub-pixel to the area of the portion other than the region shielded by the fourth light-shielding layer of the fourth sub-pixel.

[0011] For example, in the display substrate according to at least one embodiment of the present disclosure, the first sub-pixel further includes a first light-emitting element, the first pixel circuit controls the light emission of the first light-emitting element, the color of the light emitted by the first light-emitting element is the same as the color of the light emitted from the first effective light-emitting region, the second sub-pixel further includes a second light-emitting element, the second pixel circuit controls the light emission of the second light-emitting element, the color of the light emitted by the second light-emitting element is the same as the color of the light emitted from the second effective light-emitting region, the third sub-pixel further includes a third light-emitting element, the third pixel circuit controls the light emission of the third light-emitting element, and the color of the light emitted by the third light-emitting element is the same as the color of the light emitted from the third effective light-emitting region.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, the first sub-pixel further includes a first light-emitting element, the first pixel circuit controls the light emission of the first light-emitting element, the second sub-pixel further includes a second light-emitting element, the second pixel circuit controls the light emission of the second light-emitting element, the third sub-pixel further includes a third light-emitting element, the third pixel circuit controls the light emission of the third light-emitting element, the fourth sub-pixel further includes a fourth light-emitting element, the fourth pixel circuit controls the light emission of the fourth light-emitting element, the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element are all white light-emitting elements, and on the side of the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element away from the first base substrate, a first filter layer, a second filter layer, a third filter layer, and a light transmission layer are respectively provided. The color of the light emitted from the first filter layer is the same as the color of the light emitted from the first effective light-emitting region, the color of the light emitted from the second filter layer is the same as the color of the light emitted from the second effective light-emitting region, the color of the light emitted from the third filter layer is the same as the color of the light emitted from the third effective light-emitting region, and the color of the light emitted from the light transmission layer is the same as the color of the light emitted from the fourth effective light-emitting region.

[0013] For example, in a display substrate according to at least one embodiment of the present disclosure, the transmittance of the material of the first filter layer is λ1, the transmittance of the material of the second filter layer is λ2, the transmittance of the material of the third filter layer is λ3, the transmittance of the material of the light transmission layer is λ4, and the total transmittance of the first filter layer, the second filter layer, the third filter layer, and the light transmission layer is

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[0014] For example, in the display substrate according to at least one embodiment of the present disclosure, in a plane parallel to the main surface of the first base substrate, the range of the ratio of the sum of the areas of the first filter layer, the second filter layer, the third filter layer, and the light transmission layer to the sum of the areas of the first light-shielding layer, the second light-shielding layer, the third light-shielding layer, and the fourth light-shielding layer is 1.050 to 6.800.

[0015] For example, in the display substrate according to at least one embodiment of the present disclosure, in a plane parallel to the main surface of the first base substrate, the range of the ratio of the area of the first filter layer to the area of the first light-shielding layer is 2.000 to 3.000.

[0016] For example, in the display substrate according to at least one embodiment of the present disclosure, in a plane parallel to the main surface of the first base substrate, the range of the ratio of the area of the second filter layer to the area of the second light-shielding layer is 1.1074 to 1.6938.

[0017] For example, the display substrate according to at least one embodiment of the present disclosure further includes a data line and a first guiding line extending in a first direction, and a second guiding line extending in a second direction. The data line and the second guiding line intersect to define a plurality of pixel regions, and each of the pixel regions has the sub-pixels. Between the adjacent sub-pixels, a first power supply voltage line parallel to the data line is provided. On a side of the first light-shielding layer of the first effective light-emitting region close to the first light-shielding layer, a second power supply voltage line parallel to the second direction is provided. The second power supply voltage line intersects the first power supply voltage line and is connected to a first drain of a first driving transistor of the first pixel circuit. A positive projection of the second power supply voltage line on the first base substrate overlaps a positive projection of the first light-shielding layer on the first base substrate.

[0018] For example, in the display substrate according to at least one embodiment of the present disclosure, a positive projection of the second power supply voltage line on the first base substrate overlaps a positive projection of the fourth light-shielding layer on the first base substrate.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, a projection of the second power supply voltage line onto the first base substrate overlaps a projection of the third light-shielding layer onto the first base substrate and also overlaps a projection of the second light-shielding layer onto the first base substrate.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, an overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the first light-shielding layer onto the first base substrate is larger than an overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the second light-shielding layer onto the first base substrate.

[0021] For example, in a display substrate according to at least one embodiment of the present disclosure, an overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the first light-shielding layer onto the first base substrate is larger than an overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the third light-shielding layer onto the first base substrate.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, an overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the first light-shielding layer onto the first base substrate is larger than an overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the fourth light-shielding layer onto the first base substrate; the overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the fourth light-shielding layer onto the first base substrate is larger than an overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the third light-shielding layer onto the first base substrate; and the overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the third light-shielding layer onto the first base substrate is larger than an overlapping area between a projection of the second power supply voltage line onto the first base substrate and a projection of the second light-shielding layer onto the first base substrate.

[0023] For example, in the display substrate according to at least one embodiment of the present disclosure, in one of the first sub-pixels, the overlapping area between the orthographic projection of the second power supply voltage line on the first base substrate and the orthographic projection of the first light-shielding layer on the first base substrate is 0.03 to 0.30 square microns; in one of the second sub-pixels, the overlapping area between the orthographic projection of the second power supply voltage line on the first base substrate and the orthographic projection of the fourth light-shielding layer on the first base substrate is 0.02 to 0.20 square microns; in one of the third sub-pixels, the overlapping area between the orthographic projection of the second power supply voltage line on the first base substrate and the orthographic projection of the third light-shielding layer on the first base substrate is 0 to 0.05 square microns; and in one of the fourth sub-pixels, the overlapping area between the orthographic projection of the second power supply voltage line on the first base substrate and the orthographic projection of the second light-shielding layer on the first base substrate is 0 to 0.08 square microns.

[0024] For example, in the display substrate according to at least one embodiment of the present disclosure, the second power supply voltage line includes a first portion and a second portion that are separated from each other, and the first portion and the second portion are connected to the first power supply voltage line through different via structures.

[0025] For example, in the display substrate according to at least one embodiment of the present disclosure, the first portion is connected to the first drain of the first driving transistor of the first pixel circuit and the second drain of the second driving transistor of the second pixel circuit, and the second portion is connected to the third drain of the third driving transistor of the third pixel circuit and the fourth drain of the fourth driving transistor of the fourth pixel circuit.

[0026] For example, in the display substrate according to at least one embodiment of the present disclosure, the extending direction of the first portion and the extending direction of the second portion are parallel, both the first portion and the second portion extend along a straight line, and the first portion is located on the side close to the second induction line of the second portion.

[0027] For example, in a display substrate according to at least one embodiment of the present disclosure, the first portion is connected to a central region of the first drain and the second drain, and the second portion is connected to an edge away from the second lead line of the third drain and an edge away from the second lead line of the fourth drain.

[0028] For example, in a display substrate according to at least one embodiment of the present disclosure, both the first portion and the second portion extend along a broken line. The first portion is connected to an edge away from the second lead line of the first drain and is connected to a central region of the second drain. The second portion is connected to an edge away from the second lead line of the third drain and is connected to a central region of the fourth drain.

[0029] For example, in a display substrate according to at least one embodiment of the present disclosure, the first drain and the first light-shielding layer are connected via a first via that sequentially penetrates an interlayer insulating layer, a gate insulating layer, and a buffer layer.

[0030] For example, a display substrate according to at least one embodiment of the present disclosure further includes a first gate line extending in the second direction and a first gate extending from the first gate line and extending on a side close to the second power supply voltage line. A planar shape of the first light-shielding layer includes a first sub-portion and a second sub-portion extending in the first direction. A first distance between a first side of the first sub-portion close to the first gate line and the first gate line is greater than a second distance between a second side of the second sub-portion close to the first gate and the first gate.

[0031] For example, a display substrate according to at least one embodiment of the present disclosure further includes a second gate line parallel to the first gate line. The first gate is configured as a gate of a first switching transistor, and the second gate line is configured as a gate of a first induction transistor included in the first pixel circuit, a gate of a second induction transistor included in the second pixel circuit, a gate of a third induction transistor included in the third pixel circuit, and a gate of a fourth induction transistor included in the fourth pixel circuit.

[0032] At least one embodiment of the present disclosure includes a display substrate described in any one of the above embodiments, and a cover plate provided opposite to the display substrate, the cover plate includes a second base substrate, and a quantum dot layer is provided on a side of the second base substrate close to the display substrate, the quantum dot layer includes a plurality of quantum dot units, the plurality of quantum dot units correspond one-to-one to the plurality of sub-pixels, and colors of each of the plurality of quantum dot units are the same as colors of the corresponding sub-pixels, and further provides a display device.

[0033] The display device according to at least one embodiment of the present disclosure further includes a black matrix provided on a side of the second base substrate close to the display substrate, the black matrix has a plurality of openings, and each of the quantum dot units is located in one of the openings.

[0034] At least one embodiment of the present disclosure includes the steps of providing a first base substrate, forming a plurality of sub-pixels on the first base substrate, wherein the formation of the plurality of sub-pixels includes forming a first sub-pixel and a second sub-pixel, the formation of the first sub-pixel includes forming a first pixel circuit and a first effective light-emitting region, the formation of the second sub-pixel includes forming a second pixel circuit and a second effective light-emitting region, forming a first light-shielding layer between the first pixel circuit and the first base substrate, wherein a positive projection of the first light-shielding layer onto the first base substrate at least partially overlaps a positive projection of the first pixel circuit onto the first base substrate, and forming a second light-shielding layer between the second pixel circuit and the first base substrate, wherein a positive projection of the second light-shielding layer onto the first base substrate at least partially overlaps a positive projection of the second pixel circuit onto the first base substrate. The wavelength of light emitted from the first effective light-emitting region is greater than the wavelength of light emitted from the second effective light-emitting region. The ratio of the area of the first light-shielding layer to the area of the first sub-pixel is a, and the ratio of the area of the second light-shielding layer to the area of the second sub-pixel is b. The range of the ratio M1 of a to b is 1.020 to 1.120. Further provided is a method for manufacturing a display substrate.

[0035] For example, in the manufacturing method according to at least one embodiment of the present disclosure, the aperture ratio of the first sub-pixel is n1(1 - a), and the aperture ratio of the second sub-pixel is n2(1 - b).

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[0036] To more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

Brief Description of the Drawings

[0037]

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DETAILED DESCRIPTION OF THE INVENTION

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art without creative efforts based on the described embodiments of the present disclosure fall within the protection scope of the present disclosure.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the conventional meanings understood by those skilled in the art. The "first", "second", and similar words used in the present disclosure do not indicate an order, number, or importance, but are only used to distinguish different components. Similar words such as "include" or "comprise" mean that the element or article appearing before the word covers the elements or articles listed after the word and their equivalents, but do not exclude other elements or articles. Similar words such as "connect" or "couple" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and if the absolute position of the object to be described changes, the corresponding relative positional relationship may also change accordingly.

[0040] As the resolution of a light-emitting diode display device improves, the pixel size of the light-emitting diode display device continues to decrease. The emission luminance of the red sub-pixels, green sub-pixels, and blue sub-pixels of the light-emitting diode display device does not match, and since the wavelengths of the light emitted by the red sub-pixels, green sub-pixels, and blue sub-pixels are different, it is necessary to adjust the aperture ratio corresponding to the sub-pixels of different colors to enhance the light mixing effect of the red sub-pixels, green sub-pixels, and blue sub-pixels. In the case of a light-emitting element that emits white light or blue light, it is necessary to provide a filter layer in the regions corresponding to the red sub-pixels, green sub-pixels, and blue sub-pixels. As the pixel size of the light-emitting diode display device decreases, the distance between the filter layers corresponding to the sub-pixels of different colors becomes smaller, and the problem of cross-color is likely to occur, making it difficult to adjust the aperture ratio of the red sub-pixels, green sub-pixels, and blue sub-pixels by adjusting the size of the filter layer. The inventors of the present disclosure have found that the aperture ratio corresponding to different sub-pixels can be adjusted by designing the size of the light-shielding layer corresponding to different sub-pixels, thereby making the entire process of the manufacturing process of the display substrate easier.

[0041] At least one embodiment of the present disclosure provides a display substrate, which includes a first base substrate and a plurality of sub-pixels provided on the first base substrate and including a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first pixel circuit and a first effective light-emitting region, and the second sub-pixel includes a second pixel circuit and a second effective light-emitting region. A first light-shielding layer is provided between the first pixel circuit and the first base substrate, and a positive projection of the first light-shielding layer onto the first base substrate at least partially overlaps a positive projection of the first pixel circuit onto the first base substrate. A second light-shielding layer is provided between the second pixel circuit and the first base substrate, and a positive projection of the second light-shielding layer onto the first base substrate at least partially overlaps a positive projection of the second pixel circuit onto the first base substrate. The wavelength of the light emitted from the first effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region. The ratio of the area of the first light-shielding layer to the area of the first sub-pixel is a, and the ratio of the area of the second light-shielding layer to the area of the second sub-pixel is b. The range of the ratio M1 of a to b is 1.020 to 1.120. Embodiments of the present disclosure adjust the aperture ratio corresponding to different sub-pixels by designing the sizes of the light-shielding layers corresponding to different sub-pixels, thereby making the entire process of the manufacturing process of the display substrate easier.

[0042] For example, FIG. 1 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 1, the display substrate 100 includes a first base substrate 101 and a plurality of sub-pixels 102 provided on the first base substrate 101. The direction in which the plurality of sub-pixels 102 are arranged is the second direction Y. That is, the plurality of sub-pixels 102 are provided side by side in the second direction Y. The plurality of sub-pixels 102 include a first sub-pixel 1021 and a second sub-pixel 1022 provided side by side in the second direction Y. The direction intersecting or perpendicular to the second direction Y is the first direction X. The first sub-pixel 1021 includes a first pixel circuit 1021a and a first effective light-emitting region 1021b in the first direction X. The second sub-pixel 1022 includes a second pixel circuit 1022a and a second effective light-emitting region 1022b in the first direction X. In a direction perpendicular to the main surface of the first base substrate 101, a first light-shielding layer 103 is provided between the first pixel circuit 1021a and the first base substrate 101. The orthographic projection of the first light-shielding layer 103 onto the first base substrate 101 at least partially overlaps the orthographic projection of the first pixel circuit 1021a onto the first base substrate 101. A second light-shielding layer 104 is provided between the second pixel circuit 1022a and the first base substrate 101. The orthographic projection of the second light-shielding layer 104 onto the first base substrate 101 at least partially overlaps the orthographic projection of the second pixel circuit 1022a onto the first base substrate 101. For example, the wavelength of the light emitted from the first effective light-emitting region 1021b is greater than the wavelength of the light emitted from the second effective light-emitting region 1022b. The ratio of the area of the first light-shielding layer 103 to the area of the first sub-pixel 1021 is a, and the ratio of the area of the second light-shielding layer 104 to the area of the second sub-pixel 1022 is b. The range of the ratio M1 of a to b is 1.020 to 1.120. When the ratio M1 of a to b is less than 1.020, the ratio a of the area of the first light-shielding layer 103 to the area of the first sub-pixel 1021 is slightly small, the aperture ratio of the first sub-pixel 1021 is large, and the aperture ratio of the second sub-pixel 1022 is small. As a result, the final color mixing effect is not good. On the other hand, when the ratio M1 of a to b is greater than 1.120, the ratio a of the area of the first light-shielding layer 103 to the area of the first sub-pixel 1021 is slightly large, the aperture ratio of the first sub-pixel 1021 is small, and the aperture ratio of the second sub-pixel 1022 is large. As a result, the final color mixing effect is not good.Also, when the ratio M1 of a to b is less than 1.020, the ratio a of the area of the first light-shielding layer 103 to the area of the first sub-pixel 1021 is slightly small, the first light-shielding layer 103 corresponding to the first sub-pixel 1021 is slightly small, and the shielding and protecting effect of the first pixel circuit 1021a is slightly weak (for example, the first light-shielding layer 103 overlaps at least the active layer of the driving transistor of the first pixel circuit 1021a, exhibits a shielding and protecting effect, and avoids current leakage due to external light irradiation). When the ratio M1 of a to b is greater than 1.120, the second light-shielding layer 104 corresponding to the second sub-pixel 1022 is slightly small, and the shielding and protecting effect of the second pixel circuit 1022a is slightly weak (for example, the first light-shielding layer 103 overlaps at least the active layer of the driving transistor of the second pixel circuit 1022a, exhibits a shielding and protecting effect, and avoids current leakage due to external light irradiation).

[0043] For example, the first sub-pixel and the second sub-pixel included in the plurality of sub-pixels may be two adjacent sub-pixels arranged side by side in the second direction in one pixel unit, or two sub-pixels spaced apart from each other and arranged side by side in the second direction in one pixel unit. In the embodiments of the present disclosure, this is not limited, and it is only necessary to satisfy that the first sub-pixel and the second sub-pixel are in the same pixel unit.

[0044] For example, in one example, the first sub-pixel 1021 and the second sub-pixel 1022 are a red sub-pixel and a green sub-pixel respectively. Correspondingly, the first effective light-emitting region 1021b is a red light-emitting region, and the second effective light-emitting region 1022b is a green light-emitting region. Usually, the light-emitting area of the red sub-pixel is larger than that of the green sub-pixel, that is, the area of the first effective light-emitting region 1021b is larger than the area of the second effective light-emitting region 1022b. By setting the area of the first light-shielding layer 103 to be larger than the area of the second light-shielding layer 104, the aperture ratios of the first sub-pixel 1021 and the second sub-pixel 1022 can be adjusted to enhance the final light mixing effect. Also, the entire process of the manufacturing process of the display substrate becomes easier, and the light-emitting efficiency of the display substrate becomes higher. Also, the wavelength of the light emitted from the red sub-pixel is larger than the wavelength of the light emitted from the green sub-pixel. The red sub-pixel is more likely to generate diffraction and further affects the pixel circuit of the same sub-pixel or other sub-pixels. By setting the area of the first light-shielding layer 103 to be larger than the area of the second light-shielding layer 104, the diffraction effect of the light emitted from the red sub-pixel can be reduced.

[0045] For example, the first light-shielding layer 103 and the second light-shielding layer 104 may be formed of the same material in the same process step. The materials of the first light-shielding layer 103 and the second light-shielding layer 104 may be a light-shielding metal material or other light-shielding materials. In the embodiments of the present disclosure, this is not limited.

[0046] For example, as shown in FIG. 1, the orthographic projection of the first effective light-emitting region 1021b onto the first base substrate 101 and the orthographic projection of the first light-shielding layer 103 onto the first base substrate 101 have no overlapping part. The orthographic projection of the second effective light-emitting region 1022b onto the first base substrate 101 and the orthographic projection of the second light-shielding layer 104 onto the first base substrate 101 have no overlapping part. When the display substrate is used in a display panel, top emission, bottom emission, or dual emission can be realized. In the embodiments of the present disclosure, this is not limited.

[0047] For example, as shown in FIG. 1, in one example, a is equal to the area of the first light-shielding layer / the area of the first sub-pixel, b is equal to the area of the second light-shielding layer / the area of the second sub-pixel, and M1 = a / b. In one example, the area of the first sub-pixel 1021 is equal to the area of the second sub-pixel 1022. In this case, in a plane parallel to the main surface of the first base substrate 101, the ratio of the area of the first light-shielding layer 103 to the area of the second light-shielding layer 104 is equal to M1.

[0048] For example, as shown in FIG. 1, the area shielded by the first light-shielding layer 103 is not an opening area. The first sub-pixel 1021 further includes other areas in addition to the area shielded by the first light-shielding layer 103 and the opening area. The area shielded by the second light-shielding layer 104 is not an opening area. The second sub-pixel 1022 further includes other areas in addition to the area shielded by the second light-shielding layer 104 and the opening area. The aperture ratio of the first sub-pixel 1021 is n1(1 - a), where n1 is the ratio of the area of the opening area of the first sub-pixel 1021 to the area of the portion other than the area shielded by the first light-shielding layer 103 of the first sub-pixel 1021. The aperture ratio of the second sub-pixel is n2(1 - b), where n2 is the ratio of the area of the opening area of the second sub-pixel 1022 to the area of the portion other than the area shielded by the second light-shielding layer 104 of the second sub-pixel 1022.

Number

Number

[0049] For example, the above formula

Number

[0050] (Initial luminance of the first sub-pixel * aperture ratio of the first sub-pixel / initial luminance of pixel unit) * emission lifetime of the first sub-pixel = M2 * (Initial luminance of the second sub-pixel * aperture ratio of the second sub-pixel / initial luminance of pixel unit) * emission lifetime of the second sub-pixel

[0051] Furthermore, (Aperture ratio of the first sub-pixel) / (aperture ratio of the second sub-pixel) = M2 * ((Initial luminance of the second sub-pixel / initial luminance of pixel unit) * emission lifetime of the second sub-pixel) / ((Initial luminance of the first sub-pixel / initial luminance of pixel unit) * emission lifetime of the first sub-pixel) is derived, and the first sub-pixel and the second sub-pixel are associated with the same pixel unit. In this case, the initial luminance of the pixel unit corresponding to the first sub-pixel is equal to the initial luminance of the pixel unit corresponding to the second sub-pixel, and the above formula is simplified to formula (I).

[0052] (Formula (I)) (Aperture ratio of the first sub-pixel) / (aperture ratio of the second sub-pixel) = M2 * ((Initial luminance of the second sub-pixel * emission lifetime of the second sub-pixel) / (Initial luminance of the first sub-pixel * emission lifetime of the first sub-pixel))

[0053] Substitute the aperture ratio of the first sub-pixel = n1(1 - a) and the aperture ratio of the second sub-pixel = n2(1 - b) into formula (I) to obtain the following formula (II).

[0054] (Formula (II)) (Aperture ratio of the first sub-pixel) / (aperture ratio of the second sub-pixel) = (n1 / n2)(1 - a) / (1 - b) = M2 * ((Initial luminance of the second sub-pixel * emission lifetime of the second sub-pixel) / (Initial luminance of the first sub-pixel * emission lifetime of the first sub-pixel))

[0055] According to formula (II), (1 - a) / (1 - b) = (n2 / n1)M2 * ((Initial luminance of the second sub - pixel * Emission lifetime of the second sub - pixel) / (Initial luminance of the first sub - pixel * Emission lifetime of the first sub - pixel)) = (n2 / n1)M2 * K1 * K2 We obtain the equation, where K1 = Initial luminance of the second sub - pixel / Initial luminance of the first sub - pixel, K2 = Emission lifetime of the second sub - pixel / Emission lifetime of the first sub - pixel. For example, in one example, (n2 / n1)M2 = 1.000 to 1.130. For example, when n2 = n1, M2 = 1.000 to 1.130.

[0056] For example, in one example, the initial luminance of the first sub - pixel is 26.1 cd / m 2 and the initial luminance of the second sub - pixel is 86.1 cd / m 2 The emission lifetime of the first sub - pixel is 150,000 hours, the emission lifetime of the second sub - pixel is 40,000 hours, n2 = n1, M2 = 1.130. In this case,

Number

[0057] For example, in one example, the first sub - pixel is a red sub - pixel, the second sub - pixel is a green sub - pixel. Usually, the initial luminance of the green sub - pixel is high, the lifetime of the green sub - pixel is short, the initial luminance of the red sub - pixel is low, and the lifetime of the red sub - pixel is long. Therefore, K1 is smaller than K2.

[0058] For example, in the structure shown in FIG. 1, the plurality of sub-pixels 102 further includes a third sub-pixel 1023, that is, on the first base substrate 101, there is also a third sub-pixel 1023 provided side by side with the first sub-pixel 1021 and the second sub-pixel 1022, and the third sub-pixel 1023 may include a third pixel circuit 1023a and a third effective light-emitting region 1023b.

[0059] For example, a third light-shielding layer 105 is provided between the third pixel circuit 1023a and the first base substrate 101, and the orthographic projection of the third light-shielding layer 105 onto the first base substrate 101 at least partially overlaps with the orthographic projection of the third pixel circuit 1023a onto the first base substrate 101. The wavelength of the light emitted from the third effective light-emitting region 1023b is smaller than the wavelength of the light emitted from the second effective light-emitting region 1022b. In a plane parallel to the main surface of the first base substrate 101, the area ratio c of the third light-shielding layer 105 is equal to the ratio of the area of the third light-shielding layer 105 to the area of the third sub-pixel 1023, and the aperture ratio of the third sub-pixel 1023 is n3(1 - c).

[0060] Similarly, according to the above

Number

Number

[0061] For example, the first effective light-emitting region 1021b, the second effective light-emitting region 1022b, and the third effective light-emitting region 1023b respectively correspond to a red light-emitting region, a green light-emitting region, and a blue light-emitting region, and the corresponding first sub-pixel 1021, second sub-pixel 1022, and third sub-pixel 1023 are a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0062] For example, in one example, the initial luminance of the second sub-pixel 1022 is 86.1 cd / m 2 , the luminous life of the second sub-pixel 1022 is 40,000 hours, the initial luminance of the third sub-pixel 1023 is 11.3 cd / m 2 , the luminous life of the third sub-pixel 1023 is 60,000 hours, n2 = n3, M3 = 0.260, and in this case,

Equation

[0063] For example, as shown in FIG. 1, the first sub-pixel 1021 further includes a first light-emitting element 1021c, the first pixel circuit 1021a controls the light emission of the first light-emitting element 1021c, and the color of the light emitted by the first light-emitting element 1021c is the same as the color of the light emitted from the first effective light-emitting region 1021b. The second sub-pixel 1022 further includes a second light-emitting element 1022c, the second pixel circuit 1022a controls the light emission of the second light-emitting element 1022c, and the color of the light emitted by the second light-emitting element 1022c is the same as the color of the light emitted from the second effective light-emitting region 1022b. The third sub-pixel 1023 further includes a third light-emitting element 1023c, the third pixel circuit 1023a controls the light emission of the third light-emitting element 1023c, and the color of the light emitted by the third light-emitting element 1023c is the same as the color of the light emitted from the third effective light-emitting region 1023b. For example, the first light-emitting element 1021c, the second light-emitting element 1022c, and the third light-emitting element 1023c respectively emit a first color light, a second color light, and a third color light, and the first color light, the second color light, and the third color light can be mixed to form white light.

[0064] For example, in one example, the first light-emitting element, the second light-emitting element, and the third light-emitting element respectively emit red light, green light, and blue light.

[0065] For example, in one example, the area of the first light-shielding layer 103 corresponding to the red sub-pixel > the area of the second light-shielding layer 104 corresponding to the green sub-pixel > the area of the third light-shielding layer 105 corresponding to the blue sub-pixel. For example, the area of the first light-shielding layer 103: the area of the second light-shielding layer 104: the area of the third light-shielding layer 105 = 20:19:18. The wavelength of the light emitted from the red pixel > the wavelength of the light emitted from the green sub-pixel > the wavelength of the light emitted from the blue sub-pixel. The longer the wavelength, the easier it is for diffraction to occur, and it will further affect the pixel circuit of the same sub-pixel or other sub-pixels. Therefore, the area of the light-shielding layer corresponding to the sub-pixel with a longer wavelength is larger to reduce the diffraction effect of the light emitted therefrom. For example, in one example, the area of the first light-shielding layer 103 corresponding to the red sub-pixel > the area of the second light-shielding layer 104 corresponding to the green sub-pixel > the area of the third light-shielding layer 105 corresponding to the blue sub-pixel. For example, a:b:c = 20:19:18.

[0066] For example, FIG. 2 is a schematic plan view of another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 2, compared with the structure of the display substrate shown in FIG. 1, in the structure shown in FIG. 2, the plurality of sub-pixels 102 further includes a fourth sub-pixel 1024, that is, on the first base substrate 101, there is also a fourth sub-pixel 1024 provided side by side with the first sub-pixel 1021, the second sub-pixel 1022, and the third sub-pixel 1023.

[0067] Note that in FIG. 2, the first sub-pixel 1021, the second sub-pixel 1022, the fourth sub-pixel 1024, and the third sub-pixel 1023 are provided side by side in sequence, but the embodiments of the present disclosure are not limited thereto. The third sub-pixel 1023 may be provided between the second sub-pixel 1022 and the fourth sub-pixel 1024, or arranged in other orders, and the embodiments of the present disclosure do not limit this.

[0068] For example, for the related features of the first sub-pixel 1021, the second sub-pixel 1022, and the third sub-pixel 1023, reference can be made to the above related description about FIG. 1.

[0069] For example, as shown in FIG. 2, the fourth sub-pixel 1024 includes a fourth pixel circuit 1024a and a fourth effective light-emitting region 1024b. A fourth light-shielding layer 106 is provided between the fourth pixel circuit 1024a and the first base substrate 101, and the orthographic projection of the fourth light-shielding layer 106 onto the first base substrate 101 at least partially overlaps with the orthographic projection of the fourth pixel circuit 1024a onto the first base substrate 101. The wavelength of the light emitted from the fourth effective light-emitting region 1024b is greater than the wavelength of the light emitted from the second effective light-emitting region 1022b. In a plane parallel to the main surface of the first base substrate 101, the area ratio d of the fourth light-shielding layer 106 is equal to the ratio of the area of the fourth light-shielding layer 106 to the area of the fourth sub-pixel 1024, and the value range of the aperture ratio n4(1 - d) of the fourth sub-pixel 1024 is 0.230 to 0.950. Here, n4 is the ratio of the area of the opening region of the fourth sub-pixel to the area of the portion other than the region shielded by the fourth light-shielding layer of the fourth sub-pixel.

[0070] For example, in one example, the light emitted from the fourth sub-pixel 1024 is white light, that is, the fourth sub-pixel 1024 is a white sub-pixel. Correspondingly, the fourth effective light-emitting region 1024b is a white light-emitting region.

[0071] For example, FIG. 3 is a schematic plan view of still another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 3, the first sub-pixel 1021 includes a first light-emitting element 1021c, and the first pixel circuit 1021a controls the light emission of the first light-emitting element 1021c. The second sub-pixel 1022 further includes a second light-emitting element 1022c, and the second pixel circuit 1022a controls the light emission of the second light-emitting element 1022c. The third sub-pixel 1023 further includes a third light-emitting element 1023c, and the third pixel circuit 1023a controls the light emission of the third light-emitting element 1023c. The fourth sub-pixel 1024 further includes a fourth light-emitting element 1024c, and the fourth pixel circuit 1024a controls the light emission of the fourth light-emitting element 1024c. The first light-emitting element 1021c, the second light-emitting element 1022c, the third light-emitting element 1023c, and the fourth light-emitting element 1024c are all white light-emitting elements. On the side of the first light-emitting element 1021c, the second light-emitting element 1022c, the third light-emitting element 1023c, and the fourth light-emitting element 1024c away from the first base substrate 101, a first filter layer 1021d, a second filter layer 1022d, a third filter layer 1023d, and a light-transmitting layer 1024d are respectively provided. The color of the light emitted from the first filter layer 1021d is the same as the color of the light emitted from the first effective light-emitting region 1021b, the color of the light emitted from the second filter layer 1022d is the same as the color of the light emitted from the second effective light-emitting region 1022b, the color of the light emitted from the third filter layer 1023d is the same as the color of the light emitted from the third effective light-emitting region 1023b, and the color of the light emitted from the light-transmitting layer 1024d is the same as the color of the light emitted from the fourth effective light-emitting region 1024b, that is, it is still white light.

[0072] Note that for the sake of simplicity of illustration, in FIG. 3, the first base substrate 101 is omitted.

[0073] For example, as shown in FIG. 3, the transmittance of the material of the first filter layer 1021d is λ1, the transmittance of the material of the second filter layer 1022d is λ2, the transmittance of the material of the third filter layer 1023d is λ3, and the transmittance of the material of the light-transmitting layer 1024d is λ4. The total transmittance of the first filter layer 1021d, the second filter layer 1022d, the third filter layer 1023d, and the light-transmitting layer 1024d is

Number

Number

[0074] For example, the first light-emitting element 1021c, the second light-emitting element 1022c, the third light-emitting element 1023c, and the fourth light-emitting element 1024c are all light-emitting elements that emit white light. With this design, the uniformity of the emitted light can be improved, and the white light can not only adjust the width of the chromatogram but also perform optical compensation.

[0075] For example, in one example, in a plane parallel to the main surface of the first base substrate 101, the range of the ratio of the sum of the areas of the first filter layer 1021d, the second filter layer 1022d, the third filter layer 1023d, and the light transmission layer 1024d to the sum of the areas of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 is 1.050 to 6.800. For example, the ratio may be 1.100, 1.200, 2.000, 2.500, 3.000, 3.500, 4.000, 4.500, 5.000, 5.500, 6.000, 6.500, and in the embodiments of the present disclosure, this is not limited.

[0076] For example, in another example, in a plane parallel to the main surface of the first base substrate 101, the range of the ratio of the sum of the areas of the first filter layer 1021d, the second filter layer 1022d, the third filter layer 1023d, and the light transmission layer 1024d to the sum of the areas of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 is 1.100 to 3.300. For example, the ratio may be 1.200, 1.300, 1.400, 1.600, 1.800, 2.000, 2.400, 2.700, 2.900, 3.100, 3.200, or 3.300, and the embodiments of the present disclosure do not limit this.

[0077] For example, in one example, in a plane parallel to the main surface of the first base substrate 101, the range of the ratio of the area of the first filter layer 1021d to the area of the first light-shielding layer 103 is 2.000 to 3.000. For example, the ratio is 2.000, 2.200, 2.400, 2.600, 2.800, or 3.000.

[0078] For example, in one example, in a plane parallel to the main surface of the first base substrate 101, the range of the ratio of the area of the second filter layer 1022d to the area of the second light-shielding layer 104 is 1.1074 to 1.6938. For example, the ratio of the area of the second filter layer 1022d to the area of the second light-shielding layer 104 is 1.1074, 1.200, 1.300, 1.400, 1.500, or 1.600, and the embodiments of the present disclosure do not limit this.

[0079] For example, in one example, in a plane parallel to the main surface of the first base substrate 101, the range of the ratio of the area of the third filter layer 1023d to the area of the third light-shielding layer 105 is 1.4650 to 2.02268. For example, the ratio of the area of the third filter layer 1023d to the area of the third light-shielding layer 105 is 1.510, 1.600, 1.700, 1.800, 1.900, or 2.100, and the embodiments of the present disclosure do not limit this.

[0080] For example, in one example, in a plane parallel to the main surface of the first base substrate 101, the range of the ratio of the area of the light transmission layer 1024d to the area of the fourth light shielding layer 106 is 2.1760 to 3.2850. For example, the ratio of the area of the light transmission layer 1024d to the area of the fourth light shielding layer 106 is 2.210, 2.600, 2.700, 2.800, 2.900, or 3.100. In the embodiments of the present disclosure, this is not limited thereto.

[0081] For example, as shown in FIGS. 1 to 3, the display substrate 100 further includes a data line 107 and a first conductive line 108 extending in the first direction X, and a second conductive line 109 extending in the second direction Y. The data line 107 and the second conductive line 109 intersect to define a plurality of pixel regions, and each pixel region has one of the sub-pixels 102. A first power supply voltage line 110 parallel to the data line 107 is provided between adjacent sub-pixels 102. A second power supply voltage line 111 parallel to the second direction Y is provided on the side of the first light shielding layer 103 of the first effective light emitting region 1021b close to the first light shielding layer 103. The second power supply voltage line 111 intersects the first power supply voltage line 110 and is connected to the first drain of the first driving transistor of the first pixel circuit 1021a. The orthographic projection of the second power supply voltage line 111 on the first base substrate 101 overlaps the orthographic projection of the first light shielding layer 103 on the first base substrate 101.

[0082] For example, as shown in FIG. 2, in one example, the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the first light shielding layer 103 on the first base substrate 101 have an overlapping portion. The orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the second light shielding layer 104 on the first base substrate 101, the orthographic projection of the third light shielding layer 105 on the first base substrate 101, and the orthographic projection of the fourth light shielding layer 106 on the first base substrate 101 have no overlapping portion. However, the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the fourth light shielding layer 106 on the first base substrate 101 have an adjacent portion. With this design, the stability of the first light shielding layer 103 can be enhanced, and a capacitance can be formed between the first light shielding layer 103 and the second power supply voltage line 111, thereby avoiding the phenomenon that the first light shielding layer 103 drifts when the gate signal is not on.

[0083] For example, as shown in FIG. 1, in another example, the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projection of the first light shielding layer 103 onto the first base substrate 101 have an overlapping portion, and the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projections of the second light shielding layer 104 and the third light shielding layer 105 onto the first base substrate 101 have no overlapping portion.

[0084] For example, in another example, the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projections of the first light shielding layer 103, the second light shielding layer 104, the third light shielding layer 105, and the fourth light shielding layer 106 onto the first base substrate 101 have no overlapping portion.

[0085] For example, the second induction line 109 extending in the second direction Y may extend along a curve, along a broken line, or along a straight line, as long as the extending direction of the entire second induction line 109 satisfies being along the second direction Y. In the structures shown in FIGS. 1 to 3, the second induction lines 109 all extend along straight lines.

[0086] For example, as shown in FIG. 3, the second power supply voltage line 111 is connected to the source S11 of the driving transistor T11 of the first sub-pixel 1021, the second power supply voltage line 111 is connected to the source S12 of the driving transistor T12 of the second sub-pixel 1022, the second power supply voltage line 111 is connected to the source S13 of the driving transistor T13 of the third sub-pixel 1023, and the second power supply voltage line 111 is connected to the source S14 of the driving transistor T14 of the fourth sub-pixel 1024.

[0087] For example, as shown in FIG. 3, the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 overlaps with the orthographic projection of the first light-shielding layer 103 onto the first base substrate 101 and also overlaps with the orthographic projection of the fourth light-shielding layer 106 onto the first base substrate 101. There is no overlapping portion between the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projections of the second light-shielding layer 104 and the third light-shielding layer 105 onto the first base substrate 101. With this design, the stability of the first light-shielding layer 103 and the fourth light-shielding layer 106 can be enhanced, and capacitances can be formed between the first light-shielding layer 103 and the second power supply voltage line 111, and between the fourth light-shielding layer 106 and the second power supply voltage line 111, thereby avoiding the phenomenon that the first light-shielding layer 103 and the fourth light-shielding layer 106 drift when the gate signal is not on.

[0088] For example, FIG. 4 is a schematic plan view of the planar structure of still another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 4, the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 has an overlapping portion with the orthographic projections of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 onto the first base substrate 101.

[0089] For example, as shown in FIG. 4, the overlapping area between the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projection of the first light-shielding layer 103 onto the first base substrate 101 is larger than the overlapping area between the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projection of the second light-shielding layer 104 onto the first base substrate 101, balancing the magnitudes of the capacitances between the first light-shielding layer 103 and the second power supply voltage line 111, and between the fourth light-shielding layer 106 and the second power supply voltage line 111.

[0090] For example, as shown in FIG. 4, the overlapping area between the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the first light-shielding layer 103 on the first base substrate 101 is larger than the overlapping area between the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the third light-shielding layer 105 on the first base substrate 101. With this design, the stability of the first light-shielding layer 103 and the third light-shielding layer 105 can be enhanced, and the magnitudes of the capacitances between the first light-shielding layer 103 and the second power supply voltage line 111, and between the third light-shielding layer 105 and the second power supply voltage line 111 can be balanced.

[0091] For example, as shown in FIG. 4, the overlapping area between the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the first light-shielding layer 103 on the first base substrate 101 is larger than the overlapping area between the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the fourth light-shielding layer 106 on the first base substrate 101. The overlapping area between the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the fourth light-shielding layer 106 on the first base substrate 101 is larger than the overlapping area between the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the third light-shielding layer 105 on the first base substrate 101. The overlapping area between the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the third light-shielding layer 105 on the first base substrate 101 is larger than the overlapping area between the orthographic projection of the second power supply voltage line 111 on the first base substrate 101 and the orthographic projection of the second light-shielding layer 104 on the first base substrate 101. With this design, the stability of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 can be enhanced, and the magnitudes of the capacitances between the first light-shielding layer 103 and the second power supply voltage line 111, between the second light-shielding layer 104 and the second power supply voltage line 111, between the third light-shielding layer 105 and the second power supply voltage line 111, and between the fourth light-shielding layer 106 and the second power supply voltage line 111 can be balanced.

[0092] For example, in one example, in one first sub-pixel 1021, the overlapping area between the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projection of the first light-shielding layer 103 onto the first base substrate 101 is 0.03 to 0.30 square microns. In one second sub-pixel 1022, the overlapping area between the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projection of the fourth light-shielding layer 106 onto the first base substrate 101 is 0.02 to 0.20 square microns. In one third sub-pixel 1023, the overlapping area between the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projection of the third light-shielding layer 105 onto the first base substrate 101 is 0 to 0.05 square microns, and in one fourth sub-pixel 1024, the overlapping area between the orthographic projection of the second power supply voltage line 111 onto the first base substrate 101 and the orthographic projection of the second light-shielding layer 104 onto the first base substrate 101 is 0 to 0.08 square microns.

[0093] For example, the second power supply voltage line 111 extending in the second direction Y may extend along a curve, along a broken line, or along a straight line, as long as the entire extending direction of the second power supply voltage line 111 satisfies being along the second direction Y. In the structures shown in FIGS. 1 to 4, the second power supply voltage line 111 all extends along a straight line.

[0094] For example, FIG. 5 is a schematic plan view of still another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 5, the second power supply voltage line 111 includes a first portion 111a and a second portion 111b separated from each other, and the first portion 111a and the second portion 111b are connected to the first power supply voltage line 110 through different via structures. For example, the second power supply voltage line 111 is provided to include a plurality of separated portions, and the plurality of portions are not directly connected, so that it can be avoided that the second power supply voltage line 111 is too long and too much charge accumulates in the second power supply voltage line 111.

[0095] For example, in the structure shown in FIG. 5, both the first portion 111a and the second portion 111b extend along a curve, but the embodiments of the present disclosure are not limited thereto, and both the first portion 111a and the second portion 111b may extend along a straight line.

[0096] For example, as shown in FIG. 5, the first portion 111a is connected to the first source S11 of the first driving transistor T11 of the first pixel circuit 1021a and the second source S12 of the second driving transistor T12 of the second pixel circuit 1022a. The second portion 111b is connected to the third source S13 of the third driving transistor T13 of the third pixel circuit 1023a and the fourth source S14 of the fourth driving transistor T14 of the fourth pixel circuit 1024a. In this way, the charges accumulated in the first portion 111a and the second portion 111b can be balanced, and the charges can be more dispersed.

[0097] For example, FIG. 6 is a schematic plan view of still another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 6, the extending direction of the first portion 111a and the extending direction of the second portion 111b are parallel, and both the first portion 111a and the second portion 111b extend along a straight line. The first portion 111a is connected to the first source S11 of the first driving transistor T11 of the first pixel circuit 1021a and the second source S12 of the second driving transistor T12 of the second pixel circuit 1022a. The second portion 111b is connected to the third source S13 of the third driving transistor T13 of the third pixel circuit 1023a and the fourth source S14 of the fourth driving transistor T14 of the fourth pixel circuit 1024a. The first portion 111a is located on the side close to the second induction line 109 of the second portion 111b. In this way, the wiring process can be made easier.

[0098] For example, as shown in FIG. 6, the first portion 111a is connected to the central region of the first source S11 and the second source S12. The second portion 111b is connected to the edge away from the second induction line 109 of the third source S13 and the edge away from the second induction line 109 of the fourth source S14. In this way, the size design of the display substrate can be made more accurate.

[0099] For example, FIG. 7 is a schematic plan view of yet another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 7, both the first portion 111a and the second portion 111b extend along a broken line. The first portion 111a is connected to an edge away from the second conductive line 109 of the first source S11 and is connected to the central region of the third source S13. The second portion 111b is connected to an edge away from the second conductive line 109 of the second source S12 and is connected to the central region of the fourth source S14. The first portion 111a and the second portion 111b are electrically connected to the first power supply voltage line 110 through the same via structure. Regarding the fact that both the first portion 111a and the second portion 111b extend along a broken line, according to the circuit design situation, the connection positions between the second power supply voltage line 111 and the first source S11, the second source S12, the third source S13, and the fourth source S14 can be adjusted flexibly.

[0100] For example, FIG. 8A is a schematic cross-sectional view along the A-A' line of the display substrate in FIGS. 1 to 3. As shown in FIG. 8A, the first drain D11 and the first light-shielding layer 103 are connected through the first via V11, and the first via V11 sequentially penetrates through the interlayer insulating layer 112, the gate insulating layer 113, and the buffer layer 114. As shown in FIG. 8A, the first drain D11 and the active layer 115 are connected through the second via V12, and the first source S11 and the active layer 115 are connected through the second via V12. The second via V12 sequentially penetrates through the interlayer insulating layer 112 and the gate insulating layer 113. In the structure shown in FIG. 8A, the gate G11 is provided on the side away from the first base substrate 101 of the active layer 115. Of course, the embodiments of the present disclosure are not limited thereto, and the gate G11 may be provided on the side close to the first base substrate 101 of the active layer 115.

[0101] For example, FIG. 8B is a schematic cross-sectional structure view along the B-B' line and the C-C' line of the display substrate in FIG. 4. As shown in FIG. 8B, on the side away from the first base substrate 101 of the first drain D11 and the first source S11, a passivation layer 121 and a planarization layer 122 are provided. On the side away from the first base substrate 101 of the planarization layer 122, a first electrode 123 is provided. The first electrode 123 may be an anode, and the first electrode 123 is connected to the first drain D11. On the side away from the first base substrate 101 of the first electrode 123, a first color light-emitting unit 1021e, a second color light-emitting unit 1022e, a third color light-emitting unit 1023e, and a fourth color light-emitting unit 1024e are arranged side by side.

[0102] For example, in one example, the first color light-emitting unit 1021e, the second color light-emitting unit 1022e, the third color light-emitting unit 1023e, and the fourth color light-emitting unit 1024e may be a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit, respectively. The first color light-emitting unit 1021e, the second color light-emitting unit 1022e, and the third color light-emitting unit 1023e may be a first color light-emitting layer that emits first color light, a second color light-emitting layer that emits second color light, and a third color light-emitting layer that emits third color light, respectively.

[0103] For example, in another example, the first color light-emitting unit 1021e, the second color light-emitting unit 1022e, the third color light-emitting unit 1023e, and the fourth color light-emitting unit 1024e may be a combination of a white light-emitting element and a first filter layer, a second filter layer, a third filter layer, and a light transmission layer. The first filter layer, the second filter layer, and the third filter layer may be a red filter layer, a green filter layer, and a blue filter layer, respectively.

[0104] For example, on the side away from the first base substrate 101 of the first color light-emitting unit 1021e, the second color light-emitting unit 1022e, the third color light-emitting unit 1023e, and the fourth color light-emitting unit 1024e, a second electrode may be further provided. The second electrode may be a cathode. For the other structures of the display substrate 100, a conventional design can be referred to, and in the embodiments of the present disclosure, this is not limited.

[0105] Note that the thin film transistor in the embodiments of the present disclosure may be a bottom gate type thin film transistor or a top gate type thin film transistor. FIGS. 8A and 8B illustrate an example in which the thin film transistor is a top gate type thin film transistor.

[0106] For example, FIG. 9 is a schematic plan view of still another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 9, the display substrate 100 further includes a first gate line 116 extending in the second direction Y, and a first gate 117 extending from the first gate line 116 and extending toward the side close to the second power supply voltage line 111. The planar shape of the first light shielding layer 103 includes a first sub-part 103a and a second sub-part 103b extending in the first direction X. There is a spacing region between the first light shielding layer 103 and the first gate line 116 and the first gate 117, so that there is a first capacitance between the first light shielding layer 103 and the first gate line 116, and a second capacitance between the first light shielding layer 103 and the first gate 117. A first distance W1 between a first side 103a' of the first sub-part 103a close to the first gate line 116 and the first gate line 116 is greater than a second distance W2 between a second side 103b' of the second sub-part 103b close to the first gate 117 and the first gate 117. In a plane parallel to the main surface of the first base substrate 101, since the area of the first sub-part 103a is larger than the area of the second sub-part 103b, the first distance W1 between the first side 103a' of the first sub-part 103a close to the first gate line 116 and the first gate line 116 is set to be greater than the second distance W2 between the second side 103b' of the second sub-part 103b close to the first gate 117 and the first gate 117, so that it can be ensured that the first capacitance between the first light shielding layer 103 and the first gate line 116 is the same as or substantially the same as the second capacitance between the first light shielding layer 103 and the first gate 117.

[0107] For example, as shown in FIG. 9, in a plane parallel to the main surface of the first base substrate 101, the overall shape formed by the first sub - portion 103a and the second sub - portion 103b included in the first light - shielding layer 103 includes a stepped shape, and the stepped shape is located at an edge close to the first gate line 116 of the first light - shielding layer 103.

[0108] For example, the first sub - portion 103a and the second sub - portion 103b included in the first light - shielding layer 103 may be integrated or may be connected via a bridge structure. In the embodiments of the present disclosure, this is not limited.

[0109] Note that FIG. 9 shows the design of the first sub - pixel 1021, but the second sub - pixel, the third sub - pixel, and the fourth sub - pixel may all have the above - mentioned structural design. That is, the second light - shielding layer 104, the third light - shielding layer 105, and the fourth light - shielding layer 106 may all have a structure including two parts similar to the first light - shielding layer 103.

[0110] For example, FIG. 10 is a schematic plan view of the planar structure of still another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 10, the second conductive line 109 includes two separated parts, and the two separated parts are connected to the first conductive line 108 via different via structures. The first conductive line 108 and the first power - supply voltage line 110 are provided adjacent to each other. Both the first conductive line 108 and the first power - supply voltage line 110 are provided between the second sub - pixel 1022 and the fourth sub - pixel 1024. For example, the second conductive line 109 is provided to include two separated parts, and since the two separated parts are not directly connected, it is possible to avoid the situation where the length of the second conductive line 109 is too long and too much charge accumulates in the second conductive line 109. For other structural designs of the display substrate 100, reference may be made to the above - related descriptions, and detailed descriptions are omitted here.

[0111] For example, FIG. 11 is a schematic plan view of still another display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 11, the display substrate 100 further includes a second gate line 118 parallel to the first gate line 116. The first gate 117 is configured as the gate of the first switching transistor N11. The second gate line 118 is configured as the gate of the first induction transistor M11 included in the first pixel circuit 1021a, the gate of the second induction transistor M12 included in the second pixel circuit 1022a, the gate of the third induction transistor M13 included in the third pixel circuit 1023a, and the gate of the fourth induction transistor M14 included in the fourth pixel circuit 1024a. The display substrate 100 includes the first gate line 116 and the second gate line 118 simultaneously. Thereby, in one sub-pixel, the switching transistor (for example, the first switching transistor) and the corresponding induction transistor (for example, the first induction transistor) are controlled by different control lines, and further, the adjustment of the switching transistor and the induction transistor in the same sub-pixel becomes more flexible.

[0112] For example, the display substrates in FIGS. 1 to 11 above are all organic light-emitting diode (OLED) display substrates, and the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element are all OLEDs. The plurality of gate lines and the plurality of data lines included in the display substrate are used to provide a scanning signal (control signal) and a data signal to the plurality of sub-pixels to drive the plurality of sub-pixels. The pixel circuit includes a drive sub-circuit for driving the light emission of the light-emitting element and a detection sub-circuit for detecting the electrical characteristics of the sub-pixel to achieve external compensation. In the embodiments of the present disclosure, the specific structure of the pixel circuit is not limited.

[0113] For example, FIG. 12 is a schematic diagram of a 3T1C pixel circuit for a display substrate according to at least one embodiment of the present disclosure. The pixel circuit may further include a compensation circuit, a reset circuit, etc. as required, and is not limited thereto in the embodiments of the present disclosure.

[0114] For example, as shown in FIG. 12, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. For example, the first transistor T1 may be a driving transistor, the second transistor T2 may be a switching transistor, the third transistor T3 may be an inductive transistor, a first pole of the second transistor T2 is electrically connected to a first capacitor electrode of the storage capacitor Cst and a gate of the first transistor T1, a second pole of the second transistor T2 is configured to receive a data signal GT, and the second transistor T2 is configured to write the data signal DT to the gate of the first transistor T1 and the storage capacitor Cst in response to a first control signal G1. A first pole of the first transistor T1 is electrically connected to a second capacitor electrode of the storage capacitor Cst and is configured to be electrically connected to a first electrode of a light-emitting element, a second pole of the first transistor T1 is configured to receive a first power supply voltage V1 (for example, a high power supply voltage VDD), and the first transistor T1 is configured to control a current for driving the light-emitting element under the control of a voltage of the gate of the first transistor T1. A first pole of the third transistor T3 is electrically connected to the first pole of the first transistor T1 and the second capacitor electrode of the storage capacitor Cst, a second pole of the third transistor T3 is connected to a first detection line and is configured to be connected to an external detection circuit, and the third transistor T3 is configured to detect an electrical characteristic of a sub-pixel where it is located and realize external compensation in response to a second control signal G2. The electrical characteristic includes, for example, a threshold voltage and / or carrier mobility of the first transistor T1, or a threshold voltage and driving current of the light-emitting element. The external detection circuit is a conventional circuit including, for example, a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), etc., and in the embodiments of the present disclosure, a detailed description thereof is omitted.

[0115] For example, any of the transistors used in the embodiments of the present disclosure may be a thin-film transistor, a field-effect transistor, or any other switching device having the same characteristics. In the embodiments of the present disclosure, it is described by taking the case where any of the transistors is a thin-film transistor as an example. Since the source and drain of the transistor used here may have a symmetric structure, the source and drain may not be structurally distinguishable. Further, according to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the on-voltage is a low-level voltage (for example, 0V, -5V, -10V, or any other appropriate voltage), and the off-voltage is a high-level voltage (for example, 5V, 10V, or any other appropriate voltage). When the transistor is an N-type transistor, the on-voltage is a high-level voltage (for example, 5V, 10V, or any other appropriate voltage), and the off-voltage is a low-level voltage (for example, 0V, -5V, -10V, or any other appropriate voltage). In the following description, it is described by taking the case where the transistor in FIG. 13 is an N-type transistor as an example, but the embodiments of the present disclosure are not limited thereto, and any other type of transistor may be used.

[0116] Hereinafter, with reference to the signal timing diagrams shown in FIGS. 13 to 15, the operation principle of the pixel circuit shown in FIG. 12 will be described. FIG. 13 is a signal timing diagram in the display process of the pixel circuit shown in FIG. 12, FIG. 14 is a first signal timing diagram in the detection process of the pixel circuit shown in FIG. 12, and FIG. 15 is a second signal timing diagram in the detection process of the pixel circuit shown in FIG. 12.

[0117] For example, as shown in FIG. 13, the display process of the image of each frame includes a data writing and resetting stage 1 and a light emitting stage 2. FIG. 13 shows the timing waveforms of each signal in each stage. In the data writing and resetting stage 1 of the operation process of the 3T1C pixel circuit, both the first control signal G1 and the second control signal G2 are on signals, the second transistor T2 and the third transistor T3 are conducting, the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, and the analog-to-digital converter writes a reset signal to the first electrode (for example, the anode of the OLED) of the light emitting element through the third transistor T3. The first transistor T1 is conducting, generating a driving current to charge the first electrode of the light emitting element to the operating voltage. In the light emitting stage 2, both the first control signal G1 and the second control signal G2 are off signals. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst does not change, the first transistor T1 operates in a saturation state, the current does not change, and it includes driving the light emitting element to emit light.

[0118] For example, FIG. 14 shows the signal timing diagram when the pixel circuit performs threshold voltage detection. The operation process of the 3T1C pixel circuit includes that both the first control signal G1 and the second control signal G2 are on signals, the second transistor T2 and the third transistor T3 are conducting, the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, and the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light emitting element through the detection line connected to the third transistor T3 and the third transistor T3. The first transistor T1 is conducting, charging node S until the first transistor T1 is cut off. Next, when the voltage on the detection line is sampled by the digital-to-analog converter, the threshold voltage of the first transistor T1 is obtained. This process can be performed, for example, when the display device formed on the display substrate is in a power-off state.

[0119] For example, FIG. 15 shows a signal timing diagram when the pixel circuit performs threshold voltage detection. In the first stage of the operation process of the 3T1C pixel circuit, both the first control signal G1 and the second control signal G2 are on signals, the second transistor T2 and the third transistor T3 are conducting, the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, and the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light-emitting element through the detection line connected to the third transistor T3 and the third transistor T3. In the second stage, the first control signal G1 is an off signal and the second control signal G1 is an on signal, the second transistor T2 is cut off, the third transistor T3 is conducting, the detection line connected to the third transistor T3 is floated, and due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst does not change, the first transistor T1 operates in a saturation state, the current does not change, the light-emitting element is driven to emit light, and then the digital-to-analog converter samples the voltage on the detection line and calculates the carrier mobility in the first transistor T1 in combination with the magnitude of the emission current. For example, this process can be performed during the blanking stage between display stages.

[0120] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained, and the corresponding compensation algorithm can be realized.

[0121] As can be understood, the first control signal G1 and the second control signal G2 may be on signals at different times. For example, the operation process of the 3T1C pixel circuit includes that in the first stage, the first control signal G1 is an on signal before the second control signal G2.

[0122] For example, the display substrate 100 may further include a data driving circuit and a scanning driving circuit. The data driving circuit is configured to be able to transmit data signals such as the above data signal DT as needed (for example, input an image signal of a display device including the display substrate). The pixel circuit of each sub-pixel is further configured to receive the data signal and apply the data signal to the gate of the first transistor. The scanning driving circuit is configured to output various scanning signals including, for example, the above first control signal G1 and second control signal G2, and is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly manufactured on the display substrate.

[0123] For example, the display substrate 100 further includes a control circuit. For example, the control circuit is configured to control the data driving circuit to apply a data signal and control the gate driving circuit to apply a scanning signal. An example of the control circuit is a timing control circuit (T-con). The control circuit may be in various forms. For example, it includes a processor and a memory. The memory includes executable code, and the processor executes the executable code to execute the above detection method.

[0124] For example, the processor may be a central processing unit (CPU) or another form of processing device having data processing ability and / or instruction execution ability, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.

[0125] For example, the memory device may include one or more computer program products, and the computer program products may include various forms of computer-readable storage media such as, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, and flash memory. One or more computer program instructions are stored in the computer-readable storage media, and the processor can execute the program instructions to realize the desired functions. The computer-readable storage media may further store various application programs and various data such as, for example, the electrical characteristic parameters obtained by the above detection method.

[0126] For example, FIG. 16 is a schematic cross-sectional structure diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 16, the display device 20 includes the display substrate 100 described in any one of the above embodiments and a cover plate 300 provided opposite to the display substrate 100. The cover plate 300 includes a second base substrate 301, and a quantum dot layer 302 is provided on the side of the second base substrate 301 close to the display substrate 100. The quantum dot layer 302 includes a plurality of quantum dot units 3021, and the plurality of quantum dot units 3021 correspond one-to-one to a plurality of sub-pixels. The color of each of the plurality of quantum dot units 3021 is the same as the color of the corresponding sub-pixel. The plurality of quantum dot units 3021 can improve the color gamut of the display device 20.

[0127] For example, in one example, the plurality of quantum dot units 3021 include a first quantum dot unit, a second quantum dot unit, and a third quantum dot unit. The color of the first quantum dot unit is the same as the color of the first sub-pixel, the color of the second quantum dot unit is the same as the color of the second sub-pixel, and the color of the third quantum dot unit is the same as the color of the third sub-pixel.

[0128] For example, in one example, the first sub-pixel, the second sub-pixel, and the third sub-pixel are a red sub-pixel, a green sub-pixel, and a blue sub-pixel respectively. Correspondingly, the first quantum dot unit, the second quantum dot unit, and the third quantum dot unit are a red quantum dot unit, a green quantum dot unit, and a blue quantum dot unit respectively.

[0129] For example, in one example, the plurality of quantum dot units 3021 includes a first quantum dot unit, a second quantum dot unit, a third quantum dot unit, and a fourth quantum dot unit. The color of the first quantum dot unit is the same as the color of the first sub-pixel, the color of the second quantum dot unit is the same as the color of the second sub-pixel, the color of the third quantum dot unit is the same as the color of the third sub-pixel, and the color of the fourth quantum dot unit is the same as the color of the fourth sub-pixel.

[0130] For example, in one example, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel respectively. Correspondingly, the first quantum dot unit, the second quantum dot unit, the third quantum dot unit, and the fourth quantum dot unit are a red quantum dot unit, a green quantum dot unit, a blue quantum dot unit, and a white quantum dot unit respectively.

[0131] For example, FIG. 16 shows, as an example, that the first sub-pixel corresponds to the first quantum dot unit. On the side of the first drain D11 and the first source S11 away from the first base substrate 101, a passivation layer 121 and a planarization layer 122 are provided. On the side of the planarization layer 122 away from the first base substrate 101, a first electrode 123 is provided. The first electrode 123 may be an anode, and the first electrode 123 is connected to the first drain D11. On the side of the first electrode 123 away from the first base substrate 101, a pixel defining layer 124 is provided. On the side of the pixel defining layer 124 away from the first base substrate 101, a first color light emitting unit 1021e is provided. In one example, the first color light emitting unit 1021e is a first color light emitting layer. On the side of the first color light emitting unit 1021e away from the first base substrate 101, a second electrode 126 is provided. The second electrode 126 may be a cathode.

[0132] For example, in another example, the first color light emitting unit 1021e, the second color light emitting unit 1022e, and the third color light emitting unit 1023e may be a combination of a white light emitting element and a first filter layer, a second filter layer, and a third filter layer. The first filter layer, the second filter layer, and the third filter layer may be a red filter layer, a green filter layer, and a blue filter layer, respectively. In the embodiments of the present disclosure, this is not limited.

[0133] For example, in another example, the first color light emitting unit 1021e, the second color light emitting unit 1022e, the third color light emitting unit 1023e, and the fourth color light emitting unit 1024e may be a combination of a white light emitting element and a first filter layer, a second filter layer, a third filter layer, and a light transmissive layer. The first filter layer, the second filter layer, and the third filter layer may be a red filter layer, a green filter layer, and a blue filter layer, respectively. In the embodiments of the present disclosure, this is not limited.

[0134] For example, as shown in FIG. 16, the first drain D11 and the first light-shielding layer 103 are connected via a first via V11, and the first via V11 sequentially penetrates through the interlayer insulating layer 112 and the buffer layer 114. The first drain D11 and the active layer 115 are connected via a second via V12, the first source S11 and the active layer 115 are connected via the second via V12, and the second via V12 penetrates through the interlayer insulating layer 112. For example, the gate G11 is provided on the side of the active layer 115 away from the first base substrate 101.

[0135] Note that the thin-film transistor in the embodiments of the present disclosure may be a bottom-gate type thin-film transistor or a top-gate type thin-film transistor. The drawings of the embodiments of the present disclosure will be described by taking the thin-film transistor as a top-gate type thin-film transistor as an example.

[0136] For example, the pixel defining layer 124 has a plurality of openings, and each opening of the pixel defining layer 124 corresponds one-to-one to the opening region of each sub-pixel of the display device 20.

[0137] For example, the first color light-emitting unit 1021e covers the pixel defining layer 124 and the plurality of openings of the pixel defining layer 124. As shown in FIG. 16, the portion located within the plurality of openings of the pixel defining layer 124 of the first color light-emitting unit 1021e is in contact with the first electrode 123 (anode), and the portion covering the pixel defining layer 124 of the first color light-emitting unit 1021e is not in contact with the first electrode 123 (anode). In this way, when the first color light-emitting unit 1021e realizes the light-emitting function, the portion that is not in contact with the pixel defining layer 124 of the first color light-emitting unit 1021e emits light, and the portion covering the pixel defining layer 124 of the first color light-emitting unit 1021e does not emit light.

[0138] For example, the first color light-emitting unit 1021e is a first color light-emitting layer. In some other embodiments, in addition to including the first color light-emitting layer, the first color light-emitting unit 1021e further includes one or more of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0139] For example, the display substrate 100 further includes a first thin-film package layer 129 and a second thin-film package layer 127. The second thin-film package layer 127 covers the side of the second electrode 126 (cathode) away from the first base substrate 101 and serves as a package. The first thin-film package layer 129 can be used to package the quantum dot layer described later. The first thin-film package layer 129 is provided on the side of the support layer 132 away from the second base substrate 302. After the display substrate 100 and the cover plate 300 are aligned to form the display device 20, the first thin-film package layer 129 and the second thin-film package layer 127 are provided opposite to each other.

[0140] For example, the second thin-film package layer 127 may be a high water resistance film layer, and the high water resistance film layer can be used to prevent external water and oxygen from affecting the display substrate 100. For example, the second thin-film package layer 127 may be made of a material such as silicon nitride or silicon oxide.

[0141] For example, as shown in FIG. 16, the display device 20 further includes a filling material 128 provided between the cover plate 300 and the display substrate 100. The filling material 128 can fill the gap formed after aligning the cover plate 300 and the display substrate 100 of the display device 20. Specifically, the filling material 128 is provided between the first thin film package layer 129 and the second thin film package layer 127. The first thin film package layer 129, the second thin film package layer 127, and the filling material 128 provided therebetween constitute a package structure and serve to package the display device 100. The filling material 128 can not only serve to support the cover plate 300 of the display device 20, but also serve to package the cover plate 300 and the display substrate 100 of the display device 20. When the filling material 128 is a curable transparent liquid, the display device 100 further includes a filling material bank structure provided on the side away from the first base substrate 101 of the second thin film package layer 127 of the display substrate 100. The filling material bank structure is annular, surrounds the periphery of the second thin film package layer 127, and the filling material 128 is filled in the region surrounded by the filling material bank structure.

[0142] For example, as shown in FIG. 16, each opening of the pixel defining layer 124 of the display substrate 100 corresponds one-to-one to the opening region of each sub-pixel of the display device 20, and each opening region S of the cover plate 300 of the display device 20 corresponds one-to-one to each opening of the pixel defining layer 124 of the display substrate 100. When the display device 20 realizes the display function, the light emitted from the portion that does not contact the pixel defining layer 124 of the first color light emitting unit 1021e passes through each opening region S of the cover plate 300 of the display device 20 and enters the human eye, thereby realizing the display of the screen.

[0143] For example, as shown in FIG. 16, the cover plate 300 includes a second base substrate 301, a black matrix 303 and a support layer 304 provided by being laminated on the side of the second base substrate 301 close to the display substrate 100. Both the black matrix 303 and the support layer 304 have a plurality of openings, and the plurality of openings of the black matrix 303 at least partially overlap with the plurality of openings of the support layer 304 respectively. For example, by almost overlapping or basically overlapping, the plurality of opening regions S are formed. The black matrix 303 is used to avoid the lateral light emitted by the first color light-emitting unit 1021e of the display substrate 100 from irradiating adjacent sub-pixels, thereby avoiding the problem that color mixing occurs in the display device 20. The support layer 304 has a specific height and can function as a spacer. After aligning the display substrate 100 and the cover plate 300, the support layer 304 is used to support the cover plate 300 of the display device 20.

[0144] For example, in one example, the black matrix 303 may be farther from the second base substrate 301 than the support layer 304. In another example, the black matrix 303 may be closer to the second base substrate 301 than the support layer 304.

[0145] For example, in the embodiments of the present disclosure, the material of the black matrix 303 is not limited, and the material can be selected according to the standard that the function of preventing pixel light leakage can be achieved. For example, the material of the black matrix 303 may be a metal material such as chromium, aluminum, silver or an aluminum-silver alloy.

[0146] For example, as shown in FIG. 16, the cover plate 300 of the display device 20 further includes a quantum dot layer 302 provided on the second base substrate 301, and the quantum dot layer 302 includes a plurality of quantum dot units 3021, and each quantum dot unit 3021 is located within one opening region S.

[0147] For example, since each opening region S corresponds one-to-one to each opening of the pixel defining layer 124 of the display substrate 100, each quantum dot unit 3021 located within each opening region S also corresponds one-to-one to each opening of the pixel defining layer 124. The light emitted from the portion of the first color light-emitting unit 1021e of the display substrate 100 that does not contact the pixel defining layer 124 passes through each quantum dot unit 3021 in the process of passing through each opening region S.

[0148] For example, the quantum dots in the quantum dot unit 3021 are spherical semiconductor nanoparticles composed of II-VI or III-V group elements, and the particle size of the quantum dots ranges from several nanometers to dozens of nanometers. Due to the existence of the quantum confinement effect, the originally continuous energy band of the quantum dot material becomes a discrete energy level structure, and the quantum dot can be excited by external light to emit visible light. The frequency of the emitted visible light changes with the change of the particle size of the quantum dot, and by adjusting the particle size of the quantum dot, the color of the light it emits can be controlled. In the embodiments of the present disclosure, each quantum dot unit 3021 can be excited by the light emitted by the first color light-emitting unit 1021e of the display substrate 100 to emit light of a corresponding color to enhance the color gamut.

[0149] For example, due to the influence of the material properties of the quantum dots, the quantum dot unit may not be able to completely absorb the excitation light irradiated thereon. By increasing the thickness of the quantum dot unit, the quantum dot unit may be made to absorb as much excitation light as possible, thereby improving the light emission efficiency of the quantum dot unit. For example, the black matrix may be in a bank structure to isolate each quantum dot unit, thereby ensuring that no color mixing phenomenon occurs between quantum dot units of different colors. Due to the influence of the material and manufacturing process of the black matrix, it is impossible for the thickness of the black matrix to reach 2 μm or more, so it is also impossible for the thickness of each quantum dot unit to reach 2 μm or more. Therefore, simply isolating each quantum dot unit with the black matrix in a bank structure makes it difficult to make the quantum dot unit very thick, and as a result, the thickness of the quantum dot unit is limited.

[0150] For example, each quantum dot unit 3021 is located within the opening region S formed by the black matrix 303 and the support layer 304, and the black matrix 303 and the support layer 304 constitute the bank structure of each quantum dot unit 3021. As the material of the support layer 304 can be a material that can be manufactured thickly, in this way, since the support layer 304 can be manufactured thickly, the bank structure composed of the black matrix 303 and the support layer 304 can also be manufactured thickly, and further the thickness of each first-color light-emitting unit 1021e can be increased, so that the first-color light-emitting unit 1021e can absorb as much excitation light as possible, improving the light emission efficiency of the first-color light-emitting unit 1021e and further improving the light emission efficiency of the display device 100.

[0151] For example, as shown in FIG. 16, the display device 100 may be a top emission type display device, and the light emitted by the first-color light-emitting unit 1021e of the display substrate 100 passes through the second electrode 126, the second thin film package layer 127, and the first thin film package layer 129 in sequence and irradiates the quantum dot layer 302.

[0152] For example, as shown in FIG. 16, the cover plate 300 of the display device 20 according to an embodiment of the present disclosure further includes a color filter layer 305 provided between the first color light-emitting unit 1021e and the second base substrate 301. The color filter layer 305 includes a plurality of filter units 3051, and each filter unit 3051 is located within one opening region S. For example, the filter unit 3051 located within one opening region S has the same color as the quantum dot unit 3021 corresponding thereto. For example, in the structure shown in FIG. 16, the filter unit 3051 is a red filter unit.

[0153] For example, in one example, the filter unit 3051 may include a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units. When the plurality of quantum dot units 3021 include a plurality of red quantum dot units and a plurality of green quantum dot units, the plurality of red filter units and the plurality of red quantum dot units are located within one opening region S, and the plurality of green filter units and the plurality of green quantum dot units are located within one opening region S.

[0154] Embodiments of the present disclosure further provide a method for manufacturing a display substrate. The manufacturing method includes the steps of: providing a first base substrate; forming a plurality of sub-pixels on the first base substrate, where the formation of the plurality of sub-pixels includes the formation of a first sub-pixel and a second sub-pixel; the formation of the first sub-pixel includes the formation of a first pixel circuit and a first effective light-emitting region; the formation of the second sub-pixel includes the formation of a second pixel circuit and a second effective light-emitting region; forming a first light-shielding layer between the first pixel circuit and the first base substrate, where the orthographic projection of the first light-shielding layer onto the first base substrate at least partially overlaps with the orthographic projection of the first pixel circuit onto the first base substrate; forming a second light-shielding layer between the second pixel circuit and the first base substrate, where the orthographic projection of the second light-shielding layer onto the first base substrate at least partially overlaps with the orthographic projection of the second pixel circuit onto the first base substrate. The wavelength of the light emitted from the first effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region. The ratio of the area of the first light-shielding layer to the area of the first sub-pixel is a, and the ratio of the area of the second light-shielding layer to the area of the second sub-pixel is b. The range of the ratio M1 of a to b is 1.020 to 1.120. The display substrate formed by this manufacturing method can adjust the aperture ratio of the plurality of sub-pixels 102 to enhance the final light mixing effect. Also, the process of manufacturing the display substrate becomes easier, and the light-emitting efficiency becomes higher.

[0155] For example, FIG. 17 is a flowchart of a method for manufacturing a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 17, the manufacturing method includes the following steps.

[0156] S11: Provide a first base substrate.

[0157] S12: Form a plurality of sub-pixels on the first base substrate, and the formation of the plurality of sub-pixels includes the formation of a first sub-pixel and a second sub-pixel.

[0158] S13: The formation of the first sub-pixel includes the formation of a first pixel circuit and a first effective light-emitting region.

[0159] S14: The formation of the second sub-pixel includes the formation of the second pixel circuit and the second effective light-emitting region.

[0160] S15: A first light-shielding layer is formed between the first pixel circuit and the first base substrate, and the orthographic projection of the first light-shielding layer onto the first base substrate at least partially overlaps with the orthographic projection of the first pixel circuit onto the first base substrate.

[0161] S16: A second light-shielding layer is formed between the second pixel circuit and the first base substrate, and the orthographic projection of the second light-shielding layer onto the first base substrate at least partially overlaps with the orthographic projection of the second pixel circuit onto the first base substrate. The wavelength of the light emitted from the first effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region. The ratio of the area of the first light-shielding layer to the area of the first sub-pixel is a, and the ratio of the area of the second light-shielding layer to the area of the second sub-pixel is b. The range of the ratio M1 of a to b is 1.020 to 1.120.

[0162] For example, the material of the first base substrate may include glass, plastic, or other light-transmissive materials.

[0163] For example, the plurality of sub-pixels formed on the first base substrate may be arranged in a matrix, that is, a plurality of sub-pixels are provided in both a first direction and a second direction that intersect each other.

[0164] For example, the first sub-pixel and the second sub-pixel included in the plurality of sub-pixels may be two adjacent sub-pixels arranged side by side in the second direction in one pixel unit, or two spaced-apart sub-pixels arranged side by side in the second direction in one pixel unit. In the embodiments of the present disclosure, this is not limited, and it is only necessary to satisfy that the first sub-pixel and the second sub-pixel are in the same pixel unit.

[0165] For example, in one example, the first sub-pixel and the second sub-pixel are a red sub-pixel and a green sub-pixel respectively. Correspondingly, the first effective light-emitting region is a red light-emitting region, and the second effective light-emitting region is a green light-emitting region. Usually, the light-emitting area of the red sub-pixel is larger than that of the green sub-pixel, that is, the area of the first effective light-emitting region is larger than the area of the second effective light-emitting region. By setting the area of the first light-shielding layer to be larger than the area of the second light-shielding layer, the aperture ratio of a plurality of sub-pixels can be adjusted to enhance the light mixing effect. Also, the manufacturing process of the display substrate becomes easier, and the light-emitting efficiency becomes higher.

[0166] For example, the first light-shielding layer and the second light-shielding layer may be formed of the same material in the same process step. The materials of the first light-shielding layer and the second light-shielding layer may be a light-shielding metal material or other conductive materials having light-shielding properties. The embodiments of the present disclosure do not limit this.

[0167] For example, when the ratio M1 of a to b is less than 1.020, the ratio a of the area of the first light-shielding layer to the area of the first sub-pixel is slightly small, the aperture ratio of the first sub-pixel is large, and the aperture ratio of the second sub-pixel is small. As a result, the final color mixing effect is not good. When the ratio M1 of a to b is greater than 1.120, the ratio a of the area of the first light-shielding layer to the area of the first sub-pixel is slightly large, the aperture ratio of the first sub-pixel is small, and the aperture ratio of the second sub-pixel is large. As a result, the final color mixing effect is not good.

[0168] For example, in one example, the aperture ratio of the first sub-pixel is n1(1 - a), and the aperture ratio of the second sub-pixel is n2(1 - b),

Number

Number

[0169] For example, the above formula [Number] is (Initial luminance of sub-pixel * aperture ratio of pixel / Initial luminance of pixel unit) * Emission lifetime of sub-pixel = C 定数 can be derived by this formula. For the specific derivation process, reference can be made to the relevant description of the above display substrate, and detailed description is omitted here.

[0170] For example, the process of forming one sub-pixel (for example, the first sub-pixel) among a plurality of sub-pixels is as shown in FIGS. 18A to 18H. FIGS. 18A to 18H illustrate by taking the sub-pixel as the first sub-pixel as an example, that is, FIGS. 18A to 18H are diagrams of the formation process of the first sub-pixel according to at least one embodiment of the present disclosure.

[0171] For example, as shown in FIG. 18A, a first base substrate 101 is provided, and a first light-shielding layer 103 is formed on the first base substrate 101. For example, for the materials of the first base substrate 101 and the first light-shielding layer 103, reference can be made to the above relevant description of the display substrate, and detailed description is omitted here.

[0172] For example, a first light-shielding layer thin film may be formed on the first base substrate 101. The formation process of the first light-shielding layer thin film includes depositing a metal material having light-shielding properties or forming the first light-shielding layer thin film by a magnetron sputtering method, and then patterning the first light-shielding layer thin film using a lithography process to form the first light-shielding layer 103.

[0173] For example, as shown in FIG. 18B, a buffer layer 114 and an active layer 115 are sequentially formed on the first light-shielding layer 103.

[0174] For example, the buffer layer 114 covers the entire first base substrate 101, and the orthographic projection of the active layer 115 onto the first base substrate 101 overlaps with the orthographic projection of the first light-shielding layer 103 onto the first base substrate 101. For example, the overlapping area between the orthographic projection of the active layer 115 onto the first base substrate 101 and the orthographic projection of the first light-shielding layer 103 onto the first base substrate 101 is 75% - 95% of the area of the orthographic projection of the active layer 115 onto the first base substrate 101. For example, the overlapping area between the orthographic projection of the active layer 115 onto the first base substrate 101 and the orthographic projection of the first light-shielding layer 103 onto the first base substrate 101 is 90% or more of the area of the orthographic projection of the active layer 115 onto the first base substrate 101.

[0175] For example, as shown in FIG. 18C, a gate insulating layer thin film and a first metal layer thin film are formed on the side of the active layer 115 away from the first base substrate 101, and a patterning process is performed on the gate insulating layer thin film and the first metal layer thin film to form a gate insulating layer 113 and a first metal layer 133. The first metal layer 133 includes a second power supply voltage line 111, a first gate line 116, and a second induction line 109.

[0176] For example, as shown in FIG. 18D, an interlayer insulating layer 112 is formed on the side of the first metal layer 133 away from the first base substrate 101, a first via V11 penetrating the interlayer insulating layer 112, the gate insulating layer 113, and the buffer layer 114 is formed, a second via V12 penetrating the interlayer insulating layer 112, and a plurality of third vias V13 penetrating the interlayer insulating layer 112 and the gate insulating layer 113 are formed.

[0177] For example, as shown in FIG. 18E, a second metal layer 134 is formed on the side of the interlayer insulating layer 112 away from the first base substrate 101. The second metal layer 134 includes a first power supply voltage line 110, a data line 107, a first induction line 108, a first source S11 of the first driving transistor T11, a first drain D11 of the first driving transistor T11, a source of the first switching transistor N11, a drain of the first switching transistor N11, a source of the first induction transistor M11, and a drain of the first induction transistor M11. The first source S11 of the first driving transistor T11 and the second power supply voltage line 111 are connected via a second via V12. The drain of the first induction transistor M11 and the second induction line 109 are connected via a second via V12. The first drain D11 of the first driving transistor T11 and the first light shielding layer 103 are connected via a first via V11. The first source S11 of the first driving transistor T11 is connected to the active layer 115 via a third via V13, the first drain D11 of the first driving transistor T11 is connected to the active layer 115 via a third via V13, the source of the first switching transistor N11 is connected to the active layer 115 via a third via V13, the drain of the first switching transistor N11 is connected to the active layer 115 via a third via V13, the source of the first induction transistor M11 is connected to the active layer 115 via a third via V13, and the drain of the first induction transistor M11 is connected to the active layer 115 via a third via V13.

[0178] For example, as shown in FIG. 18F, a passivation layer 121 and a planarization layer 122 are formed on the side of the second metal layer 134 away from the first base substrate 101, and a fourth via V14 penetrating the passivation layer 121 and the planarization layer 122 is formed. For example, the fourth via V14 may be an anode via, that is, the anode formed subsequently can be electrically connected to the second metal layer 134 via the fourth via V14.

[0179] For example, as shown in FIG. 18G, a first electrode 123 is formed on the side of the planarization layer 122 away from the first base substrate 101. The first electrode 123 is an anode, and the first electrode 123 is electrically connected to the second metal layer 134 through a fourth via V14.

[0180] For example, as shown in FIG. 18H, a first color light-emitting unit 1021e is formed on the side of the first electrode 123 away from the first base substrate 101. The first color light-emitting unit 1021e includes a first color light-emitting layer. For example, the first color light-emitting layer is a light-emitting layer that emits red light.

[0181] For example, in one example, for the formation processes of the second sub-pixel, the third sub-pixel, and the fourth sub-pixel located in the same pixel unit as the first sub-pixel, the related description of the formation process of the first sub-pixel can be referred to, and the detailed description is omitted here.

[0182] For example, in one example, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel may be a green sub-pixel, a blue sub-pixel, and a white sub-pixel respectively. For the structure of the finally formed display substrate, the related description of the display substrate can be referred to, and the detailed description is omitted here.

[0183] The display substrate, its manufacturing method, and the display device according to at least one embodiment of the present disclosure have at least one of the following beneficial technical effects.

[0184] (1) The display substrate according to at least one embodiment of the present disclosure adjusts the aperture ratio corresponding to different sub-pixels by designing the size of the light-shielding layer corresponding to different sub-pixels, thereby making the entire process of the manufacturing process of the display substrate easier.

[0185] (2) The display substrate according to at least one embodiment of the present disclosure can enhance the final color mixing effect by setting the range of the ratio M1 of the ratio a of the area of the first light-shielding layer to the area of the first sub-pixel and the ratio b of the area of the second light-shielding layer to the area of the second sub-pixel to be 1.020 to 1.120.

[0186] (3) The display substrate according to at least one embodiment of the present disclosure can increase the final light mixing effect by adjusting the aperture ratios of the first sub-pixel and the second sub-pixel by setting the area of the first light-shielding layer to be larger than the area of the second light-shielding layer. Also, the entire manufacturing process of the display substrate becomes easier, and the light-emitting efficiency of the display substrate becomes higher.

[0187] The following points need to be explained.

[0188] (1) The drawings of the embodiments of the present disclosure relate only to the structures according to the embodiments of the present disclosure, and other structures can refer to the conventional designs.

[0189] (2) For clarity, in the drawings for explaining the embodiments of the present disclosure, the thickness of the layer or region is enlarged or reduced, that is, these drawings are not drawn to the actual scale.

[0190] (3) If there is no contradiction, the embodiments and features of the embodiments of the present disclosure can be combined with each other to obtain a new embodiment.

[0191] The above are only specific embodiments of the present disclosure, and the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be in accordance with the protection scope of the foregoing claims.

Claims

1. A display board, First base board and A plurality of subpixels provided on the first base substrate, including a first subpixel and a second subpixel, The first subpixel includes a first pixel circuit and a first effective light-emitting region. The aforementioned second subpixel includes a second pixel circuit and a second effective light-emitting region, A first light-shielding layer is provided between the first pixel circuit and the first base substrate. The orthographic projection of the first light-shielding layer onto the first base substrate overlaps at least partially with the orthographic projection of the first pixel circuit onto the first base substrate. A second light-shielding layer is provided between the second pixel circuit and the first base substrate. The orthographic projection of the second light-shielding layer onto the first base substrate overlaps at least partially with the orthographic projection of the second pixel circuit onto the first base substrate. A display substrate in which the wavelength of light emitted from the first effective light-emitting region is greater than the wavelength of light emitted from the second effective light-emitting region, the ratio of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel is a, the ratio of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel is b, and the range of the ratio M1 of a to b is 1.020 to 1.

120.

2. The display substrate according to claim 1, wherein the area of ​​the first subpixel is equal to the area of ​​the second subpixel, and the ratio of the area of ​​the first light-shielding layer to the area of ​​the second light-shielding layer in a plane parallel to the main surface of the first base substrate is equal to M1.

3. The aperture ratio of the first subpixel is n1(1-a), and the aperture ratio of the second subpixel is n2(1-b). [Math 1] The display substrate according to claim 1 or 2, wherein K1 is the ratio of the initial brightness of the second subpixel to the initial brightness of the first subpixel, K2 is the ratio of the lifetime of the second subpixel to the lifetime of the first subpixel, n1 is the ratio of the area of ​​the aperture region of the first subpixel to the area of ​​the portion of the first subpixel not shielded by the first light-shielding layer, n2 is the ratio of the area of ​​the aperture region of the second subpixel to the area of ​​the portion of the second subpixel not shielded by the second light-shielding layer, the range of the value of (n2 / n1)M2 is 1.000 to 1.130, and the range of the value of (1-a) / (1-b) is 0.877 to 0.

997.

4. The aforementioned plurality of subpixels further include a third subpixel, The aforementioned three subpixels include a third pixel circuit and a third effective light-emitting region. A third light-shielding layer is provided between the third pixel circuit and the first base substrate. The orthographic projection of the third light-shielding layer onto the first base substrate overlaps at least partially with the orthographic projection of the third pixel circuit onto the first base substrate. The wavelength of light emitted from the third effective light-emitting region is smaller than the wavelength of light emitted from the second effective light-emitting region, and in a plane parallel to the main surface of the first base substrate, the area ratio c of the third light-shielding layer is equal to the ratio of the area of ​​the third light-shielding layer to the area of ​​the third subpixel, and the aperture ratio of the third subpixel is n3(1-c). [Math 2] The display substrate according to claim 1, wherein K3 is the ratio of the initial brightness of the second subpixel to the initial brightness of the third subpixel, K4 is the ratio of the lifetime of the second subpixel to the lifetime of the third subpixel, n3 is the ratio of the area of ​​the aperture region of the third subpixel to the area of ​​the portion of the third subpixel other than the region shielded by the third light-shielding layer, the range of the value of (n2 / n3)M3 is 0.190 to 0.260, and the range of the value of (1-c) / (1-b) is 1.002 to 1.

350.

5. The aforementioned plurality of subpixels further include a fourth subpixel, The aforementioned fourth subpixel includes a fourth pixel circuit and a fourth effective light-emitting region, A fourth light-shielding layer is provided between the fourth pixel circuit and the first base substrate. The orthographic projection of the fourth light-shielding layer onto the first base substrate overlaps at least partially with the orthographic projection of the fourth pixel circuit onto the first base substrate. The display substrate according to claim 4, wherein the wavelength of light emitted from the fourth effective light-emitting region is greater than the wavelength of light emitted from the second effective light-emitting region, and in a plane parallel to the main surface of the first base substrate, the area ratio d of the fourth light-shielding layer is equal to the ratio of the area of ​​the fourth light-shielding layer to the area of ​​the fourth subpixel, and the range of the aperture ratio n4(1-d) of the fourth subpixel is 0.230 to 0.950, where n4 is the ratio of the area of ​​the aperture region of the fourth subpixel to the area of ​​the portion of the fourth subpixel other than the region shielded by the fourth light-shielding layer.

6. The first subpixel further includes a first light-emitting element, the first pixel circuit controls the emission of light from the first light-emitting element, and the color of the light emitted by the first light-emitting element is the same as the color of the light emitted from the first effective light-emitting region. The second subpixel further includes a second light-emitting element, the second pixel circuit controls the emission of light from the second light-emitting element, and the color of the light emitted by the second light-emitting element is the same as the color of the light emitted from the second effective light-emitting region. The display substrate according to claim 4, wherein the third subpixel further includes a third light-emitting element, the third pixel circuit controls the emission of light from the third light-emitting element, and the color of the light emitted by the third light-emitting element is the same as the color of the light emitted from the third effective light-emitting region.

7. The first subpixel further includes a first light-emitting element, and the first pixel circuit controls the emission of light from the first light-emitting element. The second subpixel further includes a second light-emitting element, and the second pixel circuit controls the emission of light from the second light-emitting element. The third subpixel further includes a third light-emitting element, and the third pixel circuit controls the emission of light from the third light-emitting element. The fourth subpixel further includes a fourth light-emitting element, and the fourth pixel circuit controls the emission of light from the fourth light-emitting element. The first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element are all white light-emitting elements, and a first filter layer, a second filter layer, a third filter layer, and a light-transmitting layer are provided on the side of the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element that is away from the first base substrate, respectively. The display substrate according to claim 5, wherein the color of the light emitted from the first filter layer is the same as the color of the light emitted from the first effective light-emitting region, the color of the light emitted from the second filter layer is the same as the color of the light emitted from the second effective light-emitting region, the color of the light emitted from the third filter layer is the same as the color of the light emitted from the third effective light-emitting region, and the color of the light emitted from the light-transmitting layer is the same as the color of the light emitted from the fourth effective light-emitting region.

8. The transmittance of the material in the first filter layer is λ1, the transmittance of the material in the second filter layer is λ2, the transmittance of the material in the third filter layer is λ3, and the transmittance of the material in the light-transmitting layer is λ4. The total transmittance of the first filter layer, the second filter layer, the third filter layer and the light transmission layer is [Math 3] The range of the value of λ4 is 0.260 to 0.

950. The sum of the transmittances of the first filter layer, the second filter layer, and the third filter layer and the transmittance of the light transmission layer are 【Number 4】 The display board according to claim 7, wherein the condition is met and the range of the value of n4(1-d) is 0.260 to 0.

860.

9. The display substrate according to claim 8, wherein, in a plane parallel to the main surface of the first base substrate, the ratio of the sum of the areas of the first filter layer, the second filter layer, the third filter layer and the light transmission layer to the sum of the areas of the first light-shielding layer, the second light-shielding layer, the third light-shielding layer and the fourth light-shielding layer is in the range of 1.050 to 6.

800.

10. The display substrate according to claim 9, wherein the ratio of the area of ​​the first filter layer to the area of ​​the first light-shielding layer in a plane parallel to the main surface of the first base substrate is in the range of 2.000 to 3.

000.

11. The display substrate according to claim 9, wherein the ratio of the area of ​​the second filter layer to the area of ​​the second light-shielding layer in a plane parallel to the main surface of the first base substrate is in the range of 1.1074 to 1.6938.

12. It further includes a data line and a first guide line extending in a first direction, and a second guide line extending in a second direction, The data line and the second guide line intersect to define a plurality of pixel regions, and each of the pixel regions contains the subpixel. The display substrate according to claim 5, wherein a first power supply voltage line parallel to the data line is provided between adjacent subpixels, a second power supply voltage line parallel to the second direction is provided on the side of the first effective light-emitting region adjacent to the first light-shielding layer, the second power supply voltage line intersects with the first power supply voltage line and is connected to the first drain of the first drive transistor of the first pixel circuit, and the orthographic projection of the second power supply voltage line onto the first base substrate coincides with the orthographic projection of the first light-shielding layer onto the first base substrate.

13. The display board according to claim 12, wherein the orthographic projection of the second power supply voltage line onto the first base substrate overlaps with the orthographic projection of the fourth light-shielding layer onto the first base substrate.

14. The display board according to claim 13, wherein the orthographic projection of the second power supply voltage line onto the first base substrate overlaps with the orthographic projection of the third light-shielding layer onto the first base substrate, and also overlaps with the orthographic projection of the second light-shielding layer onto the first base substrate.

15. The display substrate according to claim 14, wherein the overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the first light-shielding layer onto the first base substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the second light-shielding layer onto the first base substrate.

16. The display substrate according to claim 14, wherein the overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the first light-shielding layer onto the first base substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the third light-shielding layer onto the first base substrate.

17. The overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the first light-shielding layer onto the first base substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the fourth light-shielding layer onto the first base substrate. The overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the fourth light-shielding layer onto the first base substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the third light-shielding layer onto the first base substrate. The display substrate according to claim 14, wherein the overlapping area of ​​the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the third light-shielding layer onto the first base substrate is greater than the overlapping area of ​​the orthographic projection of the second light-shielding layer onto the first base substrate.

18. In one of the first subpixels, the overlap area between the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the first light-shielding layer onto the first base substrate is 0.03 to 0.30 square microns. In one of the second subpixels, the overlap area between the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the fourth light-shielding layer onto the first base substrate is 0.02 to 0.20 square microns. In one of the third subpixels, the overlap area between the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the third light-shielding layer onto the first base substrate is 0 to 0.05 square microns. The display substrate according to claim 14, wherein in one of the fourth subpixels, the overlap area between the orthographic projection of the second power supply voltage line onto the first base substrate and the orthographic projection of the second light-shielding layer onto the first base substrate is 0 to 0.08 square microns.

19. The display board according to claim 12, wherein the second power supply voltage line includes a first portion and a second portion that are separated from each other, and the first portion and the second portion are connected to the first power supply voltage line via different via structures.

20. The first portion is connected to the first drain of the first drive transistor of the first pixel circuit and the second drain of the second drive transistor of the second pixel circuit. The display board according to claim 19, wherein the second portion is connected to the third drain of the third drive transistor of the third pixel circuit and the fourth drain of the fourth drive transistor of the fourth pixel circuit.

21. The display substrate according to claim 19, wherein the extending direction of the first portion and the extending direction of the second portion are parallel, both the first portion and the second portion extend along a straight line, and the first portion is located on the side of the second portion that is close to the second guide line.

22. The display board according to claim 21, wherein the first portion is connected to the central region of the first drain and the second drain, and the second portion is connected to the edge of the third drain away from the second guide line and the edge of the fourth drain away from the second guide line.

23. The display board according to claim 20, wherein both the first and second portions extend along a broken line, the first portion is connected to the edge of the first drain away from the second guide line and to the central region of the second drain, and the second portion is connected to the edge of the third drain away from the second guide line and to the central region of the fourth drain.

24. The display substrate according to claim 20, wherein the first drain and the first light-shielding layer are connected via a first via that sequentially penetrates the interlayer insulating layer, the gate insulating layer, and the buffer layer.

25. The system further includes a first gate line extending in the second direction, and a first gate extending from the first gate line and extending toward the side adjacent to the second power supply voltage line, The display substrate according to claim 12, wherein the planar shape of the first light-shielding layer includes a first sub-part and a second sub-part extending in the first direction, and the first distance between the first side of the first sub-part adjacent to the first gate line and the first gate line is greater than the second distance between the second side of the second sub-part adjacent to the first gate and the first gate.

26. The display board according to claim 25, further comprising a second gate line parallel to the first gate line, wherein the first gate is configured as the gate of a first switching transistor, and the second gate line is configured as the gate of a first inductor transistor included in the first pixel circuit, the gate of a second inductor transistor included in the second pixel circuit, the gate of a third inductor transistor included in the third pixel circuit, and the gate of a fourth inductor transistor included in the fourth pixel circuit.

27. A display device comprising a display substrate as described in claim 1 and a cover plate provided opposite to the display substrate, wherein the cover plate includes a second base substrate, a quantum dot layer is provided on the side of the second base substrate adjacent to the display substrate, the quantum dot layer includes a plurality of quantum dot units, the plurality of quantum dot units correspond one-to-one with a plurality of subpixels, and the color of each of the plurality of quantum dot units is the same as the color of the corresponding subpixel.

28. The display device according to claim 27, further comprising a black matrix provided on the side of the second base substrate adjacent to the display substrate, wherein the black matrix has a plurality of apertures, and each quantum dot unit is located within one of the apertures.

29. A method for manufacturing a display board, The steps include providing a first base substrate, A step of forming a plurality of subpixels on the first base substrate, wherein the formation of the plurality of subpixels includes the formation of a first subpixel and a second subpixel, The formation of the first subpixel includes the steps of forming a first pixel circuit and a first effective light-emitting region, The formation of the second subpixel includes the steps of forming a second pixel circuit and a second effective light-emitting region, A step of forming a first light-shielding layer between the first pixel circuit and the first base substrate, wherein the orthographic projection of the first light-shielding layer onto the first base substrate overlaps at least partially with the orthographic projection of the first pixel circuit onto the first base substrate, The process includes the step of forming a second light-shielding layer between the second pixel circuit and the first base substrate, wherein the orthographic projection of the second light-shielding layer onto the first base substrate at least partially overlaps with the orthographic projection of the second pixel circuit onto the first base substrate, A method for manufacturing a display substrate, wherein the wavelength of light emitted from the first effective light-emitting region is greater than the wavelength of light emitted from the second effective light-emitting region, the ratio of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel is a, the ratio of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel is b, and the range of the ratio M1 of a to b is 1.020 to 1.

120.

30. The aperture ratio of the first subpixel is n1(1-a), and the aperture ratio of the second subpixel is n2(1-b). [Math 5] The manufacturing method according to claim 29, wherein K1 is the ratio of the initial brightness of the second subpixel to the initial brightness of the first subpixel, K2 is the ratio of the lifetime of the second subpixel to the lifetime of the first subpixel, n1 is the ratio of the area of ​​the aperture region of the first subpixel to the area of ​​the portion of the first subpixel not shielded by the first light-shielding layer, n2 is the ratio of the area of ​​the aperture region of the second subpixel to the area of ​​the portion of the second subpixel not shielded by the second light-shielding layer, the range of the value of (n2 / n1)M2 is 1.000 to 1.130, and the range of the value of (1-a) / (1-b) is 0.877 to 0.997.

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