Semiconductor equipment

Abstract

A pulse signal output circuit capable of stable operation and a shift resistor including the same. One of the objectives is to provide [a service / product]. [Solution] A pulse signal output circuit according to one aspect of the disclosed invention includes a node connected to the output terminal. The channel length of the transistors that make up the system is the channel length of the transistor that functions as the output terminal. Make it larger than the length of the loop. This will suppress current leakage from the node and prevent leakage over a long period of time. This makes it possible to maintain a stable potential over a long period, preventing malfunctions in the pulse signal output circuit. It can be stopped.

Description

Technical Field

[0001] The disclosed invention relates to a pulse signal output circuit and a shift register.

Background Art

[0002] Transistors formed on a flat plate such as a glass substrate, which are used in liquid crystal display devices and the like, are mainly fabricated using a semiconductor material such as amorphous silicon or polycrystalline silicon. Amorphous Although the transistror using silicon has a low field-effect mobility, it can cope with the large area of the glass substrate. On the other hand, the transistror using polycrystalline silicon has a high field-effect mobility, but requires a crystallization process such as laser annealing and does not necessarily suit the large area of the glass substrate.

[0003] In contrast, transistors using an oxide semiconductor as a semiconductor material have attracted attention. For example, techniques for fabricating a transistor using zinc oxide or an In-Ga-Zn-O-based oxide semiconductor as a semiconductor material and using it as a switching element of an image display device are disclosed in Patent Document 1 and Patent Document Patent Document 2.

[0004] A transistor using an oxide semiconductor in the channel formation region has a higher field-effect mobility than a transistor using amorphous silicon. Further, since the oxide semiconductor film can be formed at a temperature of 300°C or lower by a sputtering method or the like, a transistor using an oxide semiconductor is easier to fabricate than a transistor using polycrystalline silicon. Moreover, the oxide semiconductor film can be formed at a temperature of 300°C or lower by a sputtering method or the like, so a transistor using an oxide semiconductor is easier to fabricate than a transistor using polycrystalline silicon. Moreover, since the oxide semiconductor film can be formed at a temperature of 300°C or lower by a sputtering method or the like, a transistor using an oxide semiconductor is easier to fabricate than a transistor using polycrystalline silicon. A transistor fabricated using such an oxide semiconductor is used in a liquid crystal display, an electric

[0005] Such transistors fabricated using an oxide semiconductor are used in liquid crystal displays, electric It is expected to be applied to the pixel portion and the drive circuit of a display device such as a trolluminescence display or electronic paper. For example, a technology for configuring the pixel portion and the drive circuit of a display device by a transistor manufactured using the above oxide semiconductor is disclosed in Non-Patent Document 1. However, all the transistors manufactured using the above oxide semiconductor are n-channel type transistors. Therefore, when configuring a drive circuit using a transistor manufactured using an oxide semiconductor, the drive circuit will be composed only of n-channel type transistors.

Prior Art Documents

[0006]

Patent Documents

Patent Document 1

Patent Document 2

Non-Patent Documents

[0007]

[0008]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] When the drive circuit is composed of a shift register including a pulse signal output circuit or the like, problems such as unstable operation may occur when the shift register is composed of unipolar transistors.

[0010] ​​​​​​​​In view of the above-mentioned problems, one aspect of the present invention provides a pulse signal output cycle that can operate stably. One of the objectives is to provide a path and a shift register including it. [Means for solving the problem]

[0011] We provide a pulse signal output circuit capable of stable operation and a shift register including the same. One of the objectives is to achieve the following. One form of the pulse signal output circuit is a single transistor The drain terminal or drain terminal is connected to the gate electrode of another transistor, and the other transistor The source terminal or drain terminal of the inverter forms the output terminal of the pulse signal output circuit. The channel length of the first transistor is made larger than the channel length of the other transistor. This reduces the leakage current that changes the gate potential of the other transistors. This prevents malfunction of the pulse signal output circuit.

[0012] More specifically, the following configuration can be adopted, for example.

[0013] One aspect of the present invention comprises first to ninth transistors, a first input signal generation circuit, and a second The input signal generation circuit comprises a first terminal of a first transistor and a second transistor The first terminal of the transistor is electrically connected to the first output terminal, and the first terminal of the third transistor is connected to the first output terminal of the third transistor. The first terminal of the fourth transistor is electrically connected to the second output terminal, and the first input The force signal generation circuit has a fifth transistor and a sixth transistor, and the fifth transistor The first terminal of the zista and the first terminal of the sixth transistor are electrically connected. It functions as the output terminal of the input signal generation circuit, and the second input signal generation circuit is the 7th to 9th It has a transistor, the second terminal of the seventh transistor and the second terminal of the eighth transistor The terminal and the first terminal of the ninth transistor are electrically connected to the second input signal generation circuit. It functions as the output terminal of the circuit, and the gate terminal of the first transistor and the third transistor The gate terminal and the output terminal of the first input signal generation circuit are electrically connected, and the second transistor The gate terminal of the transistor, the gate terminal of the fourth transistor, and the second input signal generation circuit. The output terminal of the sixth transistor is electrically connected to the third transistor, and the channel length of the sixth transistor is the same as that of the third transistor. The channel length of the zista and the channel length of the 4th transistor are greater than the channel length of the 9th transistor The channel length of the transistor is the channel length of the third transistor and the channel length of the fourth transistor. This is a pulse signal output circuit with a pulse length greater than the pulse duration.

[0014] Furthermore, in the pulse signal output circuit described above, the second terminal of the first transistor and the third The second terminal of the transistor receives the first clock signal, and the second transistor The second terminal, the second terminal of the fourth transistor, and the second terminal of the sixth transistor The second terminal of the ninth transistor is given the first potential, and the fifth transistor The second terminal, the first terminal of the seventh transistor, and the first terminal of the eighth transistor A second potential higher than the first potential is applied, and the gate terminal of the fifth transistor and the The gate terminal of transistor 9 receives the first pulse signal, and transistor 6... The output signal of the second input signal generation circuit is input to the gate terminal, and the gate of the seventh transistor A third pulse signal is input to the gate terminal, and a second pulse signal is input to the gate terminal of the eighth transistor. A clock signal is input, and a second pulse signal is output from either the first or second output terminal. It is preferable to output the following:

[0015] Furthermore, in the pulse signal output circuit described above, the sixth transistor or the ninth transistor At least one of the gates is a multi-gate type having at least two gates arranged in series. A transistor would also work.

[0016] Another aspect of the present invention includes a first to eleventh transistor and a first input signal generation circuit. It has a path and a second input signal generation circuit, and the first terminal of the first transistor and the second The first terminal of the transistor is electrically connected to the first output terminal, and the third transistor The first terminal of the transistor and the first terminal of the fourth transistor are electrically connected to the second output terminal. The first input signal generation circuit has a fifth transistor to a seventh transistor, The first terminal of transistor 5, the first terminal of transistor 6, and transistor 7 The first terminal of the 7th transistor is electrically connected to the first terminal of the 7th transistor. The second input signal generation circuit functions as an output terminal of the input signal generation circuit, and the 8th to 11th input signal generation circuits are It has a transistor, the second terminal of the 11th transistor and the terminal of the 9th transistor It is electrically connected to terminal 1, the second terminal of transistor 9, and transistor 8 The second terminal of the 10th transistor and the first terminal of the 10th transistor are electrically connected to the second input It functions as the output terminal of the force signal generation circuit, and the gate terminal of the first transistor and the third transistor The gate terminal of the transistor and the output terminal of the first input signal generation circuit are electrically connected. , the gate terminal of the second transistor, the gate terminal of the fourth transistor, and the second input The output terminal of the signal generation circuit is electrically connected to the sixth transistor, and the channel length of the sixth transistor is The channel length of the third transistor is greater than the channel length of the fourth transistor, The channel length of the 10 transistors is the channel length of the 3rd transistor and the 4th transistor This is a pulse signal output circuit with a longer channel length than the ZISTA.

[0017] Furthermore, in the pulse signal output circuit described above, the second terminal of the first transistor and the third The second terminal of the transistor receives the first clock signal, and the second transistor The second terminal, the second terminal of the fourth transistor, and the second terminal of the sixth transistor The second terminal of the tenth transistor is given the first potential, and the fifth transistor The second terminal of the transistor, the gate terminal of the seventh transistor, and the first terminal of the eighth transistor Then, a second potential higher than the first potential is applied to the first terminal of the 11th transistor. The gate terminal of the fifth transistor and the gate terminal of the tenth transistor are connected to the first transistor. A signal is input, and the gate terminal of the sixth transistor receives the output of the second input signal generation circuit. A power signal is input, and a third pulse signal is input to the gate terminal of the eighth transistor. The gate terminal of the ninth transistor receives the second clock signal, and the eleventh transistor... A third clock signal is input to the gate terminal of the sta, and either the first output terminal or the second output terminal. It is preferable to output a second pulse signal from the terminal.

[0018] Furthermore, in the pulse signal output circuit described above, the sixth transistor or the tenth transistor At least one of the gates is a multi-gate type having at least two gates arranged in series. A transistor would also be acceptable.

[0019] Furthermore, in the pulse signal output circuit according to one aspect of the present invention described above, one terminal is a second terminal The gate terminal of the transistor, the gate terminal of the fourth transistor, and the second input signal generation circuit The output terminal of the path further comprises a capacitive element electrically connected to a node to which it is electrically connected. It's fine if you do that.

[0020] Furthermore, in the above, it is preferable to use an oxide semiconductor in one of the multiple transistors. Yes. Furthermore, a shift register can be constructed using multiple of the above-mentioned pulse signal output circuits. can.

[0021] In addition, in the above, an oxide semiconductor may be used to construct a transistor, but disclosure The inventions are not limited to these.

[0022] In this specification, the terms "above" and "below" refer to the relative position of the constituent elements, meaning "directly above". Or, it does not necessarily mean "directly below". For example, "gate on the gate insulating layer The term "electrode" implies that there are other components between the gate insulating layer and the gate electrode. Do not exclude it.

[0023] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to that. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes." This also includes cases where "or wiring" is formed as a single unit.

[0024] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are interchangeable. It is assumed that this is possible.

[0025] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0026] For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. These include switching elements, resistive elements, inductors, capacitors, and various other functional elements. This includes elements such as [specific components]. [Effects of the Invention]

[0027] We provide a pulse signal output circuit capable of stable operation and a shift register including the same. It is possible. [Brief explanation of the drawing]

[0028] [Figure 1] A diagram showing an example configuration of a pulse signal output circuit and a shift register. [Figure 2] Shift register timing chart. [Figure 3] A diagram illustrating the operation of a pulse signal output circuit. [Figure 4] A diagram illustrating the operation of a pulse signal output circuit. [Figure 5] A diagram showing an example configuration of a pulse signal output circuit. [Figure 6] A diagram showing an example configuration of a pulse signal output circuit and a shift register. [Figure 7] Shift register timing chart. [Figure 8] A diagram illustrating the operation of a pulse signal output circuit. [Figure 9] A diagram illustrating the operation of a pulse signal output circuit. [Figure 10] A diagram showing an example configuration of a pulse signal output circuit. [Figure 11] A diagram showing an example of a transistor configuration. [Figure 12] A diagram illustrating an example of a transistor fabrication method. [Figure 13] A diagram illustrating one form of semiconductor device. [Figure 14] A diagram showing electronic equipment. [Modes for carrying out the invention]

[0029] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0030] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0031] Furthermore, in this specification, ordinal numbers such as "1st," "2nd," and "3rd" are used in relation to the constituent elements. This note is added to avoid ambiguity and does not indicate a numerical limitation.

[0032] (Embodiment 1) In this embodiment, a pulse signal output circuit and a shift resistance including a pulse signal output circuit The configuration and operation of the device will be explained with reference to Figures 1 to 4. <Circuit Configuration>

[0033] First, the pulse signal output circuit and the circuit of the shift register including the pulse signal output circuit. An example configuration will be explained with reference to Figure 1.

[0034] The shift register shown in this embodiment is a first pulse signal output circuit 10 _1 ~The nth Pal S signal output circuit 10 _n (n≧2) and the first signal line 11 to the fourth that transmit the clock signal It has a signal line 14 (see Figure 1(A)). The first signal line 11 has a first clock signal ( A clock signal (CLK1) is applied, and a second clock signal (CLK2) is applied to the second signal line 12. Then, the third signal line 13 is supplied with the third clock signal (CLK3), and the fourth signal line 1 A fourth clock signal (CLK4) is applied to 4.

[0035] A clock signal is a signal that alternates between an H signal (high potential) and an L signal (low potential) at regular intervals. Here, the first clock signal (CLK1) to the fourth clock signal (CLK4) are: The signal is delayed by 1 / 4 period at a time. In this embodiment, the above clock signal is used, It controls the pulse signal output circuit, etc.

[0036] First pulse signal output circuit 10 _1 ~nth pulse signal output circuit 10 _n These are, First input terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, It has a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see Figure 1(B)). see).

[0037] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first signal line 11 It is electrically connected to one of the fourth signal lines 14. For example, the first pulse signal output cycle road 10 _1 The first input terminal 21 is electrically connected to the first signal line 11, and the second input Terminal 22 is electrically connected to the second signal line 12, and the third input terminal 23 is connected to the third signal line 1 It is electrically connected to 3. Also, the second pulse signal output circuit 10 _2 is the first input Terminal 21 is electrically connected to the second signal line 12, and the second input terminal 22 is connected to the third signal line 1 The third input terminal 23 is electrically connected to the fourth signal line 14. Here, the nth pulse signal output circuit 10 _n The signal line connected to the second This shows the case where signal line 12, third signal line 13, and fourth signal line 14 are connected. The signal lines will differ depending on the value of n. Therefore, the configuration shown here is only a partial representation. Please note that this is just one example.

[0038] Furthermore, in the m-th pulse signal output circuit (m≧2) of the shift register shown in this embodiment, The fourth input terminal 24 is connected to the first output terminal 26 of the (m-1) pulse signal output circuit. Connected electrically, the fifth input terminal 25 is the first output of the (m+2) pulse signal output circuit. The terminal 26 is electrically connected, and the first output terminal 26 is the (m+1) pulse signal output circuit. The fourth input terminal 24 is electrically connected, and the second output terminal 27 sends a signal to OUT(m). Output.

[0039] For example, the third pulse signal output circuit 10 _3 So, the fourth input terminal 24 is the second pulse signal No. output circuit 10_2 is electrically connected to the first output terminal 26, and the fifth input terminal 25 is the fifth pulse signal output circuit 10 _5 is electrically connected to the first output terminal 26, and the first output terminal 26 is the fourth pulse signal output circuit 10 _4 of the fourth input terminal 24 and the first pulse signal output circuit 10 _1 is electrically connected to the fifth input terminal 25.

[0040] Also, in the first pulse signal output circuit 10 _1 , the first start pulse (SP1) from the fifth wiring 15 or the like is input to the fourth input terminal 24. Also, in the k-th pulse signal output circuit 1 0 0 _k (where k is a natural number from 2 to n), the output pulse of the previous stage is input to the fourth input terminal 24. Also, in the (n - 1)-th pulse signal output circuit 10 , the second start pulse (SP2) is input to the fifth input _(nー1) terminal 25. Also, in the n-th pulse signal output circuit 10 circuit 10 _n , the third start pulse (SP3) is input to the fifth input terminal 25 . Note that the second start pulse (SP2) and the third start pulse (SP3) may be signals input from the outside or signals generated inside the circuit.

[0041] Next, the specific _1 configuration of the first pulse signal output circuit 10 to the n-th pulse signal output circuit 10 _n will be described. configuration will be described.

[0042] Each of the first pulse signal output circuit 10 _1 to the n-th pulse signal output circuit 10 _n is composed of a pulse signal generation circuit composed of the first transistor 101 to the fourth transisttor 104, and The first input signal generator consists of the fifth transistor 105 to the seventh transistor 107. The circuit and the second input consisting of the 8th transistor 108 to the 11th transistor 111 It includes a force signal generation circuit (see Figure 1(C)). Also, the first input terminal 21 to the above-mentioned terminal In addition to the input terminal 25 of 5, the first transistor receives power from the first power line 31 and the second power line 32. Signals are supplied to transistors 101 through 111.

[0043] A specific example of the configuration of a pulse signal generation circuit is as follows:

[0044] The first terminal of the first transistor 101 (either the source terminal or the drain terminal; the same applies hereafter) The first terminal of the second transistor 102 is electrically connected to the first output terminal 26. Similarly, the first terminal of the third transistor 103 and the fourth transistor 104 The first terminal is electrically connected to the second output terminal 27. And the first transistor The gate terminal of transistor 101, the gate terminal of the third transistor 103, and the first input signal The output terminal of the circuit is electrically connected to the gate of the second transistor 102. The terminal, the gate terminal of the fourth transistor 104, and the output terminal of the second input signal generation circuit. These are electrically connected.

[0045] The second terminal of the first transistor 101 (the other terminal of the source and drain terminals, the same applies hereafter) The first clock signal is input to this. Also, the second terminal of the first transistor 101 It also functions as the first input terminal 21 of the pulse signal output circuit. Second transistor 1 The second terminal of 02 is connected to a first potential (e.g., low potential VSS) via the first power line 31. The first clock signal is input to the second terminal of the third transistor 103. It also functions as the first input terminal 21 of the pulse signal output circuit. The fourth transistor 1 A first potential is applied to the second terminal of 04 via the first power line 31.

[0046] A specific example of the configuration of the first input signal generation circuit is as follows:

[0047] The first terminal of the fifth transistor 105 and the first terminal of the sixth transistor 106, The first terminal of the seventh transistor 107 is electrically connected to the seventh transistor The second terminal of the ZISTA 107 functions as the output terminal of the first input signal generation circuit.

[0048] A second potential is applied to the second terminal of the fifth transistor 105 via the second power supply line 32. And the second terminal of the sixth transistor 106 is connected to the first power line 31 A potential is applied, and the gate terminal of the fifth transistor 105 receives a pulse signal from the previous stage. The first pulse signal output circuit receives a signal (including a start pulse signal). Also, the fifth The gate terminal of transistor 105 is used as the first input terminal of the first input signal generation circuit. It also functions as the fourth input terminal 24 of the pulse signal output circuit. The gate terminal of the inverter 106 receives the output signal from the second input signal generation circuit. Furthermore, the gate terminal of the sixth transistor 106 is connected to the second input terminal of the first input signal generation circuit. It functions as a child. The gate terminal of the seventh transistor 107 is connected to the second power line 32. Then a second potential is given.

[0049] In this embodiment, a seventh transistor 107 is provided, but the seventh transistor It is also possible to have a configuration without providing transistor 107. If a seventh transistor 107 is provided, The potential of the first terminal of the fifth transistor 105 that may occur due to the strapping action The rise can be suppressed. In other words, between the gate and source of the fifth transistor 105 (or gate This prevents a large bias voltage from being applied (between the terminal and the drain), thus the fifth transistor This can suppress the deterioration of Zista 105.

[0050] A specific example of the configuration of the second input signal generation circuit is as follows:

[0051] The second terminal of the 11th transistor 111 and the first terminal of the 9th transistor 109 They are electrically connected. Also, the second terminal of the ninth transistor and the eighth transistor The second terminal of the transistor and the first terminal of the 10th transistor are electrically connected to the second input. It functions as the output terminal of a signal generation circuit.

[0052] The first terminal of the eighth transistor 108 and the first terminal of the eleventh transistor 111 A second potential is applied via the second power line 32. The tenth transistor 110 The second terminal is supplied with a first potential via the first power line 31. The eighth transistor The gate terminal of TA108 receives a pulse signal from two stages behind. Also, the 8th transistor The gate terminal of ZISTA 108 functions as the first input terminal of the second input signal generation circuit. It also functions as the fifth input terminal 25 of the pulse signal output circuit. The ninth transistor The gate terminal of transistor 109 receives the second clock signal. Also, the ninth transistor... The gate terminal of 109 functions as the second input terminal of the second input signal generation circuit, and It also functions as the second input terminal 22 of the pulse signal output circuit. 10th transistor 1 The gate terminal 10 receives the pulse signal from the previous stage (in the first pulse signal output circuit, the start terminal...) A signal (L-S) is input. Also, the gate terminal of the 10th transistor 110 is connected to the second input. It functions as the third input terminal of the force signal generation circuit, and also as the fourth input of the pulse signal output circuit. It also functions as power terminal 24. The gate terminal of the 11th transistor 111 has a third cross-connector. A ping signal is input. Also, the gate terminal of the 11th transistor 111 is connected to the second input. It functions as the fourth input terminal of the signal generation circuit and as the third input of the pulse signal output circuit. It also functions as terminal 23.

[0053] In the pulse signal output circuit shown in this embodiment, the sixth transistor 106 The channel length is the channel length of the third transistor 103 and the channel length of the fourth transistor 104. It is larger than the channel length. Also, the channel length of the 10th transistor 110 is greater than that of the 3rd transistor It is greater than the channel length of transistor 103 and the channel length of the fourth transistor 104. This results in the threshold voltage of the sixth transistor 106 and the tenth transistor 110. This reduces the amount of pressure shift and suppresses deterioration.

[0054] The configurations of the pulse signal output circuit described above (pulse signal generation circuit, first input signal generation) are as follows: The circuit and the configuration example of the second input signal generation circuit are merely examples, and the disclosed invention is not limited to these examples. This is not the only example.

[0055] In the following description of this embodiment, the first to The gate terminal of transistor 101, the gate terminal of the third transistor 103, and the first input Let Node A be the node formed by the connection between the output terminal of the force signal generation circuit and the other terminal. , the gate terminal of the second transistor 102 and the gate terminal of the fourth transistor 104 The node formed by the connection between the output terminal of the second input signal generation circuit and node B is called node B. do.

[0056] Between node A and the first output terminal 26, in order to suitably perform the bootstrap operation, A capacitive element may be provided. Also, in order to maintain the potential of node B, A capacitive element connected by gas may be provided.

[0057] Furthermore, the first transistor 101 to the eleventh transistor 111 use oxide semiconductors. It is preferable to have one. By using an oxide semiconductor, the off-current of the transistor can be reduced. It is possible to do so. Furthermore, compared to amorphous silicon, etc., on-current and field effect transfer are possible. The degree can be increased. Also, transistor degradation can be suppressed. This enables the creation of electronic circuits with low power consumption, high-speed operation, and improved operational accuracy. Transistors using oxide semiconductors will be described in detail in a later embodiment. Therefore, I will omit it here.

[0058] <Operation> Next, the operation of the shift register shown in Figure 1 will be explained with reference to Figures 2 to 4. Specifically, each period from the first period 51 to the sixth period 56 in the timing chart shown in Figure 2. The operation in this case will be explained using Figures 3 and 4. In the timing chart, CLK1~ CLK4 indicates the clock signal, SP1 indicates the first start pulse, and OUT 1 to OUT4 are the first pulse signal output circuit 10 _1 ~Fourth pulse signal output circuit 10 _ This shows the output from the second output terminal of node 4, where node A and node B are respectively connected to node A. The potentials of node B are shown, and SROUT1 to SROUT4 are the first pulse signal output circuit 1. 0 _1 ~Fourth pulse signal output circuit 10 _4 This shows the output from the first output terminal.

[0059] In the following explanation, the first transistor 101 to the eleventh transistor 111 are All transistors are assumed to be n-channel type transistors. Also, in Figures 3 and 4, When a transistor is represented by a solid line, it indicates that the transistor is in a conductive state (on state). This indicates that the transistor is in a non-conductive state, and if it is represented by a dashed line, it means that the transistor is in a non-conductive state. This indicates that the state is "off".

[0060] Typical example, the first pulse signal output circuit 10 _1 The operation will be explained. The first pulse signal No. output circuit 10 _1 The configuration is as described above. Also, each input signal and the supplied The relationships between the potentials are as described above. In the following explanation, each input terminal and each power line is used. All given high potentials (also called H level, H signal, etc.) are treated as VDD, and low potentials (L level) are treated as VDD. All signals (also called L signals, etc.) are treated as VSS.

[0061] During the first period 51, SP1 is at a high level, so the first pulse signal output circuit 10 _1The gate terminal of the fifth transistor 105 functions as the fourth input terminal 24 and the first A high potential is applied to the gate terminal of transistor 110, and the fifth transistor 105 and The tenth transistor 110 becomes conductive. During the first period 51, CLK3 is also high. Because it is at a certain level, the 11th transistor 111 also turns on. Also, the 7th transistor Because a high potential is applied to the gate terminal of transistor 107, the seventh transistor 107 This also turns on (see Figure 3(A)).

[0062] When the fifth transistor 105 and the seventh transistor 107 are turned ON, The potential of line A rises. Also, the 10th transistor 110 turns on. Therefore, the potential of node B decreases. The potential of the second terminal of the fifth transistor 105 is VDD. Therefore, the potential of the first terminal of the fifth transistor 105 is the same as the potential of the second terminal. This value (VDD-Vth105) is the value obtained by the threshold voltage of transistor 105. And, since the potential of the gate terminal of the seventh transistor 107 is VDD, the seventh transistor If the threshold voltage Vth107 of the inverter 107 is Vth105 or higher, then node A The potential becomes (VDD-Vth107), and the seventh transistor 107 turns off. On the other hand, if Vth107 is less than Vth105, the seventh transistor 107 is ON. While maintaining this state, the potential of node A rises to (VDD-Vth105). Below, the first The point at which the potential of node A reaches during period 51 is V. AH Let's assume that Vth105 is Vth107 are the fifth transistor 105 and the seventh transistor 10, respectively. This is the threshold voltage of 7. The same applies to the other transistors below. The voltage of node A V AH When it reaches this point, the fifth transistor 105 and the seventh transistor 107 When it turns off, node A becomes V AH It remains suspended while maintaining that state.

[0063] The potential at node A is V AH Then, the first transistor 101 and the third transistor 103 is turned ON. Here, CLK1 is at a low level, so the first output terminal 26 And an L level output is output from the second output terminal 27.

[0064] During the second period 52, CLK1 switches from the L level to the H level. Here, Since transistor 101 and transistor 303 are in the ON state, the first output The potential of the power terminal 26 and the potential of the second output terminal 27 rise. Furthermore, the first transistor A capacitance exists between the gate terminal and source terminal (or drain terminal) of the TA101, This results in capacitive coupling between the gate terminal and the source terminal (or drain terminal). Similarly, the gate terminal and source terminal (or drain terminal) of the third transistor 103 A capacitance exists between them, which causes the gate terminal and the source terminal (or drain terminal) to They are capacitively coupled. Therefore, the potential of the first output terminal 26 and the potential of the second output terminal 27 As the potential increases, the potential of node A, which is in a floating state, will also increase (bootstrike (P-operation). The potential of node A eventually becomes higher than VDD+Vth101, and the first output The potential at terminal 26 and the potential at the second output terminal 27 are VDD (H level) (Figure 2) See Figure 3(B).

[0065] Furthermore, during the second period 52, the tenth transistor 110 is in the ON state, Node B is also maintained at an L level. Therefore, the first output terminal 26 changes from an L level to an H level. This suppresses the potential fluctuations at node B caused by capacitive coupling when the level changes, and prevents the following It can prevent the onset of illness.

[0066] During the third period 53, SP1 becomes L level, and the fifth transistor 105 and the first Transistor 110, which is set to 0, is turned off. Also, CLK1 is maintained at a high level, and no Since the potential of A does not change, VD is emitted from the first output terminal 26 and the second output terminal 27. D (H level) is output (see Figure 3(C)). Note that in the third period 53, node B Although it enters a floating state, the potential of the first output terminal 26 does not change, thus preventing malfunctions due to capacitive coupling. It is negligible.

[0067] In the fourth period 54, CLK2 and CLK3 are at the H level, therefore Node B The potential rises rapidly. Also, CLK1 becomes low. As a result, the second transient When transistor 102 and the fourth transistor 104 are turned on, the first output terminal 26 and The potential of the second output terminal 27 drops rapidly (see Figure 4(A)).

[0068] During the fifth period 55, the fifth input terminal 25 (i.e., SROUT3) maintains a high level. By holding, the potential of node B is maintained. Therefore, the second transistor 102 The ON state of the fourth transistor 104 and the sixth transistor 106 is maintained. The potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level (Figure 4(B) )reference).

[0069] During the sixth period 56, the fifth input terminal 25 (i.e., SROUT3) becomes L level. As a result, the eighth transistor 108 turns off. At this time, node B has the aforementioned potential It remains suspended while being held. As a result, the second transistor 102 and the fourth transistor The ON state of transistor 104 and the sixth transistor 106 continues (see Figure 4(C)).

[0070] Note that the potential of node B usually decreases due to the transistor's off-current, etc., but Apply a transistor with a low off-current (for example, a transistor using an oxide semiconductor). In this case, such problems do not occur, and the decrease in the potential of node B can be suppressed. can.

[0071] Furthermore, transistors using wide-bandgap semiconductors such as oxide semiconductors use silicon Because, unlike transistors, threshold control through doping cannot be applied. Even when the gate is not biased (the gate and source are at the same potential), the source and source Current may flow between rains. However, the pulse signal output shown in this embodiment In the power circuit, the channel length of the 10th transistor 110 is set to that of the 3rd transistor 103. By making it larger than the channel length of the fourth transistor 104, the current from node B Because leakage can be suppressed, it is possible to stably maintain the potential of node B. Furthermore, the channel length of the sixth transistor 106 is set to the same length as that of the third transistor 103. By making it larger than the channel length of transistor 104, the current from node A is This suppresses the process, thus stabilizing the bootstrap operation at node A. This can be achieved by applying the configuration of this embodiment, the potential of node A and the node Because the potential of circuit B can be maintained for a long period of time, for example, in low-frequency circuits Even when applied, it can prevent malfunctions.

[0072] Furthermore, in order to further mitigate the decrease in potential at node B, as shown in Figure 5(A), one of the electric currents A capacitive element 120 with its pole electrically connected to node B may be provided separately. The other electrode may be provided, for example, by being electrically connected to the first power line 31.

[0073] Also, as shown in Figure 5(B), the sixth transistor 106 or the tenth transistor 110 is a multi-gate type transistor having at least two gates arranged in series. As a structure, the potential drop at node B can be further mitigated. Note that in Figure 5(B) This uses a multi-gate type for both the sixth transistor 106 and the tenth transistor 110. An example is shown where the transistor is the sixth transistor 106 or the tenth transistor One of the TA110 components may also be a multi-gate transistor. Of course, as shown in Figure 5(A) The configuration shown and the configuration shown in Figure 5(B) may be used in combination.

[0074] As shown in Figure 5(B), by applying a multi-gate transistor, the transistor This allows for redundancy of the staves, thereby improving the yield of the pulse signal output circuit. It is possible.

[0075] Furthermore, if both CLK2 and CLK3 are at the H level during the following period, Transistor 9 (109) and transistor 111 (11) are turned on, and periodically no A potential is applied to B. Therefore, when using a transistor with a relatively large off-current... Even so, it is possible to prevent malfunctions in the pulse signal output circuit.

[0076] In this embodiment, the shift register is output from the mth pulse signal output circuit. The pulse being generated and the pulse output from the (m+1)th pulse signal output circuit overlap by half. This drive method is employed. Therefore, compared to cases where this drive method is not employed, the wiring load is The time that can be used for power can be extended. In other words, this drive method allows for a large negative charge. A pulse signal output circuit that can withstand loads and operate at high frequencies is provided.

[0077] (Embodiment 2) In this embodiment, the pulse signal output circuit and shifted signal shown in the previous embodiment are used. Examples of configurations different from the ZISTA and their operation will be explained with reference to Figures 6 to 9. . <Circuit Configuration>

[0078] First, the pulse signal output circuit and the circuit of the shift register including the pulse signal output circuit. An example configuration will be explained with reference to Figure 6.

[0079] The shift register configuration shown in this embodiment is the same as the shift register shown in the previous embodiment. It is similar to the configuration of the sta. One difference is the first pulse signal output circuit 10 _1 ~the nth Pulse signal output circuit 10 _n The difference is that it does not have a third input terminal 23 (Figure 6(A)). (See Figure 6(C)). In other words, two types of clock signals are input to one pulse signal output circuit. It is powered. The other configurations are the same as in the previous embodiment.

[0080] First pulse signal output circuit 10 _1 ~nth pulse signal output circuit 10 _n This is the third input Since it does not have terminal 23, it does not have an 11th transistor connected to it (Figure 6(C) (See reference). Consequently, some of the connection relationships within the second input signal generation circuit have been changed. Yes, they are.

[0081] A specific example of the configuration of the second input signal generation circuit is as follows:

[0082] The second terminal of the ninth transistor 109 and the second terminal of the eighth transistor 108, The first terminal of the tenth transistor 110 is electrically connected to the second input signal generation circuit. It functions as an output terminal for the circuit.

[0083] The first terminal of the eighth transistor 108 and the first terminal of the ninth transistor 109 are A second potential is applied via the second power line 32. The tenth transistor 110 A first potential is applied to terminal 2 via the first power line 31. Eighth transistor A pulse signal is input to the gate terminal of transistor 108. Also, the gate of the 8th transistor 108 The terminal functions as the first input terminal of the second input signal generation circuit, and also as a pulse signal It also functions as the fifth input terminal 25 of the output circuit. The gate of the ninth transistor 109. The second clock signal is input to the terminal. Also, the gate terminal of the ninth transistor 109 The child functions as the second input terminal of the second input signal generation circuit and also as a pulse signal output. It also functions as the second input terminal 22 of the circuit. Gate terminal of the 10th transistor 110 A pulse signal is input to it. Also, the gate terminal of the 10th transistor 110 is the 2 It functions as the third input terminal of the input signal generation circuit, and also as the fourth input terminal of the pulse signal output circuit. It also functions as input terminal 24.

[0084] In the pulse signal output circuit shown in this embodiment, the sixth transistor 106 The channel length is the channel length of the third transistor 103 and the channel length of the fourth transistor 104. It is larger than the channel length. Also, the channel length of the 10th transistor 110 is greater than that of the 3rd transistor It is greater than the channel length of transistor 103 and the channel length of the fourth transistor 104. This results in the threshold voltage of the sixth transistor 106 and the tenth transistor 110. This reduces the amount of pressure shift and suppresses deterioration.

[0085] The above-described configuration is merely an example, and the disclosed invention is not limited to this.

[0086] In the following description of this embodiment, as in the previous embodiment, the pulse signal output shown in Figure 6(C) In the power circuit, the gate terminal of the first transistor 101 and the third transistor 103 A node formed by connecting the gate terminal and the output terminal of the first input signal generation circuit Let this be node A. Also, the gate terminal of the second transistor 102 and the fourth transistor It is formed by connecting the gate terminal of TA104 and the output terminal of the second input signal generation circuit. Let the node be called node B.

[0087] Between node A and the first output terminal 26, in order to suitably perform the bootstrap operation, A capacitive element may be provided. Also, in order to maintain the potential of node B, A capacitive element connected by gas may be provided.

[0088] Furthermore, the first transistor 101 to the tenth transistor 110 use oxide semiconductors. It is preferable to have one. By using an oxide semiconductor, the off-current of the transistor can be reduced. It is possible to do so. Furthermore, compared to amorphous silicon, etc., on-current and field effect transfer are possible. The degree can be increased. Also, transistor degradation can be suppressed. This enables the creation of electronic circuits with low power consumption, high-speed operation, and improved operational accuracy. Transistors using oxide semiconductors will be described in detail in a later embodiment. Therefore, I will omit it here.

[0089] <Operation> Next, the operation of the shift register shown in Figure 6 will be explained with reference to Figures 7 to 9. Specifically Specifically, each period from the first period 51 to the fifth period 55 in the timing chart shown in Figure 7. The operation in this case will be explained using Figures 8 and 9. In the timing chart, CLK1~ CLK4 indicates the clock signal, SP1 indicates the first start pulse, and OUT 1 to OUT4 are the first pulse signal output circuit 10 _1 ~Fourth pulse signal output circuit 10 _ This shows the output from the second output terminal of node 4, where node A and node B are respectively connected to node A. The potentials of node B are shown, and SROUT1 to SROUT4 are the first pulse signal output circuit 1. 0 _1 ~Fourth pulse signal output circuit 10 _4 This shows the output from the first output terminal.

[0090] In the following explanation, the first transistor 101 to the tenth transistor 110 are All transistors are assumed to be n-channel type transistors. Also, in Figures 8 and 9, When a transistor is represented by a solid line, it indicates that the transistor is in a conductive state (on state). This indicates that the transistor is in a non-conductive state, and if it is represented by a dashed line, it means that the transistor is in a non-conductive state. This indicates that the state is "off".

[0091] Typical example, the first pulse signal output circuit 10 _1 The operation of the first pulse output will be explained. power circuit 10 _1 The configuration is as described above. Furthermore, each input signal and each supplied power The positional relationships are as described above. In the following explanation, the input terminals and power lines are supplied with All high potentials (also called H level, H signal, etc.) are treated as VDD, and low potentials (L level, All signals (also called L signals, etc.) are treated as VSS.

[0092] During the first period 51, SP1 is at a high level, so the first pulse output circuit 10 _1 The gate terminal of the fifth transistor 105, which functions as the fourth input terminal 24, and the tenth A high potential is applied to the gate terminal of transistor 110, and the fifth transistor 105 and the first Transistor 110 (number 0) becomes conductive. Also, the gate terminal of the seventh transistor 107 Since a high potential is applied to the child, the seventh transistor 107 also turns ON (Figure 8). (See (A)).

[0093] When the fifth transistor 105 and the seventh transistor 107 are turned ON, The potential of line A rises. Also, the 10th transistor 110 turns on. Therefore, the potential of node B decreases. The potential of the second terminal of the fifth transistor 105 is VDD. Therefore, the potential of the first terminal of the fifth transistor 105 is the same as the potential of the second terminal. This value (VDD-Vth105) is the value obtained by the threshold voltage of transistor 105. And, since the potential of the gate terminal of the seventh transistor 107 is VDD, the seventh transistor If the threshold voltage Vth107 of the inverter 107 is Vth105 or higher, then node A The potential becomes (VDD-Vth107), and the seventh transistor 107 turns off. On the other hand, if Vth107 is less than Vth105, the seventh transistor 107 is ON. While maintaining this state, the potential of node A rises to (VDD-Vth105). Below, the first The point at which the potential of node A reaches during period 51 is V. AH Let's assume that the potential at node A is V AH to When this is reached, the fifth transistor 105 and the seventh transistor 107 turn off. Therefore, node A is V AH It remains suspended while maintaining that state.

[0094] The potential at node A is V AH Then, the first transistor 101 and the third transistor 103 is turned ON. Here, CLK1 is at a low level, so the first output terminal 26 And an L level output is output from the second output terminal 27.

[0095] During the second period 52, CLK1 switches from the L level to the H level. Here, Since transistor 101 and transistor 303 are in the ON state, the first output The potential of the power terminal 26 and the potential of the second output terminal 27 rise. Furthermore, the first transistor A capacitance exists between the gate terminal and source terminal (or drain terminal) of the TA101, This results in capacitive coupling between the gate terminal and the source terminal (or drain terminal). Similarly, the gate terminal and source terminal (or drain terminal) of the third transistor 103 A capacitance exists between them, which causes the gate terminal and the source terminal (or drain terminal) to They are capacitively coupled. Therefore, the potential of the first output terminal 26 and the potential of the second output terminal 27 As the potential increases, the potential of node A, which is in a floating state, will also increase (bootstrike (P-operation). The potential of node A eventually becomes higher than VDD+Vth101, and the first output The potential at terminal 26 and the potential at the second output terminal 27 are VDD (H level) (Figure 7) See Figure 8(B).

[0096] In the third period 53, CLK2 becomes high level, and the ninth transistor 109 is off This results in a state where the potential of node B increases. Due to the increase in the potential of node B, The second transistor 102, the fourth transistor 104, and the sixth transistor 10 When 6 is turned ON, the potential of node A decreases. Therefore, the potential of the first output terminal 26 The potential of the second output terminal 27 becomes L level (see Figure 8(C)).

[0097] During the fourth period 54, CLK2 becomes L level, and the ninth transistor 109 is O The state becomes F, but the 5th input terminal 25 (i.e., SROUT3) becomes H level, Transistor 108 of node 8 is turned ON. Therefore, the potential of node A and the potential of node B The voltage is maintained, and the potential of the first output terminal 26 and the potential of the second output terminal 27 are at the L level. It is retained (see Figure 9(A)).

[0098] During the fifth period 55, the fifth input terminal 25 (i.e., SROUT3) becomes L level. Therefore, the potential of node B is maintained. For this reason, the second transistor 102 and the fourth transistor The ON state of transistor 104 and the sixth transistor 106 is maintained, and the first output terminal The potentials of terminals 26 and the second output terminal 27 are maintained at an L level (see Figure 9(B)).

[0099] Note that the potential of node B usually decreases due to the transistor's off-current, etc., but Apply a transistor with a low off-current (for example, a transistor using an oxide semiconductor). If you do that, then this problem will not occur.

[0100] Furthermore, transistors using wide-bandgap semiconductors such as oxide semiconductors use silicon Because, unlike transistors, threshold control through doping cannot be applied. Even when the gate is not biased (the gate and source are at the same potential), the source and source Current may flow between rains. However, the pulse signal output shown in this embodiment In the power circuit, the channel length of the 10th transistor 110 is set to that of the 3rd transistor 103. By making it larger than the channel length of the fourth transistor 104, the current from node B Because leakage can be suppressed, it is possible to stably maintain the potential of node B. Furthermore, the channel length of the sixth transistor 106 is set to the same length as that of the third transistor 103. By making it larger than the channel length of transistor 104, the current from node A is This suppresses the process, thus stabilizing the bootstrap operation at node A. This can be achieved by applying the configuration of this embodiment, the potential of node A and the node Because the potential of circuit B can be maintained for a long period of time, for example, in low-frequency circuits Even when applied, it can prevent malfunctions.

[0101] Furthermore, in order to further mitigate the decrease in potential at node B, as shown in Figure 10(A), one side A capacitive element 120 with electrodes electrically connected to node B may be provided separately. The other electrode can be provided, for example, by being electrically connected to the first power line 31.

[0102] Also, as shown in Figure 10(B), the sixth transistor 106 or the tenth transistor The 110 is a multi-gate type transistor having at least two gates arranged in series. As a sta structure, the potential drop at node B can be further mitigated. See Figure 10(B) In this case, both the sixth transistor 106 and the tenth transistor 110 are multi-gauge An example of a T-type transistor is shown, but the sixth transistor 106 or the tenth transistor One of the ZISTA 110 components may also be a multi-gate type transistor. Of course, as shown in Figure 10 ( The configuration shown in A) and the configuration shown in Figure 10(B) may be used in combination.

[0103] As shown in Figure 10(B), by applying a multi-gate type transistor, the transistor This allows for redundancy of the DISTRA, thereby improving the yield of the pulse signal output circuit. It is possible.

[0104] Furthermore, if CLK2 becomes high during the subsequent period, the ninth transistor 109 turns on, and a potential is periodically applied to node B. Therefore, the off current Even when using relatively large transistors, this prevents malfunctions in the pulse signal output circuit. can.

[0105] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined with those shown in other embodiments and used.

[0106] (Embodiment 3) In this embodiment, an example of a transistor applicable to the pulse signal output circuit and the shift register described in the above embodiment will be described with reference to FIG. 11. Note that the structure of the transistor is not particularly limited, and for example, an appropriate structure such as a top gate structure or a bottom gate structure, a staggered type or a planar type can be adopted. Also, the transistor may have a single gate structure having one channel formation region or a multi-gate structure having two or more channel formation regions . Further, a structure having two gate electrode layers disposed via a gate insulating layer above and below the channel region may also be used.

[0107] Examples of the cross-sectional structure of the transistor are shown in FIGS. 11(A) to 11(D). The transistor shown in FIG. 11(A) to FIG. 11(D) uses an oxide semiconductor as the semiconductor . The merit of using an oxide semiconductor is that high mobility and low off-current can be realized with a simple process and a low-temperature process.

[0108] The transistor 410 shown in FIG. 11(A) is an example of a transistor having a bottom gate structure and is also referred to as an inverted staggered transistor.

[0109] The transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 40 5b on a substrate 400 having an insulating surface. Also, an insulating layer 407 in contact with the oxide semiconductor layer 403 is provided. Insulation A protective insulating layer 409 is further formed on layer 407.

[0110] The transistor 420 shown in Figure 11(B) is a channel protection type (also known as a channel stop type). This is an example of a bottom-gate transistor called an inverse staggered transistor. It is also said that.

[0111] Transistor 420 has a gate electrode layer 401 on a substrate 400 having an insulating surface, and a gate Insulating layer 402, oxide semiconductor layer 403, insulating layer 427 which functions as a channel protection layer, It includes an electrode layer 405a and a drain electrode layer 405b. A protective insulating layer 409 is also provided. It's being kicked.

[0112] The transistor 430 shown in Figure 11(C) is an example of a bottom-gate type transistor. The transistor 430 has a gate electrode layer 401 on a substrate 400 having an insulating surface, and a gate electrode layer 401. Insulating layer 402, source electrode layer 405a, drain electrode layer 405b, and oxide semiconductor layer It includes 403. Furthermore, an insulating layer 407 is provided in contact with the oxide semiconductor layer 403. A protective insulating layer 409 is further formed on the edge layer 407.

[0113] In transistor 430, the gate insulating layer 402 is connected to the substrate 400 and the gate electrode layer 40 1 is provided in contact with the gate insulating layer 402, and on the gate insulating layer 402, the source electrode layer 405a, An in electrode layer 405b is provided in contact with it. And a gate insulating layer 402 and a source An oxide semiconductor layer 403 is provided on the electrode layer 405a and the drain electrode layer 405b.

[0114] The transistor 440 shown in Figure 11(D) is an example of a top-gate structure transistor. Transistor 440 is located on a substrate 400 having an insulating surface, an insulating layer 437, an oxide semiconductor Conductor layer 403, source electrode layer 405a, drain electrode layer 405b, gate insulating layer 402, and includes gate electrode layer 401. And source electrode layer 405a, drain electrode layer 405 Wiring layers 436a and 436b are provided in contact with each other on b.

[0115] In this embodiment, as described above, an oxide semiconductor layer 403 is used as the semiconductor layer. As the oxide semiconductor used in the material semiconductor layer 403, the quaternary metal oxide In-Sn- Ga-Zn-O systems, and ternary metal oxides such as In-Ga-Zn-O and In-Sn-Z nO system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system Sn-Al-Zn-O system, and binary metal oxides such as In-Zn-O system, Sn-Zn- O-based, Al-Zn-O-based, Zn-Mg-O-based, Sn-Mg-O-based, In-Mg-O-based, Examples include In-O, Sn-O, and Zn-O systems. Furthermore, SiO2 can be added to the above oxide semiconductors. It may be added. Here, for example, In-Ga-Zn-O based oxide semiconductors are at least It is also an oxide containing In, Ga, and Zn, and there are no particular restrictions on its composition ratio. It may contain elements other than a and Zn.

[0116] Furthermore, the oxide semiconductor layer 403 contains a material with the chemical formula InMO3(ZnO) m (m>0) An oxide semiconductor can be used. Here, M is derived from Ga, Al, Mn, and Co. This indicates one or more selected metallic elements. For example, M could be Ga, Ga and Al, G Examples include a and Mn, or Ga and Co.

[0117] Transistors 410, 420, and transistors 430, 440 can have an extremely small off-current. Therefore , by using these in a pulse signal output circuit or a shift register, the potential holding of each node becomes easy, and the probability of malfunction of the pulse signal output circuit or the shift register can be extremely reduced .

[0118] There are no major restrictions on the substrate that can be used for the substrate 400 having an insulating surface. For example, a glass substrate used in a liquid crystal display device or the like, a quartz substrate, or the like can be used. Also , a substrate having an insulating layer formed on a silicon wafer or the like may be used.

[0119] In the transistors 410, 420, 430 having a bottom gate structure , an underlying insulating layer may be provided between the substrate and the gate electrode layer. The insulating layer has a function of preventing the diffusion of impurity elements from the substrate and can be formed of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride silicon oxide film, or a silicon oxynitride film.

[0120] The gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum neodymium, copper, neodymium, scandium, or an alloy material having these as a main component . Also, its structure may be a single layer structure or a laminated structure .

[0121] The gate insulating layer 402 is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a nitride Aluminum film, aluminum oxide nitride film, aluminum nitride oxide film, hafnium oxide film It can be formed by one or more films selected from the above. For example, the first gate insulation As the border layer, a silicon nitride film with a thickness of 50 nm to 200 nm is produced by plasma CVD. SiN y (y>0)) is formed, and a second gate insulating layer is formed on the first gate insulating layer as a spall layer. By the tutter method, silicon oxide films (SiO) with a thickness of 5 nm to 300 nm are produced. x (x>0) This can be used to form a gate insulating layer with a total film thickness of approximately 300 nm.

[0122] The source electrode layer 405a and drain electrode layer 405b are made of molybdenum, titanium, chromium, and tan. Metal materials such as tungsten, aluminum, copper, neodymium, scandium or These can be formed using alloy materials that are the main components of these materials. For example, aluminum or copper A laminated structure of metal layers such as titanium, molybdenum, and tungsten, and high-melting-point metal layers. It is possible to prevent the formation of hillocks and whiskers by using elements (silicon, neodymium, Even if heat resistance is improved by using aluminum materials to which scandium (and other elements) are added, good.

[0123] Furthermore, source electrode layer 405a, drain electrode layer 405b (wiring formed from the same layer) A conductive metal oxide film may be used as the conductive film (including the layer). Examples of oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO2). ), indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) ), indium zinc oxide alloy (In2O3-ZnO) or these metal oxide materials Materials containing silicon oxide, etc., can be used.

[0124] Source electrode layer 405a, wiring layer 436a in contact with drain electrode layer 405b, wiring layer 436 For b, the same material as the source electrode layer 405a and drain electrode layer 405b is used to form It is possible.

[0125] Typical examples of insulating layers 407, 427, and 437 are silicon oxide films, and oxide films. Inorganic insulating films such as silicon nitride films, aluminum oxide films, or aluminum oxide-nitride films. You can use it.

[0126] The protective insulating layer 409 may be a silicon nitride film, an aluminum nitride film, or a silicon nitride oxide film. Inorganic insulating films such as aluminum nitride oxide films can be used.

[0127] Furthermore, on the protective insulating layer 409, a planar insulating layer is used to reduce surface irregularities caused by transistors. A border film may be formed. As the planarizing insulating film, polyimide, acrylic, benzocyclob Organic materials such as tungsten can be used. In addition to the above organic materials, low dielectric constant materials (l Materials such as ow-k materials can be used. Furthermore, multiple insulating films formed from these materials can be used. A planar insulating film may be formed by stacking layers.

[0128] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0129] (Embodiment 4) In this embodiment, an example of a transistor including an oxide semiconductor layer and a method for manufacturing the same is provided. This will be explained in detail using Figure 12.

[0130] Figures 12(A) to 12(E) are cross-sectional views relating to the transistor manufacturing process. The transistor 510 shown here is the same inverse transistor as the transistor 410 shown in Figure 11(A). It is a staggered transistor.

[0131] The oxide semiconductor used in the semiconductor layer of this embodiment is an oxide semiconductor in which hydrogen, which is an n-type impurity, is used. By removing impurities other than the main components of the oxide semiconductor and purifying it to a high degree, This results in an i-type (intrinsic) oxide semiconductor, or an oxide semiconductor that is very close to an i-type (intrinsic) one. That is what happened.

[0132] Furthermore, in highly purified oxide semiconductors, the number of carriers is extremely low, and the carrier concentration is 1× 10 14 / cm 3 Less than 1 × 10 12 / cm 3 Less than 1 × 1 0 11 / cm 3 It will be less than this. Also, because there are so few carriers, in the off state The off-current becomes sufficiently small.

[0133] Specifically, in a transistor having the oxide semiconductor layer described above, at room temperature (25°C) The off-current density per 1 μm channel width is given for a transistor channel length L of 10 μm. Under the condition that the source-drain voltage of the transistor is 3V, 100zA / μm(1 ×10 -19 A / μm) or less, and even 10 zA / μm (1 × 10⁻⁶ -20 A / μm) or less It is possible to do so.

[0134] Furthermore, the transistor 510, which has a highly purified oxide semiconductor layer, has an on-current temperature There is almost no dependence observed, and the off-current remains very low.

[0135] The transistor 510 is fabricated on the substrate 505 using Figures 12(A) to 12(E) below. I will explain the process.

[0136] First, a conductive film is formed on a substrate 505 having an insulating surface, and then a first photolithography is performed. The gate electrode layer 511 is formed by the process. The resist mask may be formed by an inkjet method. Since the T method does not require the use of a photomask, manufacturing costs can be reduced.

[0137] The substrate 505 having an insulating surface is a substrate similar to the substrate 400 in the above embodiment. It is possible to do so. In this embodiment, a glass substrate is used as the substrate 505.

[0138] Furthermore, an insulating base layer may be provided between the substrate 505 and the gate electrode layer 511. The insulating layer has the function of preventing the diffusion of impurity elements from the substrate 505, and the silicon nitride film , one or selected from silicon oxide film, silicon nitride film, silicon oxide-nitride film, etc. It can be formed by multiple films.

[0139] Furthermore, the gate electrode layer 511 is made of molybdenum, titanium, chromium, tantalum, tungsten, Metal materials such as aluminum, copper, neodymium, scandium, or compounds mainly composed of these materials It can be formed using gold material. Furthermore, the structure may be a single-layer structure, or a multi-layer structure. A layered structure would also work.

[0140] Next, a gate insulating layer 507 is formed on the gate electrode layer 511. The gate insulating layer 507 is It can be formed using methods such as plasma CVD and sputtering. Silicon film, silicon nitride film, silicon oxide nitride film, silicon oxide nitride film, aluminum oxide film Aluminum nitride film, aluminum oxide nitride film, aluminum oxide nitride film, hafni oxide It can be formed by one or more films selected from materials such as um film.

[0141] Furthermore, the gate insulating layer 507 and the oxide semiconductor film 530 should contain as much hydrogen, hydroxyl groups, and moisture as possible. To prevent contamination, a sputtering apparatus is used as a pretreatment for the deposition of the oxide semiconductor film 530. In the preheating chamber, the substrate 505 or gate insulating layer 507 on which the gate electrode layer 511 is formed The substrate 505, which has been formed up to this point, is preheated to remove hydrogen, moisture, etc. adsorbed on the substrate 505. It is preferable to remove impurities. Furthermore, the exhaust means provided in the preheating chamber is cryopreserved. It is preferable to use a pump. Furthermore, this preheating is performed on the source electrode layer 515a and the drain. This may also be performed on a substrate 505 to which the electrode layer 515b has been formed. The reason can be omitted.

[0142] Next, a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or less, is applied to the gate insulating layer 507. An oxide semiconductor film 530 with a wavelength of 30 nm or less is formed (see Figure 12(A)).

[0143] The oxide semiconductor film 530 includes the quaternary metal oxide and ternary metal oxide shown in the above embodiment. Materials such as binary metal oxides, In-O systems, Sn-O systems, and Zn-O systems can be used. .

[0144] In particular, as a target for fabricating oxide semiconductor film 530 by sputtering, In: A composition expressed in the ratio Ga:Zn=1:x:y (where x is greater than or equal to 0, and y is between 0.5 and 5). It is preferable to use the following. For example, In2O3:Ga2O3:ZnO=1:1:2[mo Targets having a composition ratio of [1-number ratio] can be used. Also, In2O3:G Targets with a composition ratio of a2O3:ZnO=1:1:1 [molar ratio], or In2O A target having a composition ratio of 3:Ga2O3:ZnO=1:1:4 [molar ratio], or I It is also possible to use a target with a composition ratio of n2O3:ZnO=1:2 [molar ratio]. Cut.

[0145] In this embodiment, an amorphous oxide semiconductor layer is made of an In-Ga-Zn-O-based metal oxide The material will be formed by sputtering using a physical target.

[0146] The relative density of metal oxides in the metal oxide target is 80% or more, preferably 95% or more. More preferably, the density should be 99.9% or higher. A metal oxide target with a high relative density is used. This makes it possible to form an oxide semiconductor layer with a dense structure.

[0147] The formation atmosphere for the oxide semiconductor film 530 is a noble gas atmosphere (typically argon), an oxygen atmosphere. A gaseous atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen, is preferable. Specifically, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides must be present at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the gas has been removed to a concentration of 10 ppb or less (preferably). That is the case.

[0148] During the formation of the oxide semiconductor film 530, for example, the workpiece is placed in a processing chamber maintained under reduced pressure. The device holds the object and ensures the temperature of the object to be processed is between 100°C and 550°C, preferably between 200°C and 40°C. The workpiece is heated to a temperature of 0°C or below. Alternatively, the workpiece during the formation of the oxide semiconductor film 530 The temperature of the material to be processed may be room temperature (25°C ± 10°C). Then, moisture is removed from the processing chamber. Meanwhile, sputtered gas from which hydrogen and water have been removed is introduced, and oxidation is performed using the above target. A material semiconductor film 530 is formed. The oxide semiconductor film 530 is formed while heating the workpiece. This makes it possible to reduce impurities contained in the oxide semiconductor layer. Also, sputtering Damage caused by this can be reduced. To remove moisture from the processing chamber, an adsorption type vacuum is used. It is preferable to use a pump. For example, a cryopump, ion pump, or titanium sublimation pump. A cold trap can be used with a turbomolecular pump. A mixture containing [the specified substance] may also be used. By exhausting using a cryopump or the like, the treatment room can be [removed] Because it can remove hydrogen, water, and other impurities, it reduces the concentration of impurities in the oxide semiconductor film 530. can.

[0149] The conditions for forming the oxide semiconductor film 530 include, for example, the distance between the workpiece and the target. The diameter is 170 mm, the pressure is 0.4 Pa, the DC power is 0.5 kW, and the atmosphere is oxygen (oxygen 100% argon atmosphere, or argon (100% argon) atmosphere, or oxygen and argon Conditions such as a mixed atmosphere can be applied. Furthermore, a pulsed DC power supply can be used. When used, it can reduce the amount of powdery material (also called particles or dust) generated during film formation, and the film thickness The uniform distribution is also preferable. The thickness of the oxide semiconductor film 530 is 1 nm to 50 nm. Preferably, the wavelength is 1 nm to 30 nm, and more preferably 1 nm to 10 nm. By using an oxide semiconductor film 530 of this thickness, the short channel effect associated with miniaturization is reduced. It is possible to suppress this. However, this depends on the oxide semiconductor material to be applied and the application of the semiconductor device. The appropriate thickness varies depending on factors such as the material used and its application. It is also possible to do so.

[0150] Furthermore, before forming the oxide semiconductor film 530 by sputtering, argon gas is introduced. Reverse sputtering is performed to generate plasma, and the formed surface (for example, the surface of the gate insulating layer 507) is formed. It is preferable to remove the deposits from the following: Here, reverse sputtering is a method of removing the odor of normal sputtering. Instead of colliding ions with the sputtering target, we instead collide ions with the processing surface. This refers to a method of modifying a surface by causing it to collide with ions. One method involves applying a high-frequency voltage to the surface to be treated under an argon atmosphere, and then attaching the material to be treated. There are methods for generating plasma in the near future. Note that nitrogen and helium can be used instead of an argon atmosphere. Alternatively, an atmosphere containing oxygen or similar substances may be applied.

[0151] Next, the oxide semiconductor film 530 is transformed into island-shaped oxide semiconductors by a second photolithography process. The material is processed into layers. The resist mask used in this photolithography process is made of ink. It may also be formed by the jet method. If the resist mask is formed by the inkjet method, photomask Because no screws are used, manufacturing costs can be reduced.

[0152] Furthermore, when forming contact holes in the gate insulating layer 507, the process is carried out in an oxide semiconductor. This can be done simultaneously with the processing of film 530.

[0153] Etching of the oxide semiconductor film 530 can be done by either dry etching or wet etching. Both may be used. For example, when used for wet etching of oxide semiconductor film 530. As an etching solution, a solution containing a mixture of phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0154] Subsequently, the oxide semiconductor layer is subjected to heat treatment (first heat treatment), and the oxide semiconductor layer 53 Obtain 1 (see Figure 12(B)). This first heat treatment removes excess water from the oxide semiconductor layer. By removing elements (including water and hydroxyl groups) and arranging the structure of the oxide semiconductor layer, in the energy gap... The defect level can be reduced. The temperature of the first heat treatment is, for example, 300°C or higher. The temperature should be below 0°C, or between 400°C and 500°C.

[0155] Heat treatment involves, for example, introducing the workpiece into an electric furnace using a resistance heating element, and performing the treatment under a nitrogen atmosphere. This can be done under conditions of 450°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the atmosphere. Furthermore, ensure that no water or hydrogen is mixed in.

[0156] Heat treatment equipment is not limited to electric furnaces; it also utilizes heat conduction or thermal radiation from a heated medium such as gas. A device that heats the object to be processed may be used. For example, GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Annealing) for devices such as thermal annealing equipment. ) A device can be used. An LRTA device is a halogen lamp, metal halide lamp Xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps This device heats the object to be processed by radiating light (electromagnetic waves) from lamps such as lamps. A GRTA apparatus is a device that performs heat treatment using high-temperature gas. The gas used is aluminum. Noble gases such as gon, or inert gases such as nitrogen that do not react with the material being treated by heat treatment. The body is used.

[0157] For example, as a first heat treatment, the object to be treated is placed in a heated inert gas atmosphere for several minutes. After interheating, a GRTA treatment may be performed in which the workpiece is removed from the inert gas atmosphere. Using GRTA treatment enables high-temperature heat treatment in a short time. Furthermore, the heat resistance temperature of the workpiece... It can be applied even under temperature conditions exceeding [a certain degree]. Furthermore, during the process, an inert gas is used, along with oxygen. You may switch to a gas containing [the specified substance]. Perform the first heat treatment in an oxygen-containing atmosphere. This is because it can reduce defect levels in the energy gap caused by oxygen deficiency. .

[0158] The inert gas atmosphere can be nitrogen or a noble gas (helium, neon, argon, etc.). It is desirable to apply an atmosphere whose main component is ( ) and which does not contain water, hydrogen, etc. For example, nitrogen, helium, neon, argon, and other noble gases introduced into heat treatment equipment. The purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher. That is, the impurity concentration should be 1 ppm or less, preferably 0.1 ppm or less.

[0159] In any case, the first heat treatment reduces impurities, resulting in a type i (intrinsic) semiconductor or type i By forming an oxide semiconductor layer that is extremely close to the original, transistors with extremely superior characteristics can be realized. It can be expressed.

[0160] By the way, the heat treatment described above (the first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydrogenation treatment is performed after the formation of the oxide semiconductor film 530, before processing it into island-shaped oxide semiconductor layers. It is also possible to carry this out in [location]. Furthermore, such dehydration and dehydrogenation treatments can be performed in one go. You can go multiple times, not just once.

[0161] In addition, the first heat treatment involves forming the source electrode layer and the drain electrode layer, This is performed at timings such as after forming an insulating layer on the source electrode layer and the drain electrode layer. It is possible.

[0162] Next, a source electrode layer and a drain are placed on the gate insulating layer 507 and the oxide semiconductor layer 531. A conductive film is formed to form the electrode layer (including wiring formed from the same layer). Source electrode The conductive film used for the layer and the drain electrode layer is the material shown in the above embodiment. It can be used.

[0163] A third photolithography step forms a resist mask on the conductive film, and selectively extracts the residue. After performing ching to form the source electrode layer 515a and the drain electrode layer 515b, a resist is applied. Remove the mask (see Figure 12(C)).

[0164] For exposure during resist mask formation in the third photolithography process, ultraviolet light and KrF light are used. It is preferable to use laser light or ArF laser light. Note that the channel length (L) of the transistor is... It is determined by the distance between the electrode layer and the drain electrode layer. Therefore, the channel length (L) is For exposure during mask formation used in the fabrication of transistors smaller than 25 nm, several nanometers to several tens of nanometers are required. It is preferable to use ultra-ultraviolet light with a short wavelength of m. Exposure with ultra-ultraviolet light has high resolution and a large depth of field. Therefore, later formation The channel length (L) of the transistor is set to be between 10 nm and 1000 nm (1 μm). This is also possible, and it is possible to increase the operating speed of the circuit. Furthermore, miniaturization allows for a semi- It is also possible to reduce the power consumption of the conductor device.

[0165] Furthermore, in order to reduce the number of photomasks and processes used in the photolithography process, multi-stage The etching process may be performed using the resist mask formed by the adjustment mask. A resist mask formed using a grayscale mask has regions of different thicknesses, and etching By doing so, the shape can be further deformed, making it possible to process into multiple different patterns. It can be used in multiple etching processes. Therefore, a single multi-tone mask can be used to reduce the number of etching steps. It is possible to form a resist mask that corresponds to at least two different patterns. This reduces the number of exposure masks and also eliminates the corresponding photolithography steps. Because it can be reduced, the process can be simplified.

[0166] Furthermore, during etching of the conductive film, the oxide semiconductor layer 531 is separated by etching. To prevent this from happening, it is desirable to optimize the etching conditions. However, conductivity The condition is obtained in which only the film is etched, and the oxide semiconductor layer 531 is not etched at all. This is difficult, and during the etching of the conductive film, a portion of the oxide semiconductor layer 531 is etched. A groove (recess) may also be formed.

[0167] Either wet etching or dry etching can be used for etching conductive films. Furthermore, from the standpoint of miniaturizing the elements, dry etching is preferable. The etching gas and etching solution can be appropriately selected depending on the material to be etched. In this embodiment, a titanium film is used as the conductive film, and the oxide semiconductor layer 531 is made of In -Because it uses a Ga-Zn-O system material, for example, when wet etching is applied... For this, the etchant is ammonia peroxide solution (a mixture of ammonia, water, and hydrogen peroxide solution). You can use it.

[0168] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar, and the exposed material is then... It is desirable to remove hydrogen, water, etc., that have adhered to the surface of the oxide semiconductor layer. If processing is performed, after processing, the insulating layer 516, which will serve as a protective insulating film, is formed under conditions that prevent it from being exposed to the atmosphere. To accomplish.

[0169] The insulating layer 516 has a thickness of at least 1 nm, and water is applied to the insulating layer 516 by sputtering or other methods. It is desirable to form it using a method that does not introduce impurities such as hydrogen. When hydrogen is present, it can penetrate the oxide semiconductor layer, and hydrogen can penetrate the oxide semiconductor layer. Oxygen abstraction occurs, and the back channel of the oxide semiconductor layer becomes less resistive (n-type). This is because parasitic channels may be formed. In addition, the insulating layer 516 contains oxides Silicon oxide film, silicon oxide nitride film, aluminum oxide film, or aluminum oxide nitride film It is preferable to use [this].

[0170] In this embodiment, a silicon oxide film with a thickness of 200 nm is used as the insulating layer 516 by sputtering. The film is deposited using [a specific method]. The substrate temperature during film deposition should be between room temperature (25°C) and 300°C. In this embodiment, the temperature is set to 100°C. The silicon oxide film is deposited by sputtering using a rare gas. Under an atmosphere (typically argon), an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen It can be done in a place. Also, silicon oxide target or silico A target can be used.

[0171] Similar to the deposition of the oxide semiconductor film 530, residual moisture in the deposition chamber of the insulating layer 516 is removed. For this purpose, it is preferable to use an adsorption-type vacuum pump (such as a cryopump). By forming a film in a deposition chamber that has been evacuated using an optopod, impurities contained in the insulating layer 516 are eliminated. The concentration can be reduced. In addition, an exhaust fan is used to remove residual moisture in the film deposition chamber of the insulating layer 516. Alternatively, a turbomolecular pump with a cold trap added may be used.

[0172] The sputtering gas used for forming the insulating layer 516 is high-purity gas from which impurities such as hydrogen and water have been removed. It is preferable that it be a gas.

[0173] Next, a second heat treatment is performed under an inert gas atmosphere or an oxygen atmosphere. Heat treatment temperature The temperature should be between 200°C and 450°C, preferably between 250°C and 350°C. For example, A heat treatment at 250°C for 1 hour under a nitrogen atmosphere is sufficient. By performing a second heat treatment... This reduces variations in the electrical characteristics of the transistor. Also, insulating layer 516 By supplying oxygen from to the oxide semiconductor layer 531, oxygen vacancies in the oxide semiconductor layer 531 are eliminated. Filling in the gaps to form a type i (intrinsic) semiconductor or an oxide semiconductor layer that is as close to type i as possible. It's also possible.

[0174] In this embodiment, the second heat treatment is performed after the formation of the insulating layer 516, but the second The timing of the heat treatment is not limited to this. For example, the second heat treatment may be performed immediately after the first heat treatment. Alternatively, the first heat treatment may be combined with the second heat treatment.

[0175] As described above, the oxide semiconductor layer 531 is subjected to the first heat treatment and the second heat treatment. By purifying it to a high degree so that it contains as few impurities as possible other than its main component, it can be made into type i (true) ion. Cut.

[0176] The transistor 510 is formed through the above process (see Figure 12(D)).

[0177] Furthermore, it is desirable to form a protective insulating layer 506 on top of the insulating layer 516 (Figure 12). See E). The protective insulating layer 506 prevents the intrusion of external elements such as hydrogen and water. For the border layer 506, for example, a silicon nitride film, an aluminum nitride film, etc., can be used. Yes, it is possible. The film deposition method is not particularly limited, but RF sputtering is suitable for mass production and provides protective insulation. This method is suitable for forming layer 506.

[0178] Furthermore, after the formation of the protective insulating layer 506, the material is further exposed to air at a temperature of 100°C to 200°C. Heat treatment may be performed under conditions of more than 1 hour but less than 30 hours.

[0179] Thus, a trace containing a highly purified oxide semiconductor layer fabricated using this embodiment The inverter has the characteristic of having an extremely low off-current. Therefore, it is used This makes it easier to maintain the potential of the node. Therefore, this can be used in pulse signal output circuits and shifters. By using it in a shift register, the probability of malfunction in pulse signal output circuits and shift registers is minimized. This allows it to be kept low.

[0180] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0181] (Embodiment 5) Using the shift register shown as an example in Embodiment 1 or Embodiment 2 above, display function A semiconductor device (also called a display device) having the following can be manufactured. To form a system-on-panel by integrally forming a part or the whole on the same substrate as the pixel part. It is possible.

[0182] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements (light-emitting elements). A light-emitting element (also called a display element) can be applied. The brightness of the light-emitting element depends on the current or voltage. This category includes elements whose properties are controlled, specifically inorganic EL (Electroluminescent Luminous Light). This includes (minescence), organic EL, etc. Also, electronic inks and other materials that have an electrical effect. Display media with greater contrast variations can also be applied.

[0183] In Figure 13(A), surrounding the pixel portion 4002 provided on the first substrate 4001 A sealing material 4005 is provided and sealed by the second substrate 4006. Figure 1 In 3(A), the area surrounded by the sealing material 4005 on the first substrate 4001 In a different area from the scanning area, a scan line drive circuit 4004 and a signal line drive circuit are provided on a separately prepared substrate. 4003 is implemented. In addition, a separately formed signal line drive circuit 4003 and scan line drive The various signals and potentials applied to circuit 4004 or pixel unit 4002 are FPC (Flexible Printed Circuit). (Ible printed circuit) Supplied from 4018a, 4018b ru.

[0184] In Figures 13(B) and 13(C), the pixel portion 40 is provided on the first substrate 4001. A sealing material 4005 is provided so as to surround 02 and the scan line drive circuit 4004. Furthermore, a second substrate 4006 is provided on the pixel section 4002 and the scan line driving circuit 4004. Therefore, the pixel section 4002 and the scan line driving circuit 4004 are connected to the first substrate 4001. The display element is sealed together with the sealing material 4005 and the second substrate 4006. In Figures 13(B) and 13(C), the sealing material 4005 on the first substrate 4001 is Therefore, a signal line drive circuit 40 is placed on a separate circuit board in a region different from the enclosed area. 03 is implemented. In Figures 13(B) and 13(C), separately formed signals The line drive circuit 4003 and various signals supplied to the scan line drive circuit 4004 or the pixel unit 4002 The signals and potentials are supplied from the FPC4018.

[0185] Furthermore, in Figures 13(B) and 13(C), a signal line drive circuit 4003 is formed separately. An example of mounting on the first substrate 4001 is shown, but the configuration is not limited to this. The drive circuit may be formed and implemented separately, or it may be part of the signal line drive circuit or the scan line drive circuit It is also acceptable to separately form and implement only a part of it.

[0186] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG(Ch ip On Glass) method, wire bonding method, or TAB (Tape A Methods such as utmost bonding can be used. Figure 13(A) shows This is an example of implementing the signal line drive circuit 4003 and the scan line drive circuit 4004 using the COG method. Figure 13(B) shows an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 1 3(C) is an example of implementing the signal line drive circuit 4003 using the TAB method.

[0187] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. Includes modules with ICs and other components mounted on them.

[0188] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC or TAB tape. A module with TCP attached, a TAB tape, or a printed circuit board at the end of the TCP. An IC (integrated circuit) is directly mounted to the provided module or display element using the COG method. All modules that have been modified shall also be included in the display device.

[0189] Furthermore, the pixel portion provided on the first substrate has multiple transistors, and the transistor As the transistor, one of the transistors exemplified in the previous embodiment may be used.

[0190] When using liquid crystal elements as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, and polymer liquid crystals are used. Crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. are used. Depending on the conditions, the cholesteric phase, smectic phase, cubic phase, chiral nematics This shows the cubic phase, isotropic phase, etc.

[0191] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, it is preferable to use a liquid crystal composition containing several weight percent or more of a chiral agent in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less. Furthermore, because it is optically isotropic, orientation processing is unnecessary, and it has low dependence on viewing angle. Since it is not necessary to provide a rubbing process, the rubbing process is unnecessary. This prevents electrostatic discharge damage that can occur, and reduces defects and damage to liquid crystal displays during the manufacturing process. This can be mitigated, thus improving the productivity of liquid crystal display devices.

[0192] Furthermore, the resistivity of the liquid crystal material is 1 × 10⁻⁶ 9 The value is Ω·cm or greater, preferably 1 × 10⁻⁶. 11 It is Ω·cm or greater, and more preferably 1 × 10⁻⁶ 12 It is greater than Ω·cm. Furthermore, this specification... The resistivity values ​​in this document shall be those measured at 20°C.

[0193] The size of the retention capacitance provided in a liquid crystal display device depends on the regeneration of the transistors arranged in the pixel area. The system is set to hold the charge for a predetermined period of time, taking into account currents, etc. The size should be set considering the transistor's off-current, etc.

[0194] LCD displays include TN (Twisted Nematic) mode and IPS (In-Place Printed Display). lane-Switching) mode, FFS(Fringe Field Switching) mode, ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optically Compensated) Birefringence mode, FLC (Ferroelectric Liq uid Crystal) mode, AFLC(AntiFerroelectric L Use modes such as iquid Crystal.

[0195] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, It may also be used as a transmissive liquid crystal display device. Several vertical orientation modes are possible, For example, MVA (Multi-Domain Vertical Alignment) Mode, PVA (Patterned Vertical Alignment) mode ASV mode and other modes can be used.

[0196] Furthermore, it can also be applied to VA-type liquid crystal display devices. A VA-type liquid crystal display device is a liquid crystal display device. This is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. VA-type liquid crystal display devices are... This method aligns the liquid crystal molecules perpendicular to the panel surface when no voltage is applied. Furthermore, a pixel is divided into several subpixel regions, each in a different direction. This is called multi-domainization or multi-domain design, which is a method designed to defeat molecules. A method can be used.

[0197] Furthermore, in a display device, the black matrix (light-shielding layer), polarizing member, phase difference member, and reflector are used. Optical components (optical substrates) such as protective members are provided as appropriate. For example, polarizing substrates and phase difference substrates Circularly polarized light from a plate may be used. Also, backlights, sidelights, etc., may be used as light sources. It's okay to be there.

[0198] Furthermore, the display method used in the pixel area may be a progressive or interlaced method. It is possible. Also, when displaying in color, the color elements controlled by pixels are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (where W represents white). Alternatively, some models use RGB with one or more additional colors such as yellow, cyan, or magenta. The size of the display area for each dot of the color element may differ. However, the disclosed invention This is not limited to color display devices, but also applies to monochrome display devices. It is also possible to do so.

[0199] Furthermore, as a display element included in the display device, an electroluminescent light-emitting element is used. It can be applied to light-emitting devices that utilize electroluminescence. They are distinguished by whether they are organic or inorganic compounds, and generally the former are organic E The latter is called an L element, and the latter an inorganic EL element.

[0200] In organic EL devices, applying a voltage to the light-emitting element allows electrons and positive charge to be emitted from a pair of electrodes. Each pore is injected into a layer containing a luminescent organic compound, and an electric current flows through it. The recombination of carriers (electrons and holes) causes the luminescent organic compound to form an excited state. It then emits light when the excited state returns to the ground state. From this mechanism, such emission Optical devices are called current-excited light-emitting devices.

[0201] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized type of luminescence used.

[0202] Furthermore, it is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and it is a paper-like material. It offers the same readability, lower power consumption compared to other display devices, and a thin and light form factor. It has the advantage of being such.

[0203] Electrophoresis display devices can take various forms, but one is a first particle with a positive charge and Multiple microcapsules containing a second particle having a negative charge are in the solvent or solute. It is a dispersed substance, and by applying an electric field to the microcapsules, the microcapsules Move the particles in the cell in opposite directions and display only the color of the particles that have gathered on one side. Furthermore, the first or second particle contains dye and moves in the absence of an electric field. It is immovable. Also, the color of the first particle and the color of the second particle are different (including colorless). )

[0204] Thus, electrophoretic devices can detect the movement of substances with high dielectric constants into high electric field regions. This display utilizes a mild dielectrophoretic effect.

[0205] When the above microcapsules are dispersed in a solvent, it is called an electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0206] Furthermore, the first and second particles in the microcapsules contain conductive material and insulating material. Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A type of material selected from chromochromic materials, magnetophoretic materials, or a composite of these materials. You can use it.

[0207] Furthermore, a display device using the twist ball display method can also be applied as electronic paper. Yes, it is possible. The twist ball display method uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, which are electrode layers, and the first electrode layer and the second This method of displaying information involves controlling the orientation of spherical particles by creating a potential difference in the electrode layer. be.

[0208] The display device described above has a pulse signal output frequency as shown in Embodiment 1 or Embodiment 2. By applying this method, it is possible to provide a display device with various functions.

[0209] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0210] (Embodiment 6) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Cameras such as LA, digital photo frames, and mobile phones (also known as mobile phones or mobile phone devices) (u) Portable game consoles, personal information terminals, sound playback devices, and large game machines such as pachinko machines. Some examples include:

[0211] Figure 14(A) shows a semiconductor device disclosed herein being fabricated by mounting at least one component. This is a notebook-type personal computer consisting of a main unit 3001, a casing 3002, and a display unit 3 It consists of 003, keyboard 3004, etc.

[0212] Figure 14(B) shows a semiconductor device disclosed herein being fabricated by mounting at least one component. This is a personal digital assistant (PDA), and the main unit 3021 has a display unit 3023 and an external interface. Face 3025 and operation buttons 3024 are provided. Also included are accessories for operation. There is a stylus 3022.

[0213] Furthermore, the semiconductor device disclosed herein can be used as electronic paper. Figure 14(C) is an e-book manufactured by implementing the electronic paper as a component. C) shows an example of an e-book. For example, the e-book 2700 is housed in a casing 2701 and It consists of two enclosures, enclosure 2701 and enclosure 2703. Enclosures 2701 and 2703 are shafts It is integrated with part 2711, and can open and close using the shaft part 2711 as an axis. This configuration allows it to function like a physical book.

[0214] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 14(C)), and on the left-hand side An image can be displayed on the display unit (display unit 2707 in Figure 14(C)).

[0215] Furthermore, Figure 14(C) shows an example in which the housing 2701 is equipped with an operating section, etc. For example, The enclosure 2701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, etc. It is possible to turn pages using operation key 2723. Note that it is the same as the display unit of the casing. The enclosure may also be configured to include a keyboard, pointing device, etc. on its surface. On the back and sides, there are external connection terminals (earphone jack, USB terminal, etc.), a recording medium insertion slot, etc. It may also be configured to include the following. Furthermore, the e-book 2700 has the function of an electronic dictionary. It can also be structured in this way.

[0216] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0217] Figure 14(D) shows a semiconductor device disclosed herein being fabricated by mounting at least one component. This is a mobile phone, and it consists of two casings, casing 2800 and casing 2801. The body 2801 includes a display panel 2802, a speaker 2803, a microphone 2804, Pointing device 2806, camera lens 2807, external connection terminal 2808, etc. It is equipped with a solar cell 28 for charging the portable information terminal. 10. It is equipped with an external memory slot 2811, etc. Also, the antenna is located inside the housing 2801. It is built into the section.

[0218] Furthermore, the display panel 2802 is equipped with a touch panel, and the image displayed in Figure 14(D) is Multiple operation keys 2805 are shown with dotted lines. Note that the output is from solar cell 2810. A boost circuit is also implemented to increase the voltage to the voltage required for each circuit.

[0219] The display panel 2802 changes its display orientation as appropriate depending on the usage mode. Since the camera lens 2807 is located on the same plane as the 2802, video calls are possible. Speaker 2803 and microphone 2804 are not limited to voice calls, but also video calls. Recording and playback are possible. Furthermore, the casings 2800 and 2801 slide apart, as shown in the diagram. As shown in 14(D), it can be changed from an unfolded state to an overlapping state, making it suitable for carrying around. Further miniaturization is possible.

[0220] External connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication with personal computers, etc. By inserting a recording medium into memory slot 2811, you can store and move larger amounts of data. We can handle it.

[0221] Furthermore, even if it has infrared communication capabilities, television reception capabilities, etc. in addition to the above functions good.

[0222] Figure 14(E) shows a semiconductor device disclosed herein, fabricated by mounting at least one component. This is a digital video camera consisting of a main unit 3051, a first display unit 3057, and an eyepiece unit 3053. It consists of an operation switch 3054, a second display unit 3055, a battery 3056, and the like. It is being done.

[0223] Figure 14(F) shows a telescope mounted with at least one of the semiconductor devices disclosed herein as a component. An example of a vision device is shown. In the television device 9600, the display is located on the housing 9601. The unit 9603 is incorporated. The display unit 9603 makes it possible to display images. Furthermore, this shows a configuration in which the chassis 9601 is supported by the stand 9605. .

[0224] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit. Furthermore, the remote control unit can be accessed from the said remote control unit. The configuration may also include a display unit that shows the information to be output.

[0225] The television system 9600 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0226] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination. [Explanation of symbols]

[0227] 11 signal lines 12 signal lines 13 signal lines 14 signal lines 21 Input terminals 22 Input terminals 23 Input terminals 24 input terminals 25 Input terminals 26 output terminals 27 Output terminals 31 Power line 32 Power line 51 period 52 period 53 period 54 period 55 period 56 period 101 Transistors 102 transistors 103 Transistors 104 transistors 105 transistors 106 transistors 107 transistors 108 transistors 109 transistors 110 transistors 111 transistors 120 Capacitive elements 400 circuit boards 401 Guard Layer 402 Gate Insulation Layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating layer 409 Protective insulating layer 410 transistors 420 transistors 427 Insulating layer 430 transistors 436a Wiring layer 436b wiring layer 437 Insulating layer 440 transistors 505 circuit board 506 Protective insulating layer 507 Gate Insulation Layer 510 transistors 511 Gridgate Layer 515a Source electrode layer 515b Drain electrode layer 516 Insulating layer 530 Oxide semiconductor film 531 Oxide semiconductor layer 2700 eBooks 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Keys 2725 Speakers 2800 cabinets 2801 enclosure 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation Keys 2806 Pointing device 2807 Camera Lens 2808 External connection terminal 2810 solar cells 2811 External memory slot 3001 Main Unit 3002 enclosure 3003 Display section 3004 Keyboard 3021 Main Unit 3022 Stylus 3023 Display section 3024 Operation Buttons 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Second display unit 3056 Battery 3057 First display unit 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4018 FPC 9600 Television equipment 9601 enclosure 9603 Display section 9605 Stand

Claims

[Claim 1] It has first to eighth transistors and capacitive elements, Either the source or the drain of the first transistor is always in conductivity with the output signal wiring. The source or drain of the first transistor, the other of which is always in contact with the first clock signal line, Either the source or the drain of the second transistor is always in contact with the power line. The source or drain of the second transistor is always in conductivity with the output signal wiring. The gate of the third transistor is always in electrical contact with the gate of the second transistor. Either the source or the drain of the fourth transistor is always in electrical contact with the power line. The source or drain of the fourth transistor, the other of which is always in contact with the gate of the second transistor, The gate of the fourth transistor is always in contact with the signal line. Either the source or the drain of the fifth transistor is always in electrical contact with the first wiring. The gate of the fifth transistor is always in conductivity with the signal line. Either the source or the drain of the sixth transistor is always in contact with the gate of the second transistor. The source or drain of the sixth transistor, the other of which is always in electrical contact with the first wiring, The gate of the sixth transistor is always in electrical contact with the second wiring. Either the source or the drain of the seventh transistor is always in contact with the gate of the second transistor. The source or drain of the seventh transistor is always in electrical contact with the source or drain of the eighth transistor. The gate of the seventh transistor is always in electrical contact with the third wiring. The source or drain of the eighth transistor is always in electrical contact with the first wiring. The gate of the eighth transistor is always in contact with the second clock signal line. One electrode of the capacitive element is always in electrical contact with the gate of the second transistor. The other electrode of the capacitive element is always in electrical contact with the power line. When either the source or drain of the third transistor is in a conductive state with the gate of the first transistor through at least the channel forming region of the third transistor, the third transistor is ON. When the first wiring is in a conductive state with the gate of the fifth transistor via the channel forming region of the fifth transistor, the fifth transistor is on. The second wiring is input to a signal having a high potential and a low potential. The third wiring is input to a signal having a high potential and a low potential. The third transistor described above has a multi-gate transistor structure, The fourth transistor is a semiconductor device having a multi-gate transistor structure.

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