Liquid crystal panels and display devices

Abstract

The present invention provides a liquid crystal panel with suppressed signal delay, and a display device equipped with the above-mentioned liquid crystal panel. [Solution] A liquid crystal panel comprising a display area and a bezel area, having a first substrate, a second substrate and a liquid crystal layer, the first substrate or the second substrate having bezel wiring, the first substrate comprising a first electrode and a second electrode electrically connected to the bezel wiring and a switching element, wherein a first input signal input to the first electrode and a second input signal input to the second electrode are periodically repeated in the following order: a first period in which they are set to a potential positive from a reference potential, a second period in which they are set to the reference potential or temporarily set to a potential negative from the reference potential and then set to the reference potential, a third period in which they are set to a potential negative from the reference potential, and a fourth period in which they are set to the reference potential or temporarily set to a potential positive from the reference potential and then set to the reference potential.

Description

Technical Field

[0001] The following disclosure relates to a liquid crystal panel and a display device.

Background Art

[0002] As a technology related to a liquid crystal panel, Patent Document 1 discloses a first and a second gate wiring formed on a substrate including first and second pixel regions, a common wiring formed parallel and separated from the first gate wiring, a data wiring intersecting with the first and second gate wirings to define the first and second pixel regions, a first thin film transistor connected to the first gate wiring and the data wiring and disposed in the first pixel region, a second thin film transistor connected to the second gate wiring and the data wiring and disposed in the second pixel region, a repair pattern extending from the first thin film transistor to the second pixel region, a plurality of pixel electrodes disposed in the first pixel region and connected to the first thin film transistor, a plurality of common electrodes disposed in the first pixel region and connected to the common wiring and arranged alternately with the plurality of pixel electrodes, and a first pixel pattern disposed in the second pixel region and connected to the second thin film transistor and overlapping with the repair pattern. An array substrate for a horizontal electric field type liquid crystal display device is disclosed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One proposed method for 3D display involves a display device with two stacked liquid crystal panels. In this device, the rear liquid crystal panel (image display panel) alternately displays images for the left and right eyes, while the observation-side liquid crystal panel controls the polarization state of each image. Polarized glasses are then used to separate and view the left and right eye images. The observation-side liquid crystal panel functions as an active retarder and is therefore also called an active retarder panel. A display device that creates a sense of depth by delivering separate images to the left and right eyes in a time-division manner is also called an active retarder type 3D display device.

[0005] Figure 30 is a schematic plan view showing the configuration of a conventional active retarder panel. Figure 31 is a diagram showing an image of the charging delay in the first to fourth segments of the conventional active retarder panel shown in Figure 30. An active retarder panel includes, for example, a liquid crystal layer and a pair of electrodes (pixel electrodes and common electrodes) that apply voltage to the liquid crystal layer. The pixel electrodes and common electrodes are formed of transparent electrodes with relatively high resistance. The pixel electrodes (segment electrodes) or common electrodes (COM electrodes) of the active retarder panel 11R shown in Figure 30 are divided into segments of a size that depends on the number of divisions, for example, a fraction of the display area 1AA. Specifically, as shown in Figure 30, the pixel electrodes or common electrodes are divided into a first segment 1S, a second segment 2S, a third segment 3S, and a fourth segment 4S.

[0006] The bezel area 1NA of the active retarder panel 11R can be fitted with low-resistance metal wiring, namely bezel wiring 100NL. Therefore, near the outer edge of the display area 1AA, signals are quickly supplied to the transparent electrodes (pixel electrodes and common electrodes) from the bezel wiring 100NL. However, in areas far from the bezel wiring 100NL (near the center of the display area 1AA), signals can only be input via high-resistance transparent electrodes (pixel electrodes and common electrodes), which is prone to signal delay.

[0007] Furthermore, when the number of pixel divisions is three or more, there will inevitably be pixels whose contact with the outer frame wiring 100NL is limited to two sides. In such cases, a more significant signal delay occurs. For example, when the number of pixel divisions is four (four-segment divisions), as shown in Figure 30, the first segment 1S and the fourth segment 4S receive signals from three sides, but the second segment 2S and the third segment 3S receive signals from only two sides.

[0008] Since the central parts of the first segment 1S and the fourth segment 4S are close to the frame wiring 100NL, signal delays are less likely to occur in the central parts of the first segment 1S and the fourth segment 4S. However, since the central parts of the second segment 2S and the third segment 3S are far from the frame wiring 100NL, signal delays are more likely to occur in the central parts of the second segment 2S and the third segment 3S. As a result, as shown in Figure 31, the second segment 2S and the third segment 3S experience greater charging delays compared to the first segment 1S and the fourth segment 4S.

[0009] Thus, in the active retarder panel 11R, signal delays can occur, such as delays in the signals input to the pixel electrodes, and time it takes for the potential fluctuated by noise generated in the common electrode to return to its original potential.

[0010] The above-mentioned Patent Document 1 does not disclose a liquid crystal panel in which signal delay is suppressed.

[0011] This invention has been made in view of the above-mentioned circumstances, and aims to provide a liquid crystal panel with suppressed signal delay and a display device equipped with the liquid crystal panel. [Means for solving the problem]

[0012] (1) One embodiment of the present invention comprises a display area and a frame area provided around the display area, and includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, wherein the first substrate or the second substrate has frame wiring disposed in the frame area, and the first substrate includes a first electrode and a second electrode electrically connected to the frame wiring within the display area, and a switching element that controls the electrical connection between the first electrode and the second electrode, wherein a first input signal is input to the first electrode, a second input signal is input to the second electrode, and the first input signal and the second input signal are set to a potential positive from a reference potential for a first period, and set to the reference potential or temporarily set to a potential negative from the reference potential before being set to the reference potential A liquid crystal panel wherein the following are periodically repeated in this order: a second period in which the signal is fixed, a third period in which the signal is set to a potential negative of the reference potential, and a fourth period in which the signal is set to the reference potential or temporarily set to a potential positive of the reference potential before being set to the reference potential; the first, second, third, and fourth periods of the first input signal overlap with and begin earlier than the first, second, third, and fourth periods of the second input signal, and the first electrode is electrically connected to the second electrode via the switching element during the period from the start of the second period of the second input signal to the end of the second period of the first input signal, and during the period from the start of the fourth period of the second input signal to the end of the fourth period of the first input signal.

[0013] (2) In addition, one embodiment of the present invention is a liquid crystal panel in which, in addition to the configuration of (1) above, the first electrode is electrically connected to the second electrode via the switching element during the period from the start of the first period of the second input signal to the end of the first period of the first input signal, and during the period from the start of the third period of the second input signal to the end of the third period of the first input signal.

[0014] (3) In addition, one embodiment of the present invention is a liquid crystal panel wherein, in addition to the configuration of (1) or (2) above, the timing at which the first electrode is electrically connected to the second electrode via the switching element is later than the timing at which the first period of the second input signal begins.

[0015] (4) In addition, one embodiment of the present invention is a liquid crystal panel in which, in addition to the configuration of (1) above, the first electrode is not electrically connected to the second electrode during the period from the start of the first period of the second input signal to the end of the first period of the first input signal, and during the period from the start of the third period of the second input signal to the end of the third period of the first input signal.

[0016] (5) In addition, one embodiment of the present invention is a liquid crystal panel in which, in addition to the configuration of (1), (2), (3) or (4) above, the first electrode and the second electrode are arranged along a first direction of the liquid crystal panel and extend along a second direction perpendicular to the first direction.

[0017] (6) In addition, one embodiment of the present invention is a liquid crystal panel in which, in addition to the configuration of (5) above, the liquid crystal panel comprises a plurality of switching elements, and the plurality of switching elements are arranged from one end to the other end in the second direction of the liquid crystal panel.

[0018] (7) In addition, one embodiment of the present invention is a liquid crystal panel in which, in addition to the configuration of (5) above, the liquid crystal panel comprises one or more of the switching elements, the one or more switching elements are arranged in the central part of the liquid crystal panel in the second direction, and are not arranged near the frame in the second direction.

[0019] (8) In addition, one embodiment of the present invention is a liquid crystal panel in which, in addition to the configuration of (5) above, the liquid crystal panel comprises a plurality of switching elements, wherein the plurality of switching elements comprises a central switching element disposed in the central part of the liquid crystal panel in the second direction, and a frame-near switching element disposed in the frame-near part of the liquid crystal panel in the second direction.

[0020] (9) In addition, one embodiment of the present invention, in addition to the configuration of (8) above, during the second period, the first input signal and the second input signal are temporarily set to a negative potential from the reference potential and then set to the reference potential, the first electrode connected to the central switching element is electrically connected to the second electrode connected to the central switching element via the central switching element at the timing when the second period of the second input signal begins, and the first electrode connected to the frame-near switching element is electrically connected to the second electrode connected to the frame-near switching element via the frame-near switching element after the timing when the second period of the second input signal begins, the liquid crystal panel.

[0021] (10) In addition, one embodiment of the present invention is a liquid crystal panel in which, in addition to the configuration of (1), (2), (3), (4), (5), (6), (7), (8) or (9) above, the switching element is controlled by a control signal different from the first input signal and the second input signal.

[0022] (11) In addition, one embodiment of the present invention is a liquid crystal panel in which, in addition to the configuration of (1), (2), (3), (4), (5), (6), (7), (8), (9), or (10) above, in a plan view, the edge of the first electrode facing the frame region is longer than the edge of the second electrode facing the frame region.

[0023] (12) Further, another embodiment of the present invention is a display device comprising a liquid crystal panel according to any one of (1), (2), (3), (4), (5), (6), (7), (8), (9), (10) or (11) above, an image display panel disposed on the back side of the liquid crystal panel, and a backlight disposed on the back side of the image display panel.

Effects of the Invention

[0024] According to the present invention, it is possible to provide a liquid crystal panel with suppressed signal delay and a display device including the liquid crystal panel.

Brief Description of the Drawings

[0025] [Figure 1] It is a cross-sectional schematic view of a display device according to Embodiment 1. [Figure 2] It is a plan schematic view of a liquid crystal panel according to Embodiment 1. [Figure 3] It is an enlarged plan schematic view of a range surrounded by region 11A in FIG. 2. [Figure 4] It is a cross-sectional schematic view taken along line A1 - A2 in FIG. 3. [Figure 5] It is a timing chart showing a first input signal input to a first pixel electrode included in the liquid crystal panel according to Embodiment 1, a second input signal input to a second pixel electrode, and a first control signal input to a first switching element. [Figure 6] It is an equivalent circuit diagram of a liquid crystal panel according to Embodiment 1. [Figure 7] It is an enlarged plan schematic view of a range surrounded by region 11B in FIG. 2. [Figure 8] It is a cross-sectional schematic view taken along line B1 - B2 in FIG. 7. [Figure 9] It is a timing chart showing a second input signal input to a second pixel electrode included in the liquid crystal panel according to Embodiment 1, a third input signal input to a third pixel electrode, and a second control signal input to a second switching element. [Figure 10]This is an enlarged schematic plan view of the area enclosed by region 11C in Figure 2. [Figure 11] This is a schematic cross-sectional view along the line C1-C2 in Figure 10. [Figure 12] This is a timing chart showing the third input signal input to the third pixel electrode, the fourth input signal input to the fourth pixel electrode, and the third control signal input to the third switching element of the liquid crystal panel according to Embodiment 1. [Figure 13] This is a timing chart showing the first, second, third, and fourth input signals input to the first, second, third, and fourth pixel electrodes of the liquid crystal panel according to Embodiment 1. [Figure 14] This is a timing chart showing the time variation of the potentials of the first pixel electrode and the second pixel electrode of the liquid crystal panel according to Embodiment 1, and the first control signal. [Figure 15] This is a timing chart showing the time variation of the potentials of the first pixel electrode and the second pixel electrode of the liquid crystal panel according to Embodiment 2, and the first control signal. [Figure 16] This is a timing chart showing a first input signal input to a first pixel electrode, a second input signal input to a second pixel electrode, and a first control signal input to a first switching element, all of which are part of a liquid crystal panel according to Embodiment 1. [Figure 17] This is a timing chart showing a first input signal input to a first pixel electrode, a second input signal input to a second pixel electrode, and a first control signal input to a first switching element, all of which are part of a liquid crystal panel according to Embodiment 3. [Figure 18] This is a schematic plan view of a liquid crystal panel according to Embodiment 1. [Figure 19] This is a timing chart showing the time change of the potential of the second pixel electrode when an overshoot is applied to the second input signal input to the second pixel electrode of the liquid crystal panel according to Embodiment 1. [Figure 20]This is a schematic plan view illustrating a case in which the first pixel electrode and the second pixel electrode are connected by a first switching element in the entire left and right region of the liquid crystal panel according to Embodiment 1. [Figure 21] This is a timing chart showing the time variation of the potential of the first and second pixel electrodes in a liquid crystal panel having the configuration shown in Figure 20, near the edge of the liquid crystal panel. [Figure 22] This is a schematic plan view of the liquid crystal panel according to Embodiment 4. [Figure 23] This is a timing chart showing the time change in the potential of the first pixel electrode and the second pixel electrode of the liquid crystal panel according to Embodiment 4, in the vicinity of the frame of the liquid crystal panel. [Figure 24] This is a schematic plan view of a liquid crystal panel according to Embodiment 5. [Figure 25] This is a schematic cross-sectional view of the central part of the liquid crystal panel according to Embodiment 5. [Figure 26] This is a schematic cross-sectional view of the area near the frame of the liquid crystal panel according to Embodiment 5. [Figure 27] This is an equivalent circuit diagram of the liquid crystal panel according to Embodiment 5. [Figure 28] This is a timing chart showing the time change in the potential of the second pixel electrode of the liquid crystal panel according to Embodiment 5, in the central part of the liquid crystal panel and near the bezel. [Figure 29] This is a timing chart showing the time variation of the potential of the first pixel electrode and the second pixel electrode in the liquid crystal panels of Example 1 and Comparative Example 1, as well as the first control signal. [Figure 30] This is a schematic plan view illustrating the configuration of a conventional active retarder panel. [Figure 31] Figure 30 shows an image illustrating the charging delay in the first to fourth segments of a conventional active retarder panel. [Modes for carrying out the invention]

[0026] Embodiments of the present invention will be described below. The present invention is not limited to the embodiments described below, and design modifications can be made as appropriate within the scope of satisfying the configuration of the present invention. In the following description, the same reference numerals will be used in common across different drawings for the same parts or parts having similar functions, and repeated descriptions will be omitted as appropriate. Each aspect of the present invention may be combined as appropriate without departing from the spirit of the present invention.

[0027] In this specification, "observation side" means the side of the liquid crystal panel closer to the screen (display surface), and "back side" means the side of the liquid crystal panel further away from the screen (display surface).

[0028] (Embodiment 1) Figure 1 is a schematic cross-sectional view of a display device according to Embodiment 1. Embodiment 1 will be explained with reference to Figures 1 to 13. In this embodiment, the display device 10 is illustrated. Note that parts of each drawing show the X, Y, and Z axes, and each axis is drawn so as to be in the direction shown in each drawing.

[0029] The display device 10 according to this embodiment is a type of 3D image display device that allows the user to view a 3D image (stereoscopic image), and employs an active retarder method. As shown in Figure 1, the display device 10 comprises a liquid crystal panel 11, an image display panel 12 located on the back side of the liquid crystal panel 11, and a backlight 13 located on the back side of the image display panel 12.

[0030] The image display panel 12 has the function of displaying images.

[0031] The backlight 13 is an external light source that illuminates the image display panel 12 with light for display purposes. The backlight 13 includes a light source that emits white light (such as an LED) or an optical component that converts the light from the light source into planar light by applying an optical effect.

[0032] The liquid crystal panel 11 functions as a modulator for converting linearly polarized light emitted from the image display panel 12 into circularly polarized light. More specifically, the liquid crystal panel 11 can switch between right-circular polarization and left-circular polarization in synchronization with the image display panel 12, which alternately displays images for the right eye and the left eye. In other words, the liquid crystal panel 11 functions as an active retarder panel.

[0033] The display device 10 of this embodiment is used in combination with circularly polarized glasses equipped with circularly polarized films whose rotation directions are reversed on the left and right sides. The user can view 3D images by looking at the display device 10 while wearing the circularly polarized glasses described above. In this way, since the liquid crystal panel 11 is driven at high speed in synchronization with the display of the image display panel 12, it is required to suppress signal delay in the liquid crystal panel 11.

[0034] Figure 2 is a schematic plan view of a liquid crystal panel according to Embodiment 1. Figure 3 is an enlarged schematic plan view of the area enclosed by region 11A in Figure 2. Figure 4 is a schematic cross-sectional view along the line A1-A2 in Figure 3. Figure 5 is a timing chart showing the first input signal input to the first pixel electrode, the second input signal input to the second pixel electrode, and the first control signal input to the first switching element of the liquid crystal panel according to Embodiment 1. Figure 6 is an equivalent circuit diagram of the liquid crystal panel according to Embodiment 1.

[0035] As shown in Figures 2 to 4, the liquid crystal panel 11 of this embodiment comprises a display area 1AA and a bezel area 1NA provided around the display area 1AA, and includes a first substrate 100, a second substrate 200 arranged opposite to the first substrate 100, and a liquid crystal layer 300 arranged between the first substrate 100 and the second substrate 200. The first substrate 100 or the second substrate 200 has bezel wiring 100NL arranged in the bezel area 1NA. The first substrate 100 includes, within the display area 1AA, a first pixel electrode 131 as the first electrode and a second pixel electrode 132 as the second electrode, which are electrically connected to the bezel wiring 100NL, and a switching element 12T (hereinafter also referred to as the first switching element 12T) that controls the electrical connection between the first pixel electrode 131 and the second pixel electrode 132. By adopting this configuration, the first pixel electrode 131 and the second pixel electrode 132 can be electrically connected via the switching element 12T by turning on the switching element 12T. As a result, in addition to the frame wiring 100NL, the first pixel electrode 131 can also become a signal input path to the second pixel electrode 132, making it possible to suppress the delay of the signal input to the second pixel electrode 132. Hereinafter, the first pixel electrode 131 and the second pixel electrode 132 may be collectively referred to as the pixel electrode 130.

[0036] Furthermore, as shown in Figure 5, a first input signal is input to the first pixel electrode 131, and a second input signal is input to the second pixel electrode 132. The first and second input signals are periodically repeated in this order: a first period in which they are set to a potential positive from the reference potential; a second period in which they are set to the reference potential or temporarily set to a potential negative from the reference potential before being set to the reference potential; a third period in which they are set to a potential negative from the reference potential; and a fourth period in which they are set to the reference potential or temporarily set to a potential positive from the reference potential before being set to the reference potential. The first, second, third, and fourth periods of the first input signal overlap with the first, second, third, and fourth periods of the second input signal, respectively, and start at an earlier timing. The first pixel electrode 131 is electrically connected to the second pixel electrode 132 via the switching element 12T during the period from the start of the second period of the second input signal to the end of the second period of the first input signal, and during the period from the start of the fourth period of the second input signal to the end of the fourth period of the first input signal. By adopting this configuration, the following effects can be obtained.

[0037] In Figure 5, during the period indicated by the dashed arrow, both electrodes of the first pixel electrode 131 and the second pixel electrode 132 are set to a potential different from the reference potential, or both electrodes are set to the reference potential. On the other hand, during the period indicated by the dashed arrow, one of the first pixel electrode 131 and the second pixel electrode 132 is set to a potential different from the reference potential, while the other is set to the reference potential. In this embodiment, during the period when both electrodes are set to a reference potential, specifically, from the start of the second period of the second input signal to the end of the second period of the first input signal, and from the start of the fourth period of the second input signal to the end of the fourth period of the first input signal, the first pixel electrode 131 is electrically connected to the second pixel electrode 132 via the switching element 12T (i.e., the switching element 12T is turned on). As a result, in Figure 2, in addition to the frame wiring 100NL (specifically, the frame wiring 100NL located on both the left and right sides of the liquid crystal panel 11), the charged first pixel electrode 131 can also be used as a signal input path to the second pixel electrode 132, thereby effectively improving the signal delay of the second pixel electrode 132. Thus, in this embodiment, the signal delay can be further improved by connecting two electrodes (preferably adjacent electrodes) via a switching element at an appropriate timing and utilizing an already charged electrode as wiring.

[0038] Here, when the start of the first, second, third, and fourth periods of the first input signal coincides with the start of the first, second, third, and fourth periods of the second input signal, respectively, the phase of the first input signal and the phase of the second input signal coincide. When the start of the first, second, third, and fourth periods of the first input signal differs from the start of the first, second, third, and fourth periods of the second input signal, respectively, the phase of the first input signal and the phase of the second input signal are different. When the start of the first, second, third, and fourth periods of the first input signal is earlier than the start of the first, second, third, and fourth periods of the second input signal, respectively, the phase of the first input signal is earlier than the phase of the second input signal.

[0039] In the above-mentioned Patent Document 1, in an array substrate for a liquid crystal display device, the pixel electrode of a defective pixel and the pixel electrodes of adjacent pixels (upper and lower adjacent to the defective pixel) are connected by melting, thereby inputting the same signal to the defective pixel as to the adjacent pixels. Therefore, in the liquid crystal display device array substrate of Patent Document 1, the exact same signal is input to two vertically adjacent pixels at the same timing. In other words, in Patent Document 1, the phase of the signals input to the two pixels is the same, which is different from the configuration of this embodiment, where the phase of the input signal to the first pixel electrode 131 and the phase of the input signal to the second pixel electrode 132 are different.

[0040] The liquid crystal panel of this embodiment will be described in detail below.

[0041] As shown in Figure 2, the liquid crystal panel 11 of this embodiment comprises a display area 1AA and a frame area 1NA provided around the display area 1AA. The display area 1AA can be any area in which the phase difference can be controlled. The display area 1AA is the area in which the first pixel electrode 131 and the second pixel electrode 132 are arranged. In the display area 1AA, the phase difference of the liquid crystal layer 300 is controlled by changing the orientation state of the liquid crystal molecules by the magnitude of the voltage applied to the liquid crystal layer 300.

[0042] As shown in Figure 4, the liquid crystal panel 11 of this embodiment includes a first substrate 100, a second substrate 200 positioned opposite the first substrate 100, and a liquid crystal layer 300 sandwiched between the first substrate 100 and the second substrate 200. In this embodiment, the first substrate 100, the liquid crystal layer 300, and the second substrate 200 are arranged in order from the back side toward the observation surface, but the second substrate 200, the liquid crystal layer 300, and the first substrate 100 may also be arranged in order from the back side toward the observation surface.

[0043] As shown in Figure 2, the first substrate 100 or the second substrate 200 has a frame wiring 100NL arranged in the frame region 1NA. The frame wiring 100NL only needs to be conductive. The frame wiring 100NL is electrically connected to the first pixel electrode 131 and the second pixel electrode 132 in the frame region 1NA. The frame wiring 100NL is, for example, a segment signal line. The segment signal line is electrically connected to the first pixel electrode 131 and the second pixel electrode 132 and is wiring for supplying a segment signal to the pixel electrode 130.

[0044] The frame wiring 100NL is preferably arranged on the first substrate 100. This configuration allows for easy connection between the frame wiring 100NL and the pixel electrodes 130.

[0045] The frame wiring 100NL includes, for example, metals such as copper, titanium, aluminum, molybdenum, and tungsten, or alloys thereof. The frame wiring 100NL can be formed by depositing metals such as copper, titanium, aluminum, molybdenum, and tungsten, or alloys thereof, in single or multiple layers using a sputtering method, and then patterning them using a photolithography method.

[0046] As shown in Figures 3 and 4, the first substrate 100 comprises, in order toward the liquid crystal layer 300 side, a first support substrate 110, a first semiconductor layer 12A, a first insulating layer 121, a first gate electrode 12G, a second insulating layer 122, a first metal portion 12B connected to the first pixel electrode 131 and the first semiconductor layer 12A, a second metal portion 12C connected to the second pixel electrode 132 and the first semiconductor layer 12A, a third insulating layer 123, and the first pixel electrode 131 and the second pixel electrode 132.

[0047] The second substrate 200 comprises, in order toward the liquid crystal layer 300 side, a second support substrate 210, an insulating layer 220, and a common electrode 230. The common electrode 230 is electrically connected to the common signal line provided by the liquid crystal panel 11. The common signal line is, for example, a wiring for supplying a common signal to the common electrode 230.

[0048] Alignment films, which have the function of controlling the orientation of liquid crystal molecules contained in the liquid crystal layer 300, are placed between the first substrate 100 and the liquid crystal layer 300, and between the second substrate 200 and the liquid crystal layer 300. In the no-voltage state, when no voltage is applied between the pixel electrode 130 and the common electrode 230, the liquid crystal molecules contained in the liquid crystal layer 300 are oriented substantially perpendicular to the main surface of each of the pair of substrates.

[0049] The liquid crystal panel 11 of this embodiment is a vertical electric field type liquid crystal panel in which a first substrate 100 has pixel electrodes 130 and a second substrate 200 has common electrodes 230, and display is performed by applying a vertical electric field to a liquid crystal layer 300 sandwiched between the pixel electrodes 130 and the common electrodes 230. A vertical electric field type is vertical alignment (VA), in which the liquid crystal molecules in the liquid crystal layer are oriented perpendicular to the substrate surface when no voltage is applied.

[0050] In this embodiment, the common electrode 230 is described in which it is arranged on the second substrate 200, but the common electrode 230 may also be arranged on the first substrate 100. In this case, the liquid crystal panel 11 is a liquid crystal panel that displays by applying a transverse electric field to the liquid crystal layer 300. Examples of transverse electric field methods include FFS (Fringe Field Switching) mode and IPS (In Plane Switching) mode, in which the liquid crystal molecules in the liquid crystal layer are oriented parallel to the substrate surface when no voltage is applied.

[0051] The liquid crystal panel 11 includes segment signal lines and common signal lines. Segment signals are supplied to the pixel electrodes 130 from an external drive circuit via the segment signal lines, setting them to a potential corresponding to the segment signals. Similarly, common signals are supplied to the common electrodes from an external drive circuit via the common signal lines, setting them to a potential corresponding to the common signals. This generates a longitudinal electric field between the pixel electrodes 130 and the common electrodes 230, controlling the orientation of the liquid crystal molecules in the liquid crystal layer 300. In the liquid crystal panel 11, the polarization state of light passing through the liquid crystal layer 300 is adjusted by changing the orientation state of the liquid crystal molecules in each pixel (first segment 1S, second segment 2S, third segment 3S, and fourth segment 4S) by changing the voltage applied to the liquid crystal layer 300.

[0052] The liquid crystal panel 11 may also include gate lines, source lines, TFTs as switching elements, source drivers, gate drivers, and controllers instead of segment signal lines and common signal lines. In this case, the bezel wiring 100NL is, for example, a source line. The first substrate 100 or the second substrate 200 includes, in the display area 1AA, a plurality of gate lines extending parallel to each other on a support substrate (first support substrate 110 or second support substrate 210), and a plurality of source lines extending parallel to each other in a direction intersecting each gate line via an insulating film. The plurality of gate lines and the plurality of source lines are formed in a grid pattern as a whole to demarcate each pixel. For example, a TFT as a switching element is placed at the intersection of each source line and each gate line.

[0053] The pixel electrodes 130 are electrodes positioned in each region enclosed by, for example, two adjacent source lines and two adjacent gate lines. For example, the pixel electrodes 130 are set to a potential corresponding to the data signal supplied via the corresponding TFT. The common electrode 230 is an electrode formed on almost the entire surface, regardless of the pixel boundary, except for certain parts such as the connection between the pixel electrodes 130 and the drain electrode. A common signal kept at a constant value is supplied to the common electrode 230, and the common electrode 230 is kept at a constant potential.

[0054] For example, the liquid crystal panel 11 further includes a source driver electrically connected to the source line, a gate driver electrically connected to the gate line, and a controller. The gate driver sequentially supplies scanning signals to the gate line based on control by the controller. The source driver supplies data signals to the source line based on control by the controller at the timing when the TFT enters a voltage-applied state due to the scanning signal. Each pixel electrode 130 is set to a potential corresponding to the data signal supplied via the corresponding TFT, and a longitudinal electric field is generated between the pixel electrode 130 and the common electrode 230, controlling the orientation of liquid crystal molecules in the liquid crystal layer 300. In the liquid crystal panel 11, the light transmittance in the liquid crystal layer 300 is adjusted by changing the orientation state of the liquid crystal molecules in each pixel (the first segment 1S where the first pixel electrode 131 is located, the second segment 2S where the second pixel electrode 132 is located, the third segment 3S where the third pixel electrode 133 is located, and the fourth segment 4S where the fourth pixel electrode 134 is located) by changing the magnitude of the voltage applied to the liquid crystal layer 300.

[0055] Examples of the first support substrate 110 and the second support substrate 210 include insulating substrates such as glass substrates and plastic substrates. Examples of glass substrate materials include float glass and soda glass. Examples of plastic substrate materials include polyethylene terephthalate, polybutylene terephthalate, polyethersulfone, polycarbonate, and alicyclic polyolefins.

[0056] The first insulating layer 121, the second insulating layer 122, the third insulating layer 123, and the insulating layer 220 can be an inorganic insulating film, an organic insulating film, or a laminate of the organic insulating film and the inorganic insulating film. As the inorganic insulating film, for example, an inorganic film such as silicon nitride (SiNx) or silicon oxide (SiO2) (relative permittivity ε=5~7) or a laminate thereof can be used. As the organic insulating film, for example, an organic film with a low relative permittivity such as photosensitive acrylic resin (relative permittivity ε=2~5) or a laminate thereof can be used.

[0057] The liquid crystal layer 300 contains liquid crystal material, and the amount of light transmitted is controlled by applying a voltage to the liquid crystal layer 300 and changing the orientation of the liquid crystal molecules in the liquid crystal material according to the applied voltage.

[0058] Liquid crystal molecules may have a positive or negative dielectric anisotropy (Δε) defined by the following formula (L). Liquid crystal molecules with positive dielectric anisotropy are also called positive-type liquid crystals, and liquid crystal molecules with negative dielectric anisotropy are also called negative-type liquid crystals. The direction of the long axis of the liquid crystal molecule is the direction of the slow axis. Furthermore, liquid crystal molecules are homogeneously oriented when no voltage is applied (no-voltage state), and the direction of the long axis of the liquid crystal molecule in the no-voltage state is also called the direction of the initial orientation of the liquid crystal molecule. Δε = (dielectric constant in the long axis direction of the liquid crystal molecule) - (dielectric constant in the short axis direction of the liquid crystal molecule) (L)

[0059] The first pixel electrode 131, the second pixel electrode 132, and the common electrode 230 are transparent electrodes. The first pixel electrode 131, the second pixel electrode 132, and the common electrode 230 include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), tin oxide (SnO), etc. The first pixel electrode 131, the second pixel electrode 132, and the common electrode 230 can be formed by depositing a transparent conductive material such as ITO, IZO, ZnO, SnO, or an alloy thereof in a single or multiple layer by sputtering or the like, and then patterning it using photolithography. In this specification, transparent means that the total light transmittance is 90% or more and 100% or less. Preferably, the total light transmittance is 95% or more and 100% or less, and more preferably, the total light transmittance is 98% or more and 100% or less. The total light transmittance is determined according to JIS K7361-1.

[0060] It is preferable that the first pixel electrode 131 and the second pixel electrode 132 are arranged in the same layer. It is preferable that the first pixel electrode 131 and the second pixel electrode 132 contain the same material.

[0061] As shown in Figure 2, the first pixel electrode 131 and the second pixel electrode 132 are arranged along the y-axis direction (vertical direction), which is the first direction of the liquid crystal panel 11, and extend along the x-axis direction (horizontal direction), which is the second direction perpendicular to the first direction. By adopting this configuration, the signal delay in the central part of the second pixel electrode 132 in the second direction (the region far from the bezel wiring 100NL) can be suppressed more effectively.

[0062] As shown in Figure 2, in a plan view, it is preferable that the edge of the first pixel electrode 131 facing the frame region 1NA is longer than the edge of the second pixel electrode 132 facing the frame region 1NA. In such a liquid crystal panel 11, the signal from the frame wiring 100NL is more easily input to the first pixel electrode 131 than to the second pixel electrode 132, so that the first pixel electrode 131 can be sufficiently charged at the timing when the signal input to the second pixel electrode 132 changes. As a result, the already charged first pixel electrode 131 can function as wiring, and the signal delay of the second pixel electrode 132 can be more effectively improved. Here, the edge of an electrode facing the frame region refers to all the edges of an electrode that face the frame region without passing through other electrodes.

[0063] The first pixel electrode 131 receives a first input signal in which positive and negative potentials alternate with respect to a reference potential, and the second pixel electrode 132 receives a second input signal in which positive and negative potentials alternate with respect to a reference potential, with the phase of the first input signal being different from the phase of the second input signal. The reference potential is, for example, 0V.

[0064] The first input signal input to the first pixel electrode 131 only needs to have a different phase from the second input signal input to the second pixel electrode 132, and the waveforms of the first input signal and the second input signal may be the same or different from each other. An example of a case where the waveforms of the first input signal and the second input signal are different is when overshoot is applied to either the first input signal or the second input signal. Details of overshoot will be explained in detail in Embodiment 4 below.

[0065] The waveforms of the first and second input signals have the shapes shown in Figure 5, for example. The first input signal periodically repeats in this order: a first period in which it is set to a potential positive from the reference potential; a second period in which it is set to the reference potential or temporarily set to a potential negative from the reference potential before being set to the reference potential; a third period in which it is set to a potential negative from the reference potential; and a fourth period in which it is set to the reference potential or temporarily set to a potential positive from the reference potential before being set to the reference potential. For example, the first pixel electrode 131 is periodically subjected to the application of a positive voltage, no voltage application, application of a negative voltage, and no voltage application in this order. In this configuration, the first pixel electrode 131 is repeatedly charged.

[0066] Similarly, the second input signal is periodically repeated in the following order: a first period in which it is set to a potential positive from the reference potential; a second period in which it is set to the reference potential or temporarily set to a potential negative from the reference potential before being set to the reference potential; a third period in which it is set to a potential negative from the reference potential; and a fourth period in which it is set to the reference potential or temporarily set to a potential positive from the reference potential before being set to the reference potential. For example, the second pixel electrode 132 is periodically repeated in the order of positive voltage application, no voltage application, negative voltage application, and no voltage application. In this configuration, the second pixel electrode 132 is repeatedly charged.

[0067] The positive potentials of the first and second input signals set during the first period may be different from each other, but are preferably the same. The negative potentials of the first and second input signals set during the third period may be different from each other, but are preferably the same. By adopting this configuration, signal delay can be suppressed more effectively.

[0068] It is preferable that the lengths of the first period of the first input signal and the second input signal are the same. It is preferable that the lengths of the second period of the first input signal and the second input signal are the same. It is preferable that the lengths of the third period of the first input signal and the second input signal are the same. It is preferable that the lengths of the fourth period of the first input signal and the second input signal are the same. By adopting this configuration, signal delay can be suppressed more effectively.

[0069] As shown in Figure 5, the waveforms of the first input signal and the second input signal are the same, but the first, second, third, and fourth periods of the first input signal overlap with the first, second, third, and fourth periods of the second input signal, respectively, and start at an earlier timing. By adopting this configuration, it becomes possible to fully charge the first pixel electrode 131 and then have it function as wiring, thereby further improving the signal delay of the second pixel electrode 132.

[0070] As shown in Figure 5, it is preferable that the first pixel electrode 131 is electrically connected to the second pixel electrode 132 via the switching element 12T (i.e., the switching element 12T is ON) during the period from the start of the first period of the second input signal to the end of the first period of the first input signal, and during the period from the start of the third period of the second input signal to the end of the third period of the first input signal. By adopting this configuration, when charging the second pixel electrode 132, the already charged first pixel electrode 131 can be used as wiring, and the input delay of the signal input to the second pixel electrode 132 can be effectively improved.

[0071] It is more preferable that the first pixel electrode 131 is fully charged at the time charging of the second pixel electrode 132 begins. By adopting this configuration, the already charged first pixel electrode 131 can function as wiring, and the signal delay of the second pixel electrode 132 can be further improved. The timing at which charging of the electrode begins is the timing at which the input signal to the electrode changes from a reference potential to a potential that is positive or negative compared to the reference potential. Examples of timings at which charging of the second pixel electrode 132 begins include the timing at which the first period of the second input signal begins, and the timing at which the third period of the second input signal begins.

[0072] As shown in Figure 5, it is preferable that the first pixel electrode 131 is electrically connected to the second pixel electrode 132 via the switching element 12T (i.e., the switching element 12T is turned on) during the period when the potential of the first input signal and the potential of the second input signal are the same. By adopting this configuration, the already charged first pixel electrode 131 can function as wiring, and the signal delay of the second pixel electrode 132 can be further improved.

[0073] For example, during the first common period from the start of the first period of the second input signal to the end of the first period of the first input signal, the second common period from the start of the second period of the second input signal to the end of the second period of the first input signal, the third common period from the start of the third period of the second input signal to the end of the third period of the first input signal, and the fourth common period from the start of the fourth period of the second input signal to the end of the fourth period of the first input signal, it is preferable that the first pixel electrode 131 is electrically connected to the second pixel electrode 132 via the switching element 12T (i.e., the switching element 12T is in the ON state). By adopting this configuration, it becomes possible to make the already charged first pixel electrode 131 function as wiring, and the signal delay of the second pixel electrode 132 can be further improved.

[0074] Furthermore, when a switching element controls the electrical connection between one electrode and another, when the switching element is turned ON, one electrode is electrically connected to the other electrode, and when the switching element is turned OFF, one electrode is electrically disconnected from the other electrode. Also, when an electrode is electrically connected to another electrode via a switching element during a certain period, it may be electrically connected throughout the entire period or only during a part of the period, but it is preferable that it is electrically connected throughout the entire period. Similarly, when an electrode is not electrically connected to another electrode via a switching element during a certain period, it may not be electrically connected throughout the entire period or only during a part of the period, but it is preferable that it is not electrically connected throughout the entire period.

[0075] As shown in Figures 3 and 4, the first pixel electrode 131 and the second pixel electrode 132 are arranged adjacent to each other. The switching element 12T is positioned at the boundary between the first pixel electrode 131 and the second pixel electrode 132.

[0076] The switching element 12T is, for example, a thin-film transistor (TFT). The switching element 12T comprises a first semiconductor layer 12A electrically connected to the first pixel electrode 131 and the second pixel electrode 132, and a first gate electrode 12G superimposed on the first semiconductor layer 12A via a first insulating layer 121. With this configuration, the on and off states of the switching element 12T can be controlled based on the first control signal, which is the control signal input to the first switching element 12T (specifically the first gate electrode 12G). As a result, the first pixel electrode 131 and the second pixel electrode 132 can be electrically connected via the switching element 12T. Therefore, in addition to the frame wiring 100NL, the first pixel electrode 131, which has already been charged, can also become a signal input path to the second pixel electrode 132, making it possible to suppress the delay of the signal input to the second pixel electrode 132. The first pixel electrode 131 functions as the source electrode of the switching element 12T, and the second pixel electrode 132 functions as the drain electrode of the switching element 12T.

[0077] The first control signal is a signal different from the first input signal and the second input signal. The first control signal periodically repeats, in this order, a first control period in which it is set to a first potential, and a second control period in which it is set to a second potential lower than the first potential. The first potential of the first control signal should be a potential that can turn on the switching element 12T, and the second potential of the first control signal should be a potential that can turn off the switching element 12T. That is, during the first control period of the first control signal, the switching element 12T is in the ON state, and during the second control period of the first control signal, the switching element 12T is in the OFF state.

[0078] The first semiconductor layer 12A preferably contains an oxide semiconductor material such as indium gallium zinc oxide (IGZO). This configuration makes it easier to obtain good switching characteristics and increase the on-current even in large panels where charging is often a challenge. Any material other than IGZO may be used, as long as it makes it easier to obtain good switching characteristics and increase the on-current even in large panels.

[0079] The first pixel electrode 131 is electrically connected to the first semiconductor layer 12A via the first metal portion 12B. The second pixel electrode 132 is electrically connected to the first semiconductor layer 12A via the second metal portion 12C.

[0080] As shown in Figure 6, the first substrate 100 of the liquid crystal panel 11 further includes a first gate line 1G, and the first gate electrode 12G of the switching element 12T is composed of a part of the first gate line 1G. By inputting a first control signal to the first gate electrode 12G via the first gate line 1G, the on and off states of the switching element 12T can be controlled.

[0081] The liquid crystal panel 11 is provided with a plurality of switching elements 12T, and it is preferable that the plurality of switching elements 12T are arranged from one end to the other in a second direction of the liquid crystal panel 11. By adopting this configuration, it becomes possible to connect the first pixel electrode 131 and the second pixel electrode 132 at more points, thereby more effectively improving the signal delay of the second pixel electrode 132.

[0082] The liquid crystal panel 11 is equipped with a plurality of switching elements 12T, and the first pixel electrode 131 and the second pixel electrode 132 are arranged adjacent to each other. Preferably, the plurality of switching elements 12T are arranged from one end to the other of the boundary between the first pixel electrode 131 and the second pixel electrode 132. This configuration makes it possible to connect the first pixel electrode 131 and the second pixel electrode 132 at more points, thereby more effectively improving the signal delay of the second pixel electrode 132.

[0083] As shown in Figure 6, a first liquid crystal capacitance 1LC is formed between the first pixel electrode 131 and the common electrode 230, and a second liquid crystal capacitance 2LC is formed between the second pixel electrode 132 and the common electrode 230.

[0084] Figure 7 is an enlarged planar schematic view of the area enclosed by region 11B in Figure 2. Figure 8 is a schematic cross-sectional view along the line B1-B2 in Figure 7. Figure 9 is a timing chart showing the second input signal input to the second pixel electrode, the third input signal input to the third pixel electrode, and the second control signal input to the second switching element of the liquid crystal panel according to Embodiment 1.

[0085] As shown in Figures 7 and 8, the first substrate 100 further includes a third pixel electrode 133 as a third electrode electrically connected to the frame wiring 100NL within the display area 1AA, and a second switching element 23T (hereinafter also simply referred to as the switching element 23T) that controls the electrical connection between the second pixel electrode 132 and the third pixel electrode 133. With this configuration, by turning on the switching element 23T, it becomes possible to electrically connect the second pixel electrode 132 and the third pixel electrode 133 via the switching element 23T. As a result, in addition to the frame wiring 100NL, the second pixel electrode 132 can also become a signal input path to the third pixel electrode 133, making it possible to suppress the delay of the signal input to the third pixel electrode 133. Hereinafter, the third pixel electrode 133, in addition to the first pixel electrode 131 and the second pixel electrode 132, may also be collectively referred to as the pixel electrode 130.

[0086] Furthermore, as shown in Figure 9, a third input signal is input to the third pixel electrode 133, and the third input signal periodically repeats in this order: a first period in which it is set to a potential positive from the reference potential, a second period in which it is set to the reference potential or temporarily set to a potential negative from the reference potential and then set to the reference potential, a third period in which it is set to a potential negative from the reference potential, and a fourth period in which it is set to the reference potential or temporarily set to a potential positive from the reference potential and then set to the reference potential. The first, second, third, and fourth periods of the second input signal overlap with the first, second, third, and fourth periods of the third input signal, respectively, and start at an earlier timing. The second pixel electrode 132 is electrically connected to the third pixel electrode 133 via a switching element 23T during the period from the start of the second period of the third input signal to the end of the second period of the second input signal, and during the period from the start of the fourth period of the third input signal to the end of the fourth period of the second input signal. This configuration provides the following effects.

[0087] In Figure 9, during the period indicated by the dashed arrow, both electrodes of the second pixel electrode 132 and the third pixel electrode 133 are set to a potential different from the reference potential, or both electrodes are set to the reference potential. On the other hand, during the period indicated by the dashed arrow, one of the second pixel electrode 132 and the third pixel electrode 133 is set to a potential different from the reference potential, while the other is set to the reference potential. In this embodiment, during the period when both electrodes are set to a reference potential, specifically, from the start of the second period of the third input signal to the end of the second period of the second input signal, and from the start of the fourth period of the third input signal to the end of the fourth period of the second input signal, the second pixel electrode 132 is electrically connected to the third pixel electrode 133 via the switching element 23T (i.e., the switching element 23T is turned on). As a result, in Figure 9, in addition to the frame wiring 100NL (specifically, the frame wiring 100NL located on both the left and right sides of the liquid crystal panel 11), the charged second pixel electrode 132 can also be used as a signal input path to the third pixel electrode 133, thereby effectively improving the signal delay of the third pixel electrode 133.

[0088] Figure 10 is an enlarged plan schematic view of the area enclosed by region 11C in Figure 2. Figure 11 is a schematic cross-sectional view along the line C1-C2 in Figure 10. Figure 12 is a timing chart showing the third input signal input to the third pixel electrode, the fourth input signal input to the fourth pixel electrode, and the third control signal input to the third switching element of the liquid crystal panel according to Embodiment 1.

[0089] As shown in Figures 10 and 11, the first substrate 100 further includes a fourth pixel electrode 134 as a fourth electrode electrically connected to the frame wiring 100NL within the display area 1AA, and a third switching element 34T (hereinafter also simply referred to as the switching element 34T) that controls the electrical connection between the third pixel electrode 133 and the fourth pixel electrode 134. With this configuration, by turning on the switching element 34T, it becomes possible to electrically connect the third pixel electrode 133 and the fourth pixel electrode 134 via the switching element 34T. As a result, in addition to the frame wiring 100NL, the third pixel electrode 133 can also become a signal input path to the fourth pixel electrode 134, making it possible to suppress the delay of the signal input to the fourth pixel electrode 134. Hereinafter, the fourth pixel electrode 134, in addition to the first pixel electrode 131, the second pixel electrode 132, and the third pixel electrode 133, may also be collectively referred to as the pixel electrode 130. Furthermore, the first switching element 12T, the second switching element 23T, and the third switching element 34T are sometimes collectively referred to as the switching element 10T.

[0090] Furthermore, as shown in Figure 12, a fourth input signal is input to the fourth pixel electrode 134, and the fourth input signal periodically repeats in this order: a first period in which it is set to a potential positive from the reference potential, a second period in which it is set to the reference potential or temporarily set to a potential negative from the reference potential before being set to the reference potential, a third period in which it is set to a potential negative from the reference potential, and a fourth period in which it is set to the reference potential or temporarily set to a potential positive from the reference potential before being set to the reference potential. The first, second, third, and fourth periods of the third input signal overlap with the first, second, third, and fourth periods of the fourth input signal, respectively, and start at an earlier timing. The third pixel electrode 133 is electrically connected to the fourth pixel electrode 134 via a switching element 34T during the period from the start of the second period of the fourth input signal to the end of the second period of the third input signal, and during the period from the start of the fourth period of the fourth input signal to the end of the fourth period of the third input signal. This configuration provides the following effects.

[0091] In Figure 12, during the period indicated by the dashed arrow, both electrodes of the third pixel electrode 133 and the fourth pixel electrode 134 are set to a potential different from the reference potential, or both electrodes are set to the reference potential. On the other hand, during the period indicated by the dashed arrow, one of the third pixel electrode 133 and the fourth pixel electrode 134 is set to a potential different from the reference potential, while the other is set to the reference potential. In this embodiment, during the period when both electrodes are set to a reference potential, specifically, from the start of the second period of the fourth input signal to the end of the second period of the third input signal, and from the start of the fourth period of the fourth input signal to the end of the fourth period of the third input signal, the third pixel electrode 133 is electrically connected to the fourth pixel electrode 134 via the switching element 34T (i.e., the switching element 34T is turned on). As a result, in Figure 12, in addition to the frame wiring 100NL (specifically, the frame wiring 100NL located on both the left and right sides of the liquid crystal panel 11), the charged third pixel electrode 133 can also be used as a signal input path to the fourth pixel electrode 134, thereby effectively improving the signal delay of the fourth pixel electrode 134.

[0092] The third pixel electrode 133 and the fourth pixel electrode 134 can be formed in the same manner as the first pixel electrode 131 and the second pixel electrode 132.

[0093] The third pixel electrode 133 and the fourth pixel electrode 134 are preferably arranged in the same layer as the first pixel electrode 131 and the second pixel electrode 132. The first pixel electrode 131, the second pixel electrode 132, the third pixel electrode 133, and the fourth pixel electrode 134 are preferably made of the same material.

[0094] As shown in Figure 2, the first pixel electrode 131, the second pixel electrode 132, the third pixel electrode 133, and the fourth pixel electrode 134 are arranged along the y-axis direction (vertical direction), which is the first direction of the liquid crystal panel 11, and extend along the x-axis direction (horizontal direction), which is the second direction perpendicular to the first direction. By adopting this configuration, signal delay in the central part of the first pixel electrode 131, the second pixel electrode 132, the third pixel electrode 133, and the fourth pixel electrode 134 in the second direction (the region far from the bezel wiring 100NL) can be suppressed more effectively.

[0095] As shown in Figure 2, the first pixel electrode 131, the second pixel electrode 132, the third pixel electrode 133, and the fourth pixel electrode 134 are arranged in this order along the y-axis direction (vertical direction), which is the first direction of the liquid crystal panel 11.

[0096] A third input signal is input to the third pixel electrode 133, in which a positive potential and a negative potential alternate with respect to the reference potential. A fourth input signal is input to the fourth pixel electrode 134, in which a positive potential and a negative potential alternate with respect to the reference potential.

[0097] The phase of the second input signal is different from the phase of the third input signal. The second input signal input to the second pixel electrode 132 only needs to have a different phase from the third input signal input to the third pixel electrode 133, and the waveforms of the second input signal and the waveforms of the third input signal may be the same or different from each other.

[0098] The phase of the third input signal is different from the phase of the fourth input signal. The third input signal input to the third pixel electrode 133 only needs to have a different phase from the fourth input signal input to the fourth pixel electrode 134, and the waveforms of the third input signal and the fourth input signal may be the same or different from each other.

[0099] The waveforms of the third and fourth input signals have shapes, for example, as shown in Figures 9 and 12. The third input signal periodically repeats in this order: a first period in which it is set to a potential positive from the reference potential; a second period in which it is set to the reference potential or temporarily set to a potential negative from the reference potential before being set to the reference potential; a third period in which it is set to a potential negative from the reference potential; and a fourth period in which it is set to the reference potential or temporarily set to a potential positive from the reference potential before being set to the reference potential. For example, the third pixel electrode 133 is periodically repeated in this order: positive voltage application, no voltage application, negative voltage application, and no voltage application. In this configuration, the third pixel electrode 133 is repeatedly charged.

[0100] Similarly, the fourth input signal is periodically repeated in this order: a first period in which it is set to a potential positive from the reference potential; a second period in which it is set to the reference potential or temporarily set to a potential negative from the reference potential before being set to the reference potential; a third period in which it is set to a potential negative from the reference potential; and a fourth period in which it is set to the reference potential or temporarily set to a potential positive from the reference potential before being set to the reference potential. For example, the fourth pixel electrode 134 is periodically repeated in this order: positive voltage application, no voltage application, negative voltage application, and no voltage application. In this configuration, the fourth pixel electrode 134 is repeatedly charged.

[0101] The potentials positive to the reference potential set during the first period of the first, second, third, and fourth input signals may differ from the others, but it is preferable that they are the same. The potentials negative to the reference potential set during the third period of the first, second, third, and fourth input signals may differ from the others, but it is preferable that they are the same. By adopting this configuration, signal delay can be suppressed more effectively.

[0102] It is preferable that the lengths of the first, second, third, and fourth input signals are the same for the first period. It is preferable that the lengths of the second period of the first, second, third, and fourth input signals are the same for the second period. It is preferable that the lengths of the third period of the first, second, third, and fourth input signals are the same for the third period. It is preferable that the lengths of the fourth period of the first, second, third, and fourth input signals are the same for the fourth period. By adopting this configuration, signal delay can be suppressed more effectively.

[0103] As shown in Figure 9, the waveforms of the second and third input signals are the same, but the first, second, third, and fourth periods of the second input signal overlap with the first, second, third, and fourth periods of the third input signal, respectively, and start at an earlier timing. By adopting this configuration, it becomes possible to fully charge the second pixel electrode 132 and then use it as wiring, thereby further improving the signal delay of the third pixel electrode 133.

[0104] As shown in Figure 9, it is preferable that the second pixel electrode 132 is electrically connected to the third pixel electrode 133 via the switching element 23T (i.e., the switching element 23T is ON) during the period from the start of the first period of the third input signal to the end of the first period of the second input signal, and during the period from the start of the third period of the third input signal to the end of the third period of the second input signal. By adopting this configuration, when charging the third pixel electrode 133, the already charged second pixel electrode 132 can be used as wiring, and the input delay of the signal input to the third pixel electrode 133 can be effectively improved.

[0105] It is more preferable that the second pixel electrode 132 is fully charged at the time charging of the third pixel electrode 133 begins. By adopting this configuration, the already charged second pixel electrode 132 can function as wiring, thereby further improving the signal delay of the third pixel electrode 133. Examples of the timing at which charging of the third pixel electrode 133 begins include the timing at which the first period of the third input signal begins, and the timing at which the third period of the third input signal begins.

[0106] As shown in Figure 9, it is preferable that the second pixel electrode 132 is electrically connected to the third pixel electrode 133 via the switching element 23T (i.e., the switching element 23T is turned on) during the period when the potential of the second input signal and the potential of the third input signal are the same. By adopting this configuration, the second pixel electrode 132, which is already charged in this embodiment, can function as wiring, and the signal delay of the third pixel electrode 133 can be further improved.

[0107] For example, during the first common period from the start of the first period of the third input signal to the end of the first period of the second input signal, the second common period from the start of the second period of the third input signal to the end of the second period of the second input signal, the third common period from the start of the third period of the third input signal to the end of the third period of the second input signal, and the fourth common period from the start of the fourth period of the third input signal to the end of the fourth period of the second input signal, the second pixel electrode 132 is preferably electrically connected to the third pixel electrode 133 via the switching element 23T (i.e., the switching element 23T is ON). By adopting this configuration, the already charged second pixel electrode 132 can be made to function as wiring, and the signal delay of the third pixel electrode 133 can be further improved.

[0108] As shown in Figures 7 and 8, the second pixel electrode 132 and the third pixel electrode 133 are arranged adjacent to each other. The switching element 23T is positioned at the boundary between the second pixel electrode 132 and the third pixel electrode 133.

[0109] The switching element 23T is, for example, a TFT. The switching element 23T comprises a second semiconductor layer 23A electrically connected to the second pixel electrode 132 and the third pixel electrode 133, and a second gate electrode 23G superimposed on the second semiconductor layer 23A via the first insulating layer 121. With this configuration, the on and off states of the switching element 23T can be controlled based on a second control signal input to the second switching element 23T (specifically, the second gate electrode 23G). As a result, the second pixel electrode 132 and the third pixel electrode 133 can be electrically connected via the switching element 23T. Therefore, in addition to the frame wiring 100NL, the second pixel electrode 132, which has already been charged, can also become a signal input path to the third pixel electrode 133, making it possible to suppress the delay of the signal input to the third pixel electrode 133. The second pixel electrode 132 functions as the source electrode of the switching element 23T, and the third pixel electrode 133 functions as the drain electrode of the switching element 23T.

[0110] As shown in Figure 6, the first substrate 100 of the liquid crystal panel 11 further includes a second gate line 2G. The second gate electrode 23G of the switching element 23T is composed of a part of the second gate line 2G. By inputting a second control signal to the second gate electrode 23G via the second gate line 2G, the on and off states of the switching element 23T can be controlled.

[0111] The liquid crystal panel 11 is equipped with a plurality of switching elements 23T, and the second pixel electrode 132 and the third pixel electrode 133 are arranged along a first direction of the liquid crystal panel 11 and extend along a second direction perpendicular to the first direction, and it is preferable that the plurality of switching elements 23T are arranged from one end to the other in the second direction of the liquid crystal panel 11. By adopting this configuration, it becomes possible to connect the second pixel electrode 132 and the third pixel electrode 133 at more points, thereby more effectively improving the signal delay of the third pixel electrode 133.

[0112] The liquid crystal panel 11 is equipped with a plurality of switching elements 23T, and the second pixel electrode 132 and the third pixel electrode 133 are arranged adjacent to each other. Preferably, the plurality of switching elements 23T are arranged from one end to the other of the boundary between the second pixel electrode 132 and the third pixel electrode 133. This configuration makes it possible to connect the second pixel electrode 132 and the third pixel electrode 133 at more points, thereby more effectively improving the signal delay of the third pixel electrode 133.

[0113] The second control signal is a signal different from the second and third input signals. The second control signal periodically repeats, in this order, a first control period set to a first potential and a second control period set to a second potential lower than the first potential. The first potential of the second control signal should be a potential that can turn on the switching element 23T, and the second potential of the second control signal should be a potential that can turn off the switching element 23T. That is, during the first control period of the second control signal, the switching element 23T is in the ON state, and during the second control period of the second control signal, the switching element 23T is in the OFF state.

[0114] As shown in Figure 12, the waveforms of the third input signal and the fourth input signal are the same, but the first, second, third, and fourth periods of the third input signal overlap with the first, second, third, and fourth periods of the fourth input signal, respectively, and start at an earlier timing. By adopting this configuration, it becomes possible to fully charge the third pixel electrode 133 and then have it function as wiring, thereby further improving the signal delay of the fourth pixel electrode 134.

[0115] As shown in Figure 12, it is preferable that the third pixel electrode 133 is electrically connected to the fourth pixel electrode 134 via the switching element 34T (i.e., the switching element 34T is ON) during the period from the start of the first period of the fourth input signal to the end of the first period of the third input signal, and during the period from the start of the third period of the fourth input signal to the end of the third period of the third input signal. By adopting this configuration, when charging the fourth pixel electrode 134, the already charged third pixel electrode 133 can be used as wiring, and the input delay of the signal input to the fourth pixel electrode 134 can be effectively improved.

[0116] It is more preferable that the third pixel electrode 133 is fully charged at the time charging of the fourth pixel electrode 134 begins. By adopting this configuration, the already charged third pixel electrode 133 can function as wiring, thereby further improving the signal delay of the fourth pixel electrode 134. Examples of the timing at which charging of the fourth pixel electrode 134 begins include the timing at which the first period of the fourth input signal begins, and the timing at which the third period of the fourth input signal begins.

[0117] As shown in Figure 12, it is preferable that the third pixel electrode 133 is electrically connected to the fourth pixel electrode 134 via the switching element 34T (i.e., the switching element 34T is turned on) during the period when the potential of the third input signal and the potential of the fourth input signal are the same. By adopting this configuration, the third pixel electrode 133, which is already charged in this embodiment, can function as wiring, and the signal delay of the fourth pixel electrode 134 can be further improved.

[0118] For example, during the first common period from the start of the first period of the fourth input signal to the end of the first period of the third input signal, the second common period from the start of the second period of the fourth input signal to the end of the second period of the third input signal, the third common period from the start of the third period of the fourth input signal to the end of the third period of the third input signal, and the fourth common period from the start of the fourth period of the fourth input signal to the end of the fourth period of the third input signal, it is preferable that the third pixel electrode 133 is electrically connected to the fourth pixel electrode 134 via the switching element 34T (i.e., the switching element 34T is in the ON state). By adopting this configuration, it becomes possible to make the already charged third pixel electrode 133 function as wiring, and the signal delay of the fourth pixel electrode 134 can be further improved.

[0119] As shown in Figures 10 and 11, the third pixel electrode 133 and the fourth pixel electrode 134 are arranged adjacent to each other. The switching element 34T is positioned at the boundary between the third pixel electrode 133 and the fourth pixel electrode 134.

[0120] The switching element 34T is, for example, a TFT. The switching element 34T comprises a third semiconductor layer 34A electrically connected to the third pixel electrode 133 and the fourth pixel electrode 134, and a third gate electrode 34G superimposed on the third semiconductor layer 34A via the first insulating layer 121. With this configuration, the on and off states of the switching element 34T can be controlled based on a third control signal input to the third switching element 34T (specifically, the third gate electrode 34G). As a result, the third pixel electrode 133 and the fourth pixel electrode 134 can be electrically connected via the switching element 34T. Therefore, in addition to the frame wiring 100NL, the already charged third pixel electrode 133 can also become a signal input path to the fourth pixel electrode 134, making it possible to suppress the delay of the signal input to the fourth pixel electrode 134. The third pixel electrode 133 functions as the source electrode of the switching element 34T, and the fourth pixel electrode 134 functions as the drain electrode of the switching element 34T.

[0121] As shown in Figure 6, the first substrate 100 of the liquid crystal panel 11 further includes a third gate line 3G. The third gate electrode 34G of the switching element 34T is composed of a part of the third gate line 3G. By inputting a third control signal to the third gate electrode 34G via the third gate line 3G, the on and off states of the switching element 34T can be controlled.

[0122] The liquid crystal panel 11 is equipped with a plurality of switching elements 34T, and the third pixel electrode 133 and the fourth pixel electrode 134 are arranged along a first direction of the liquid crystal panel 11 and extend along a second direction perpendicular to the first direction, and it is preferable that the plurality of switching elements 34T are arranged from one end to the other in the second direction of the liquid crystal panel 11. By adopting this configuration, it becomes possible to connect the third pixel electrode 133 and the fourth pixel electrode 134 at more points, thereby more effectively improving the signal delay of the fourth pixel electrode 134.

[0123] The liquid crystal panel 11 is provided with a plurality of switching elements 34T, and the third pixel electrode 133 and the fourth pixel electrode 134 are arranged adjacent to each other. Preferably, the plurality of switching elements 34T are arranged from one end to the other of the boundary between the third pixel electrode 133 and the fourth pixel electrode 134. By adopting this configuration, it becomes possible to connect the third pixel electrode 133 and the fourth pixel electrode 134 at more points, thereby more effectively improving the signal delay of the fourth pixel electrode 134.

[0124] The third control signal is a signal different from the third input signal and the fourth input signal. The third control signal periodically repeats, in this order, a first control period set to a first potential and a second control period set to a second potential lower than the first potential. The first potential of the third control signal should be a potential that can turn on the switching element 34T, and the second potential of the third control signal should be a potential that can turn off the switching element 34T. That is, during the first control period of the third control signal, the switching element 34T is in the ON state, and during the second control period of the third control signal, the switching element 34T is in the OFF state.

[0125] The first potentials set during the first control period of the first, second, and third control signals may be the same or different from each other. The second potentials set during the second control period of the first, second, and third control signals may be the same or different from each other.

[0126] It is preferable that the lengths of the first control periods of the first, second, and third control signals are the same. It is also preferable that the lengths of the second control periods of the first, second, and third control signals are the same. By adopting this configuration, signal delay can be suppressed more effectively.

[0127] The second semiconductor layer 23A and the third semiconductor layer 34A are the same as the first semiconductor layer 12A.

[0128] The second pixel electrode 132 is electrically connected to the second semiconductor layer 23A via the first metal portion 23B. The third pixel electrode 133 is electrically connected to the second semiconductor layer 23A via the second metal portion 23C. The third pixel electrode 133 is electrically connected to the third semiconductor layer 34A via the first metal portion 34B. The fourth pixel electrode 134 is electrically connected to the third semiconductor layer 34A via the second metal portion 34C.

[0129] The first metal parts 23B, 34B and the second metal parts 23C, 34C are the same as the first metal part 12B and the second metal part 12C.

[0130] As shown in Figure 6, a third liquid crystal capacitance 3LC is formed between the third pixel electrode 133 and the common electrode 230, and a fourth liquid crystal capacitance 4LC is formed between the fourth pixel electrode 134 and the common electrode 230.

[0131] Figure 13 is a timing chart showing the first, second, third, and fourth input signals input to the first, second, third, and fourth pixel electrodes of the liquid crystal panel according to Embodiment 1. In the liquid crystal panel 11 of this embodiment, it is sufficient that adjacent pixel electrodes 130 are connected to each other by a switching element such as a TFT. Figures 3 to 5 show a configuration in which the first pixel electrode 131 and the second pixel electrode 132 are connected by a first switching element 12T, but the same applies to the connection between the second pixel electrode 132 and the third pixel electrode 133 as shown in Figures 7 to 9, and between the third pixel electrode 133 and the fourth pixel electrode 134 as shown in Figures 10 to 12. The first input signal input to the first pixel electrode 131, the second input signal input to the second pixel electrode 132, the third input signal input to the third pixel electrode 133, and the fourth input signal input to the fourth pixel electrode 134 change as shown in Figure 13, for example.

[0132] Next, the image display panel 12 will be described. The image display panel 12 preferably includes multiple pixels. These pixels are display units for displaying an image, and in the case of color display, for example, it includes red, blue, and green pixels.

[0133] The image display panel 12 may have a TFT substrate on which a plurality of TFTs are arranged. The TFT substrate may have a plurality of gate lines extending parallel to each other on a support substrate, and a plurality of source lines extending parallel to each other in a direction intersecting each gate line via a gate insulating film. The plurality of gate lines and the plurality of source lines may be formed in a grid pattern in a plan view, and each region demarcated by the plurality of gate lines and the plurality of source lines corresponds to a pixel.

[0134] The support substrate is preferably a transparent substrate, such as a glass substrate or a plastic substrate.

[0135] A TFT may be placed as a switching element at each intersection of each gate line and each source line for each pixel. The gate terminal of the TFT may be connected to the gate line, the source terminal to the source line, and the drain terminal to the pixel electrode. The image display panel 12 may have a common electrode to which a common electrode voltage is applied, separate from the pixel electrodes.

[0136] The image display panel 12 may be a liquid crystal display panel, an OLED panel including an organic light-emitting diode (OLED), or a QD-LED panel including a quantum dot light-emitting diode (QD-LED). In this specification, unless otherwise specified, OLED and QD-LED are also referred to as light-emitting diodes (LEDs).

[0137] If the image display panel 12 is a liquid crystal display panel, the image display panel 12 comprises a TFT substrate, a counter substrate positioned opposite the TFT substrate, and a liquid crystal layer located between the TFT substrate and the counter substrate. A color filter layer is disposed on either the TFT substrate or the counter substrate.

[0138] When the image display panel 12 is an OLED panel or a QD-LED panel, the configuration of the light-emitting diode is not particularly limited, and examples include a configuration in which a cathode, electron transport layer, light-emitting layer, hole transport layer, and anode are stacked in this order.

[0139] The materials for the cathode and anode are not particularly limited, but examples include transparent conductive materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), In3O3, SnO2, ZnO, aluminum, silver, or alloys thereof.

[0140] In the case of a top-emission type LED, the pixel electrodes of the TFT substrate may be used as the anode and the common electrode as the cathode. A reflective electrode made of aluminum, silver, or an alloy thereof may be used as the anode, and the transparent conductive material may be used as the cathode.

[0141] The hole transport layer is a layer that transports holes injected from the anode to the light-emitting layer. The material of the hole transport layer is not particularly limited, but examples include amine compounds such as N,N,N',N'-tetraphenylbenzidine and its derivatives.

[0142] The electron transport layer is a layer that transports electrons injected from the cathode to the light-emitting layer. The material of the electron transport layer is not particularly limited, but examples include phenanthroline derivatives such as 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), quinoline derivatives such as tris(8-quinolinolato)aluminum (Alq3), azaindidine derivatives, oxadiazole derivatives, perylene derivatives, pyridine derivatives, pyrimidine derivatives, quinoxaline derivatives, diphenylquinone derivatives, and nitro-substituted fluorene derivatives.

[0143] An electron injection layer may be provided between the cathode and the electron transport layer. A hole injection layer may also be provided between the anode and the hole transport layer. As the material for the electron injection layer, an inorganic insulating material can be used, such as alkali metal oxides or halides, and alkaline earth metal oxides or halides.

[0144] If the image display panel 12 is an OLED, the light-emitting layer may include fluorescent materials, phosphorescent materials, etc., as light-emitting materials.

[0145] If the image display panel 12 is a QD-LED panel, the light-emitting layer may include quantum dots as the light-emitting material. Quantum dots are nanoscale semiconductor crystals (for example, with an average particle diameter of 2 to 10 nm) that have optical properties that follow quantum mechanics, and examples include colloidal particles composed of about 10 to 50 atoms.

[0146] (Embodiment 2) In this embodiment, we will mainly describe the features specific to this embodiment, and will omit explanations of content that overlaps with Embodiment 1 described above. This embodiment is substantially the same as Embodiment 1, except that the first control signal is different.

[0147] Figure 14 is a timing chart showing the time variation of the potentials of the first and second pixel electrodes and the first control signal in the liquid crystal panel according to Embodiment 1. As shown in Figure 14, in Embodiment 1, the timing at which the switching element 12T turns on is the same as the timing at which the second input signal input to the second pixel electrode 132 changes. Specifically, the timing at which the first period of the first control signal begins is the same as the timing at which the first period of the second input signal begins. That is, the timing at which the first pixel electrode 131 is electrically connected to the second pixel electrode 132 via the switching element 12T is the same as the timing at which the first period of the second input signal begins. In this case, depending on the input resistance of the first pixel electrode 131, the potential of the first pixel electrode 131 may drop sharply instantaneously, potentially adversely affecting the display quality.

[0148] Figure 15 is a timing chart showing the time variation of the potentials of the first and second pixel electrodes and the first control signal in the liquid crystal panel according to Embodiment 2. In this embodiment, as shown in Figure 15, the first control signal is made to rise slightly later than the second input signal, and by connecting it to the first pixel electrode 131 when the second pixel electrode 132 has been charged to a certain extent, the potential drop of the first pixel electrode 131 that may occur in Embodiment 1 can be improved.

[0149] In this embodiment, the timing at which the first pixel electrode 131 is electrically connected to the second pixel electrode 132 via the switching element 12T is later than the timing at which the first period of the second input signal begins. That is, the timing at which the switching element 12T turns on in this embodiment is later than the timing at which charging of the second pixel electrode 132 begins. Specifically, the timing at which the switching element 12T turns on is later than the timing at which the first period of the second input signal begins. By adopting this configuration, it becomes possible to connect the first pixel electrode 131 when the second pixel electrode 132 has been charged to a certain extent, thereby improving the potential drop of the first pixel electrode 131 that may occur in Embodiment 1.

[0150] The timing at which the first pixel electrode 131 is electrically connected to the second pixel electrode 132 via the switching element 12T (the timing at which the switching element 12T turns on, i.e., the timing at which the first control period of the first control signal begins) is preferably 1 msec or more and 0.3 msec or less later than the timing at which the first period of the second input signal begins (the timing at which charging of the second pixel electrode 132 begins). By adopting this configuration, the potential drop of the first pixel electrode 131 can be effectively suppressed.

[0151] In the liquid crystal panel 11 of Embodiment 2, compared to the liquid crystal panel of Embodiment 1, the two pixel electrodes are electrically connected while the potential difference between the first pixel electrode 131 and the second pixel electrode 132 is small. Compared to Embodiment 1, Embodiment 2 has a reduced effect on speeding up charging, but the potential drop of the first pixel electrode 131 is improved, thus avoiding adverse effects on display quality.

[0152] The switching element 23T is the same as the switching element 12T, and the timing at which the second pixel electrode 132 in this embodiment is electrically connected to the third pixel electrode 133 via the switching element 23T is later than the timing at which the first period of the third input signal begins. In other words, the timing at which the switching element 23T turns on is later than the timing at which the charging of the third pixel electrode 133 begins. Specifically, the timing at which the switching element 23T turns on is later than the timing at which the first period of the third input signal begins. By adopting this configuration, it becomes possible to connect the second pixel electrode 132 when the third pixel electrode 133 has been charged to a certain extent, thereby improving the potential drop of the second pixel electrode 132 that may occur in Embodiment 1.

[0153] The timing at which the second pixel electrode 132 is electrically connected to the third pixel electrode 133 via the switching element 23T (the timing at which the switching element 23T turns on, i.e., the timing at which the first control period of the second control signal begins) is preferably 1 msec or more and 0.3 msec or less later than the timing at which the first period of the third input signal begins (the timing at which charging of the third pixel electrode 133 begins). By adopting this configuration, the potential drop of the second pixel electrode 132 can be effectively suppressed.

[0154] In the liquid crystal panel 11 of Embodiment 2, compared to the liquid crystal panel of Embodiment 1, the two pixel electrodes are electrically connected while the potential difference between the second pixel electrode 132 and the third pixel electrode 133 is small. Compared to Embodiment 1, Embodiment 2 has a reduced effect on speeding up charging, but the potential drop of the second pixel electrode 132 is improved, thus avoiding adverse effects on display quality.

[0155] The switching element 34T is the same as the switching element 12T, and the timing at which the third pixel electrode 133 is electrically connected to the fourth pixel electrode 134 via the switching element 34T in this embodiment is later than the timing at which the first period of the fourth input signal begins. In other words, the timing at which the switching element 34T turns on is later than the timing at which the charging of the fourth pixel electrode 134 begins. Specifically, the timing at which the switching element 34T turns on is later than the timing at which the first period of the fourth input signal begins. By adopting this configuration, it becomes possible to connect the third pixel electrode 133 when the fourth pixel electrode 134 has been charged to a certain extent, and the potential drop of the third pixel electrode 133 that may occur in Embodiment 1 can be improved.

[0156] The timing at which the third pixel electrode 133 is electrically connected to the fourth pixel electrode 134 via the switching element 34T (the timing at which the switching element 34T turns on, i.e., the timing at which the first control period of the third control signal begins) is preferably 1 msec or more and 0.3 msec or less later than the timing at which the first period of the fourth input signal begins (the timing at which charging of the fourth pixel electrode 134 begins). By adopting this configuration, the potential drop of the third pixel electrode 133 can be effectively suppressed.

[0157] In the liquid crystal panel 11 of Embodiment 2, the third pixel electrode 133 and the fourth pixel electrode 134 are electrically connected while the potential difference between them is smaller compared to the liquid crystal panel of Embodiment 1. Compared to Embodiment 1, Embodiment 2 has a reduced effect on speeding up charging, but the potential drop of the third pixel electrode 133 is improved, thus avoiding adverse effects on display quality.

[0158] (Embodiment 3) In this embodiment, we will mainly describe the features specific to this embodiment, and will omit explanations of content that overlaps with Embodiment 1 described above. This embodiment is substantially the same as Embodiment 1, except that the first control signal is different.

[0159] Figure 16 is a timing chart showing a first input signal input to a first pixel electrode, a second input signal input to a second pixel electrode, and a first control signal input to a first switching element in a liquid crystal panel according to Embodiment 1. In Embodiment 1, the first control signal turns on the switching element 12T in both cases: when a positive or negative voltage is applied to the first pixel electrode 131 and the second pixel electrode 132, i.e., when a voltage is applied (on state) and when no voltage is applied (off state). Specifically, the switching element 12T remains on from the start of the first period of the second input signal until the end of the first period of the first input signal, from the start of the second period of the second input signal until the end of the second period of the first input signal, from the start of the third period of the second input signal until the end of the third period of the first input signal, and from the start of the fourth period of the second input signal until the end of the fourth period of the first input signal.

[0160] Here, regarding the first and second potentials of the first, second, and third control signals, in order to ensure a sufficiently high voltage between the gate electrode and source electrode of the TFT as a switching element 10T when writing positive polarity to the pixel electrode 130, the first potential of the first, second, and third control signals must be high. Also, when the pixel electrode 130 is negative polarity, it is necessary to reliably turn off the TFT, and in this case, the second potential must be sufficiently low. For these reasons, the driving voltage of the control signals tends to be high. Although it depends on the liquid crystal material and cell thickness, for example, as shown in Figure 16, it is up to about ±25V. If the driving voltage is high, power consumption will increase in addition to the degradation of the TFT itself, so it is desirable to reduce the driving voltage.

[0161] Based on the above, in this embodiment 3, in order to reduce the drive voltage, the switching element 12T is turned on only at the timing when the first pixel electrode 131 and the second pixel electrode 132 are changed from the ON state to the OFF state.

[0162] Figure 17 is a timing chart showing a first input signal input to a first pixel electrode, a second input signal input to a second pixel electrode, and a first control signal input to a first switching element in a liquid crystal panel according to Embodiment 3. As shown in Figure 17, the first pixel electrode 131 in this embodiment is not electrically connected to the second pixel electrode 132 during the period from the start of the first period of the second input signal to the end of the first period of the first input signal, and during the period from the start of the third period of the second input signal to the end of the third period of the first input signal. In other words, the switching element 12T is ON during the second common period from the start of the second period of the second input signal to the end of the second period of the first input signal, and during the fourth common period from the start of the fourth period of the second input signal to the end of the fourth period of the first input signal, and OFF during the first common period from the start of the first period of the second input signal to the end of the first period of the first input signal, and during the third common period from the start of the third period of the second input signal to the end of the third period of the first input signal. By adopting this configuration, the drive voltage of the switching element 12T can be reduced. By reducing the drive voltage in this way, in addition to reducing power consumption, an improvement in TFT reliability can also be expected.

[0163] The switching element 23T is the same as the switching element 12T. In this embodiment, the second pixel electrode 132 is not electrically connected to the third pixel electrode 133 during the period from the start of the first period of the third input signal to the end of the first period of the second input signal, and during the period from the start of the third period of the third input signal to the end of the third period of the second input signal. That is, the switching element 23T is ON during the second common period from the start of the second period of the third input signal to the end of the second period of the second input signal, and during the fourth common period from the start of the fourth period of the third input signal to the end of the fourth period of the second input signal, and is OFF during the first common period from the start of the first period of the third input signal to the end of the first period of the second input signal, and during the third common period from the start of the third period of the third input signal to the end of the third period of the second input signal. By adopting this configuration, the driving voltage of the switching element 23T can be reduced. By lowering the drive voltage in this way, in addition to reducing power consumption, improvements in TFT reliability can also be expected.

[0164] The switching element 34T is the same as the switching element 12T. In this embodiment, the third pixel electrode 133 is not electrically connected to the fourth pixel electrode 134 during the period from the start of the first period of the fourth input signal to the end of the first period of the third input signal, and during the period from the start of the third period of the fourth input signal to the end of the third period of the third input signal. That is, the switching element 34T is ON during the second common period from the start of the second period of the fourth input signal to the end of the second period of the third input signal, and during the fourth common period from the start of the fourth period of the fourth input signal to the end of the fourth period of the third input signal, and is OFF during the first common period from the start of the first period of the fourth input signal to the end of the first period of the third input signal, and during the third common period from the start of the third period of the fourth input signal to the end of the third period of the third input signal. By adopting this configuration, the driving voltage of the switching element 34T can be reduced. By lowering the drive voltage in this way, in addition to reducing power consumption, improvements in TFT reliability can also be expected.

[0165] (Embodiment 4) In this embodiment, we will mainly describe the features specific to this embodiment, and will omit explanations of content that overlaps with Embodiment 1 described above. This embodiment is substantially the same as Embodiment 1, except that overshoot is applied to the second input signal input to the second pixel electrode 132. First, we will explain the problems that arise when overshoot is applied to the second input signal in Embodiment 1.

[0166] Figure 18 is a schematic plan view of a liquid crystal panel according to Embodiment 1. Figure 19 is a timing chart showing the time change in the potential of the second pixel electrode when an overshoot is applied to the second input signal input to the second pixel electrode of the liquid crystal panel according to Embodiment 1. Figure 20 is a schematic plan view illustrating the case in which the first pixel electrode and the second pixel electrode are connected by a first switching element in the entire left and right region of the liquid crystal panel according to Embodiment 1. Figure 21 is a timing chart showing the time change in the potential of the first pixel electrode and the second pixel electrode of the liquid crystal panel having the configuration of Figure 20, near the edge of the liquid crystal panel. Figure 22 is a schematic plan view of a liquid crystal panel according to Embodiment 4. Figure 23 is a timing chart showing the time change in the potential of the first pixel electrode and the second pixel electrode of the liquid crystal panel according to Embodiment 4, near the edge of the liquid crystal panel.

[0167] Typically, the internal waveform of the second pixel electrode 132 experiences the greatest delay in the central part 11X of the liquid crystal panel 11, as shown in Figure 18. To approach the desired potential (for example, 0V (reference potential) in Figure 19) as quickly as possible in the central part 11X of the liquid crystal panel 11 where this delay is most pronounced, one can consider applying an overshoot, as shown in Figure 19, which involves instantaneously applying the second input signal to a negative potential (a potential negative from the reference potential) and then returning it to 0V (reference potential).

[0168] When this overshoot is applied, the second pixel electrode 132 changes quickly to the desired potential (0V (reference potential)) in the central part 11X of the liquid crystal panel 11, although there is some delay and noise. However, in the area near the bezel 11Y, the voltage change including the overshoot of the second input signal is input almost directly, so the potential change of the second pixel electrode 132 tends to be steep and excessive. Therefore, as shown in Figure 19, when the overshoot is applied, the voltage waveform within the plane of the second pixel electrode 132 may change significantly.

[0169] In such a case, if the first pixel electrode 131 and the second pixel electrode 132 are connected across the entire left and right region of the liquid crystal panel 11, as shown by the dashed rectangle in Figure 20, excessive potential changes near the bezel 11Y may propagate to the already charged first pixel electrode 131, as shown by the dashed circle in Figure 21, potentially causing a temporary large shift in the potential of the first pixel electrode 131 and leading to a decrease in display quality.

[0170] As a countermeasure, in this embodiment, as shown in Figure 22, the switching elements 12T provided within the display area 1AA are not provided in the entire left and right areas of the liquid crystal panel 11, but are placed only near the worst point in the plane (in most cases the central part 11X). That is, the liquid crystal panel 11 is equipped with one or more switching elements 12T, and these one or more switching elements 12T are placed in the central part 11X in the second direction of the liquid crystal panel 11, and are not placed near the bezel 11Y in the second direction of the liquid crystal panel 11. When overshoot is applied to the second input signal, the potential of the second pixel electrode 132 tends to shift outside the central part 11X of the liquid crystal panel 11. However, by placing the switching element 12T in the central part 11X of the liquid crystal panel 11 and not in the area near the bezel 11Y of the liquid crystal panel 11, the adjacent first pixel electrode 131 and second pixel electrode 132 are not connected in the area near the bezel 11Y. This suppresses the influence of the shifted potential of the second pixel electrode 132 on the already charged adjacent first pixel electrode 131. As a result, as shown by the dashed circle in Figure 23, it becomes possible to avoid the first pixel electrode 131 shifting from the desired potential, thereby improving display quality.

[0171] The central portion 11X of the liquid crystal panel 11 is the region located in the center when the area from one end to the other end of the liquid crystal panel 11 is divided into three equal parts in the first direction.

[0172] The same applies to the switching element 23T as to the switching element 12T. That is, the liquid crystal panel 11 is equipped with one or more switching elements 23T, and these one or more switching elements 23T are located in the central part 11X in the second direction of the liquid crystal panel 11, and are not located in the area near the bezel 11Y in the second direction of the liquid crystal panel 11. When overshoot is applied to the third input signal, the potential of the third pixel electrode 133 tends to shift outside the central part 11X of the liquid crystal panel 11. However, by arranging the switching element 23T in the central part 11X of the liquid crystal panel 11 and not in the area near the bezel 11Y of the liquid crystal panel 11, the adjacent second pixel electrode 132 and the third pixel electrode 133 are not connected in the area near the bezel 11Y. Therefore, it is possible to suppress the influence of the third pixel electrode 133, whose potential has shifted, on the adjacent second pixel electrode 132, which is already charged. As a result, it becomes possible to avoid the second pixel electrode 132 deviating from the desired potential, thereby improving the display quality.

[0173] The same applies to the switching element 34T as to the switching element 12T. That is, the liquid crystal panel 11 is equipped with one or more switching elements 34T, and these one or more switching elements 34T are located in the central part 11X in the second direction of the liquid crystal panel 11, and are not located in the area near the bezel 11Y in the second direction of the liquid crystal panel 11. When overshoot is applied to the fourth input signal, the potential of the fourth pixel electrode 134 tends to shift outside the central part 11X of the liquid crystal panel 11. However, by arranging the switching element 34T in the central part 11X of the liquid crystal panel 11 and not in the area near the bezel 11Y of the liquid crystal panel 11, the adjacent third pixel electrode 133 and the fourth pixel electrode 134 are not connected in the area near the bezel 11Y. Therefore, it is possible to suppress the effect of the fourth pixel electrode 134, whose potential has shifted, on the adjacent third pixel electrode 133, which is already charged. As a result, it becomes possible to avoid the third pixel electrode 133 deviating from the desired potential, thereby improving the display quality.

[0174] (Embodiment 5) In this embodiment, we will mainly describe the features specific to this embodiment, and will omit explanations of content that overlaps with Embodiment 1 described above. This embodiment is substantially the same as Embodiment 4, except that in the vicinity of the frame 11Y of the liquid crystal panel 11, the first pixel electrode 131 and the second pixel electrode 132 are connected via a switching element having a first gate electrode for the vicinity of the frame, which is different from the first gate electrode 12G.

[0175] Figure 24 is a schematic plan view of the liquid crystal panel according to Embodiment 5. Figure 25 is a schematic cross-sectional view of the central part of the liquid crystal panel according to Embodiment 5. Figure 26 is a schematic cross-sectional view of the area near the frame of the liquid crystal panel according to Embodiment 5. Figure 27 is an equivalent circuit diagram of the liquid crystal panel according to Embodiment 5. Figure 28 is a timing chart showing the time change in the potential of the second pixel electrode of the liquid crystal panel according to Embodiment 5 in the central part of the liquid crystal panel and near the frame.

[0176] In the above embodiment 4, the switching element 12T is placed only in the central part 11X of the liquid crystal panel 11. However, in this embodiment, a switching element controlled by a different control signal than that of the central part 11X of the liquid crystal panel 11 is placed in the area near the frame 11Y at the boundary between the first pixel electrode 131 and the second pixel electrode 132.

[0177] Specifically, as shown in Figures 24 to 27, the liquid crystal panel 11 includes a plurality of first switching elements 12T arranged between a first pixel electrode 131 and a second pixel electrode 132. The plurality of first switching elements 12T include a central first switching element 12TX, which is arranged in the central part of the liquid crystal panel 11 in a second direction, and a frame-near first switching element 12TY, which is arranged in the frame-near part 11Y of the liquid crystal panel 11 in a second direction.

[0178] As described in Embodiment 4 above, when overshoot is applied to the second input signal, the potential change in the area near the frame 11Y of the second pixel electrode 132 may differ significantly from the potential change in the central area 11X. In such cases, by arranging the first switching element 12TX for the central area in the central area 11X of the liquid crystal panel 11, and the first switching element 12TY for the area near the frame in the area near the frame 11Y of the liquid crystal panel 11, as in this embodiment, the difference in potential change between the central area 11X and the area near the frame 11Y of the second pixel electrode 132 can be reduced.

[0179] Specifically, as shown in Figures 24 and 28, during the second period, the first input signal and the second input signal are temporarily set to a negative potential below the reference potential and then set to the reference potential. The first pixel electrode 131 connected to the first central switching element 12TX is electrically connected to the second pixel electrode 132 connected to the first central switching element 12TX via the first central switching element 12TX at the timing when the second period of the second input signal begins. The first pixel electrode 131 connected to the first frame-near switching element 12TY is electrically connected to the second pixel electrode 132 connected to the first frame-near switching element 12TY via the first frame-near switching element 12TY after the timing when the second period of the second input signal begins.

[0180] In other words, the first and second input signals are periodically repeated in this order: a first period in which they are set to a potential positive from the reference potential; a second period in which they are temporarily set to a potential negative from the reference potential and then set to the reference potential; a third period in which they are set to a potential negative from the reference potential; and a fourth period in which they are set to the reference potential or temporarily set to a potential positive from the reference potential and then set to the reference potential. The first switching element 12TX for the central part turns on at the timing when the second period of the second input signal begins, and the first switching element 12TY for the frame vicinity turns on after the timing when the second period of the second input signal begins (preferably at the timing when the second input signal becomes the reference potential).

[0181] The first switching element 12TX for the central part is input a first control signal for the central part that periodically repeats in the order of a first control period in which it is set to a first potential and a second control period in which it is set to a second potential lower than the first potential. The first switching element 12TY for the area near the frame is input a first control signal for the area near the frame that periodically repeats in the order of a first control period in which it is set to a first potential and a second control period in which it is set to a second potential lower than the first potential.

[0182] Specifically, as indicated by the arrow in the first control signal for the central part in Figure 28, the central part of the second pixel electrode 132 requires high-speed charging, so the first switching element 12TX for the central part is turned on simultaneously with the change in the second input signal. On the other hand, the first switching element 12TY for the area near the frame is turned on, for example, after the second input signal returns to the reference potential (0V), so that excessive potential changes due to overshoot do not affect the first pixel electrode 131, as indicated by the arrow in the first control signal for the area near the frame in Figure 28.

[0183] By adopting this configuration, it becomes possible to drive the second pixel electrode 132 at an appropriate timing in accordance with the potential change in each region within the liquid crystal panel 11. This reduces the difference in potential change between the central part 11X and the edge vicinity part 11Y of the second pixel electrode 132, effectively preventing the first pixel electrode 131 from deviating from the desired potential, and effectively improving display quality.

[0184] The first potential of the first control signal for the central part should be a potential that can turn on the first switching element 12TX for the central part, and the second potential of the first control signal for the central part should be a potential that can turn off the first switching element 12TX for the central part. That is, during the first control period of the first control signal for the central part, the first switching element 12TX for the central part is in the ON state, and during the second control period of the first control signal for the central part, the first switching element 12TX for the central part is in the OFF state.

[0185] The first potential of the first control signal for the frame vicinity is a potential that can turn on the first switching element 12TY for the frame vicinity, and the second potential of the first control signal for the frame vicinity is a potential that can turn off the first switching element 12TY for the frame vicinity. That is, during the first control period of the first control signal for the frame vicinity, the first switching element 12TY for the frame vicinity is in the ON state, and during the second control period of the first control signal for the frame vicinity, the first switching element 12TY for the frame vicinity is in the OFF state.

[0186] The liquid crystal panel 11 includes a plurality of first gate lines 1G, each of which includes a first gate line 1GX for the central part and a first gate line 1GY for the area near the bezel. The liquid crystal panel 11 also includes a plurality of first gate electrodes 12G, each of which includes a first gate electrode 12GX for the central part and a first gate electrode 12GY for the area near the bezel. The first gate electrode 12GX for the central part is a part of the first gate line 1GX for the central part. The first gate electrode 12GY for the area near the bezel is a part of the first gate line 1GY for the area near the bezel.

[0187] The first switching element 12TX for the central part comprises a first semiconductor layer 12A electrically connected to a first pixel electrode 131 and a second pixel electrode 132, and a first gate electrode 12GX for the central part superimposed on the first semiconductor layer 12A via a first insulating layer 121. The first switching element 12TY for the area near the frame comprises a first semiconductor layer 12A electrically connected to a first pixel electrode 131 and a second pixel electrode 132, and a first gate electrode 12GY for the area near the frame superimposed on the first semiconductor layer 12A via a first insulating layer 121.

[0188] Similarly, the liquid crystal panel 11 includes a plurality of second switching elements 23T arranged between the second pixel electrode 132 and the third pixel electrode 133, and the plurality of second switching elements 23T include a central second switching element 23TX arranged in the central part of the liquid crystal panel 11 in a second direction, and a second switching element 23TY arranged in the frame vicinity part 11Y of the liquid crystal panel 11 in a second direction.

[0189] During the second period described above, the second input signal and the third input signal are temporarily set to a negative potential below the reference potential and then set to the reference potential. The second pixel electrode 132 connected to the second central switching element 23TX is electrically connected to the third pixel electrode 133 connected to the second central switching element 23TX via the second central switching element 23TX at the timing when the second period described above for the third input signal begins. The second pixel electrode 132 connected to the second frame-near switching element 23TY is electrically connected to the third pixel electrode 133 connected to the second frame-near switching element 23TY via the second frame-near switching element 23TY after the timing when the second period described above for the third input signal begins.

[0190] In other words, the second and third input signals are periodically repeated in this order: a first period in which they are set to a potential positive from the reference potential; a second period in which they are temporarily set to a potential negative from the reference potential and then set to the reference potential; a third period in which they are set to a potential negative from the reference potential; and a fourth period in which they are set to the reference potential or temporarily set to a potential positive from the reference potential and then set to the reference potential. The second switching element 23TX for the central part turns on at the timing when the second period of the third input signal begins, and the second switching element 23TY for the frame vicinity turns on after the timing when the second period of the third input signal begins (preferably at the timing when the third input signal becomes the reference potential (0V)).

[0191] The second switching element 23TX for the central part is input a second control signal for the central part that periodically repeats in the order of a first control period set to a first potential and a second control period set to a second potential lower than the first potential. The second switching element 23TY for the area near the frame is input a second control signal for the area near the frame that periodically repeats in the order of a first control period set to a first potential and a second control period set to a second potential lower than the first potential.

[0192] By adopting this configuration, it becomes possible to drive the third pixel electrode 133 at an appropriate timing in response to the potential change in each region within the liquid crystal panel 11. This reduces the difference in potential change between the central part 11X and the edge-near part 11Y of the third pixel electrode 133, effectively preventing the second pixel electrode 132 from deviating from the desired potential, and effectively improving display quality.

[0193] The first potential of the second control signal for the central part should be a potential that can turn on the second switching element 23TX for the central part, and the second potential of the second control signal for the central part should be a potential that can turn off the second switching element 23TX for the central part. That is, during the first control period of the second control signal for the central part, the second switching element 23TX for the central part is in the ON state, and during the second control period of the second control signal for the central part, the second switching element 23TX for the central part is in the OFF state.

[0194] The first potential of the second control signal for the frame vicinity only needs to be a potential that can turn on the second switching element 23TY for the frame vicinity, and the second potential of the second control signal for the frame vicinity only needs to be a potential that can turn off the second switching element 23TY for the frame vicinity. That is, during the first control period of the second control signal for the frame vicinity, the second switching element 23TY for the frame vicinity is in the ON state, and during the second control period of the second control signal for the frame vicinity, the second switching element 23TY for the frame vicinity is in the OFF state.

[0195] The liquid crystal panel 11 includes a plurality of second gate lines 2G, each of which includes a second gate line 2GX for the central part and a second gate line 2GY for the area near the bezel. The liquid crystal panel 11 also includes a plurality of second gate electrodes 23G, each of which includes a second gate electrode for the central part and a second gate electrode for the area near the bezel. The second gate electrode for the central part is a part of the second gate line 2GX for the central part. The second gate electrode for the area near the bezel is a part of the second gate line 2GY for the area near the bezel.

[0196] The second switching element 23TX for the central part comprises a second semiconductor layer 23A electrically connected to the second pixel electrode 132 and the third pixel electrode 133, and a second gate electrode for the central part superimposed on the second semiconductor layer 23A via the first insulating layer 121. The second switching element 23TY for the area near the frame comprises a second semiconductor layer 23A electrically connected to the second pixel electrode 132 and the third pixel electrode 133, and a second gate electrode for the area near the frame superimposed on the second semiconductor layer 23A via the first insulating layer 121.

[0197] Similarly, the liquid crystal panel 11 includes a plurality of third switching elements 34T arranged between the third pixel electrode 133 and the fourth pixel electrode 134, and the plurality of third switching elements 34T include a central third switching element 34TX arranged in the central part of the liquid crystal panel 11 in a second direction, and a third switching element 34TY arranged in the bezel vicinity part 11Y of the liquid crystal panel 11 in a second direction.

[0198] During the third period described above, the third input signal and the fourth input signal are temporarily set to a negative potential below the reference potential and then set to the reference potential. The third pixel electrode 133 connected to the third switching element 34TX for the central part is electrically connected to the fourth pixel electrode 134 connected to the third switching element 34TX for the central part via the third switching element 34TX at the timing when the second period described above for the fourth input signal begins. The third pixel electrode 133 connected to the third switching element 34TY for the frame vicinity is electrically connected to the fourth pixel electrode 134 connected to the third switching element 34TY for the frame vicinity via the third switching element 34TY at a later timing than when the second period described above for the fourth input signal begins.

[0199] In other words, the third and fourth input signals are periodically repeated in this order: a first period in which they are set to a potential positive from the reference potential; a second period in which they are temporarily set to a potential negative from the reference potential and then set to the reference potential; a third period in which they are set to a potential negative from the reference potential; and a fourth period in which they are set to the reference potential or temporarily set to a potential positive from the reference potential and then set to the reference potential. The third switching element 34TX for the central part turns on at the timing when the second period of the fourth input signal begins, and the third switching element 34TY for the frame vicinity turns on after the timing when the second period of the fourth input signal begins (preferably at the timing when the fourth input signal becomes the reference potential (0V)).

[0200] The third switching element 34TX for the central part is input a third control signal for the central part that periodically repeats in the order of a first control period set to a first potential and a second control period set to a second potential lower than the first potential. The third switching element 34TY for the area near the frame is input a third control signal for the area near the frame that periodically repeats in the order of a first control period set to a first potential and a second control period set to a second potential lower than the first potential.

[0201] By adopting this configuration, it becomes possible to drive the fourth pixel electrode 134 at an appropriate timing corresponding to the potential change in each region within the liquid crystal panel 11. This reduces the difference in potential change between the central part 11X and the edge vicinity part 11Y of the fourth pixel electrode 134, effectively preventing the third pixel electrode 133 from deviating from the desired potential, and effectively improving display quality.

[0202] The first potential of the third control signal for the central part should be a potential that can turn on the third switching element 34TX for the central part, and the second potential of the third control signal for the central part should be a potential that can turn off the third switching element 34TX for the central part. That is, during the first control period of the third control signal for the central part, the third switching element 34TX for the central part is in the ON state, and during the second control period of the third control signal for the central part, the third switching element 34TX for the central part is in the OFF state.

[0203] The first potential of the third control signal for the frame vicinity is sufficient to turn on the third switching element 34TY for the frame vicinity, and the second potential of the third control signal for the frame vicinity is sufficient to turn off the third switching element 34TY for the frame vicinity. That is, during the first control period of the third control signal for the frame vicinity, the third switching element 34TY for the frame vicinity is in the ON state, and during the second control period of the third control signal for the frame vicinity, the third switching element 34TY for the frame vicinity is in the OFF state.

[0204] The liquid crystal panel 11 includes a plurality of third gate lines 3G, each of which includes a third gate line 3GX for the central part and a third gate line 3GY for the area near the bezel. The liquid crystal panel 11 also includes a plurality of third gate electrodes 34G, each of which includes a third gate electrode for the central part and a third gate electrode for the area near the bezel. The third gate electrode for the central part is part of the third gate line 3GX for the central part. The third gate electrode for the area near the bezel is part of the third gate line 3GY for the area near the bezel.

[0205] The third switching element 34TX for the central part comprises a third semiconductor layer 34A electrically connected to the third pixel electrode 133 and the fourth pixel electrode 134, and a third gate electrode for the central part superimposed on the third semiconductor layer 34A via the first insulating layer 121. The third switching element 34TY for the area near the frame comprises a third semiconductor layer 34A electrically connected to the third pixel electrode 133 and the fourth pixel electrode 134, and a third gate electrode for the area near the frame superimposed on the third semiconductor layer 34A via the first insulating layer 121.

[0206] (Modifications of Embodiments 1-5) In embodiments 1 to 5 described above, the first electrode and the second electrode were each described as pixel electrodes 130, but the first electrode and the second electrode may each be common electrodes 230. That is, the first pixel electrode 131 corresponds to the first common electrode, and the second pixel electrode 132 corresponds to the second common electrode. Signal delay can also be suppressed by this configuration.

[0207] In this modified example, the frame wiring 100NL is, for example, a common signal line.

[0208] Furthermore, the first substrate 100 comprises, in order toward the liquid crystal layer 300 side, a first support substrate 110, a first semiconductor layer 12A, a first insulating layer 121, a first gate electrode 12G, a second insulating layer 122, a first common electrode and a first metal portion 12B connected to the first semiconductor layer 12A, a second common electrode and a second metal portion 12C connected to the first semiconductor layer 12A, a third insulating layer 123, a first common electrode and a second common electrode.

[0209] The second substrate 200 comprises, in order toward the liquid crystal layer 300 side, a second support substrate 210, an insulating layer 220, and a pixel electrode 130. The pixel electrode 130 is electrically connected to the segment signal lines of the liquid crystal panel 11.

[0210] In this embodiment, the pixel electrode 130 is described in which it is arranged on the second substrate 200, but the pixel electrode 130 may also be arranged on the first substrate 100.

[0211] The effects of the present invention will be explained below with reference to examples, but the present invention is not limited to these examples.

[0212] (Example 1) The liquid crystal panel 11 of Embodiment 1 corresponds to the liquid crystal panel 11 of Embodiment 1 described above. The reference potential was set to 0V. The liquid crystal panel 11 of this embodiment comprises pixel electrodes (segments) 130, a common (COM) electrode 230, and a liquid crystal layer 300, and is an active retarder panel that actively controls the orientation state of the liquid crystal layer 300 by the voltage applied between the pixel electrodes 130 and the common electrode 230. The pixel electrodes 130 are composed of transparent electrodes within the display area 1AA. In the bezel area 1NA, a low-resistance metal layer bus line (specifically, a segment signal line) is arranged as bezel wiring 100NL. Each pixel electrode 130 is connected to the metal layer bus line in the bezel area 1NA.

[0213] The liquid crystal panel 11 in this example is particularly suitable when there are pixel electrodes 130 (the second pixel electrode 132 and the third pixel electrode 133 in Figure 2) that have fewer connection sides with the frame wiring 100NL located in the frame region 1NA, due to the number of pixel electrodes 130.

[0214] A switching element 10T is provided at the boundary between two adjacent pixel electrodes 130, connecting the two pixel electrodes 130. The switching element 10T is controlled by control signals (a first control signal input to the first gate electrode 12G, a second control signal input to the second gate electrode 23G, and a third control signal input to the third gate electrode 34G).

[0215] Here, the boundary between the first pixel electrode 131 and the second pixel electrode 132 is shown as an example, but the boundary between other pixel electrodes 130 is similar. As shown in Figure 5, an input signal is input to each pixel electrode 130 that periodically repeats the sequence of positive voltage application → no voltage application → negative voltage application → no voltage application → positive voltage application. The input signals to the first pixel electrode 131, the second pixel electrode 132, the third pixel electrode 133, and the fourth pixel electrode 134 are phase-delayed in this order. The positive and negative writing voltages in the input signal are binary only, with no intermediate tones.

[0216] As shown in Figure 5, by turning on the switching element 12T at the timing when the input signals of the first pixel electrode 131 and the second pixel electrode 132 are at the same potential (the period indicated by the dashed-dotted arrow in Figure 5), the first pixel electrode 131 and the second pixel electrode 132 can be electrically connected via the switching element 12T.

[0217] The first pixel electrode 131 is connected on three sides to the frame wiring 100NL (bus line) located in the frame region 1NA and can be charged quickly. Therefore, it is already charged to the desired potential at the timing when the first control period of the first control signal is disclosed (i.e., when the first period of the second input signal begins (when the second pixel electrode 132 starts charging)).

[0218] The first semiconductor layer 12A, the second semiconductor layer 23A, and the third semiconductor layer 34A of the liquid crystal panel 11 in this example are IGZO and of n-type. The driving voltages are approximately ±10 to ±20V for segment signals and ±15 to ±25V for control signals.

[0219] (Comparative Example 1) The liquid crystal panel of Comparative Example 1 is the same as the liquid crystal panel of Example 1, except that the first pixel electrode 131 and the second pixel electrode 132 are not connected by a switching element, the second pixel electrode 132 and the third pixel electrode 133 are not connected by a switching element, and the third pixel electrode 133 and the fourth pixel electrode 134 are not connected by a switching element.

[0220] (Comparison of Example 1 and Comparative Example 1) Figure 29 is a timing chart showing the time variation of the potential of the first and second pixel electrodes in the liquid crystal panels of Example 1 and Comparative Example 1, and the first control signal. When positive polarity writing is performed on the liquid crystal panels of Example 1 and Comparative Example 1 from a state where no voltage is applied, as shown in Figure 29, the signal delay is large in the second pixel electrode of the liquid crystal panel of Comparative Example 1. However, the signal delay is suppressed in the second pixel electrode 132 of the liquid crystal panel 11 of Example 1. This is thought to be because the second pixel electrode 132 of the liquid crystal panel 11 of Example 1 also receives a signal from the first pixel electrode 131.

[0221] (Example 2) The liquid crystal panel 11 of Example 2 corresponds to the liquid crystal panel 11 of Embodiment 2 described above. The reference potential was set to 0V. In the liquid crystal panel 11 of Example 1, the timing at which the switching element 12T turns on is the same as the timing at which charging of the second pixel electrode 132 begins. However, in the liquid crystal panel 11 of this example, the timing at which the switching element 12T turns on is later than the timing at which charging of the second pixel electrode 132 begins. Therefore, the liquid crystal panel 11 of Example 2 can suppress the potential drop of the first pixel electrode 131 that may occur in the liquid crystal panel 11 of Example 1.

[0222] (Example 3) The liquid crystal panel 11 of Embodiment 3 corresponds to the liquid crystal panel 11 of Embodiment 3 described above. The reference potential was set to 0V. In the liquid crystal panel 11 of Embodiment 1, the voltage range of the first control signal is set to ±25V, but in the liquid crystal panel 11 of Embodiment 3, it is set to -25V to +10V.

[0223] In the liquid crystal panel 11 of Example 3, it is possible to halve the frequency of the control signal compared to Example 1. In other words, it is possible to halve the number of electrodes consumed by the control signal in Example 3 compared to Example 1.

[0224] Furthermore, in Example 1, in order to charge the first pixel electrode 131 and the second pixel electrode 132 with +20V, the potential of the first control signal needs to be set to approximately +25V. However, in Example 3, it is sufficient to set the first pixel electrode 131 and the second pixel electrode 132 to a state with no voltage applied (=0V), so setting the potential of the first control signal to approximately +5V is sufficient.

[0225] (Example 4) The liquid crystal panel 11 of Embodiment 4 corresponds to the liquid crystal panel 11 of Embodiment 4 described above. In the liquid crystal panel 11 of Embodiment 1, multiple switching elements 12T are arranged throughout the entire left and right region of the liquid crystal panel 11. However, in the liquid crystal panel 11 of this example, one or more switching elements 12T are arranged in the central part 11X in the second direction of the liquid crystal panel 11, and are not arranged in the area near the frame 11Y in the second direction of the liquid crystal panel 11. By adopting this configuration, it is possible to suppress the effect of excessive potential changes of the second pixel electrode 132 on the already charged first pixel electrode 131 in the area near the frame 11Y. As a result, it is possible to avoid the first pixel electrode 131 deviating from the desired potential, and the display quality can be improved.

[0226] (Example 5) The liquid crystal panel 11 of Embodiment 5 corresponds to the liquid crystal panel 11 of Embodiment 5 described above. In the liquid crystal panel 11 of Embodiment 4, the switching element 12T is located in the central part 11X in the second direction of the liquid crystal panel 11, and is not located in the area near the bezel 11Y in the second direction of the liquid crystal panel 11. However, the liquid crystal panel 11 of this example is provided with a first switching element 12TX for the central part in the central part 11X in the second direction of the liquid crystal panel 11, and a first switching element 12TY for the area near the bezel, which is different from the first switching element 12TX for the central part, is provided in the area near the bezel 11Y in the second direction of the liquid crystal panel 11. Furthermore, the first switching element 12TX for the central part is turned on at the timing when the second period of the second input signal begins, and the first switching element 12TY for the area near the bezel is turned on after the timing when the second period of the second input signal begins (preferably at the timing when the second input signal becomes 0V). By adopting this configuration, the second pixel electrode 132 can be driven at an appropriate timing corresponding to the potential change in each region within the liquid crystal panel 11. As a result, it becomes possible to effectively avoid the first pixel electrode 131 deviating from the desired potential, thereby effectively improving display quality. [Explanation of symbols]

[0227] 1AA:Display area 1G, 1GX, 1GY, 2G, 2GX, 2GY, 3G, 3GX, 3GY: Gate lines 1LC, 2LC, 3LC, 4LC: Liquid crystal capacity 1NA: Frame area 1S, 2S, 3S, 4S: Segments 10:Display device 10T, 12T, 12TX, 12TY, 23T, 23TX, 23TY, 34T, 34TX, 34TY: Switching elements 11: LCD panel 11A, 11B, 11C: Area 11X: Central part 11Y: Picture frame 11R: Active Retarder Panel 12: Image display panel 12A, 23A, 34A: Semiconductor layer 12B, 12C, 23B, 23C, 34B, 34C: Metal part 12G, 12GX, 12GY, 23G, 34G: Gates 13: Backlight 100, 200: Circuit board 100NL: Picture frame wiring 110, 210: Support substrate 121, 122, 123, 220: Insulating layer 130, 131, 132, 133, 134: Pixel electrodes 230: Common electrode 300: Liquid crystal layer

Claims

1. It comprises a display area and a frame area provided around the display area, It comprises a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate or the second substrate has frame wiring arranged in the frame region, The first substrate comprises, within the display area, a first electrode and a second electrode electrically connected to the frame wiring, and a switching element that controls the electrical connection between the first electrode and the second electrode. A first input signal is input to the first electrode, and a second input signal is input to the second electrode. The first input signal and the second input signal are periodically repeated in this order: a first period during which they are set to a potential positive from the reference potential; a second period during which they are set to the reference potential or temporarily set to a potential negative from the reference potential before being set to the reference potential; a third period during which they are set to a potential negative from the reference potential; and a fourth period during which they are set to the reference potential or temporarily set to a potential positive from the reference potential before being set to the reference potential. The first, second, third, and fourth periods of the first input signal each overlap with the first, second, third, and fourth periods of the second input signal, and each starts at an earlier timing. A liquid crystal panel in which the first electrode is electrically connected to the second electrode via the switching element during the period from the start of the second period of the second input signal to the end of the second period of the first input signal, and during the period from the start of the fourth period of the second input signal to the end of the fourth period of the first input signal.

2. The liquid crystal panel according to claim 1, wherein the first electrode is electrically connected to the second electrode via the switching element during the period from the start of the first period of the second input signal to the end of the first period of the first input signal, and during the period from the start of the third period of the second input signal to the end of the third period of the first input signal.

3. The liquid crystal panel according to claim 1, wherein the timing at which the first electrode is electrically connected to the second electrode via the switching element is later than the timing at which the first period of the second input signal begins.

4. The liquid crystal panel according to claim 1, wherein the first electrode is not electrically connected to the second electrode during the period from the start of the first period of the second input signal to the end of the first period of the first input signal, and during the period from the start of the third period of the second input signal to the end of the third period of the first input signal.

5. The liquid crystal panel according to claim 1, wherein the first electrode and the second electrode are arranged along a first direction of the liquid crystal panel and extend along a second direction perpendicular to the first direction.

6. The liquid crystal panel comprises a plurality of the switching elements, The liquid crystal panel according to claim 5, wherein the plurality of switching elements are arranged from one end to the other end in the second direction of the liquid crystal panel.

7. The liquid crystal panel comprises one or more of the switching elements, The liquid crystal panel according to claim 5, wherein the one or more switching elements are arranged in the central part of the liquid crystal panel in the second direction and are not arranged near the frame in the second direction.

8. The liquid crystal panel comprises a plurality of the switching elements, The liquid crystal panel according to claim 5, wherein the plurality of switching elements comprises a central switching element disposed in the central part of the liquid crystal panel in the second direction, and a frame-near switching element disposed in the frame-near part of the liquid crystal panel in the second direction.

9. During the second period, the first input signal and the second input signal are temporarily set to a negative potential below the reference potential and then set to the reference potential. The first electrode connected to the central switching element is electrically connected to the second electrode connected to the central switching element via the central switching element at the timing when the second period of the second input signal begins. The liquid crystal panel according to claim 8, wherein the first electrode connected to the switching element for the vicinity of the frame is electrically connected to the second electrode connected to the switching element for the vicinity of the frame via the switching element for the vicinity of the frame after the timing of the start of the second period of the second input signal.

10. The liquid crystal panel according to claim 1, wherein the switching element is controlled by a control signal different from the first input signal and the second input signal.

11. The liquid crystal panel according to claim 1, wherein, in a plan view, the edge of the first electrode facing the frame region is longer than the edge of the second electrode facing the frame region.

12. A liquid crystal panel according to any one of claims 1 to 11, An image display panel is located on the back side of the aforementioned liquid crystal panel, A display device comprising a backlight positioned on the rear side of the image display panel.

Images