Chip stacking heat dissipation structure, three-dimensional stacking packaging system and manufacturing method

Abstract

Provided in the present disclosure are a chip stacking heat dissipation structure, a three-dimensional stacking packaging system and a manufacturing method. The chip stacking heat dissipation structure comprises: a re-distributed layer, a connecting layer and a chip layer which are successively stacked from bottom to top, a plurality of cooling fins being embedded in the re-distributed layer to form a heat dissipation layer, and the heat dissipation layer and the re-distributed layer being located on the same side of the chip layer. The re-distributed layer and the heat dissipation layer of the present application are both located on the same side of the chip layer, such that the re-distributed layer and the heat dissipation layer occupy relatively smaller spaces, and chip layers are stacked at a higher integration level, thus achieving a greater number of chip lays stacked per unit height, reducing the overall size and the packaging thickness of the chip stacking heat dissipation structure, enabling the chip stacking heat dissipation structure to be applied to more terminal devices having higher requirements for thickness while not losing heat dissipation effects.

Description

Chip stacking heat dissipation structure, three-dimensional stacking packaging system and manufacturing method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to Chinese patent application number 202310989239.5 filed with the State Intellectual Property Office of China on August 7, 2023, entitled “Chip stacking heat dissipation structure, three-dimensional stacking packaging system and manufacturing method,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present application relates to the field of electronic technology, and in particular to a chip stacking heat dissipation structure, a three-dimensional stacking packaging system and a manufacturing method. Background Art

[0004] As the functions of integrated circuits continue to improve, the number of chips required is increasing, and therefore more heat sinks or heat dissipation covers are needed to form heat dissipation structures.

[0005] In related technologies, the heat dissipation structure and the RDL layer (re-distributed layer) are located on opposite sides of the chip. When the chips are stacked vertically, the heat sink and the RDL layer need to occupy space at the same time, resulting in a larger integrated circuit, more complex processing, and poor heat dissipation effect for the stacked chips.

[0006] Summary of the Invention

[0007] An embodiment of the present application provides a chip stacking heat dissipation structure, in which the redistribution layer and the heat dissipation layer are both located on the same side of the chip layer, so that the redistribution layer and the heat dissipation layer each occupy a smaller space, and the chip layers are stacked with a higher degree of integration, thereby achieving a greater number of stacked chip layers per unit height, reducing the overall size and packaging thickness of the chip stacking heat dissipation structure, and enabling the chip stacking heat dissipation structure to be more widely used in terminal devices with higher thickness requirements without sacrificing heat dissipation effect.

[0008] In some embodiments, the present application provides a chip stacking heat dissipation structure, which may include: a redistribution layer, a connection layer, and a chip layer stacked in sequence from bottom to top, and a plurality of heat sinks may be embedded in the redistribution layer to form a heat dissipation layer, and the heat dissipation layer and the redistribution layer may be located on the same side of the chip layer.

[0009] In one embodiment, the redistribution layer may include metal wiring and a dielectric layer. The metal wiring may be provided as one or more layers and distributed between the dielectric layers, and the metal wiring may expose the dielectric layer.

[0010] In one embodiment, the projected area of ​​the heat dissipation layer projected onto the passive surface of the chip layer may be no less than the surface area of ​​the passive surface of the chip layer.

[0011] In one embodiment, the active surface of the chip layer may be connected to the metal wiring for data transmission in the redistribution layer via a soldering member, and the passive surface of the chip layer may be connected to the connection layer.

[0012] In one embodiment, the thickness of the heat dissipation layer may be no less than the thickness of the redistribution layer.

[0013] In one embodiment, the heat sinks may be stacked sequentially from bottom to top within the redistribution layer.

[0014] In one embodiment, the connection layer may be one of a hot-pressed non-conductive adhesive, a hot-pressed non-conductive film, a die-bonding film, or a silver adhesive.

[0015] In other embodiments, the present application provides a three-dimensional stacking packaging system, which may include: at least one layer of chip stacking heat dissipation structure and copper pillars as described in any of the aforementioned embodiments; adjacent chip stacking heat dissipation structures can be connected through the copper pillars to achieve electrical connection.

[0016] In one embodiment, the three-dimensional stacked packaging system may further include: a molding material layer; the molding material layer may be filled between the redistribution layers on the adjacent chip stacking heat dissipation structures, and surround and fix the chip layer and the copper pillars.

[0017] In one embodiment, the molding material layer may be made of a resin material and may be filled with filler particles.

[0018] In one embodiment, an adhesive may be coated between the passive surface of the chip layer and the connection layer.

[0019] In yet other embodiments, the present application provides a method for manufacturing a chip stack heat dissipation structure, which may include:

[0020] preparing the redistribution layer, and arranging metal wiring in the redistribution layer;

[0021] The chip layer is arranged on the upper surface of the redistribution layer so that the passive surface of the chip layer contacts the redistribution layer, and the active surface of the chip layer is connected to the metal wiring through a welding piece;

[0022] Wherein, a plurality of heat sinks are stacked from bottom to top in the redistribution layer at the contact surface between the redistribution layer and the active surface of the chip layer to form a heat dissipation layer.

[0023] In one embodiment, the method may further include: etching a cavity at the connection between the upper surface of the redistribution layer and the chip layer, so that the passive surface of the chip layer is exposed in the cavity, and the area of ​​the cavity is not less than the surface area of ​​the passive surface of the chip layer.

[0024] In one embodiment, the method may further include: providing a connection layer between the upper surface of the redistribution layer and the passive surface of the chip layer.

[0025] In one embodiment, when preparing the redistribution layer, an interconnection path can be connected on the surface of the redistribution layer, one end of the interconnection path can be connected to the metal wiring of the redistribution layer, and the passive surface of the chip layer can be directly connected on the upper surface of the redistribution layer. The passive surface of the chip layer can connect the chip layer and the heat dissipation layer through the connecting layer.

[0026] In one embodiment, the connection between the heat dissipation layer and the passive surface of the chip layer can be bonded by directly growing and depositing heat sink material.

[0027] In some further embodiments, the present application provides a method for manufacturing a three-dimensional stacked packaging system, which may include:

[0028] Arrange the chip stacking heat dissipation structure of any of the aforementioned embodiments in a relative stack;

[0029] Electroplating the copper pillars on the surface of the redistribution layer on the adjacent chip stack heat dissipation structure, and connecting the copper pillars by bonding;

[0030] A molding material layer is filled around the adjacent chip layers to fix the chip layers and the copper pillars.

[0031] In one embodiment, a metal wiring may be provided in the redistribution layer, one end of the metal wiring may be exposed on the surface of the molding material layer along a preset direction, the preset direction may be perpendicular to the direction of the surface of the molding material layer, and one end of the metal wiring is connected to the active surface of the chip layer in another layer of the chip stacking heat dissipation structure.

[0032] In one embodiment, the method may further include: grinding the surface of the molding material layer according to a preset thickness of the chip stacking heat dissipation structure so that the surface thickness of the molding material layer is not less than the preset thickness of the chip stacking heat dissipation structure.

[0033] In the present application, the redistribution layer and the heat dissipation layer are both located on the same side of the chip layer, so that the redistribution layer and the heat dissipation layer each occupy a smaller space, and the chip layers are stacked with a higher degree of integration, thereby achieving a greater number of stacked chip layers per unit height, reducing the overall size and packaging thickness of the chip stacking heat dissipation structure, and enabling the chip stacking heat dissipation structure to be more widely used in terminal devices with higher thickness requirements without sacrificing heat dissipation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application.

[0035] FIG1 is a structural schematic diagram 1 of a chip stacking heat dissipation structure provided by an embodiment of the present application;

[0036] FIG2 is a second structural diagram of a chip stacking heat dissipation structure provided by an embodiment of the present application;

[0037] FIG3 is a schematic structural diagram of a three-dimensional stacked packaging system provided in one embodiment of the present application;

[0038] FIG4 is a schematic flow chart of a method for manufacturing a chip stacking heat dissipation structure according to an embodiment of the present application;

[0039] FIG5 is a schematic flow chart of a method for manufacturing a three-dimensional stacked packaging system according to an embodiment of the present application.

[0040] Figure numerals: 1-chip stacking heat dissipation structure; 100-rewiring layer; 110-metal wiring; 120-dielectric layer; 200-connection layer; 300-chip layer; 310-active surface; 320-passive surface; 400-heat dissipation layer; 410-heat sink; 500-adhesive; 600-weld; 2-three-dimensional stacking packaging system; 21-copper pillar; 22-molding material layer. DETAILED DESCRIPTION

[0041] The terms "first", "second", "third", etc. are only used to distinguish and describe, and do not indicate the order of arrangement, nor can they be understood as indicating or implying relative importance.

[0042] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0043] In the description of this application, it should be noted that the terms "inside", "outside", "left", "right", "up", "down", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0044] In the description of this application, unless otherwise clearly specified and limited, the terms "set", "install", "connected" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be a connection between the internal parts of two elements.

[0045] The technical solution of this application will be described below with reference to the accompanying drawings.

[0046] Please refer to Figure 1. The present application provides a chip stacking heat dissipation structure 1, which may include: a redistribution layer 100, a connection layer 200 and a chip layer 300 stacked in sequence from bottom to top. A plurality of heat sinks 410 may be embedded in the redistribution layer 100 to form a heat dissipation layer 400. The heat dissipation layer 400 and the redistribution layer 100 may be located on the same side of the chip layer 300.

[0047] The redistribution layer 100 may include metal wiring 110 and a dielectric layer 120. The metal wiring 110 may be one or more layers, distributed between the dielectric layers 120, and the metal wiring 110 may be exposed from the dielectric layer 120 to achieve connection with external terminals. The connection layer 200 is located on the upper surface of the redistribution layer 100. The chip layer 300 is located on the upper surface of the connection layer 200.

[0048] Optionally, the chip layer 300 may include an active surface 310 and a passive surface 320. The active surface 310 may be understood as containing components (or circuits) that require power to achieve intended functions. Opposite to the active surface 310 is the passive surface 320, which does not require power.

[0049] Optionally, the surface of the active surface 310 of the chip layer 300 can be connected to the metal wiring 110 for data transmission in the redistribution layer 100 through the welding member 600 , and the surface of the passive surface 320 of the chip layer 300 can be connected to the connection layer 200 .

[0050] Optionally, the welding member 600 may be a pad. Before the chip layer 300 is shipped, an aluminum pad (AP) may be pre-prepared on the active surface 310. This pad is used to electrically connect the chip layer 300 to the metal wiring 110 within the redistribution layer 100, which serves as data transmission, during packaging, thereby achieving electrical connection with the outside world. This pad is conductive.

[0051] Furthermore, the pads can also be connected to pins that connect the chip layer 300 to the outside. At least some of the pins of the chip layer 300 can be interconnected with the metal wiring 110 exposed from the dielectric layer 120. Some of the pins of the chip layer 300 can also be led out of the chip layer 300 through fan-out wafer-level packaging technology and connected to the metal wiring 110.

[0052] Optionally, the heat sinks 410 may be stacked sequentially from bottom to top in the redistribution layer 100 . Furthermore, the thickness of the heat sink layer 400 may be no less than that of the redistribution layer 100 .

[0053] In this embodiment, the heat sink 410 may include, but is not limited to, a single layer. Multiple heat sinks 410 may be stacked sequentially from bottom to top to form a heat dissipation layer 400. The thickness of the heat dissipation layer 400 formed by stacking multiple heat sinks 410 is the sum of the thicknesses of each individual heat sink 410. The thickness of the heat dissipation layer 400 may be equal to the thickness of the redistribution layer 100; alternatively, the thickness of the heat dissipation layer 400 may exceed the thickness of the redistribution layer 100. This ensures that the heat dissipation layer 400 has a certain heat dissipation capacity. Assume that the number of heat sinks 410 is n, where n ≥ 1, and n is an integer.

[0054] Optionally, the projected area of ​​the heat dissipation layer 400 projected onto the surface of the passive surface 320 of the chip layer 300 may be no less than the surface area of ​​the passive surface 320 of the chip layer 300 .

[0055] In this embodiment, the surface area of ​​the heat dissipation layer 400 projected onto the passive surface 320 of the chip layer 300 may be equal to the surface area of ​​the passive surface 320 of the chip layer 300. For example, as viewed from the cross-section of FIG1 , the portion where the contact surface of the heat dissipation layer 400 overlaps with the contact surface of the connection layer 200 may represent the width direction of the projected area of ​​the heat dissipation layer 400 projected onto the passive surface 320 of the chip layer 300.

[0056] In other optional embodiments, the surface area of ​​the heat dissipation layer 400 projected onto the passive surface 320 of the chip layer 300 may be larger than the surface area of ​​the passive surface 320 of the chip layer 300. That is, the width of the contact and overlapping portion of the heat dissipation layer 400 and the connection layer 200 is larger than the width of the chip layer 300, thereby making the surface area of ​​the heat dissipation layer 400 projected onto the passive surface 320 of the chip layer 300 larger than the surface area of ​​the passive surface 320 of the chip layer 300.

[0057] Optionally, the connection layer 200 may be one of a hot-pressed non-conductive adhesive, a hot-pressed non-conductive film, a chip bonding film or a silver adhesive.

[0058] Please refer to Figure 2, which is a second structural schematic diagram of a chip stack heat dissipation structure 1 provided in another embodiment of the present application. The chip stack heat dissipation structure 1 may include: a redistribution layer 100 and a chip layer 300, stacked sequentially from bottom to top. A plurality of heat sinks 410 may be embedded within the redistribution layer 100 to form a heat dissipation layer 400. The heat dissipation layer 400 and the redistribution layer 100 are located on the same side of the chip layer 300. The passive surface 320 of the chip layer 300 and the upper surface of the redistribution layer 100 may be connected without the connection layer 200.

[0059] In the embodiments described in Figures 1 and 2, since the redistribution layer 100 and the heat dissipation layer 400 are both located on the same side of the chip layer 300, that is, in this embodiment, the redistribution layer 100 and the heat dissipation layer 400 are both located below the chip layer 300, the redistribution layer 100 and the heat dissipation layer 400 each occupy a smaller space, and the chip layer 300 is stacked with a higher degree of integration, thereby achieving more stacking layers of chip layers 300 per unit height, reducing the overall size and packaging thickness of the chip stacking heat dissipation structure 1, so that the chip stacking heat dissipation structure 1 can be more applied to terminal devices with higher thickness requirements without losing the heat dissipation effect.

[0060] Please refer to Figure 3. The present application provides a three-dimensional stacked packaging system 2. The three-dimensional stacked packaging system 2 may include: at least one layer of chip stacking heat dissipation structure 1 and copper pillars 21; adjacent chip stacking heat dissipation structures 1 can be connected through copper pillars 21 to achieve electrical connection.

[0061] 3 , the three-dimensional stacked packaging system 2 may further include: a molding material layer 22 ; the molding material layer 22 may be filled between the redistribution layers 100 on the adjacent chip stacking heat dissipation structures 1 , and surround and fix the chip layer 300 and the copper pillars 21 .

[0062] The molding material layer 22 (Molding Compound, referred to as "MC") can fill the space between the redistribution layer 100 on the adjacent chip stacking heat dissipation structure 1 and surround the chip layer 300 from all sides to isolate the chip layer 300 from the outside world, thereby playing a role in moisture-proof, dust-proof and buffering, and at the same time, it can also prevent the relative movement between the chip layers 300 on the two chip stacking heat dissipation structures 1.

[0063] In addition, the molding material layer 22 may also surround the side surfaces and the back surface of the chip layer 300 ; or surround the side surfaces of the chip layer 300 to reduce the impact of the outside world on the chip layer 300 .

[0064] Optionally, referring to FIG. 3 , an adhesive 500 may be applied between the passive surface 320 of the chip layer 300 and the connection layer 200 to fix the passive surface 320 of the chip layer 300 to the connection layer.

[0065] The molding material layer 22 may be made of a resin material and may be added with filler particles to improve its properties.

[0066] 4 , the present application provides a method for manufacturing a chip stack heat dissipation structure, which may include: steps S410 to S420;

[0067] Step S410 : preparing a redistribution layer 100 , and disposing metal wiring 110 in the redistribution layer 100 .

[0068] In this step, dielectric layer 120 is first applied, and metal wiring 110 is formed inside and on the surface of dielectric layer 120. Redistribution layer 100 can be prepared through processes such as coating, exposure, development, curing, sputtering, electroplating, and etching. Metal wiring 110 can be made of conductive materials such as copper and aluminum. Redistribution layer 100 can be a single layer or multiple layers.

[0069] Step S420: A chip layer 300 is arranged on the upper surface of the redistribution layer 100, so that the passive surface of the chip layer 300 contacts the redistribution layer 100, and the active surface 310 of the chip layer 300 is connected to the metal wiring 110 through the welding part 600; wherein, a plurality of heat sinks 410 are stacked from bottom to top in the redistribution layer 100 at the contact surface between the redistribution layer 100 and the active surface 310 of the chip layer 300 to form a heat dissipation layer 400.

[0070] Optionally, when preparing the redistribution layer 100, an interconnection path can be connected on the surface of the redistribution layer 100, one end of the interconnection path is connected to the metal wiring 110 of the redistribution layer 100, and the passive surface 320 of the chip layer 300 is directly connected on the upper surface of the redistribution layer 100, and the chip layer 300 is connected to the heat dissipation layer 400 through the connecting layer 200 on the passive surface 320 of the chip layer 300.

[0071] Optionally, the interconnection path may also be other equivalent structures with electrical interconnection functions, for example, a printed circuit board block, a through silicon via module, etc.

[0072] Optionally, the method may further include: step S430: etching a cavity at the connection between the upper surface of the redistribution layer 100 and the chip layer 300, so that the surface of the passive surface 320 of the chip layer 300 is exposed in the cavity, and the area of ​​the cavity is not less than the surface area of ​​the passive surface 320 of the chip layer 300.

[0073] Specifically, the active surface 310 of the chip layer 300 can be welded to one end of the metal wiring 110 extending out of the dielectric layer 120 through a pad to achieve electrical interconnection between the chip layer 300 and the redistribution layer 100 .

[0074] In this embodiment, a cavity is etched at the junction between the upper surface of the redistribution layer 100 and the passive surface 320 of the chip layer 300, thereby exposing the passive surface 320 of the chip layer 300 to the cavity. Etching can be performed using wet or dry etching, and the photoresist can be a positive photoresist, a negative photoresist, a dry film, or a liquid photoresist. The etching method is not further described here.

[0075] Optionally, the method may further include: step S440 : disposing a connection layer 200 between the upper surface of the redistribution layer 100 and the surface of the passive surface 320 of the chip layer 300 .

[0076] In this step, the upper surface of the redistribution layer 100 and the passive surface 320 of the chip 300 can be bonded and fixed by hot-pressing non-conductive adhesive; or by hot-pressing non-conductive film; or by connecting the upper surface of the redistribution layer 100 and the passive surface 320 of the chip 300 with a die bonding film; or by bonding the upper surface of the redistribution layer 100 and the passive surface 320 of the chip 300 with silver glue. All of the above bonding methods can achieve a stable connection between the upper surface of the redistribution layer 100 and the passive surface 320 of the chip 300.

[0077] Optionally, the connection between the heat dissipation layer 400 and the passive surface 320 of the chip layer 300 may be bonded by directly growing and depositing heat dissipation fin material.

[0078] The chip stacking heat dissipation structure 1 manufactured by the above solution can not only reduce the thickness of the overall structure, so that the chip stacking heat dissipation structure 1 can be more widely used in terminal devices with higher thickness requirements, but also improve the integration accuracy.

[0079] According to the same method as above, multiple chip stacking heat dissipation structures 1 are manufactured to carry out the manufacture and installation of the three-dimensional stacking packaging system 2.

[0080] 5 , the present application provides a method for manufacturing a three-dimensional stacked packaging system, which may include: steps S510 to S530;

[0081] Step S510: stacking and arranging the chip stacking heat dissipation structures 1 relative to each other.

[0082] In this step, a plurality of chip stacking heat dissipation structures 1 are manufactured in the manner shown in FIG. 1 and FIG. 2 , and the plurality of chip stacking heat dissipation structures 1 are arranged relative to each other so that adjacent chip stacking heat dissipation structures 1 are electrically connected.

[0083] Step S520: electroplating copper pillars 21 on the surface of the redistribution layer 100 on the adjacent chip stacking heat dissipation structure 1, and connecting the copper pillars 21 by bonding.

[0084] In this step, two chip stacking heat dissipation structures 1 are arranged relative to each other, with the active surfaces 310 of adjacent chip layers 300 facing each other. Copper pillars 21 are electroplated on the upper surfaces of the redistribution layers 100 of the adjacent chip stacking heat dissipation structures 1. Adjacent copper pillars 21 can be soldered together by thermocompression bonding. In other optional embodiments, the copper pillars 21 can also be connected by hot air reflow soldering.

[0085] As a way to realize vertical interconnection path, copper pillar 21 can be prepared by sputtering seed layer, dry film lithography, development, curing, electroplating, degumming, deseed layer, plastic packaging and other processes. That is, copper pillar 21 can be electroplated at the position where metal wiring 110 exposes dielectric layer 120. In other optional embodiments, vertical interconnection path can also be made by laser drilling, deep reactive ion etching and other methods, and then fill the hole with conductive material to achieve electrical interconnection. The conductive material in the hole can be metal such as aluminum, copper, tin, or conductive glue, and the filling method can be electroplating, chemical plating, dispensing and other methods.

[0086] It should be noted that the top of the copper pillar 21 needs to contain a material that is easy to solder, such as a tin-based bump, to improve the reliability of the connection between the copper pillar 21 and the metal wiring 110. For example, other barrier layers such as nickel (Ni) and titanium (Ti) can be added to the top of the copper pillar 21 to achieve isolation between copper (Cu) and tin (Sn).

[0087] Step S530 : Filling the surroundings of the adjacent chip layers 300 with a molding material layer 22 to fix the chip layers 300 and the copper pillars 21 .

[0088] Optionally, a metal wiring 110 can be set in the redistribution layer 100, and one end of the metal wiring 110 is exposed on the surface of the molding material layer 22 along a preset direction, and the preset direction can be perpendicular to the direction of the surface of the molding material layer 22. One end of the metal wiring 110 is connected to the active surface 310 of the chip layer 300 in another layer of the chip stacking heat dissipation structure 1.

[0089] As described in step S520, taking the structure of one of the chip stacking heat dissipation structures 1 as an example, one end of the metal wiring 110 in the redistribution layer 100 on the chip stacking heat dissipation structure 1 is vertically exposed to the surface of the molding material layer 22, and the end of the metal wiring 110 exposed to the molding material layer 22 is connected to the surface of the active surface 310 of the chip layer 300 of another chip stacking heat dissipation structure 1 arranged opposite to the chip stacking heat dissipation structure 1 through a pad welding to achieve electrical interconnection.

[0090] By using the metal wiring 100 of the vertical interconnection path to achieve the purpose of electrical connection, instead of realizing electrical interconnection by means of thermal compression solder balls, the thickness of the overall structure of the chip stacking heat dissipation structure 1 can be further reduced.

[0091] Optionally, the method may further include: step S540: grinding the surface of the molding material layer 22 according to the preset thickness of the chip stacking heat dissipation structure 1 so that the surface thickness of the molding material layer 22 is not less than the preset thickness of the chip stacking heat dissipation structure 1.

[0092] In this step, the filling height or filling thickness of the molding material layer 22 can be reduced by grinding. The grinding thickness of the molding material layer 22 can be ground as needed, so that the copper pillars 21 are exposed on the upper surface of the redistribution layer 100; alternatively, the surface thickness of the molding material layer 22 can be ground so that the surface thickness of the molding material layer 22 is not less than or equal to the preset thickness of the chip stacking heat dissipation structure 1. The preset thickness of the chip stacking heat dissipation structure 1 can be obtained in advance based on production and processing parameters. In other words, the thickness parameters of the chip stacking heat dissipation structure 1 can be obtained after production and processing.

[0093] Through steps S510 to S530, multiple chip stacking heat dissipation structures 1 are stacked to form a multi-layer structure of a three-dimensional stacked packaging system 2. In the three-dimensional stacked packaging system 2 of the present application, the heat dissipation layer 400 and the redistribution layer 100 are arranged on the same side of the chip layer 300, thereby reducing the overall structure and thickness of the integrated circuit and improving the integration of the three-dimensional stacked packaging system 2.

[0094] It should be noted that, unless there is any conflict, the features in the embodiments of this application can be combined with each other.

[0095] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application. Industrial Applicability

[0096] The present disclosure provides a chip stacking heat dissipation structure, a three-dimensional stacking packaging system, and a manufacturing method. The chip stacking heat dissipation structure includes: a redistribution layer, a connection layer, and a chip layer stacked in sequence from bottom to top. A plurality of heat sinks are embedded in the redistribution layer to form a heat dissipation layer. The heat dissipation layer and the redistribution layer are located on the same side of the chip layer. The redistribution layer and the heat dissipation layer in the present application are both located on the same side of the chip layer, so that the redistribution layer and the heat dissipation layer each occupy a smaller space, and the chip layers are stacked with a higher degree of integration, thereby achieving a greater number of chip layers stacked per unit height, reducing the overall size and packaging thickness of the chip stacking heat dissipation structure, and enabling the chip stacking heat dissipation structure to be more widely used in terminal devices with higher thickness requirements without sacrificing heat dissipation effect.

[0097] Furthermore, it is understood that the disclosed chip stacking heat dissipation structure, three-dimensional stacking packaging system, and manufacturing method are reproducible and can be used in a variety of industrial applications. For example, the disclosed chip stacking heat dissipation structure, three-dimensional stacking packaging system, and manufacturing method can be used in the field of electronics.

Claims

1. A chip stacking heat dissipation structure, wherein: The chip stacking heat dissipation structure includes: a redistribution layer, a connection layer and a chip layer stacked in sequence from bottom to top, a plurality of heat sinks are embedded in the redistribution layer to form a heat dissipation layer, and the heat dissipation layer and the redistribution layer are located on the same side of the chip layer.

2. The chip stacking heat dissipation structure according to claim 1, wherein: The redistribution layer includes metal wiring and a dielectric layer. The metal wiring is provided as one or more layers and distributed between the dielectric layers, and the metal wiring can expose the dielectric layer.

3. The chip stacking heat dissipation structure according to claim 1 or 2, wherein: The projection area of ​​the heat dissipation layer projected onto the passive surface of the chip layer is not less than the surface area of ​​the passive surface of the chip layer.

4. The chip stacking heat dissipation structure according to any one of claims 1 to 3, wherein: The surface of the active side of the chip layer is connected to the metal wiring used for data transmission in the redistribution layer through a soldering member, and the surface of the passive side of the chip layer is connected to the connection layer.

5. The chip stacking heat dissipation structure according to any one of claims 1 to 4, wherein: The thickness of the heat dissipation layer is not less than the thickness of the redistribution layer.

6. The chip stacking heat dissipation structure according to any one of claims 1 to 5, wherein: The heat sinks are stacked in sequence from bottom to top in the redistribution layer.

7. The chip stacking heat dissipation structure according to any one of claims 1 to 6, wherein: The connection layer is one of a hot-pressed non-conductive glue, a hot-pressed non-conductive film, a chip bonding film or a silver glue.

8. A three-dimensional stacked packaging system, wherein: include: At least one layer of the chip stacking heat dissipation structure and copper pillars as described in any one of claims 1 to 7; adjacent chip stacking heat dissipation structures are connected via the copper pillars to achieve electrical connection.

9. The three-dimensional stacked packaging system according to claim 8, wherein: The three-dimensional stacking packaging system further includes: a molding material layer; the molding material layer is filled between the redistribution layers on the adjacent chip stacking heat dissipation structures, and surrounds and fixes the chip layer and the copper pillars.

10. The three-dimensional stacked packaging system according to claim 9, wherein: The molding material layer is made of a resin material and is added with filler particles.

11. The three-dimensional stacked packaging system according to any one of claims 8 to 10, wherein: An adhesive is applied between the passive surface of the chip layer and the connection layer.

12. A method for manufacturing a chip stacking heat dissipation structure, wherein: include: preparing a redistribution layer, and disposing metal wiring in the redistribution layer; A chip layer is arranged on the upper surface of the redistribution layer so that the passive surface of the chip layer is adjacent to the redistribution layer. The active surface of the chip layer is connected to the metal wiring through a welding piece; Wherein, a plurality of heat sinks are stacked and arranged from bottom to top in the redistribution layer at the contact surface between the redistribution layer and the active surface of the chip layer to form a heat dissipation layer.

13. The method for manufacturing a chip stacking heat dissipation structure according to claim 12, wherein: The method further comprises: A cavity is etched at the connection between the upper surface of the redistribution layer and the chip layer, so that the passive surface of the chip layer is exposed in the cavity, and the area of ​​the cavity is not less than the surface area of ​​the passive surface of the chip layer.

14. The method for manufacturing a chip stacking heat dissipation structure according to claim 12 or 13, wherein: The method further comprises: A connection layer is provided between the upper surface of the redistribution layer and the passive surface of the chip layer.

15. The method for manufacturing a chip stacking heat dissipation structure according to claim 14, wherein: When preparing the redistribution layer, an interconnection path is connected on the surface of the redistribution layer, one end of the interconnection path is connected to the metal wiring of the redistribution layer, and the passive surface of the chip layer is directly connected on the upper surface of the redistribution layer. The passive surface of the chip layer connects the chip layer and the heat dissipation layer through the connecting layer.

16. The method for manufacturing a chip stacking heat dissipation structure according to any one of claims 12 to 15, wherein: The connection between the heat dissipation layer and the passive surface of the chip layer is bonded by directly growing and depositing heat sink material.

17. A method for manufacturing a three-dimensional stacked packaging system, wherein: The manufacturing method of the three-dimensional stacking packaging system comprises: Arrange the chip stacking heat dissipation structure according to any one of claims 1 to 11 in a stacked manner; Electroplating copper pillars on the surface of the redistribution layer on the adjacent chip stacking heat dissipation structure, and connecting the copper pillars by bonding; A molding material layer is filled around the adjacent chip layers to fix the chip layers and the copper pillars.

18. The method for manufacturing a three-dimensional stacked packaging system according to claim 17, wherein: A metal wiring is arranged in the redistribution layer, one end of the metal wiring is exposed on the surface of the molding material layer along a preset direction, the preset direction is perpendicular to the direction of the surface of the molding material layer, and one end of the metal wiring is connected to the active surface of the chip layer in another layer of the chip stacking heat dissipation structure.

19. The method for manufacturing a three-dimensional stacked packaging system according to claim 17 or 18, wherein: The method further comprises: According to the preset thickness of the chip stacking heat dissipation structure, the surface of the molding material layer is ground so that the surface thickness of the molding material layer is not less than the preset thickness of the chip stacking heat dissipation structure.

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