Electrostatic discharge device based on PNPN structure

Abstract

The present invention relates to the technical field of electrostatic discharge (ESD), and provides an ESD device based on a PNPN structure. A first junction is formed between a first P-well and an N-well, and a second junction is formed between the N-well and a second P-well; a first ion implantation region is provided in the surface region of the first P-well; a second ion implantation region is provided in the surface region of the second P-well; a first N-ion boundary implantation region is provided at a first junction formed by the intersection of the surface region of the first P-well and the surface region of the N-well; a second N-ion boundary implantation region is provided at a second junction formed by the intersection of the surface region of the N-well and the surface region of the second P-well; and a parasitic discharge circuit spans the first P-well, the N-well, and the second P-well, and is respectively connected to the first ion implantation region and the second ion implantation region. The present invention reduces snapback voltage by setting a high-concentration boundary, thereby improving ESD performance.

Description

An electrostatic discharge device based on PNPN structure

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202411118593.1, filed on August 15, 2024, and entitled "An electrostatic discharge device based on PNPN structure", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of ESD charge discharge, and particularly relates to an electrostatic discharge device based on PNPN structure. BACKGROUND

[0004] Traditional CMOS process ESD discharge devices mainly include metal-oxide-semiconductor field-effect transistor (MOS), diode, resistor, capacitor and the like, and some ESD units such as gate ground NMOS (GGNMOS) unit and power clamp unit are combined on the basis of these devices, and these ESD units make good use of the parasitic effect of the devices to achieve the purpose of discharging.

[0005] One of the ESD research directions is to improve the ESD performance by using the CMOS process parasitic PNPN structure, which does not need to adjust any process and process parameters, and has low cost and good effect. When ESD charges attack, the traditional method uses the CMOS process parasitic PNPN structure to discharge ESD charges, but due to the high snapback voltage of the ESD device, the functional device is damaged by thermal breakdown before the ESD charge is discharged and the ESD device is turned on, thereby reducing the ESD charge discharge capability and failing to improve the ESD protection capability. SUMMARY

[0006] Therefore, the purpose of the present disclosure is to at least provide an electrostatic discharge device based on PNPN structure, which reduces the snapback voltage and improves the ESD performance through high concentration boundaries.

[0007] The present disclosure mainly includes the following aspects:

[0008] In a first aspect, an optional embodiment of the present disclosure provides a PNPN structure-based electrostatic discharge device, which comprises a P-type substrate, a first P-well, an N-well, a second P-well, a first ion implantation region, a first N-ion boundary implantation region, a second N-ion boundary implantation region, a second ion implantation region, and a parasitic discharge circuit. The first P-well, the N-well, and the second P-well are sequentially arranged from left to right in a surface region of the P-type substrate, a first intersection boundary is formed between the first P-well and the N-well, and a second intersection boundary is formed between the N-well and the second P-well. The first ion implantation region is arranged in a surface region of the first P-well, the second ion implantation region is arranged in a surface region of the second P-well, the first N-ion boundary implantation region is arranged at a position of the first intersection boundary formed by the intersection of the surface region of the first P-well and the surface region of the N-well, and the second N-ion boundary implantation region is arranged at a position of the second intersection boundary formed by the intersection of the surface region of the N-well and the surface region of the second P-well. The parasitic discharge circuit spans the first P-well, the N-well, and the second P-well, and is connected to the first ion implantation region and the second ion implantation region, respectively.

[0009] In an optional embodiment, the electrostatic discharge device further comprises a third ion implantation region arranged in a surface region of the N-well.

[0010] In an optional embodiment, a third intersection boundary is formed between the N-well and the surface of the P-type substrate, and the parasitic discharge circuit comprises a first parasitic discharge module, a second parasitic discharge module, and a third parasitic discharge module. The first parasitic discharge module is arranged in a region where the P-type substrate and the first P-well are located, and is connected to the first ion implantation region, the first intersection boundary, and the third intersection boundary, respectively. The second parasitic discharge module is arranged in a region where the P-type substrate and the second P-well are located, and is connected to the second ion implantation region, the second intersection boundary, and the third intersection boundary, respectively, and is further connected to the first parasitic discharge module. The third parasitic discharge module is arranged in a region where the N-well is located, and is connected to the third ion implantation region, the first intersection boundary, the second intersection boundary, and the third intersection boundary, respectively.

[0011] In an optional embodiment, the first parasitic discharge module comprises a first parasitic resistor and a first parasitic transistor. The base of the first parasitic transistor, the emitter of the first parasitic transistor, and one end of the first parasitic resistor are connected to the first ion implantation region, respectively. The collector of the first parasitic transistor is connected to the first intersection boundary, and the other end of the first parasitic resistor is connected to the third intersection boundary and the second parasitic discharge module. The first parasitic transistor is arranged in a region where the first P-well is located, and the first parasitic resistor is arranged in a region where the P-type substrate is located.

[0012] In an alternative embodiment, the first ion implantation region comprises a first N ion implantation region and a first P ion implantation region arranged in sequence from left to right, wherein the first N ion implantation region is connected to the emitter of the first parasitic transistor and one end of the first parasitic resistor, respectively, and the first P ion implantation region is connected to the base of the first parasitic transistor.

[0013] In an alternative embodiment, the second parasitic discharge module comprises a second parasitic resistor and a second parasitic transistor, wherein the base of the second parasitic transistor, the emitter of the second parasitic transistor, and one end of the second parasitic resistor are connected to the second ion implantation region, respectively, the collector of the second parasitic transistor is connected to the second intersection boundary, and the other end of the second parasitic resistor is connected to the third intersection boundary and the first parasitic discharge module; the second parasitic transistor is arranged in the region where the second P well is located, and the second parasitic resistor is arranged in the region where the P-type substrate is located.

[0014] In an alternative embodiment, the second ion implantation region comprises a second P ion implantation region and a second N ion implantation region arranged in sequence from left to right, wherein the second N ion implantation region is connected to the emitter of the second parasitic transistor and one end of the second parasitic resistor, respectively, and the second P ion implantation region is connected to the base of the second parasitic transistor.

[0015] In an alternative embodiment, the third parasitic discharge module comprises a third parasitic resistor, a third parasitic transistor, and a fourth parasitic transistor, wherein one end of the third parasitic resistor, the emitter of the third parasitic transistor, and the emitter of the fourth parasitic transistor are connected to the third ion implantation region, respectively; the other end of the third parasitic resistor is connected to the base of the third parasitic transistor, the base of the fourth parasitic transistor, the first intersection boundary, and the second intersection boundary, respectively, and the collector of the third parasitic transistor and the collector of the fourth parasitic transistor are connected to the third intersection boundary, respectively; the third parasitic resistor, the third parasitic transistor, and the fourth parasitic transistor are arranged in the region where the N well is located.

[0016] In an alternative embodiment, the third ion implantation region comprises a third P ion implantation region, a third N ion implantation region, and a fourth P ion implantation region arranged in sequence from left to right, wherein the third P ion implantation region is connected to the emitter of the third parasitic transistor, the third N ion implantation region is connected to one end of the third parasitic resistor, and the fourth P ion implantation region is connected to the emitter of the fourth parasitic transistor.

[0017] In an alternative embodiment, the ion concentration in the first intersection boundary, the second intersection boundary, and the third intersection boundary is obtained from the N ion concentration implanted from the first N ion boundary implantation region and the second N ion boundary implantation region and the ion doping in the N well region.

[0018] The electrostatic discharge device based on the PNPN structure provided by the embodiment of the present disclosure is arranged in sequence from left to right on the surface region of the P-type substrate, and the first P-well, the N-well and the second P-well are arranged in sequence from left to right on the surface region of the P-type substrate, the first intersection boundary is formed between the first P-well and the N-well, and the second intersection boundary is formed between the N-well and the second P-well; the first ion implantation region is arranged on the surface region of the first P-well, the second ion implantation region is arranged on the surface region of the second P-well, the first N ion boundary implantation region is arranged at the position of the first intersection boundary formed by the intersection of the surface region of the first P-well and the surface region of the N-well, and the second N ion boundary implantation region is arranged at the position of the second intersection boundary formed by the intersection of the surface region of the N-well and the surface region of the second P-well; the parasitic discharge circuit crosses the first P-well, the N-well and the second P-well, and the parasitic discharge circuit is connected to the first ion implantation region and the second ion implantation region, respectively. The present disclosure reduces the hysteresis voltage and improves the ESD performance through the high-concentration boundary.

[0019] In order to make the above-mentioned purpose, features and advantages of the present disclosure more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0021] FIG. 1 shows a structure schematic diagram of an electrostatic discharge device based on a PNPN structure according to an optional embodiment of the present disclosure;

[0022] FIG. 2 shows a structure schematic diagram of an electrostatic discharge device based on a PNPN structure according to an optional embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below in combination with the drawings in the embodiments of the present disclosure. It should be understood that the drawings in the present disclosure only serve the purpose of illustration and description, and should not be used to limit the protection scope of the present disclosure. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportion. The flowchart shows the operations implemented according to some embodiments of the present disclosure. It should be understood that the operations of the flowchart can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowchart or removed from the flowchart under the guidance of the present disclosure.

[0024] In addition, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments. The components of the embodiments of the present disclosure described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure.

[0025] The conventional method utilizes the structure of CMOS process parasitic PNPN to discharge ESD charge, but due to the high ESD device hysteresis voltage, before the ESD charge is completely discharged and the ESD device is turned on, the functional device is damaged by thermal breakdown, thereby reducing the ESD charge discharge capability and failing to improve the ESD protection capability.

[0026] Based on this, the embodiments of the present disclosure provide a static discharge device based on PNPN structure, which reduces the hysteresis voltage through high concentration boundary, improves the ESD performance, and specifically as follows:

[0027] Please refer to FIG. 1, which shows one of the structure schematic diagrams of a static discharge device based on PNPN structure provided by an optional embodiment of the present disclosure. As shown in FIG. 1, the static discharge device provided by the embodiments of the present disclosure includes a P-type substrate P-SUB, a first P-well PW1, an N-well NW, a second P-well PW2, a first ion implantation region 1, a second ion implantation region 2, a third ion implantation region 3, a first N-ion boundary implantation region A1, a second N-ion boundary implantation region A2, and a parasitic discharge circuit B.

[0028] In an optional implementation, the surface region of the P-type substrate P-SUB is sequentially provided with the first P-well PW1, the N-well NW, and the second P-well PW2 from left to right, the first P-well PW1 and the N-well NW form a first intersection boundary Junction1, and the N-well NW and the second P-well PW2 form a second intersection boundary Junction2. Specifically, the first P-well PW1 transitions to the N-well NW through the first intersection boundary Junction1, and the N-well NW transitions to the second P-well PW2 through the second intersection boundary Junction2.

[0029] The first ion implantation region 1 is arranged at a surface region of the first P-well PW1, the second ion implantation region 2 is arranged at a surface region of the second P-well PW2, the third ion implantation region 3 is arranged at a surface region of the N-well NW, the first N-ion junction implantation region A1 is arranged at a position where the first P-well PW1 surface region and the N-well NW surface region intersect to form a first junction Junction1, and the second N-ion junction implantation region A2 is arranged at a position where the N-well NW surface region and the second P-well PW2 surface region intersect to form a second junction Junction2.

[0030] The parasitic discharge circuit B is across the first P-well PW1, the N-well NW and the second P-well PW2, and is connected to the first ion implantation region 1 and the second ion implantation region 2, respectively.

[0031] Referring to FIG. 2, FIG. 2 shows a structure diagram of a PNPN structure electrostatic discharge device according to an optional embodiment of the present disclosure. As shown in FIG. 2, a third junction Junction3 is formed at a surface of the N-well NW and the P-type substrate P-SUB, and the parasitic discharge circuit B includes a first parasitic discharge module B1, a second parasitic discharge module B2 and a third parasitic discharge module B3.

[0032] In an optional implementation, the first parasitic discharge module B1 is arranged at a region where the P-type substrate P-SUB and the first P-well PW1 are located, and is connected to the first ion implantation region 1, the first junction Junction1 and the third junction Junction3, respectively.

[0033] The second parasitic discharge module B2 is arranged at a region where the P-type substrate P-SUB and the second P-well PW2 are located, and is connected to the second ion implantation region 2, the second junction Junction2 and the third junction Junction3, respectively, and is also connected to the first parasitic discharge module B1.

[0034] The third parasitic discharge module B3 is arranged at a region where the N-well NW is located, and is connected to the third ion implantation region 3, the first junction Junction1, the second junction Junction2 and the third junction Junction3, respectively.

[0035] In an alternative embodiment, the first parasitic bleed module B1 comprises a first parasitic resistor R1 and a first parasitic transistor Q1, the second parasitic bleed module B2 comprises a second parasitic resistor R2 and a second parasitic transistor Q2, the third parasitic bleed module B3 comprises a third parasitic resistor R3, a third parasitic transistor Q3 and a fourth parasitic transistor Q4, the first ion implant region 1 comprises a first N ion implant region 11 and a first P ion implant region 12 arranged in sequence from left to right, the second ion implant region 2 comprises a second P ion implant region 13 and a second N ion implant region 14 arranged in sequence from left to right, and the third ion implant region 3 comprises a third P ion implant region 15, a third N ion implant region 16 and a fourth P ion implant region 17 arranged in sequence from left to right.

[0036] In an alternative embodiment, the base of the first parasitic transistor Q1 is connected to the first P ion implant region 12, the emitter of the first parasitic transistor Q1 and one end of the first parasitic resistor R1 are respectively connected to the first N ion implant region 11, the collector of the first parasitic transistor Q1 is connected to the first junction boundary Junction 1, and the other end of the first parasitic resistor R1 is connected to the third junction boundary Junction 3 and the other end of the second parasitic resistor R2.

[0037] The first parasitic transistor Q1 is arranged in the region where the first P well PW1 is located, the first parasitic resistor R1 is arranged in the region where the P-type substrate P-SUB is located, and the first parasitic transistor Q1 and the second parasitic transistor Q2 are both NPN transistors.

[0038] The base of the second parasitic transistor Q2 is connected to the second P ion implant region 13, the emitter of the second parasitic transistor Q2 and one end of the second parasitic resistor R2 are respectively connected to the second N ion implant region 14, the collector of the second parasitic transistor Q2 is connected to the second junction boundary Junction 2, and the other end of the second parasitic resistor R2 is connected to the third junction boundary Junction 3 and the other end of the first parasitic resistor R1.

[0039] The second parasitic transistor Q2 is arranged in the region where the second P well PW2 is located, and the second parasitic resistor R2 is arranged in the region where the P-type substrate P-SUB is located.

[0040] One end of the third parasitic resistor R3 is connected to the third N ion implant region 16, the emitter of the third parasitic transistor Q3 is connected to the third P ion implant region 15, and the emitter of the fourth parasitic transistor Q4 is connected to the fourth P ion implant region.

[0041] The other end of the third parasitic resistance R3 is connected to the base of the third parasitic transistor Q3, the base of the fourth parasitic transistor Q4, the first junction boundary Junction1 and the second junction boundary Junction2, respectively, and the collector of the third parasitic transistor Q3 and the collector of the fourth parasitic transistor Q4 are connected to the third junction boundary Junction3, respectively.

[0042] The third parasitic resistance R3, the third parasitic transistor Q3 and the fourth parasitic transistor Q4 are arranged in the N-well NW region, wherein the third parasitic transistor Q3 and the fourth parasitic transistor Q4 are PNP transistors.

[0043] In the present disclosure, the collector of the first parasitic transistor Q1 is connected to the base of the third parasitic transistor Q3 through the transition of the first junction boundary Junction1, and the collector of the second parasitic transistor Q2 is connected to the base of the fourth parasitic transistor Q4 through the transition of the second junction boundary Junction2.

[0044] In an optional embodiment, the ion concentration in the first junction boundary, the second junction boundary and the third junction boundary is obtained by the N ion concentration injected from the first N ion boundary injection area and the second N ion boundary injection area and the ion doping in the N-well region. Specifically, the doping concentration between the N+ ions injected from the first N ion boundary injection area A1 and the second N ion boundary injection area A2 and the ions in the N-well NW is different in the process. The reverse breakdown voltage is closely related to the concentration in the process. The reverse breakdown voltage of the high concentration is lower than that of the low concentration. According to this principle and actual demand, the present disclosure adds the high concentration doping N+, PW and the junction boundary of NW in parallel through the first N ion boundary injection area A1 and the second N ion boundary injection area. The reverse breakdown voltage can be reduced to meet the actual demand.

[0045] In an optional embodiment, the first N ion injection area 11, the first P ion injection area 12, the third P ion injection area 15, the third N ion injection area 16 and the fourth P ion injection area 17 are connected to the VDD end (the internal working voltage end of the device), respectively, and the second P ion injection area 13 and the second N ion injection area 14 are connected to the VSS end (the internal ground end of the device), respectively.

[0046] In the present disclosure, β1 is the amplification of the third parasitic transistor Q3 and the fourth parasitic transistor Q4, β2 is the amplification of the first parasitic transistor Q1 and the second parasitic transistor Q2, and Ib2 is the corresponding reverse leakage current of the N-well NW, the first P-well PW1 and the second P-well PW2.

[0047] As the electrostatic discharge device provided in FIG. 2, when the ESD charge attacks, the first junction boundary Junction1 and the second junction boundary Junction2 bear the attacking ESD charge, and the reverse breakdown leakage Ib2 begins before the junction boundary between the P-well and the N-well provided in the corresponding scheme of the conventional electrostatic discharge device starts reverse breakdown leakage Ib2. Since the first parasitic resistance R1 is the terminal resistance between the base and the emitter of the first parasitic transistor Q1, and the second parasitic resistance R2 is the terminal resistance between the base and the emitter of the second parasitic transistor Q2, according to Ohm's law, the terminal voltage between the base and the emitter of the first parasitic transistor Q1 is Vbe2(B1) = Ib2 x R1, and the terminal voltage between the base and the emitter of the second parasitic transistor Q2 is Vbe2(B2) = Ib2 x R2.

[0048] When the voltage drop on Vbe2(B1) or Vbe2(B2) is greater than 0.7v, the emitter of the first parasitic transistor Q1 or the second parasitic transistor Q2 is forward biased, and the collector is reverse biased. The first parasitic transistor Q1 or the second parasitic transistor Q2 is in the triode amplification region, and the current Ic2 flowing through the first parasitic transistor Q1 or the second parasitic transistor Q2 is Ic2 = β2 x Ib2. Since this Ic2 current passes through the third parasitic resistance R3, which is also the terminal resistance between the base and the emitter of the third parasitic transistor Q3 or the fourth parasitic transistor Q4, the terminal voltage between the base and the emitter of the third parasitic transistor Q3 or the fourth parasitic transistor Q4 can also be obtained as Vbe1 = Ic2 x R3, which is equivalent to Ib2 as Vbe1 = β2 x Ib2 x R1. At this time, the emitter of the third parasitic transistor Q3 and the fourth parasitic transistor Q4 is forward biased, and the collector is reverse biased. The third parasitic transistor Q3 and the fourth parasitic transistor Q4 are in the triode amplification region, and Ic1 = β1 x β2 x Ib2. This cycle continues until the ESD charge is discharged, thereby achieving the protection purpose of the functional device.

[0049] The difference between the present disclosure and the conventional scheme provided by the related art is that a high-concentration junction boundary is added in parallel between VDD and VSS. The reverse breakdown voltage of this junction boundary is significantly lower than the reverse breakdown voltage of the P-well and the N-well itself. Due to the reduction of the reverse breakdown bias voltage (hysteresis voltage) between VDD and VSS, the electrostatic discharge device can start the related protection at a relatively low voltage, which significantly improves the product application and ESD performance.

[0050] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the foregoing method embodiment, and will not be repeated here. In several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, devices or units, and can be electrical, mechanical or other forms.

[0051] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0052] In addition, the functional units in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0053] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present disclosure or the parts that essentially contribute to the related art or the parts of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present disclosure. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, and various program code storage media.

[0054] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A static discharge device based on PNPN structure, comprising a P-type substrate, a first P-well, an N-well, a second P-well, a first ion implantation region, a first N-ion boundary implantation region, a second N-ion boundary implantation region, a second ion implantation region and a parasitic discharge circuit, wherein a first P-well, an N-well and a second P-well are sequentially arranged from left to right in a surface region of the P-type substrate, a first intersection boundary is formed between the first P-well and the N-well, and a second intersection boundary is formed between the N-well and the second P-well; the first ion implantation region is arranged in a surface region of the first P-well, the second ion implantation region is arranged in a surface region of the second P-well, the first N-ion boundary implantation region is arranged at a position of the first intersection boundary formed by the intersection of the surface region of the first P-well and the surface region of the N-well, and the second N-ion boundary implantation region is arranged at a position of the second intersection boundary formed by the intersection of the surface region of the N-well and the surface region of the second P-well; the parasitic discharge circuit is across the first P-well, the N-well and the second P-well, and the parasitic discharge circuit is connected to the first ion implantation region and the second ion implantation region, respectively; the static discharge device further comprises a third ion implantation region arranged in a surface region of the N-well; a third intersection boundary is formed between the N-well and the surface of the P-type substrate, and the parasitic discharge circuit comprises a first parasitic discharge module, a second parasitic discharge module and a third parasitic discharge module, wherein the first parasitic discharge module is arranged in a region where the P-type substrate and the first P-well are located, and the first parasitic discharge module is connected to the first ion implantation region, the first intersection boundary and the third intersection boundary, respectively; the second parasitic discharge module is arranged in a region where the P-type substrate and the second P-well are located, and the second parasitic discharge module is connected to the second ion implantation region, the second intersection boundary and the third intersection boundary, respectively, and the second parasitic discharge module is further connected to the first parasitic discharge module; the third parasitic discharge module is arranged in a region where the N-well is located, and the third parasitic discharge module is connected to the third ion implantation region, the first intersection boundary, the second intersection boundary and the third intersection boundary, respectively; ion concentration in the first intersection boundary, the second intersection boundary and the third intersection boundary is obtained by N-ion implanted from the first N-ion boundary implantation region and the second N-ion boundary implantation region and ion doping in the N-well region.

2. The electrostatic discharge device of claim 1, wherein, the first parasitic discharge module comprises a first parasitic resistor and a first parasitic transistor, wherein a base of the first parasitic transistor, an emitter of the first parasitic transistor and one end of the first parasitic resistor are connected to the first ion implantation region, respectively, a collector of the first parasitic transistor is connected to the first intersection boundary, and the other end of the first parasitic resistor is connected to the third intersection boundary and the second parasitic discharge module; the first parasitic transistor is arranged in the region where the first P-well is located, and the first parasitic resistor is arranged in the region where the P-type substrate is located.

3. The electrostatic discharge device of claim 2, wherein, the first ion implantation region comprises a first N-ion implantation region and a first P-ion implantation region arranged sequentially from left to right, The first N ion implantation region is connected to an emitter of the first parasitic transistor and one end of the first parasitic resistance.

4. The electrostatic discharge device of claim 1, wherein, The second parasitic discharge module comprises a second parasitic resistance and a second parasitic transistor, The base of the second parasitic transistor, the emitter of the second parasitic transistor and one end of the second parasitic resistance are connected to the second ion implantation region respectively, the collector of the second parasitic transistor is connected to the second intersection boundary, and the other end of the second parasitic resistance is connected to the third intersection boundary and the first parasitic discharge module. The second parasitic transistor is arranged in the region where the second P well is located, and the second parasitic resistance is arranged in the region where the P type substrate is located.

5. The electrostatic discharge device of claim 4, wherein, The second ion implantation region comprises a second P ion implantation region and a second N ion implantation region arranged in sequence from left to right, The second N ion implantation region is connected to an emitter of the second parasitic transistor and one end of the second parasitic resistance respectively, and the second P ion implantation region is connected to a base of the second parasitic transistor.

6. The electrostatic discharge device of claim 1, wherein, The third parasitic discharge module comprises a third parasitic resistance, a third parasitic transistor and a fourth parasitic transistor, One end of the third parasitic resistance, an emitter of the third parasitic transistor and an emitter of the fourth parasitic transistor are connected to the third ion implantation region respectively. The other end of the third parasitic resistance is connected to a base of the third parasitic transistor, a base of the fourth parasitic transistor, the first intersection boundary and the second intersection boundary respectively, and the collector of the third parasitic transistor and the collector of the fourth parasitic transistor are connected to the third intersection boundary respectively. The third parasitic resistance, the third parasitic transistor and the fourth parasitic transistor are arranged in the region where the N well is located.

7. The electrostatic discharge device of claim 6, wherein, The third ion implantation region comprises a third P ion implantation region, a third N ion implantation region and a fourth P ion implantation region arranged in sequence from left to right, The third P ion implantation region is connected to an emitter of the third parasitic transistor, the third N ion implantation region is connected to one end of the third parasitic resistance, and the fourth P ion implantation region is connected to an emitter of the fourth parasitic transistor.

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