Systems and methods for rapid matrix multiplications

Abstract

The present invention relates to a DRAM memory module (10, 100, 100A). The DRAM module comprises a plurality of memory cells (Mij, Miji, MAij) organized in rows and columns. Each memory cell comprises a capacitive element (Cij; CRLij), and a transistor (Tij, Tiji) connected to the capacitive element by means of a first conduction terminal. The transistor is connected to a wordline (WL, WLij) by means of a control terminal and to a bitline (BLj, BLij) by means of a second conduction terminal. The transistors of memory cells in a same row are connected to the same wordline and the transistors of memory cells in a same column are connected to the same bitline. The DRAM module also comprises a control circuitry (20, 30, 40) adapted to provide to, and acquire from, the plurality of cells a plurality of signals. Advantageously, the control circuitry controls the plurality of memory cells to process a matrix-matrix product directly in memory. The control circuitry imposes on wordline and bitline corresponding wordline signals and bitline signals. At least a portion of such wordline signals have an amplitude that is a function of a respective element of a first matrix. Similarly, the bitline signal comprises at least one pulse whose duration is a function of a respective element of a second matrix. The bitline and wordline signals determine a first current through at least one corresponding memory cell. The control circuitry activates a second predetermined current through each memory cell and determines a resulting value of the product between the elements of the first and second matrices as a function of corresponding discharge times required to discharge the capacitive elements of the memory cells from a stored charge value to a threshold charge value.

Description

[0001] SYSTEMS AND METHODS FOR RAPID MATRIX MULTIPLICATIONS

[0002] DESCRIPTION

[0003] TECHNICAL FIELD

[0004] The present invention relates to an analogue circuit for the calculation of matrixmatrix products. More particularly, the invention refers to a circuit and a method for direct in-memory processing (In-Memory Processing or In-Memory Computing) of matrix-matrix products.

[0005] STATE OF THE ART

[0006] In the last decade, artificial intelligence (Al) has witnessed a period of remarkable growth, with an increasingly significant impact on people's lives. In particular, the transformers are considered one of the most important deep learning models starting from 2018, as they represent the basis of large language models such as BERT and GPT.

[0007] The number of required parameters has increased exponentially, resulting in a huge demand for computing power, bandwidth and memory capacitance. This has highlighted the problem, known as the Memory Wall, plaguing traditional computing systems based on von Neumann architecture.

[0008] In-Memory Computing (IMC) tries to solve this limitation by exploiting the analogue and physical properties of the memories to perform calculations in the place where data are stored. Among the various applications, IMC has demonstrated the ability to accelerate Matrix -Matrix Multiplication (MMM), which is a crucial operation in deep learning.

[0009] Despite the progress made, to date in the state of the art there are no systems capable of processing MMM with a computational speed appropriate to the needs of the sector.

[0010] The need is therefore felt for new systems and methods for calculation.

[0011] OBJECTS AND SUMMARY OF THE INVENTION

[0012] An object of the present invention is to overcome the drawbacks of the prior art.

[0013] In particular, it is an object of the present invention to provide systems and methods capable of increasing the matrix-matrix multiplication operation. Preferably, the system is an in-memory computing system.

[0014] A further object of the present invention is to propose a system and a method for a rapid execution of matrix products particularly suitable for the implementation of matrix multiplications within the multi-head attention layer present in the architecture of a transformer.

[0015] These and other objects of the present invention are achieved by means of a system incorporating the features of the annexed claims, which form an integral part of the present description.

[0016] A first aspect of the present invention relates to a DRAM memory module. The DRAM module comprises a plurality of memory cells organized in rows and columns. Each memory cell comprises a capacitive element, and a transistor connected to the capacitive element by means of a first conduction terminal. The transistor is connected, as well, to a wordline by means of a control terminal and to a bitline by means of a second conduction terminal. The transistors of memory cells in a same row are connected to the same wordline and the transistors of memory cells in a same column are connected to the same bitline. The DRAM module also comprises a control circuitry adapted to provide to, and acquire from, the plurality of cells a plurality of signals.

[0017] Advantageously, the control circuitry controls the plurality of memory cells to process a matrix-matrix product directly in memory.

[0018] The control circuitry imposes on wordlines and bitlines corresponding wordline signals and bitline signals. At least a portion of such wordline signals have an amplitude that is a function of a respective element of a first matrix. Similarly, the bitline signal comprises at least one pulse whose duration is a function of a respective element of a second matrix. The bitline and wordline signals determine a first current through at least one corresponding memory cell.

[0019] The control circuitry activates a second predetermined current through each memory cell and determines a resulting value of the product between the elements of the first and second matrices as a function of corresponding discharge times required to discharge the capacitive elements of the memory cells from a stored charge value to a threshold charge value.

[0020] The DRAM module according to the present invention allows to perform product operations between two operands and, in particular, between matrix elements directly in memory in a quick and reliable manner.

[0021] In one embodiment, the plurality of cells is organized in a single structure of rows and columns. In this case, each wordline signal comprises a plurality of portions; each portion has an amplitude that is a function of a corresponding element of the first matrix belonging to a same row thereof. Furthermore, each bitline signal comprises a plurality of pulses; the duration of each pulse is a function of a corresponding element of the second matrix belonging to the same column thereof.

[0022] The wordline and bitline signals thus composed allow MAC operations and matrix product operations to be carried out in a quick and reliable manner with a limited number of memory cells. In particular, the overall time complexity of the matrix product is equal to O( / / ), where n is the number of pairs of vectors that make up the matrices to be multiplied.

[0023] In one embodiment, the plurality of memory cells is organized in a plurality of structures of rows and columns, to form a three-dimensional DRAM memory. In particular, groups of memory cells of different structures are aligned in lines orthogonal to the rows and columns. In addition, the memory cells of the same row are connected to the same readline.

[0024] Preferably, each wordline signal comprises a portion whose amplitude is a function of a corresponding element of the first matrix, and each bitline signal comprises a pulse whose duration is a function of a corresponding element of the second matrix. In this case, in which the control circuitry activates the second current on the memory cells by means of the readlines.

[0025] The DRAM module according to the invention is adapted to perform a matrix product operation extremely quickly. In fact, the overall time complexity of the matrix product is equal to 0(1).

[0026] In one embodiment, comprising a plurality of discharge transistors. Advantageously, each discharge transistor is connected to a respective readline and activated to activate the second current through the memory cells. In this case, the control circuitry comprises a counter that measures the discharge time interval.

[0027] In one embodiment, each memory cell comprises a read transistor connected to the capacitive element and the readline by means of respective conduction terminals and connected to a control line by means of a control terminal. In this case, the control circuitry sequentially: brings each bitline and readline to a supply voltage, while bringing the wordline and control line to a precharge voltage higher than the supply voltage; provides bitline and readline signals on each bitline and readline, brings the readline up to the supply voltage, and holds the control line at the precharge voltage; brings the bitline to the supply voltage, the readline to the precharge voltage, while bringing the wordline and the control line to a reference voltage; brings the bitline to a bias voltage, the readline is brought to a high impedance state, while bringing the wordline and control line to the precharge voltage, and the bitline is held at the bias voltage, the wordline and control line at the precharge voltage, while activating the second current through the readline.

[0028] The DRAM memory module according to the present invention has a compact structure and can be easily produced through integration techniques established in the art.

[0029] Alternatively, the transistor of each memory cell is connected to the respective readline by means of a conduction terminal thereof and wherein the capacitive element comprises a readline capacitance associated with the readline to which the transistor is connected.

[0030] In one embodiment, the DRAM module comprises a plurality of charging transistors, each of which is connected to a respective readline and is activated to activate the third current adapted to charge the readline capacitance to a predetermined value.

[0031] The DRAM memory module according to the present invention has a particularly compact structure, which allows to achieve a higher density of cells compared to other known structures and, at the same time, allows obtaining the result of matrix product with a particularly simple reading cycle.

[0032] In one embodiment, the control circuitry sequentially: brings the bitline to the supply voltage and the wordline to the reference voltage, and activates the third current by turning on the charging transistor; provides bitline and readline signals on each bitline and readline, thereby activating corresponding prime currents through each memory cell, and brings the bitline to the bias voltage and the wordline to the reference voltage, while activating the second current through the readline.

[0033] In one embodiment, the DRAM module comprises an integrated capacitor connected to each readline and sized to determine a predetermined total readline capacitance.

[0034] Thanks to the integrated capacitor it is possible to precisely control the capacitance value of the readline and, at the same time, reduce the construction requirements of the readline.

[0035] A different aspect of the present invention relates to a method of direct processing in an electronic memory, wherein the electronic memory is a dynamic random access memory (DRAM). The method comprises the following steps: imposing on each wordline a wordline signal comprising at least one portion whose amplitude is a function of an element of a first matrix; imposing on each bitline a bitline signal comprising a pulse, the duration of which is a function of an element of a second matrix, pairs of said signals determining a first current through corresponding memory cells; activating a second predetermined current through the memory cells; calculating a discharge time interval of each memory cell as the time required to discharge the capacitive element from a stored charge value to a threshold charge value, and determining a resulting value of the product between the elements of the first and second matrices as a function of the calculated discharge time.

[0036] The method according to the present invention allows to obtain the same advantages set forth above in relation to the DRAM memory module. Similarly, the method provides embodiments that mirror the embodiments of the memory module set forth above mutatis mutandis.

[0037] Further features and purposes of the present invention will become more evident from the description below.

[0038] BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The invention will be described below with reference to some examples, provided for explanatory and non-limiting purposes, and illustrated in the annexed drawings. These drawings illustrate different aspects and embodiments of the present invention and reference numerals illustrating structures, components, materials and / or similar elements in different figures are indicated by similar reference numerals, where appropriate.

[0040] Figure 1 is a block diagram illustrating the structure of a DRAM module;

[0041] Figure 2 is a circuit diagram of a DRAM memory cell;

[0042] Figure 3 is a circuit diagram of a matrix of DRAM memory cells;

[0043] Figure 4 is a flowchart of a multiplication process performed by DRAM memory cells according to an embodiment of the present invention;

[0044] Figure 5 is a flowchart of an MMM process performed by a DRAM module according to an embodiment of the invention;

[0045] Figure 6 is a graph of the trend of the signals and currents in the memory cells during the execution of an MMM;

[0046] Figure 7A is a graph of the trend of the voltages of the memory cells during the execution of an MMM;

[0047] Figure 7B is a graph comparing voltages obtained through simulation and ideal voltages;

[0048] Figure 8 is a circuit diagram of a three-dimensional DRAM according to an embodiment of the invention;

[0049] Figure 9 is a flowchart of an MMM process performed by the DRAM of Figure 8 according to an embodiment of the invention;

[0050] Figures 10A-10E are circuit diagrams of a memory cell of the DRAM of Figure 8 during respective steps of the process of Figure 9;

[0051] Figure 11 is a flowchart of a process of measurement of the discharge time of the memory cells executed by the process of Figure 9;

[0052] Figures 12A and 12B are graphs of the trend of the voltages of the cell and at the ends of the cell capacitive element, respectively, during the execution of the MMM according to the process of Figure 9;

[0053] Figure 13 is a graph comparing cell discharge times obtained through simulation and ideal voltages;

[0054] Figure 14 is a circuit diagram of a portion of a three-dimensional DRAM according to a further embodiment of the present invention;

[0055] Figure 15 is a flowchart of an MMM process performed by the DRAM of Figure 14 according to an embodiment of the invention;

[0056] Figures 16A-16C are circuit diagrams of a memory cell of the DRAM of Figure 14 during respective steps of the process of Figure 15;

[0057] Figure 17 is a graph of the trend of the cell voltages during the execution of the MMM according to the process of Figure 15;

[0058] Figure 18 is a graph comparing cell discharge times obtained through simulation and ideal voltages.

[0059] DETAILED DESCRIPTION OF THE INVENTION

[0060] Some preferred embodiments will be described in detail below, although the invention is susceptible to various alternative modifications. It must in any case be understood that there is no intention to limit the invention to the specific embodiment illustrated, but, on the contrary, the invention intends covering all the modifications, alternative and equivalent constructions that fall within the scope of the invention as defined in the claims.

[0061] Unless otherwise defined, all the terms of the art, notations and other scientific terms used herein are intended to have the meanings commonly understood by those skilled in the art to which this description belongs. In some instances, terms with commonly understood meanings are defined herein for clarity and / or ready reference; the inclusion of such definitions in the present disclosure is therefore not to be construed as representing a substantial difference from what is generally understood in the art.

[0062] The terms "comprising", "having", "including" and "containing" are to be understood as open terms (i.e. with the meaning "comprising, but not limited to") and are to be considered as a support also for terms such as "to consist essentially of", "consisting essentially of", "to consist of" or "consisting of".

[0063] The use of "for example", "etc.", "or" indicates non-exclusive alternatives without limitation, unless otherwise indicated. The use of "includes" means "includes, but not limited to" unless otherwise indicated.

[0064] With reference to the principle block diagram of Figure 1, a DRAM module 1 comprises a DRAM memory bank, or DRAM 10 for short, in case of a two- dimensional (2D) DRAM or a plurality of stacked DRAMs 10, in case of a three- dimensional (3D) DRAM. As is known, a DRAM 10 comprises a plurality of memory cells arranged in rows and columns, i.e. with a matrix structure. Furthermore, the DRAM module 1 comprises circuitries of access to the DRAM 10 such as, but not limited to, row decoders 20 and column decoders 30, possibly comprising amplifiers and / or comparators, connected to an input / output interface, or I / O interface 40, which is connected to a control element 50, which can be comprised in the DRAM module 10 or belong to a different electronic module (not illustrated). In embodiments of the present invention, the control element 50 sends to the I / O interface 40 data representing the elements of two matrices A and B to be multiplied with each other. The I / O interface 40 transmits such data to the row and column decoders 20 and 30 and receives in output a plurality of data corresponding to a product matrix C obtained by multiplication of A and B, as described below, which is transmitted to the control element 50.

[0065] With reference to Figure 2, a generic DRAM memory cell, for short "cell Mij" in the following, comprises an access transistor, preferably a transistor T like, an n- type MOSFET - connected to a wordline, or wordline WLj, through a gate terminal, and to a bitline, or bitline BLi, through a source terminal. Finally, the transistor T is connected to a capacitive element, for example capacitor C, through a drain terminal. The capacitor C is connected to a reference terminal of the cell Mij - for example, a ground plane - through a corresponding terminal, opposite the terminal connected to the transistor T.

[0066] The two-dimensional DRAM 10, schematically illustrated in Figure 3, comprises a plurality of cells Mij arranged in J rows and columns I in a matrix configuration. In the example in Figure 3, the DRAM 10 comprises nine cells M11-M33 in a configuration corresponding to a 3 x 3 matrix. The cells M11-M13, M21-M23, and M31-M33 on the same row of the matrix are connected to the same wordline WLi, WL2, and WL3, respectively. Similarly, the cells M11-M31, M12-M32, and M13-M33 on a same column of the matrix are connected to the same wordline BLi, BL2, and BL3 / respectively. As known and not described in greater detail herein for brevity, the DRAM 10 further comprises read circuitry of the cells and ancillary circuitry (power circuits, 1 / O circuits, etc.) required for operation of the DRAM 10.

[0067] In one embodiment of the present invention a generic cell Mij of the DRAM 10 is used as a Multiply-and Accumulate (MAC) unit. For this purpose, the DRAM 1 is adapted to perform a multiplication process 1000, of which Figure 4 is a flowchart, providing two signals to the wordline WL and to the bitline BL which are connected to the cell Mi,:

[0068] 1. an analogue voltage Swi(t) on WLi (step 1001), and

[0069] 2. a time-controlled digital pulse SBj(t) on the BL, (step 1002).

[0070] Preferably, as illustrated in Figure 2, the analogue voltage Swi(t) is a rectangular signal having a programmable amplitude ranging between a minimum value and a selected multiplicand value in a predetermined value interval. In contrast, the digital pulse SBj(t) is a rectangular signal having a programmable width, i.e. duration, ranging from a maximum value to a minimum value for a time interval comprised in a predetermined interval of values.

[0071] As a result, a current Ik(t) flows through the transistor T. The current Ik(t) has an intensity Ik determined by the analogue voltage Swi(t) and a duration equal to a time interval tk determined by the digital pulse SBj(t).

[0072] Therefore, a charge Qk is extracted from the generic cell Mij:

[0073] Qk = Ik • tk. (1)

[0074] In particular, the extracted charge Qk depends on the product between the current intensity Ik and the time interval tk, in turn depending on the analogue voltage Swi(t) and the digital pulse SBj(t). In other words, through the process 1000 it is possible to extract a charge Qk indicative of the result of a product between a first value (multiplicand) defined by the current intensity Ik and a second value (multiplier) from the time interval tk.

[0075] By iterating the process 1000, i.e. by sending k pairs of analogue voltage Swi(t) and digital pulse SBj(t) signals, the total charge Qki extracted corresponds to the sum of the charge Qk removed from the capacitor C at every k-th iteration of the process 1000. This is equivalent to a MAC operation between a vector a of multiplicands ak and a vector b of multipliers bk.

[0076] Considering the DRAM 10, according to the present invention, a matrix -matrix multiplication (MMM) process 2000 is performed, of which Figure 5 is a flowchart. In particular, the product between a first 3 x 3 matrix A and a second 3 x 3 matrix B is considered.

[0077] Initially, the cells Mu-33 are pre-charged to a reference charge value Qo (step 2001). The matrix A is divided into three vectors (column) ak (k integer, k = [1.3]). Each of which is converted into a corresponding analogue voltage vector Swk(t) (step 2002) which in turn is propagated on a corresponding wordline WL1-3 (step 2003). Preferably in parallel, the matrix B is divided into three vectors (row) bk each of which is converted into a corresponding digital pulse vector SBk(t) (step 2004) which, in turn, is propagated on a corresponding bitline BL1-3 (step 2005). The digital pulses SBk(t) and the analogue voltages Swk(t) are propagated substantially synchronously.

[0078] Consequently, taking as reference the cell Mij located on the i-th WL and j-th BL, each pair of digital pulse SBkj(t) - analogue voltage Swki(t), for short pair SBkj(t)- Swki(t), defines a current Ikij(t), which partially discharges the capacitor CSN of the cell Mij. Similarly to what is described above, whenever a new pair of vectors ak and bk is provided, an external product of charges Qkis calculated and subtracted from the corresponding cell Mu-33.

[0079] In other words, a resulting charge matrix Q is obtained:

[0080] Q = QoJ - 2 i ik ® t£, (2) where J is an offset matrix, Ik is a current intensity vector which is a function of the elements of the vector ak, tk is a duration vector which is a function of the elements of the vector bk, and n is the number of pairs of vectors ak and bk - n =3 in the example of Figure 2. Equation (2) is, net of an offset term QoJ, an electrical equivalent of the product between matrices A and B:

[0081] Accordingly, the matrix-matrix product (MMM) just described requires n iterations, where it calculates the matrix-matrix products and the accumulation of those products.

[0082] In one embodiment, the cells comprise a 16 nm low-power transistor, with a minimum width of 48 nm and supply voltage VDD = 0.9 V. In addition, the capacitor C has a cell capacitance CSN = 10 fF and the bitlines BL1-3 have a line capacitance CBL = 100 fF. The Applicant has determined that by increasing a length of the transistors by around L = 64 nm it is possible to eliminate or, at least, attenuate, the dependence of the discharge current Ik on a charge voltage VSN at the ends of the capacitor C, caused by short channel effects.

[0083] Furthermore, the Applicant has determined that it is possible to avoid reaching the ohmic regime of the transistor T by reducing an output voltage interval between 0.35 V and 0.9 V (inclusive).

[0084] Considering a DRAM 10 with size 8 x 8 (not illustrated), the analogue voltages Swk(t) and the digital pulses SBk(t), corresponding to the vectors ak and bk, are mapped into 8 levels. Under these conditions, in order to obtain 60 accumulations considering the cell capacitance CSN substantially equal to 10 fF, the output voltage interval [0.35 V, 0.9 V] and a maximum duration of the digital pulses SBk(t) of 1 ns, the transistor T must operate in sub-threshold mode with currents comprised between 0 nA and about 100 nA (inclusive).

[0085] Figure 6 shows the digital pulse SBj(t) - analogue voltage Swi(t) signals sent to a cell Mi, of the DRAM 10, and the waveform of the discharge current lij(t) whose integration allows determining the extracted charge.

[0086] At the end of the MAC processes, the voltages stored in the cells, which are a function of the residual charge in the capacitor C, are read by means of a Charge Sharing (CS) process with the bitline capacitance CBL (not illustrated) of the bitline BL1-3 connected to the cell Mu-33. For short, the bitline BL1-3 is pre-charged to a value equal to half the supply voltage, i.e. VDD / 2, and left floating before activating the corresponding access transistor, bringing the wordline WL1-3 to a power value VDD. The final voltage Vcs of a generic cell Mu-33 is given by:

[0087] \ T _CSNVSN+ CBLVDD / 2vcs —

[0088] L77 • SN+ LU BL

[0089] The final voltages Vcs of the cells Mu-33 are read in sequence row by row. Consequently, considering both the calculation process and the process of reading the results of the MAC operations, the overall time complexity is equal to O( / / ).

[0090] Figure 7A shows the transient of the cell voltages VSN at the terminals of each capacitor C of the cells M a DRAM 10 with size 4 x 4 (not illustrated), configured to perform 60 MAC for each cell Mij. Figure 7B is a correlation graph of 64 output values between the final voltages Vcs read after the CS and an ideal value for an 8 x 8 DRAM (not illustrated). The Applicant has determined that it is possible to attenuate or at least eliminate the offset caused by charge injection effects and the difference in slope caused by short channel effects. In particular, such non-idealities are removed by detecting and eliminating a voltage variation by means of a differential reading scheme with a comparison with dummy cells, thereby reducing systematic errors. In this case, the voltage variation AVSN detected is: which, in the example considered above, corresponds to a wide interval of about 50 mV.

[0091] In one embodiment, it provides a three-dimensional (3D) type DRAM, or DRAM 100, as schematically illustrated in Figure 8 where different graphic lines (solid, dotted and dot-line) are used to represent different signal lines (wordline and bitline) or groups of cells M arranged on a same direction (e.g., R box) oriented substantially orthogonal to each other - e.g., according to a triplet of axes x, y and z. In brief, the DRAM 100 comprises a plurality of cells matrices, each substantially corresponding to a DRAM 10, described above. In the example considered, the DRAM 100 substantially comprises three DRAMs 10, i.e. three matrices, or arrays, of cells M with size 3 x 3. In other words, the DRAM 100 has a structure n x n x n, with n = 3 in the example considered and, therefore, comprises3(27) cells Miji. Accordingly, the DRAM 100 comprises / / 2(9 in the example considered) wordlines WLu-33 (generally indicated with WLij) and bitlines BLn-33 (generally indicated with BLij), connected to respective groups of cells Miji aligned along rows and columns, respectively, in a manner similar to that described above.

[0092] Preferably, though not in a limiting manner, each cell Miji of the DRAM 100 comprises a 2T1C structure (as shown in the examples of Figures 10A-10E), i.e. two transistors, a capacitor, as illustrated in detail in Figure 10B. In brief the generic cell Miji of the DRAM 100 comprises a transistor T±ji connected to a bitline BLij, to a wordline WLij and to a capacitive element, the capacitor Gji, in a manner similar to that described above for the cells of the DRAM 10. Furthermore, the cell Miji of the DRAM 100 comprises a second transistor TR^ - for example an n- type MOSFET - connected to the terminal of the capacitor Gji, opposite to the terminal connected to the transistor Tiji, through a drain terminal. Furthermore, the second transistor TRiji is connected to a control line, or control line CLij through a gate terminal and to a readline, or readline RLij, through a respective source channel. In particular, a respective readline RLij connects the source terminals of the second transistors TR^R, of different matrices of the DRAM 100, aligned along a same direction parallel to the axis z (as illustrated in the box of Figure 8). In addition, a plurality of discharge transistors, or transistor Tpdij - for example an n-type MOSFET - is provided each connected to a respective readline RLij through a drain terminal, while a source terminal receives the reference voltage GND. Finally, the gate terminal of the transistor Tpdij receives a discharge signal - which switches from the reference value GND to the supply value GND to activate the transistor Tpdij (as illustrated in Figure 10E). A read circuitry is connected to the readlines RLij of the DRAM 100, the operation of which is described below in relation to Figures 9, 10A-10E and 11.

[0093] The DRAM 100 according to the present invention is adapted to operate according to the procedure 3000 of which Figure 9 is a flowchart. In brief, unlike the two-dimensional (2D) DRAM 10, in the DRAM 100 all external products can be generated in a single step using multiple cell matrices at the same time. The matrices must be summed to obtain an output matrix comprising the results of the MMM operation. In the DRAM 100 according to the present invention, the accumulation of the products, i.e. their sum is obtained by connecting memory cells belonging to different DRAMs 10, but aligned along the direction z transverse to the directions x and y along which wordlines WL11-33 and bitlines BL11 -33 of the DRAM 100 are aligned, exploiting the stacking of the matrices of cells M - i.e. of the 2D DRAMs 10 included in the 3D DRAM 100. The overall time complexity associated with the operation of the DRAM 100 is equal to 0(1).

[0094] The procedure 3000 of writing and reading the DRAM 100 is described in greater detail below with reference to Figure 9 and Figures 10A-10E.

[0095] In writing, the generic cell Mij of the 3D DRAM 100 is initialized (step 3001, Figure 10A). In particular, the bitline BL and the readline RL are brought to the supply voltage VDD. Conversely, the wordline WL and the control line CL are brought to a precharge voltage Vpp (preferably, Vpp > VDD) and the capacitor C is discharged.

[0096] Next, a multiplication process 1000 is performed (step 3002, Figure 10B). In particular, a pair of digital pulse SBjk(t) - analogue voltage Swik(t) - function of corresponding elements bkj and aik of the matrices A and B to be multiplied - is provided on the bitlines BL and wordline WL, so as to activate a current discharge current ljk(t) function of the analogue voltage Swik(t) and of the digital pulse SBjk(t), respectively. During the process 1000 the readline RL is held at the supply voltage VDD and the control line CL is held at the precharge voltage Vpp.

[0097] After multiplication, a precharge of the cell is performed (step 3003, Figure 10C). In detail, the bitline BL is brought to the supply voltage VDD, the readline RL is brought to a precharge voltage Vpre. Otherwise, the wordline WL and the control line CL are brought to the reference voltage VGND thereby turning off the transistors T and TR, keeping the charge Qkj accumulated on the capacitor C.

[0098] Next, an accumulation step is performed, i.e. a CS phase between the cells connected to the same RL readline (step 3004, Figure 10D). In particular, the bitline BL is brought to a bias voltage Vbias, the readline RL is brought to a floating state FLT, i.e. of high impedance. Conversely, the wordline WL and the control line CL are brought to the precharge voltage Vpp thereby allowing a sharing current flow in the cell. At the end of the CS, a sum voltage Vij is obtained: where CRL is the parasitic capacitance associated with the RL readline - for example, CRL = 200 fF. Advantageously, the value interval of the sum voltage Vij is controllable by adjusting the values of the precharge voltage Vpreand the bias voltage Vbias.

[0099] Finally, the result of the MAC operation is read (step 3005, Figure 10E). In detail, with reference to the flowchart of Figure 11, the bitline BLij is held at the bias voltage Vbias, and the wordline WLij and the control line CLij are held at the precharge voltage, while the readline RLij is connected to the reference terminal by activating a discharge transistor, a transistor Tpdij - for example a P-type MOSFET (step 30051). As a result, the cell Miji is discharged with a constant discharge current Idis, thereby progressively reducing the sum voltage Vij. Upon activation of the transistor Tpdij a counter is started (step 30052) - for example, by means of the same activation signal of the transistor Tpdij. The sum voltage Vij is compared with a predetermined threshold value (decision step 30053 and branch N thereof). When the sum voltage Vij reaches the threshold value (output branch Y thereof), the counter is stopped (step 30054) - for example, a voltage comparator generates a counter stop signal when the sum voltage Vij reaches the threshold value. The result of the counting carried out by the counter represents, that is, it is a function depending on, a corresponding element of the product matrix to be calculated.

[0100] Figures 12A and 12B are graphs of the trend of the voltages of cell and at the terminals of the capacitors, respectively, during the execution of the MMM according to the process 3000.

[0101] Advantageously, since each cell Miji must carry out a single multiplication, the transistor can be driven so as to operate with a high voltage current, for example in the order of A considering the numerical parameters reported above.

[0102] This significantly slacken the precision in the voltage levels used with respect to the known solutions, as can be seen in Figure 13, which is a graph showing the results of a simulation of a DRAM 100 that compares the times measured by the DRAM 100 with ideal resulting times considering a variability of the threshold voltages of the transistors equal to about 10 mV (i.e., o(Vth) = 10 mV) and a variability of the capacitance of the capacitors C equal to 10% (i.e., O(ACSN / ACSN) = 10%).

[0103] In a further embodiment, a 3D DRAM 100A, a portion of which is schematically illustrated in Figure 14, differs from the DRAM 100 in the following. The cells MALJI of the DRAM 100A do not comprise a capacitor C, and no read transistor TR is provided. In contrast, the source terminal of the transistor T±j is directly connected to the respective readline RLij. In addition, a plurality of charge transistors Tppij is provided in Figure 14 - for example, p-type Mosfet. Each transistor Tppij which is connected to the readline RL by means of a source terminal and receives the supply voltage VDD at a drain terminal. Finally, the gate terminal receives an initialization signal - which switches from the supply value VDD to the reference value GND to activate the transistor Tppij. Similar to the DRAM 100, the DRAM 100A provides a plurality of discharge transistors, or transistor Tpdij connected to the readline RL,j in a manner similar to that described above and not repeated here for brevity.

[0104] The DRAM 100A performs a multiplication procedure 4000, of which Figure 15 is a flowchart, adapted to perform an MMM operation in which the multiplication and accumulation operations are performed simultaneously - that is, the MAC operations are performed in a single step. In particular, the procedure 4000 comprises carrying out the procedure 1000 on each cell so as to obtain on each readline RL the sum of the effects of the discharge currents Ljk(t) generated by the cells Mazz connected to said readline RL. At the end of the discharge, a resulting charge Qijk present on the capacitance of the readline CRLIJ will be a function of the product of corresponding elements aik and bq of the matrices A and B to be multiplied used to define pairs SBjk(t)-Swik(t) used to activate respective discharge currents ljk(t).

[0105] In detail, with reference also to Figures 16A-16C, the procedure 4000 comprises an initialization step (step 4001, Figure 16A). In detail, the bitline BL is brought to the supply voltage VDD and the wordline WL is brought to the reference voltage GND. In addition, the initialization signal is switched to the reference voltage GND, thereby activating the initialization FET Tppij. As a result, the readline capacitance CRL of the readline RL is pre-charged with an initial charge qo. Next, the procedure 1000 is performed in parallel on the cells MA of the DRAM 100A (step 4002, Figure 16B). In particular, a pair of digital pulses - analogue voltage - function of corresponding elements bq and a* of the matrices A and B to be multiplied - is provided on the bitlines BL and wordlines WL, so as to activate a discharge current Ljk(t). The discharge currents I.jk(t) generated by the cells MA connected to the same readline RL extract charge from the readline capacitance CRL of the readline RL.

[0106] Finally, the result of the MAC operation is read (step 4003, Figure 16C). In particular, the bitline BL is brought to the bias voltage VDD, the wordline WL is brought to the reference voltage GND, while the readline RL is connected to the reference terminal by activating the transistor Tpdij. As a result, the readline capacitance CRL is discharged with a constant discharge current lais, thereby progressively reducing the corresponding sum voltage Vij. Similarly to what is described above in relation to Figure 11, upon activation of the transistor Tpdij a counter is started - for example, by means of the same activation signal of the transistor Tpdij. In addition, the sum voltage Vij is compared with the predetermined threshold value, and when the sum voltage Vij reaches the threshold value, the counter is stopped. The result of the counting carried out by the counter represents, that is, it is a function depending on, a corresponding element of the product matrix to be calculated.

[0107] In an alternative embodiment, the transistor Tpdij is not provided but the discharge of the readline capacitance CRL is discharged by suitably driving one or more transistors Tqi of the cells MA connected to the same readline RLij without requiring substantial changes to the discharge time measurement.

[0108] The Applicant has determined that, thanks to the extremely simple structure of the cells MAIJ, it is possible to increase the length of the channel, for example up to 128 nm considering the numerical parameters reported above. Alternatively or in addition, the maximum current variation during the MAC operation is limited to 0.45 V to prevent the transistors Tqi from operating in the ohmic region and, at the same time, to ensure a residual dynamic margin during the next reading step (i.e., the constant current discharge lais of the readline capacitance CRLij).

[0109] The Applicant has determined that the optimal size of the readline capacitance CRLij depends on the number of memory cells connected to the readline RLij. For example, considering the numerical parameters above, the capacitance value for each cell MAIJI that performs charge sharing on the same readline RLij is CRL^ — 5.68 fF / cell. In other words, in a DRAM 100A 8x8x8, eight cells Maiji are connected to each RL readline, therefore, a readline capacitance CRLIJ about equal to 45.6 fF is required. Optionally, for example in order to slacken the requirements on the readline RLij, it is provided to connect a compensation capacitive element (not illustrated), for example an integrated capacitor connected to the readline RLij and to the reference terminal. In this case, the integrated capacitor will be sized so that the combination of its capacitance and the readline capacitance CRLij substantially equals the desired capacitance value for the readline RLij.

[0110] Figure 17 is a graph of a simulation of the trend of the readline voltages VRL as a function of time, during an operation of a DRAM 100A 8x8x8 according to an embodiment of the present invention. Furthermore, it is possible to implement a digital post-processing of the measured results - comprising the application of offset and scale values determined with a calibration process of the DRAM 100A - it allows to compensate for the variability in the discharges of the transistors of the cells MA due to non-idealities. Figure 18 is a graph comparing the times measured by the DRAM 100A with normalized ideal results, considering a variability of the threshold voltages of the transistors equal to about 20 mV (i.e., o(V th) = 20 mV) and a variability of the capacitance of the capacitors C equal to 10% (i.e., O(ACSN / ACSN) = 10%).

[0111] However, it is clear that the above examples must not be interpreted in a limiting sense and the invention thus conceived is susceptible of numerous modifications and variations.

[0112] For example, the transistors can belong to types different from the MOSFET type considered above. In other embodiments, the transistors may be of the finFET type or fully-depleted silicon-on-insulators (FD-SOIs), or gate-all-around fieldeffect transistors (GA A FETs), or thin-film transistors (TFTs).

[0113] As will be apparent to the person skilled in the art, one or more steps of the procedures described above can be performed in parallel with each other - for example, on different memory banks of a memory board - or in a different order from that presented above. Similarly, one or more optional steps may be added or removed from one or more of the above described procedures.

[0114] Naturally, all the details can be replaced with other technically-equivalent elements.

[0115] In conclusion, the materials used (e.g., silicon, heterojunction semiconductors, via metals, etc.), as well as the shapes and contingent dimensions of the devices, modules and components mentioned above may be any according to the specific implementation needs without departing from the scope of protection of the following claims.

Claims

CLAIMS1. DRAM memory module (10, 100, 100A) comprising: a plurality of memory cells (Mij, Miji, M Aij) organized in rows and columns, each memory cell comprising a capacitive element (Cij; CRLIJ), and a transistor (Tij, Ti ) connected to the capacitive element by means of a first conduction terminal, where the transistor is connected to a wordline (WL, WLij) by means of a control terminal and to a bitline (BLj, BLij) by means of a second conduction terminal, the transistors of memory cells in a same row being connected to a same wordline and the transistors of memory cells in a same column being connected to a same bitline, and a control circuitry (20, 30, 40) adapted to provide to, and acquire from, the plurality of cells a plurality of signals, characterized by the fact thatThe control circuitry controls the plurality of memory cells to process a matrixmatrix product directly in memory by: imposing on each wordline a corresponding wordline signal with at least one portion whose amplitude is a function of a respective element of a first matrix; imposing on each bitline a corresponding bitline signal comprising at least one pulse whose duration is a function of a respective element of a second matrix, said bitline and wordline voltages determining a first current through at least one corresponding memory cell, and activating a second predetermined current through each memory cell; calculating a discharge time interval of each capacitive element as the time required to discharge the capacitive element from a stored charge value to a threshold charge value, and determining a resulting value of the product between the elements of the first and second matrices as a function of each calculated discharge time.

2. A DRAM memory module (10, 100, 100A) according to claim 1, wherein the plurality of cells is arranged in a single structure of rows and columns, and wherein each wordline signal comprises a plurality of portions, where each portion has an amplitude that is a function of a corresponding element of the first matrix belonging to the same row thereof, and wherein each bit line signal comprises a plurality of pulses, where the duration of each pulse is a function of a corresponding element of the second matrix belonging to the same column thereof.

3. A DRAM memory module (10, 100, 100A) according to claim 1, wherein the plurality of memory cells is organized in a plurality of structures of rows andcolumns, wherein groups of memory cells of different structures are aligned in lines orthogonal to the rows and columns, and wherein the memory cells of the same line are connected to the same readline (RLij), and wherein each wordline signal comprises a portion whose amplitude is a function of a corresponding element of the first matrix, and where each bit line signal comprises a pulse whose duration is a function of a corresponding element of the second matrix, and wherein the control circuitry activates the second current through the memory cells by means of the readlines.

4. A DRAM memory module (10, 100, 100A) according to claim 3, comprising a plurality of discharge transistors (Tpdij), each of which is connected to a respective readline and activated to activate the second current through the memory cells, and wherein the control circuitry comprises a counter that measures the discharge time interval.

5. A DRAM memory module (10, 100, 100A) according to claim 3 or 4, wherein each memory cell comprises a read transistor (TR^I) connected to the capacitive element and the readline by means of respective conduction terminals and connected to a control line (CLij) by means of a control terminal, and wherein the control circuitry sequentially: brings each bitline and readline to a supply voltage, while bringing the wordline and control line to a precharge voltage higher than the supply voltage; provides bitline and readline signals on each bitline and readline, brings the readline up to the supply voltage, and holds the control line at the precharge voltage; brings the bitline to the supply voltage, the readline to the precharge voltage, while bringing the wordline and the control line to a reference voltage; brings the bitline to a bias voltage, the readline is brought to a high impedance state, while bringing the wordline and control line to the precharge voltage, and keeps the bitline held at the bias voltage, the wordline and control line at the precharge voltage, while activating the second current through the readline.

6. A DRAM memory module (10, 100, 100A) according to claim 3 or 4, wherein the transistor of each memory cell is connected to the respective readline by means of a conduction terminal thereof and wherein the capacitive element comprises a readline capacitance associated with the readline to which the transistor is connected.

7. A DRAM memory module (10, 100, 100A) according to claim 6,comprising a plurality of charging transistors (Tppij), each of which is connected to a respective readline and is activated to activate the third current adapted to charge the readline capacitance to a predetermined value.

8. A DRAM memory module (10, 100, 100A) according to claim 7, wherein the control circuitry sequentially: brings the bitline to the supply voltage and the wordline to the reference voltage, and activates the third current by turning on the charging transistor; provides bitline and readline signals on each bitline and readline, thereby activating corresponding prime currents through each memory cell, and brings the bitline to the bias voltage and the wordline to the reference voltage, while activating the second current through the readline.

9. A DRAM memory module (10, 100, 100A) according to any of the preceding claims 3 to 8, comprising an integrated capacitor connected to each readline and sized to determine a predetermined total readline capacitance.

10. A method (1000-4000) of directly processing in an electronic memory, wherein the electronic memory is a dynamic random access memory (DRAM), the method comprising the steps of: imposing (1001; 2002, 2003; 3002-3004; 4002) on each wordline a wordline signal comprising at least one portion whose amplitude is a function of an element of a first matrix; imposing (1002; 2004, 2005; 3002-3004; 4002) on each bitline a bitline signal comprising a pulse, the duration of which is a function of an element of a second matrix, pairs of said signals determining a first current through corresponding memory cells; activating (3005; 4003) a second predetermined current through the memory cells; calculating (3005; 4003) a discharge time interval of each memory cell as the time required to discharge the capacitive element from a stored charge value to a threshold charge value, and determine (3005; 4003) a resulting value of the product between the elements of the first and second matrices as a function of the calculated discharge time.

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