Apparatus and method for encoding and decoding a channel in a communication or broadcasting system

Abstract

The present invention relates to a 5G or pre-5G communication system supporting a higher data transmission rate after a 4G communication system such as LTE. The present invention relates to a method and apparatus for encoding a channel in a communication or broadcasting system supporting a parity check matrix having various sizes. The method for encoding a channel includes determining a block size of a parity check matrix, reading a sequence for generating the parity check matrix, and transforming the sequence by applying previously defined operations to the sequence based on the determined block size.

Description

Technical Field

[0001] This disclosure relates to apparatus and methods for encoding and decoding channels in communication or broadcasting systems. Background Technology

[0002] To meet the increased demand for wireless data services since the commercialization of fourth-generation (4G) communication systems, efforts have been made to develop advanced fifth-generation (5G) or pre-5G communication systems. Therefore, 5G or pre-5G communication systems are also referred to as "beyond 4G networks" or "post-Long Term Evolution (LTE) systems".

[0003] To achieve higher data rates, 5G communication systems are considered for implementation in higher frequency (millimeter wave) bands (e.g., the 60 GHz band). To reduce radio wave propagation loss and increase transmission distance, beamforming, massive MIMO, full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, and massive MIMO technologies are discussed in the context of 5G communication systems.

[0004] In addition, in 5G communication systems, improvements to the system network are being developed based on advanced small cells, cloud radio access networks (RAN), ultra-dense networks, device-to-device (D2D) communication, wireless backhaul, mobile networks, cooperative communication, coordinated multipoint (CoMP), and receiver interference cancellation.

[0005] In 5G systems, hybrid frequency shift keying (FSK) and quadrature amplitude modulation (QAM) modulation (FQAM) and sliding window superposition coding (SWSC) have been developed as advanced coding and modulation (ACM), as well as filter bank multicarrier (FBMC), non-orthogonal multiple access (NOMA) and sparse code multiple access (SCMA) as advanced access technologies.

[0006] In communication / broadcasting systems, link performance can be significantly degraded due to various types of channel noise, fading, and inter-symbol interference (ISI). Therefore, to achieve high-speed digital communication / broadcasting systems requiring high data throughput and reliability (such as next-generation mobile communications, digital broadcasting, and portable internet), it is necessary to develop technologies to overcome noise, fading, and ISI. As part of research into overcoming noise, etc., recent research has focused on error-correcting codes, which improve communication reliability by effectively recovering distorted information.

[0007] The above information is presented as background information only to aid in understanding this disclosure. No decision has been made, nor any assertion has been asserted, regarding whether any of the above content can be used as prior art with respect to this disclosure. Summary of the Invention

[0008] [Technical Issues]

[0009] This disclosure relates to methods and apparatus for providing low-density parity-check (LDPC) encoding / decoding capable of supporting various input lengths and coding rates. Furthermore, the object of this disclosure is to provide methods and apparatus for providing LDPC encoding / decoding capable of supporting various codeword lengths derived from a designed parity-check matrix.

[0010] [Solutions to the problem]

[0011] The aspects of this disclosure will at least address the aforementioned problems and / or disadvantages, and will at least provide the advantages described below. Therefore, the aspects of this disclosure relate to providing methods and apparatus for low-density parity-check (LDPC) encoding / decoding capable of supporting various input lengths and code rates. Furthermore, the object of this disclosure is to provide methods and apparatus for LDPC encoding / decoding capable of supporting various codeword lengths from a designed parity-check matrix.

[0012] Another aspect of this disclosure provides a method for encoding a channel, the method comprising: determining a block size for a parity check matrix; reading a sequence for generating the parity check matrix; transforming the sequence based on the determined block size; and generating parity bits for information bits based on the transformed sequence.

[0013] Another aspect of this disclosure provides a method for encoding a channel, the method comprising: identifying the size of input bits; determining the number of code blocks based on the size of the input bits and the maximum number of information bits corresponding to a maximum parity check matrix; determining the size of the code blocks; determining the number of padding bits based on the size of the code blocks; determining the code blocks by applying padding according to the determined number of padding bits; determining a parity check matrix based on the size of the code blocks; and encoding the code blocks based on the parity check matrix.

[0014] Another aspect of this disclosure provides a method for decoding a channel, the method comprising: determining the size of input bits from a received signal prior to segmentation; determining the number of code blocks based on the size of the input bits and the maximum number of information bits corresponding to a maximum parity check matrix; determining the size of the code blocks; determining the number of padding bits based on at least one of the code block sizes; applying padding according to the determined number of padding bits to determine the code blocks; determining a parity check matrix based on the size of the code blocks; and decoding the code blocks based on the parity check matrix.

[0015] Another aspect of this disclosure provides an apparatus for encoding a channel, the apparatus including a transceiver; at least one processor configured to identify the size of input bits, determine the number of code blocks based on the size of the input bits and the maximum number of information bits corresponding to the maximum parity check matrix, determine the size of the code blocks, determine the number of code blocks and the number of padding bits based on the size of the code blocks, apply padding according to the determined number of padding bits to determine code blocks, determine the parity check matrix based on the size of the code blocks, and encode the code blocks based on the parity check matrix.

[0016] Another aspect of this disclosure provides an apparatus for decoding a channel, the apparatus including a transceiver for transmitting and receiving signals, and at least one processor configured to determine the size of input bits from the received signals before applying segmentation, determine the number of code blocks based on the size of the input bits and the maximum number of information bits corresponding to the maximum parity check matrix, determine the size of the code blocks, determine the number of code blocks and the number of padding bits based on the size of the code blocks, apply padding according to the determined number of padding bits to determine the code blocks, determine the parity check matrix based on the size of the code blocks, and decode the code blocks based on the parity check matrix.

[0017] Other aspects, advantages, and salient features of this disclosure will become apparent to those skilled in the art from the following detailed description of various embodiments disclosed in conjunction with the accompanying drawings.

[0018] [Beneficial effects of the invention]

[0019] According to embodiments of this disclosure, LDPC codes applicable to variable lengths and variable rates can be supported. Attached Figure Description

[0020] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 This is a structural diagram of a systematic low-density parity-check (LDPC) codeword according to an embodiment of the present disclosure;

[0022] Figure 2 This is a tanner diagram illustrating an example of a parity check matrix H1 of an LDPC code consisting of 4 rows and 8 columns according to an embodiment of the present disclosure;

[0023] Figure 3 This is a diagram illustrating the basic structure of a parity check matrix according to an embodiment of the present disclosure;

[0024] Figure 4 This is a configuration block diagram of a transmitting device according to an embodiment of the present disclosure;

[0025] Figure 5 This is a configuration block diagram of a receiving device according to an embodiment of the present disclosure;

[0026] Figure 6 This is a graph showing the results of a performance analysis performed according to an embodiment of the present disclosure by applying Z = 12, 24, 36, 48, 60, 72, 84, 96 to the parity check matrix in Table 2;

[0027] Figures 7A and 7B are message structure diagrams illustrating message passing operations performed at any check node and variable node for LDPC decoding according to embodiments of the present disclosure.

[0028] Figure 8 This is a block diagram describing the configuration of an LDPC encoder according to embodiments of the present disclosure;

[0029] Figure 9 This is a structural diagram of an LDPC decoder according to an embodiment of the present disclosure;

[0030] Figure 10 This is a structural diagram of an LDPC decoder according to another embodiment of the present disclosure;

[0031] Figures 11A and 11B are diagrams illustrating parity check matrices according to embodiments of the present disclosure;

[0032] Figures 12A and 12B are diagrams illustrating parity check matrices according to embodiments of the present disclosure;

[0033] Figures 13A and 13B are diagrams illustrating parity check matrices according to embodiments of the present disclosure;

[0034] Figures 14A and 14B are diagrams illustrating parity check matrices according to embodiments of the present disclosure;

[0035] Figures 15A and 15B are diagrams illustrating parity check matrices according to embodiments of the present disclosure;

[0036] Figures 16A and 16B are diagrams illustrating parity check matrices according to embodiments of the present disclosure;

[0037] Figures 17A and 17B are diagrams illustrating parity check matrices according to embodiments of the present disclosure;

[0038] Figure 18 This is a diagram illustrating a segmentation method according to an embodiment of the present disclosure;

[0039] Figure 19 This is a diagram illustrating another segmented process according to an embodiment of the present disclosure; and

[0040] Figure 20This is a diagram illustrating another segmented process according to an embodiment of the present disclosure;

[0041] Throughout the accompanying drawings, the same reference numerals will be understood to refer to the same parts, components, and structures. Detailed Implementation

[0042] The following description, with reference to the accompanying drawings, is provided to aid in a full understanding of the various embodiments of the present disclosure as defined by the claims and their equivalents. It contains various specific details to aid understanding, but these are to be considered exemplary only. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the various embodiments described herein without departing from the scope and spirit of the present disclosure. Additionally, for clarity and brevity, descriptions of well-known functions and constructions may be omitted.

[0043] The terms and words used in the following description and claims are not limited to their literal meaning, but are used by the inventors only to enable a clear and consistent understanding of this disclosure. Accordingly, it should be understood by those skilled in the art that the following description, which provides various embodiments of this disclosure, is for illustrative purposes only and is not intended to limit the purpose of this disclosure as defined by the appended claims and their equivalents.

[0044] It should be understood that, unless the context clearly specifies otherwise, the singular forms “a,” “an,” and “the” contain plural indicators. Thus, for example, a reference to “component surface” contains a reference to one or more such surfaces.

[0045] The main ideas of this disclosure can also be applied to other communication systems with similar technical backgrounds, with minor modifications that do not significantly deviate from the scope of this disclosure. Those skilled in the art can determine the scope of this disclosure.

[0046] Low-density parity-check (LDPC) codes, first introduced by Gallager in the mid-1960s, were largely forgotten due to their complexity, and their practical application was hampered by the technological limitations of the time. However, since the performance of turbo codes proposed by Berrou, Glavieux, and Thitimajshima in 1993 approached Shannon's channel capacity, numerous studies have been conducted on channel coding based on iterative decoding and its graphs, offering many different interpretations of the performance and characteristics of turbo codes. Consequently, when re-examining LDPC codes from the late 1990s, by applying a sum-product algorithm based on iterative decoding to decode LDPC codes on the corresponding tanner graph, it was found that the performance of LDPC codes also approached Shannon's channel capacity.

[0047] LDPC codes can typically be constrained as parity check matrices and represented using a bipartite graph, often referred to as a tanner graph.

[0048] Figure 1 This is a structural diagram of the LDPC codeword of a system according to an embodiment of the present disclosure.

[0049] refer to Figure 1 By receiving from K ldpc The information word 102, composed of units or symbols, is used to generate N. ldpc LDPC encoding is performed using a codeword of 100, consisting of units or a sign. In the following text, for ease of explanation, it is assumed that the codeword is received containing K... ldpc The information word 102 in the unit digit is used to generate N. ldpc The codeword consisting of the units digit is 100. That is, when the codeword is composed of K... ldpc Information word formed by input bits When 102 is LDPC encoded, codewords are generated. 100. That is, a codeword is a bit string consisting of multiple bits, and the codeword bits represent each bit that forms the codeword. Similarly, an information word is a bit string consisting of multiple bits, and the information word bits represent each bit that forms the information word. In this case, the system code consists of codewords. Composition. Here, There are 104 odd / even bits, and the number of odd / even bits is N. parity As follows. N parity =N ldpc -K ldpc .

[0050] LDPC code is a type of linear block code and includes a process for determining codewords that satisfy the conditions of Equation 1 below.

[0051] [Equation 1]

[0052]

[0053] In the above equation,

[0054] In Equation 1 above, H represents the parity check matrix, C represents the codeword, and c i Let N represent the i-th codeword bit, and N represent the i-th codeword bit. ldpc This represents the codeword length. In the above equation, h... i This represents the i-th column of the parity check matrix H.

[0055] The parity check matrix H is equal to N, which is the number of LDPC codeword bits. ldpcThe system consists of columns. Equation 1 above indicates that: due to the i-th column hi and the i-th codeword bit c of the parity check matrix... i The sum of the products of the i-th column hi and the i-th codeword bit c becomes '0', therefore the sum of the products of the i-th column hi and the i-th codeword bit c becomes '0'. i related.

[0056] Reference Figure 2 A graphical representation method for describing LDPC codes.

[0057] Figure 2 This is a tanner diagram illustrating an example of a parity check matrix H1 of an LDPC code consisting of 4 rows and 8 columns according to an embodiment of the present disclosure.

[0058] refer to Figure 2 Since the parity check matrix H1 has 8 columns, it generates codewords of length 8. The codewords generated by H1 represent LDPC codes, and each column corresponds to the 8 bits being encoded.

[0059] refer to Figure 2 The Tanner graph of the LDPC code encoded and decoded based on the parity check matrix H1 consists of 8 variable nodes (i.e., x1(202), x2(204), x3(206), x4(208), x5(210), x6(212), x7(214), and x8(216)) and 8 check nodes 218, 220, 222, and 224. Here, the i-th and j-th columns of the parity check matrix H1 of the LDPC code correspond to the variable node xi and the j-th check node, respectively. Furthermore, the value at the intersection of the j-th column and the j-th row of the parity check matrix H1 of the LDPC code is 1, that is, a value other than 0 indicates that... Figure 2 The Tanner graph shown contains connections to the variable node x. i The edge between the j-th verification node and the verification node.

[0060] The degree of the variable and parity nodes on the Tanner graph of an LDPC code refers to the number of edges connected to each node, which is equal to the number of entries (excluding 0) in the column or row of the corresponding node in the parity check matrix of the LDPC code. For example, in Figure 2 In the process, the dimensions of variable nodes x1(202), x2(204), x3(206), x4(208), x5(210), x6(212), x7(214), and x8(216) are changed to 4, 3, 3, 3, 2, 2, and 2 in sequence, respectively. Furthermore, the dimensions of test nodes 218, 220, 222, and 224 are changed to 6, 5, 5, and 5 in sequence, respectively. In addition, with... Figure 2 The corresponding variable node Figure 2The number of entries (excluding 0) in each column of the parity check matrix H1 corresponds sequentially to the dimensions 4, 3, 3, 3, 2, 2, 2, and 2 mentioned above, and is consistent with... Figure 2 The corresponding inspection nodes Figure 2 The number of entries (excluding 0) in each row of the parity check matrix H1 corresponds in order to the dimensions 6, 5, 5, and 5 mentioned above.

[0061] like Figure 2 As shown, LDPC codes can be decoded using an iterative decoding algorithm based on a sum-product algorithm on a bipartite graph. Here, the sum-product algorithm is a message-passing algorithm. A message-passing algorithm is defined as follows: using edges on the bipartite graph to exchange messages, and using the messages input to variable nodes or check nodes to compute the output, and updating the computed output message.

[0062] In this paper, the value of the i-th coded bit can be determined based on the message of the i-th variable node. The value of the i-th coded bit can be applied in conjunction with both hard and soft decisions. Therefore, the i-th bit c of the LDPC codeword i The performance of LDPC codes corresponds to the performance of the i-th variable node in the Tanner graph, which can be determined by the position and number of 1s in the i-th column of the parity check matrix. In other words, the performance of the Nldpc codeword bits can depend on the position and number of 1s in the parity check matrix, meaning that the performance of LDPC codes is greatly affected by the parity check matrix. Therefore, to design LDPC codes with excellent performance, a good method for designing the parity check matrix is ​​needed.

[0063] To facilitate the implementation of parity check matrices used in communication and broadcasting systems, quasi-cyclic LDPC codes (hereinafter referred to as QC-LDPC codes) using quasi-cyclic (QC) parity check matrices are typically used.

[0064] QC-LDPC codes have a parity check matrix consisting of a zero matrix (zero matrix) or a cyclic permutation matrix, which are small square matrices. A permutation matrix is ​​a square matrix in which all elements are either 0 or 1, and each row or column contains only one 1. A cyclic permutation matrix is ​​a matrix in which each element of the identity matrix is ​​cyclically shifted to the right.

[0065] The QC-LDPC code will be described in more detail with reference [Myung2006] below.

[0066] Reference [Myung2006]

[0067] S. Myung, K. Yang, and Y. Kim, "Lifting Methods for Quasi-Cyclic LDPC Codes", IEEE Communications Letters, vol. 10, pp. 489 - 491, June 2006.

[0068] Describing reference [Myung2006], a permutation matrix P of size L×L = (P i，j ) is defined by Equation 2 below. Here, P i，j refers to the entry in the i-th row and j-th column of matrix P (0 ≤ i, j < L).

[0069] [Equation 2]

[0070]

[0071] For the permutation matrix P defined as above, it can be recognized that P i (0 ≤ i < L) is a cyclic permutation matrix, which is in the form that each entry of the identity matrix of size L×L is cyclically shifted i times in the right direction.

[0072] The parity-check matrix H of the simplest QC-LDPC code can be represented by Equation 3 below. <​​​​​​​​​​​​​​​​​​​​​​

[0079] Furthermore, the performance of LDPC codes can be determined based on the parity check matrix. Therefore, it is necessary to design parity check matrices for LDPC codes with excellent performance. In addition, LDPC encoding and decoding methods that can support various input lengths and code rates are required.

[0080] The reference [Myung 2006] describes a lifting method known for efficiently designing QC-LDPC codes. Lifting is a method for efficiently designing very large parity check matrices by setting a value L based on specific rules to determine the size of the cyclic permutation matrix or zero matrix from a given small mother matrix. Existing lifting methods and the characteristics of QC-LDPC codes designed by lifting are briefly outlined below.

[0081] First, given the LDPC code C0, the S QC-LDPC codes to be designed using the lifting method are set as C1, ..., C2. S And the size of the row block and column block of the parity check matrix corresponding to each QC-LDPC code is set to L. k Here, C0 corresponds to making C1, ..., C S The parent matrix of the code serves as the smallest LDPC code for parity checking, and the L0 value corresponding to the size of the row and column blocks is 1. Furthermore, for convenience, each code C... k Parity check matrix H k An exponential matrix of size m×n And each index Choose one of the values ​​{-1, 0, 1, 2, ..., Lk-1}.

[0082] Describe the reference [Myung2006], and elevate it from C0→C1→...→C S The steps or operations constitute, and have, for example, L k+1 =q k+1 L k (q k+1 The characteristic is that it is a positive integer, k = 0, 1, ..., S-1. Furthermore, if C is stored solely based on the characteristics of the lifting process... S Parity check matrix H S Then, according to the lifting method, all QC-LDPC codes C0, C1, ..., C can be represented by the following equation 5. S .

[0083] [Equation 5]

[0084]

[0085] [Equation 6]

[0086] E(Hk )≡E(H S )mod L k

[0087] Based on the lifting method of Equation 5 or Equation 6 above, corresponding to each QC-LDPC code C k The size L of the row or column block of the parity check matrix k The values ​​have multiple relationships with each other, and therefore the exponent matrix is ​​also chosen by a specific scheme. As mentioned above, existing lifting methods help to facilitate the design of QC-LDPC codes with improved error plane (floor) properties by making the algebraic or graphical properties of each parity check matrix designed by lifting good.

[0088] However, the following problems exist: L k Each value has multiple relationships with each other, and therefore the length of each key is greatly limited. For example, if we assume, as L... k+1 =2*L k The lifting method is applied to a minimum for each of the Lk values, so the parity check matrix of each QC-LDPC code can have a size of only 2. k m×2 k n. That is, when lifting is applied in 10 operations (S=10), the parity check matrix may only have a size of 10.

[0089] Therefore, existing enhancement methods have a slight disadvantage in designing QC-LDPC codes that support various lengths. However, considering the diverse types of data transmission, commonly used mobile communication systems require a very high level of length compatibility. Consequently, existing methods suffer from the problem of making LDPC codes difficult to apply to mobile communication systems.

[0090] The method for encoding QC-LDPC codes will be described in more detail in the next reference [Myung2005].

[0091] Reference [Myung2005]

[0092] S. Myung, K. Yang and J. Kim, “Quasi-Cyclic LDPC Codes for Fast Encoding”, IEEE Transactions on Information Theory, Vol. 51, No. 8, pp. 2894-2901, August 2005.

[0093] Figure 3 This is a diagram illustrating the basic structure of a parity check matrix according to an embodiment of the present disclosure.

[0094] The description of the above reference [Myung2005] specifies that it has the following characteristics: Figure 3 The parity check matrix shown is a special form of the cyclic permutation matrix. Furthermore, if... Figure 3 If the parity check matrix satisfies the relationship in Equation 7 or Equation 8 below, then effective encoding can be performed.

[0095] [Equation 7]

[0096] and

[0097] [Equation 8]

[0098] and

[0099] In equations 7 and 8 above, the value of l (≠1,m) refers to P. y The position of the row.

[0100] As is well known, if the parity check matrix satisfies Equations 7 and 8 above, then the matrix φ defined in the above reference [Myung2005] becomes an identity matrix, and thus encoding can be performed efficiently during encoding.

[0101] For convenience, the embodiments of this disclosure describe a block with only one cyclic permutation matrix, but it should be noted that the same disclosure can also be applied to a block containing multiple cyclic permutation matrices.

[0102] Figure 4 This is a configuration block diagram of a transmitting device according to an embodiment of the present disclosure.

[0103] refer to Figure 4 The transmitting device 400 may include a segmenter 410, a zero-filler 420, an LDPC encoder 430, a rate matcher 440, and a modulator 450 to handle variable-length input bits.

[0104] Furthermore, although not shown in this figure, the segmenter 410, zero-filler 420, LDPC encoder 430, rate matcher 440, and modulator 450 of the transmitting device are included in a controller (at least one processor) and can operate according to the control of the controller. The controller can control the operation of the transmitting device described in this disclosure. Additionally, the transmitting device may also include transceivers for transmitting and receiving signals.

[0105] here, Figure 4 The components shown are for encoding and modulating variable-length input bits; this is just an example. In some cases, they can be omitted or changed. Figure 4Some of the components shown are shown, and other components can also be added.

[0106] Figure 5 This is a configuration block diagram of a receiving device according to an embodiment of the present disclosure.

[0107] refer to Figure 5 The receiving device 500 may include a demodulator 510, a rate dematcher 520, an LDPC decoder 530, a zero remover 540, and a de-segmentator 550 to process variable-length information.

[0108] Furthermore, although not shown in this figure, the demodulator 510, rate dematcher 520, LDPC decoder 530, and zero remover 540 of the transmitting device are included in the controller and can be operated according to the control of the controller. The operation of the receiving device described in this disclosure can be controlled. In addition, the receiving device may also include transceivers for transmitting and receiving signals.

[0109] here, Figure 5 The components shown are for making corresponding Figure 4 The components shown are functional components; this is just an example, and in some cases, some components can be omitted or changed, and other components can also be added.

[0110] The detailed embodiments of this disclosure are as follows.

[0111] First, the S LDPC codes designed using the lifting method are set as C1, ..., C2. S And the parity check matrix C corresponding to each LDPC code i The size of the row and column blocks is set to Z. Furthermore, for convenience, each code C... i Parity check matrix H z An exponential matrix of size m×n index Each of the values ​​is chosen as one of the values ​​{-1, 0, 1, 2, ..., Z-1}. (For convenience, in this disclosure, the exponent representing the 0 matrix is ​​represented as -1, but it can be changed to other values ​​as convenient for the system.)

[0112] Therefore, the LDPC code C with the largest parity check matrix S The exponential matrix is ​​limited to (Here, Z) max (Limited to the maximum value of Z). In this case, when the Z value is less than Z... max When the exponent of the cyclic permutation matrix and the zero matrix that configures the parity check matrix of each LDPC code are represented, they can be determined according to the following equation 9.

[0113] [Equation 9]

[0114]

[0115] [Equation 10]

[0116]

[0117] In equation 9 or equation 10 above, Indicates passage The remainder obtained by dividing by Z.

[0118] However, [Myung2006] restricts the Z-values ​​such that they satisfy multiple relationships with each other, and therefore is not suitable for supporting various lengths. For example, the exponential matrix E(H) of the parity check matrix Hz. z ) or parent matrix M(H z The number of columns n is 36, and the Z value can be obtained through promotion by 8 operations (such as 1, 2, 4, 8, ..., 128) with a length of 36, 72, 144, ..., 4608 (=36*2) 7 This makes the difference between the shortest and longest lengths very large.

[0119] Even when the Z values ​​do not have multiple relationships with each other, embodiments of this disclosure can apply the exponential method applied to Equation 9 or Equation 10 above, and this disclosure proposes a method for designing parity check matrices with minimal performance degradation. For reference, the method proposed in Equation 9 or Equation 10 is an exponential transformation method in the case of applying a modulo-based lifting method, and it is obvious that various methods based on flooring operations or other operations, as described in reference document [Myung2006], may exist. Equation 11 or Equation 12 below indicates when the Z value is less than Z... max The exponential transformation method of the designed parity check matrix is ​​applied by plane operation to improve it.

[0120] [Equation 11]

[0121]

[0122] [Equation 12]

[0123]

[0124] The following section describes a method for designing a parity check matrix and its usage to address the problems of existing lifting methods with length compatibility.

[0125] First, this disclosure defines the improvement process after the following changes.

[0126] 1) The maximum value among the Z values ​​is limited to Z. max .

[0127] 2) One of the divisors of Zmax is constrained to be D. (Z max =D·S)

[0128] 3) Z has D, 2D, 3D, ..., SD (=Z) max One of the values.

[0129] (For convenience, the parity check matrix corresponding to Z = k × D is limited to H) k And the LDPC code corresponding to the parity check matrix is ​​limited to C. k ).

[0130] Existing lifting methods only affect the parity of the parity check matrix designed just before its design. That is, when Z-values ​​have multiple relationships with each other during each lifting process, to design the (k+1)th parity check matrix, only the kth parity check matrix is ​​affected, and the (k-1)th parity check matrix is ​​no longer used. This is due to the multiple relationships between Z-values, and its details are described in detail in reference [Myung2006].

[0131] However, since Z values ​​typically do not have multiple relationships with each other, the modified lifting method proposed in this disclosure can improve the optimal parity check matrix as described in reference [Myung2006]. Therefore, this disclosure proposes the following method for designing a suboptimal parity check matrix.

[0132] For convenience, the parent matrix of the applied lifting is limited to M(H), and each entry of the exponent matrix of the parent matrix is ​​limited to... Furthermore, when Z = k × D, the value of Z is limited to Z. k , and the entries corresponding to its exponent matrix are limited to

[0133] The method for designing the parity check matrix based on the modified lifting method is as follows.

[0134] Operation 1) If Then for

[0135] Operation 2) When k=1,

[0136] Based on the parent matrix M(H), the method was obtained using the same approach as in reference [Myung2006].

[0137] in this case, Each entry It has one of the values ​​0, 1, 2, ..., Z1-1, and the analysis is performed for each entry. of The cyclic characteristic curve of the Tanner plot. Note that the position of the 0 matrix is ​​initially determined by operation 1.

[0138] Cyclic characteristic curves refer to the following matters.

[0139] i) The size of the cycle girth on the tanner graph generated for each entry

[0140] ii) The sum of the order of the variable nodes of the loop with varying perimeters generated and configured for each entry.

[0141] iii) The number of variable nodes that generate and configure the perimeter of the loop for each entry.

[0142] In embodiments of this disclosure, the perimeter can represent the shortest cycle on the Tanner graph. That is, the cycle characteristic curve can represent the size of the shortest cycle on the Tanner graph, the sum of the orders of the variable nodes configuring the shortest cycle, and the number of variable nodes configuring the shortest cycle.

[0143] In addition, each entry The value is temporarily determined as the case with the best cycling characteristics. Here, "good cycling characteristics" means that the following conditions are met.

[0144] iv) The perimeters on the tanner diagram are equal in size.

[0145] v) The sum of the orders of the variable nodes in a loop with a perimeter is very large.

[0146] vi) When iv) and v) are equal, the number of variable nodes configured for the perimeter size loop is very small.

[0147] In detail, as loops become shorter, errors are less likely to be detected, and therefore, the larger the loop on the Tanner graph, the better the loop characteristics. Thus, a larger shortest loop size, and a larger sum of the orders of the variable nodes configuring the shortest loop, likely indicates a larger loop on the Tanner graph, which may indicate good loop characteristics. Furthermore, as the number of variable nodes configuring the shortest loop decreases, the number of short loops is small, and therefore the loop characteristics are also good.

[0148] Therefore, when the conditions are met, the entries When the value appears as a complex number, all values ​​are temporarily stored as candidate values.

[0149] For 1 < k ≤ S, repeat steps 3) and 4).

[0150] Operation 3) Each element Set as temporarily determined To analyze The cyclic characteristic curve. In this case, it should be noted that... The values ​​are 0, 1, 2, ..., Z. k-1 One of -1. Next, Entries The value of each of them is changed to Z k-1 Z k-1 +1、...、Z k -1, to analyze the cyclic characteristic curve.

[0151] Select each entry The case with optimal cycle characteristics.

[0152] Operation 4) When Applied to the selection in operation 3) Value, and then increase all When the cyclical nature of the Tanner graph is observed, the corresponding... The value is determined as Candidate values ​​for the entries. It should be noted that these are tentatively determined. Values ​​can appear in complex numbers.

[0153] Operation 5) determines the final result based on operation 4). During operations 3) and 4) Entries When the selection probability appears as a complex number, the minimum value among the candidate values ​​is determined as the final value.

[0154] Examples of parity check matrices designed using the above method are shown in Tables 1 through 6 below. The tables (Tables 1 through 6) represent the exponent matrix for each parity check matrix. (Small empty blocks represent zero matrices of size Z × Z.) For ease of design, the number of columns in the parent matrix is ​​fixed at 36, and the bitrate is set to 8 / 9 in Tables 1 and 2 below, 2 / 3 in Tables 3 and 4 below, and 4 / 9 in Tables 5 and 6 below. Furthermore, it is assumed that the Z values ​​used for boosting are set to 12, 24, 36, 48, 60, 72, 84, and 96 to support a total of 8 lengths.

[0155] [Table 1]

[0156]

[0157] [Table 2]

[0158]

[0159] [Table 3]

[0160]

[0161] [Table 4]

[0162]

[0163] [Table 5]

[0164]

[0165] [Table 6]

[0166]

[0167] Another example of the designed parity check matrix is ​​shown in the tables below (Tables 7 to 12). Tables 7 to 12 represent the exponent matrix for each parity check matrix. (Small empty blocks correspond to a 0 matrix of size Z×Z.) For ease of design, the number of columns in the parent matrix is ​​fixed at 37, and the bitrate is set to 32 / 37 in Tables 7 and 8, 24 / 37 in Tables 9 and 10, and 16 / 37 in Tables 11 and 12. Furthermore, it is assumed that the Z values ​​used for boosting are set to 12, 24, 36, 48, 60, 72, 84, and 96 to support a total of 8 lengths.

[0168] [Table 7]

[0169]

[0170] [Table 8]

[0171]

[0172] [Table 9]

[0173]

[0174] [Table 10]

[0175]

[0176] [Table 11]

[0177]

[0178] [Table 12]

[0179]

[0180] When using the parity check matrices shown in the tables above (Tables 7 to 12) for LDPC encoding, since the code rate is set to 8 / 9 in Tables 7 and 8, 2 / 3 in Tables 9 and 10, and 4 / 9 in Tables 11 and 12, the final code rate appears to be the same as that used in Tables 1 to 6 above, when the information word bits corresponding to the first column block in the subarray corresponding to the information word are transmitted via puncture. Generally, since LDPC encoding can improve performance when puncturing the information word is appropriately applied, the LDPC encoding using the tables above (Tables 7 to 12) can be used for performance improvement.

[0181] Some computational experimental results on the performance of the parity check matrix generated by the parity check design method proposed in this disclosure are presented in... Figure 6 As shown in the image.

[0182] Figure 6 This is a graph illustrating the performance analysis results of applying Z = 12, 24, 36, 48, 60, 72, 84, 96 to the parity check matrices in Table 3 above, according to embodiments of this disclosure. Describing the performance, it is understood that the LDPC encoding technique using eight parity check matrices generated from an exponential matrix operates well. In particular, it can be confirmed that the good performance is shown by the absence of an error plateau phenomenon until the frame error rate reaches 1 / 1000 in the region.

[0183] The exponent matrices shown in the tables above (Tables 1 to 12) are designed under the assumption of modulus enhancement, and the exponent matrix for each Z value can be derived by applying Equation 9 or Equation 10 above to each exponent.

[0184] Another example of the designed parity check matrix is ​​shown in the following tables—Tables 13 to 16. Tables 13 to 16 represent the exponent matrix for each parity check matrix. (Small empty blocks correspond to a 0 matrix of size Z×Z.) For ease of design, the number of columns in the parent matrix is ​​fixed at 24, and the code rate is set to 5 / 6 in Table 13, 3 / 4 in Table 14, 2 / 3 in Table 15, and 1 / 2 in Table 16. Furthermore, the Z values ​​used for boosting are set to 81, 162, and 324, and refer to the exponent matrix of the parity check matrix for LDPD codes that can be supported for at least three Z values.

[0185] [Table 13]

[0186]

[0187] [Table 14]

[0188]

[0189] [Table 15]

[0190]

[0191] [Table 16]

[0192]

[0193] Another example of the designed parity check matrix is ​​shown in the following tables—Tables 17 to 20. Tables 17 to 20 represent the exponent matrix for each parity check matrix. (Small empty blocks correspond to a 0 matrix of size Z×Z.) For ease of design, the number of columns in the parent matrix is ​​fixed at 24, and the code rate is set to 5 / 6 in Table 17, 3 / 4 in Table 18, 2 / 3 in Table 19, and 1 / 2 in Table 20. Furthermore, the Z values ​​used for boosting are set to 81, 162, 324, and 648, and refer to the exponent matrix of the parity check matrix for a total of four Z values ​​that can be supported by LDPC codes.

[0194] [Table 17]

[0195]

[0196] [Table 18]

[0197]

[0198] [Table 19]

[0199]

[0200] [Table 20]

[0201]

[0202] For reference, the exponent matrices shown in Tables 13 to 20 above are designed under the assumption of modulo lifting, and the exponent matrix for each Z value can be derived by applying Equation 9 or Equation 10 above to each exponent, and the exponent matrix for each Z value can be used for encoding. Furthermore, it can be understood that if the exponent matrices in the above tables (Tables 17 to 20) are modulo 324, the exponent matrices in Tables 13 to 16 can be obtained respectively, and if Tables 13 to 20 are modulo 81, then Tables 13 and 18, Tables 14 and 18, Tables 15 and 19, and Tables 16 and 20 each have the same exponent matrix. In other words, it can be understood that the exponent matrices shown in Tables 17 to 20 contain the information in the exponent matrices shown in Tables 13 to 16, and lifting can be applied using the same exponent matrix that can be obtained by modulo 81. The exponential matrix obtained by applying modulo 81 to the exponential matrix shown in the tables above (Tables 13 to 20) can support the parity matrix defined in the IEEE 802.11n standard. It shows that by applying the enhancement of the known parity matrix using related techniques, a new parity matrix can be designed while maintaining the characteristics of the existing parity matrix.

[0203] The above table—Tables 1 to 20—shows all the index matrices. Figure 3 The parity check matrix shown is formatted as b1 = 1, y = 0, x = 1, satisfying equation 7 or equation 8 above. Therefore, it is well known that a matrix limited to φ as in reference [Myung 2005] becomes an identity matrix, and thus can be effectively encoded during the encoding process.

[0204] However, according to another embodiment of this disclosure, the encoding method is expressed as follows.

[0205] refer to Figure 3 The exponent value of the cyclic matrix in the submatrix corresponding to parity is determined by Equation 13 below.

[0206] [Equation 13]

[0207]

[0208] Equation 13 above has different conditions for the y-values ​​in Equation 7 above, and therefore the φ matrix defined in reference [Myung 2005] is not an identity matrix. Therefore, there is a slight difference during the encoding process. However, the portion that typically contributes to the increase in complexity in LDPC encoding is φ. -1 The number of entries other than 0 is displayed here. According to Equation 13 above, φ becomes the cyclic permutation matrix Pa (a is an integer), and therefore it is obvious that φ-1 It is also a simple cyclic permutation matrix P -a Therefore, it can be expected that the coding complexity will hardly increase.

[0209] The encoding process will be described in detail below. At this point, the information word can be generated from the vector s (corresponding to...). Figure 3 Subarrays A and C) represent parity, and the parity vectors can be represented by... p 1 and p 2 represents. p 1 corresponds to Figure 3 Subarrays B and D, and p 2 corresponds to Figure 3 Subarrays T and E).

[0210] Operation 1) Calculate A s T and C s T The value of .

[0211] Operation 2) Calculate ET -1 A s T+ C s T The value of . Here, the calculation can also be performed using the following features:

[0212] ET -1 =[II … I]

[0213] Operation 3) Calculation p 1 T =φ -1 (ET -1 A s T+ C s T The value of ).

[0214] Operation 4) Using relation T p 2 T =A s T +B p 1 T To calculate p The value of 2.

[0215] In fact, according to reference [Myung2005], after obtaining Figure 3 The first parity process (operation 3) requires φ -1 The operation, and since matrix φ is the identity matrix, the parity check matrix satisfying Equation 7 above does not need φ. -1 This operation allows for efficient encoding. However, during the process of obtaining the second parity (operation 4), the first parity check is required. Related operations. The reason is that the matrix contained in B contains... And in calculating B p 1 T During the process, the first parity needs to be Related operations. If... Setting b1 to the identity matrix (i.e., setting b1 to 0) to simplify operations may worsen the cyclic properties on the Tanner graph. Therefore, to prevent this deterioration, the first parity is adjusted. The relevant operations are used to obtain the second parity.

[0216] A detailed example of the case described in Equation 13 above will be given. For example, suppose that the case corresponding to... Figure 3 The exponents for the cyclic permutations of the parity submatrix are set as follows: b1 = b2 = ... = b m =x=0, y≠0, satisfying equation 13 above. In this case, φ=P y And therefore, P is required during the process of obtaining the first parity. y The operation involves the inverse matrix. However, b1 can be set to 0, and therefore no operation related to the cyclic permutation matrix is ​​needed for the first parity during the process of obtaining the second parity. Furthermore, the y value can be set to prevent deterioration of the cyclic properties of the tanner graph. (Generally, to ensure good cyclic properties, the y value is set such that y and Z are coprime). Therefore, the increase in coding complexity can be ignored without performance degradation. Additionally, b1 = b2 = ... = b m =x=0 refers to a matrix consisting of an identity matrix, and therefore it is very advantageous to implement multiple parity check matrices in hardware.

[0217] The preceding encoding process can be presented in detail below. As mentioned above, the information word can be generated by vector s (corresponding to...). Figure 3 Subarrays A and C) represent parity vectors, and the parity vectors can be represented by... p 1 and p 2 represents. p 1 corresponds to Figure 3 Subarrays B and D, and p 2 corresponds to Figure 3 (subarrays T and E). The encoding process using Equation 13 above is similar to the aforementioned encoding process, but differs in operations 3 and 4.

[0218] Operation 1) Calculate A s T and C s T The value of .

[0219] Operation 2) Calculate ET-1 A s T +C s T The value of . Here, the following features can be used for calculation:

[0220] ET -1 =[II … I].

[0221] Operation 3) Calculation p 1 T =p -y (ET -1 A s T +C s T The value of φ (φ=P) y φ -1 =P -y ), where P -y This can be easily achieved by cyclically shifting bits by the y-axis.

[0222] Operation 4) Using T p 2 T =A s T +B p 1 T Calculate the relationship p The value of 2.

[0223] Referring to the LDPC encoding process, the calculated values ​​of the equation consisting of the information word and some parity check matrices are determined in operations 1) and 2). Next, in operation 3), an appropriate cyclic shift is applied to determine the first parity. p 1, and then in operation 4), determine based on the result. p 2.

[0224] In operation 4), B consists of I, Py, the zero matrix, etc., and therefore B can be easily implemented using the result of operation 3). p 1 T The calculation. For example, I· p 1 T Operation and p 1 T The same applies, and therefore the result of operation 3) can be used in this way. Furthermore, p y p 1 T The result of the calculation is the same as that of operation 2), so no additional calculation is required.

[0225] Finally, you can simply use T. -1 (A s T +B p 1T )get p 2 T However, calculating T -1 The computational complexity of the product increases, and therefore the back-substitution method is often used to compute T. p 2 T .

[0226] Therefore, when Figure 3 When the parity check matrix is ​​divided into submatrices corresponding to the information words and submatrices corresponding to parity, and the parity matrix corresponding to parity is further divided into a first part B consisting of an identity matrix, a cyclic permutation matrix, and a zero matrix; a second part D consisting of an identity matrix or a cyclic permutation matrix; a third part E consisting of an identity matrix or a cyclic permutation matrix; and a fourth part T in which the identity matrix or cyclic permutation matrix is ​​arranged in a double diagonal form, the following LDPC code transmission or reception method and device can have low coding complexity and can be easily implemented. This LDPC code uses a parity check matrix in which (E)(T-1)(B)+D is not an identity matrix but a cyclic permutation matrix. Furthermore, the structure of the parity check matrix can be chosen such that y is between 1 and φ = P. y Any integer between (Z-1) in the range, and thus a variety of exponents can be chosen, making it easy to design code with excellent loop characteristics.

[0227] Another example of a parity check matrix designed by the design method proposed in this disclosure is shown in Figures 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B.

[0228] Figures 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B represent the exponent matrix of each parity check matrix according to embodiments of the present disclosure.

[0229] Assume that a small empty block refers to a 0 matrix of size Z×Z, and set the Z values ​​used for boosting to 12, 24, 36, 48, 60, 72, 84 and 96 to support a total of 8 lengths.

[0230] For reference, the 37th to the last column block in Figure 11 and the 38th to the last column block in Figure 14 are both of order 1. For convenience, some blocks have been omitted from the table above. Furthermore, the first-order column blocks are composed of identity matrices.

[0231] Describing the parity check matrix of Figure 11, it can be understood that the submatrix consisting of four row blocks and 36 column blocks of all parity check matrices is identical to the parity check matrix corresponding to Table 2 above. That is, it can be understood that the parity check matrix of Figure 11 has a form that is extended by concatenating multiple individual parity check codes with the parity check matrix corresponding to Table 2 above. Furthermore, it can be readily understood that the parity check matrices of Figures 12A to 16 also each have a form that is an extension of the parity check matrices in Tables 4, 6, 8, 10, and 12 above.

[0232] Figures 17A and 17B show another example of a parity check matrix designed using the design method proposed in this disclosure.

[0233] Figures 17A and 17B represent the exponent matrix of each parity check matrix according to embodiments of the present disclosure.

[0234] In this disclosure, the parity check matrix can be represented by a sequence having the same algebraic properties as the exponential matrix. For convenience, the parity check matrix is ​​represented by a sequence indicating the positions of 1s within the exponential matrix or the parity check matrix (or the positions of 1s in the cyclic permutation matrix that configures the parity check matrix), but the notations for the sequences that can identify the positions of 1s or 0s contained in the parity check matrix are varied and therefore not limited to those in this specification. Thus, various sequence forms exist that exhibit the same algebraic effect. Assume that the small empty blocks refer to a 0 matrix of size Z×Z, and that the Z values ​​used for lifting are set to 27, 54, and 81 to support a total of 3 lengths. For reference, the 25th column block to the last column block in Figure 17 are all of order 1. Furthermore, the column blocks of order 1 are composed of identity matrices.

[0235] Parity check matrices using concatenated schemes with single parity check codes are easily extendable and therefore advantageous for applying incremental redundancy (IR) techniques. IR is a crucial technique for supporting Hybrid Automatic Repeat Request (HARQ), and thus, efficient and high-performance IR techniques improve the efficiency of HARQ systems. LDPC codes based on parity check matrices use portions extended to the single parity check code to generate new parities, and then transmit the generated parities, thereby applying efficient and high-performance IR techniques.

[0236] For reference, the parity check matrix designed in the embodiments of this disclosure refers to an exponential matrix of Z values. However, it is evident that LDPC coding techniques with various block lengths and code rates can be applied when shortening and perforation are appropriately applied to the LDPC codes corresponding to the corresponding parity checks. In other words, by applying appropriate shortening to the LDPC codes corresponding to the parity check matrices shown in Figures 11A to 17B, various information word lengths can be supported; by appropriately applying perforation, various code rates can be supported; and a single parity bit of the appropriate length can be generated and transmitted, thereby applying efficient IR techniques.

[0237] At the same time, it can be used based on Figure 2 The iterative decoding algorithm of the sum-product algorithm on the bipartite graph is shown to decode LDPC codes, and the sum-product algorithm is a message-passing algorithm.

[0238] In the following text, the message passing operations typically used in LDPC decoding will be described with reference to Figures 7A and 7B.

[0239] Figures 7A and 7B are message structure diagrams illustrating message passing operations performed at any check node and variable node for LDPC decoding according to embodiments of the present disclosure.

[0240] Referring to Figure 7A, a check node m 700 and multiple variable nodes 710, 720, 730, and 740 connected to the check node m 700 are shown. Furthermore, T is shown... n',m This represents the message passed from variable node n'710 to check node m 700, and E n,m This represents a message passed from check node m 700 to variable node n730. Here, the set of all variable nodes connected to check node m 700 is limited to N(m), and the set excluding variable node n 730 from N(m) is limited to N(m) / n.

[0241] In this case, the message update rule based on the sum-product algorithm can be represented by the following Equation 14.

[0242] [Equation 14]

[0243]

[0244]

[0245] In Equation 14 above, Sign(E) n,m ) represents the symbol for En,m, and |E n,m | indicates message E n,m The magnitude of the amplitude. Meanwhile, the function Φ(x) can be represented by the following equation 15.

[0246] [Equation 15]

[0247]

[0248] Meanwhile, Figure 7B shows variable node x 750 and multiple check nodes 760, 770, 780 and 790 connected to variable node x 750. Furthermore, E is shown... v',x This represents the message passed from check node y'760 to variable node x 750, and T v,x Let M(x) represent the message passed from variable node m 750 to variable node n 780. Here, the set of all variable nodes connected to variable node x 750 is limited to M(x), and the set excluding the check node y 780 from M(x) is limited to M(x) / y. In this case, the message update rule based on the sum-product algorithm can be represented by the following Equation 16.

[0249] [Equation 16]

[0250]

[0251] In Equation 16 above, E x This represents the initial message value of variable node x.

[0252] Furthermore, once the bit value of node x is determined, it can be represented by the following equation 17.

[0253] [Equation 17]

[0254]

[0255] In this case, it can be based on P x The value determines the encoding bits corresponding to node x.

[0256] The methods shown in Figures 7A and 7B are general decoding methods, and therefore will not be described in detail hereafter. However, in addition to the methods described in Figures 7A and 7B, other methods can be applied to determine the transmitted message value at the variable node and the check node (Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, “Factor Graphs and the Sum-Product Algorithm,” IEEE TRANSACTIONS ON INFORMATION THEORY, Vol. 47, No. 2, February 2001, pp. 498-519).

[0257] In the following text, reference will be made to Figure 4Describe the operation of the transmitter in detail.

[0258] In detail, such as Figure 4 As shown, the transmitting device 400 may include a segmenter 410, a zero-filler 420, an LDPC encoder 430, a rate matcher 440, and a modulator 450 to process variable-length input bits.

[0259] here, Figure 4 The component shown is for encoding and modulating variable-length input bits; this is merely an example and is not limited to this. In some cases, Figure 4 Some of the components shown in part 4 can be omitted or changed, and other components can be added.

[0260] at the same time, Figure 4 The LDPC encoder 430 shown can be used by... Figure 8 The operation performed by the LDPC encoder 810 shown.

[0261] The transmitting device 400 can determine the required parameters (e.g., input bit length, modulation and code rate (ModCod), parameters for zero-padding, code rate / code length of the LDPC code, parameters for interleaving, parameters for repetition, parameters for puncturing, modulation scheme, etc.), encode based on the determined parameters, and send the encoded parameters to... Figure 5 The receiving device.

[0262] Because the number of input bits is variable, when the number of input bits exceeds a preset value, the input bits can be segmented to have a length equal to or less than the preset value. Furthermore, each segmented block can correspond to one LDPC coded block. However, when the number of input bits is equal to or less than the preset value, the input bits are not segmented. Each input bit can correspond to one LDPC coded block.

[0263] In the following text, reference will be made to Figure 18 A more detailed description of the segmentation method is provided. This applies when the number of input bits is B and B is greater than the preset value K. max When segmenting, the input bits are divided based on the maximum number of input bits and the number of blocks in the LDPC code. The maximum number of input bits and the number of blocks can be shown in Table 21 below.

[0264] [Table 21]

[0265] Code Rate <![CDATA[K max ]]> <![CDATA[K min ]]> <![CDATA[N Idpc_b ]]> <![CDATA[K Idpc_b ]]> 5 / 6 1620 540 24 20 3 / 4 1458 486 24 18 2 / 3 1296 432 24 16 1 / 2 972 324 24 12 1 / 3 1620 540 60 20

[0266] In Table 21 above, K max It represents the number of LDPC information word bits in the parity check matrix corresponding to the largest LDPC codeword, and the maximum number of input bits required to generate the largest LDPC codeword, as well as K.min It is the maximum number of LDPC information words required to generate an LDPC codeword from the parity check matrix of the smallest LDP code.

[0267] For convenience, K max K represents the maximum number of LDPC input bits (or information bits) that can be encoded using the maximum parity check matrix given in the system, and K min This indicates the maximum number of LDPC input bits (or information bits) that can be encoded using the minimum parity check matrix given in the system.

[0268] It is important to note that K min This does not refer to the number of bits in a code block of the smallest possible size that can be input into the system. The transmitting device can adapt codes smaller than K by appropriately applying shortening methods to the minimum LDPC code or parity check matrix. min LDPC encoding is performed using code blocks.

[0269] N ldpc_b This represents the number of column blocks in the parity check matrix, and K ldpc_b This represents the number of column blocks in the information word portion of the parity check matrix. In Equation 3 above, n equals N. ldpc_b And m equals (N) ldpc_b -K ldpc_b ).

[0270] When the number of segments is set to C, the value of C can be represented by the following equation 18.

[0271] [Equation 18]

[0272] C = [B / K] max ]

[0273] In equation 18 above, K max The value represents the maximum number of input bits of the LDPC code when the Z value of the LDPC code is maximized. For example, it can be shown in Table 21 above. K max The value varies depending on the code rate to be applied. Typically, in order to transmit data in a system, the modulation and coding scheme (MCS) is determined based on channel conditions, and therefore it can be assumed that the code rate information is already defined. Therefore, the transmitting device uses K corresponding to the corresponding code rate. max value.

[0274] When the output bits of the code block segment are set to When r represents the r-th code block, and K r This represents the number of bits in the r-th code block.

[0275] Based on the number of input bits B of the segmented block and C in Equation 18 above, the transmitting device can obtain the J value as shown in Equation 19 below. The J value is the value that temporarily obtains the length of the code block before inserting padding bits. Therefore, the J value can be referred to as the size of the code block excluding padding bits.

[0276] [Equation 19]

[0277]

[0278] In the following text, the transmitting device adjusts J to K as the LDPC code. ldpc_b The product of the smallest Z value and the product of the smallest Z value. In the following text, it is assumed that in Equation 20 below, the smallest Z value is 27 and all other Z values ​​are multiples of 27.

[0279] [Equation 20]

[0280] or

[0281]

[0282] In equation 20 above, Z min ×K ldpc_b Equations 19 and 20 are the process for determining the number of information bits to be encoded using LDPC, and can be considered the same process as determining the LDPC code to be encoded. The above equations state that if the code block length J is greater than K... min And less than 2K min Then J / K min It is a number between 1 and 2, and therefore the number of information bits to be encoded is determined to be K' = 2K. min .

[0283] According to the equation, the transmitting device can fill in '0's so that the length of the code block is equal to the number of information word bits in the LDPC code. Therefore, in this disclosure, the number of bits K' of the LDPC encoded information word can be referred to as the length of the code block or the size of the code block.

[0284] Therefore, the transmitting device can calculate the number of "0" bits based on Equation 21 below. The number of padding bits is a multiple of the number of code blocks (=C) and the number of LDPC input bits. The number of padding bits is shown in Equation 21 below.

[0285] [Equation 21]

[0286] F'=K'×CB

[0287] This is the equation used to obtain the total number of padding bits, and the total number of information bits is calculated by multiplying the number of code blocks by the number of information bits to be LDPC encoded. Here, the number of bits to be padded with 0s can be calculated by subtracting the number of input bits.

[0288] Furthermore, in order to distribute the padding bits in each code block evenly where possible and to ensure that the number of padding bits in each code block is equal, the transmitting device obtains the number of code blocks such that the number of padding bits is equal to the number of padding bits. Equation 22 is shown below.

[0289] [Equation 22]

[0290] γ=F'mod C

[0291] In the following text, the transmitting device determines each code block K based on the values ​​derived from equations 18, 19, 20, 21, and 22 above. r The length of the padding bit at that location.

[0292] (C-γ) code blocks are composed of Each input bit and It consists of several padding bits. Therefore, the number of bits in a code block is as shown in Equation 23 below.

[0293] [Equation 23]

[0294] K r = [B / C] + F and F = [F′ / C]

[0295] The transmitting device is configured such that (γ) code blocks are generated by Each input bit and It consists of several padding bits. Therefore, the number of bits in a code block is as shown in Equation 24 below.

[0296] [Equation 24]

[0297] K r = [B / C] + F and F = [F′ / C]

[0298] In the above description, the case where there are no segments is as follows. Consider the number of blocks with padding bits as shown in Equation 25 below.

[0299] [Equation 25]

[0300]

[0301] The fill bit F can be obtained as shown in Equation 26 below.

[0302] [Equation 26]

[0303] F = K′ - B

[0304] The number of bits in a code block that includes padding bits is shown in Equation 27 below.

[0305] K r =B+F=K′

[0306] The operation can be described as follows.

[0307]

[0308]

[0309] Filler bit <null>It should be inserted at the end of each code block.

[0310]

[0311] In the above process, it is important to note that 27×K ldpc_b Substitute into K min middle.

[0312] As mentioned above, once segmented, all padded code blocks are of equal length. Equal lengths of segmented code blocks ensure that the encoding and decoding parameters of the LDPC code for each block are identical, thus reducing implementation complexity. Furthermore, if possible, the number of padded "0" bits in each code block is equal, resulting in excellent encoding performance. During this process, the difference in padded bits is only 1 bit.

[0313] Figure 18 The process according to an embodiment of the present disclosure is illustrated schematically.

[0314] In addition, the input bit K of the LDPC code ldpc equals K r And the size of the submatrix Z is as shown in Equation 28 below.

[0315] [Equation 28]

[0316]

[0317] The segmentation process is briefly arranged as follows.

[0318] The transmitting device identifies the number of input bits and then bases it on the maximum number K of LDPC input bits (or information bits) that can be encoded using the maximum parity check matrix given in the system. max To determine the number of code blocks.

[0319] Furthermore, the transmitting device can determine the size of the code block. That is, the transmitting device can determine the size based on the maximum number K of input bits (or information bits) that can be encoded using the minimum parity check matrix given in the system. min To determine the size of the code block.

[0320] Furthermore, the transmitting device determines the number of padding (shortening) bits based on the code block size. Additionally, the transmitting device can determine the parity check matrix to be used for actual LDPC encoding based on the code block size.

[0321] Next, the transmitting device applies as much padding (or shortening) as determined to determine the code block, and then LDPC encoding can be performed using the determined parity matrix.

[0322] The embodiments of this disclosure describe determining the parity check matrix based on the size of the code block, but the disclosure is not limited thereto. That is, the parity check matrix can be limited according to the range of the input bit size, and any method for determining the parity check matrix based on the input bit size can also be used.

[0323] When the number of LDPC codeword bits or the number of information bits in an LDPC code increases by a predetermined size, segmentation based on Table 21 and equations 18 to 28 above can be applied. For example, when applying an LDPC code with segmentation based on Table 21 and equations 18 to 28 above, given the number of three codeword bits or the number of information bits, the number of codeword bits increases continuously in intervals of 648 (e.g., 648, 1296, and 1944), and the number of information bits increases in K increments according to the code rate. min The interval continues to increase (e.g., K) min 2*K min and 3*K min (=K max )).

[0324] When the given number of information bits of the LDPC code increases at predetermined intervals such as Kmin, the process of determining the parity check matrix of the LDPC code based on Kmin during the segmentation process is simplified as shown in Equation 20 above. That is, it can be understood that the process of determining the parity check matrix is ​​determined using the size of the largest code block determined based on Equation 19 or Equation 20 above.

[0325] Next, embodiments of the segmentation method will be described when the given number of bits in the LDPC code or the number of information word bits in the LDPC code does not increase by a predetermined size.

[0326] First, when the number of input bits is B and B is greater than the preset value K. max Similarly, segmentation is applied. An example of segmentation based on the maximum number of input bits of the LDPC code will be described below.

[0327] First, in the embodiments of this disclosure, the maximum number K of the input bits of the LDPC code is... max The minimum number of information bits for LDPC codes is shown in Table 22 below.

[0328] [Table 22]

[0329] Code Rate <![CDATA[K max ]]> <![CDATA[K min ]]> 5 / 6 6480 540 3 / 4 5832 486 2 / 3 5184 432 1 / 2 3888 324 1 / 3 1620 540

[0330] For ease of explanation, the maximum number of information bits that can be encoded using the parity check matrix of each LDPC code given in the system is set to four, such as K. min 2×K min 3×K min and K max That is, since there are four given LDPC codes and K max It is 12×K min Therefore, it can be understood that the number of bits does not increase at predetermined intervals. As another embodiment, the number of LDPC codeword information bits can also be set to, for example, K. min 2*K min 3*K min 4*K min 5*K min and 7*K min (=K max ).

[0331] Similarly, Kmax is set to 12×K. min Table 22 above is merely an example, and K max It can be based on K min To set it.

[0332] When the number of segments is set to C, the value of C can be expressed as in Equation 18 above. In Equation 18 above, K max The value represents the maximum number of input bits for the LDPC code, corresponding to the case where the Z value of the LDPC code is at its maximum.

[0333] When the output bits of the code block segment are set to When r represents the r-th code block, and K r This represents the number of bits in the r-th code block.

[0334] Based on the number of input bits B and C in Equation 18 above, the transmitting device obtains the J value as shown in Equation 19 below. The J value is the value of the length of the code block temporarily obtained before inserting the padding bits, which can be referred to as the size of the code block excluding the padding bits mentioned above.

[0335] Next, the transmitting device can determine the size of the code block, determine the parity check matrix based on the size of the code block, and use the parity check matrix to perform LDPC encoding.

[0336] The segmentation process under the above conditions is briefly arranged as follows.

[0337] The transmitting device identifies the number of input bits and then encodes the maximum number K of LDPC input bits (or information bits) that can be encoded using the maximum parity check matrix given in the system. max To determine the number of code blocks.

[0338] Furthermore, the transmitting device can determine the size of the code block. That is, the transmitting device can determine the maximum number K of input bits (or information bits) that can be encoded using the minimum parity check matrix given in the system. min To determine the size of the code block.

[0339] Furthermore, the transmitting device determines the number of padding (shortening) bits based on the code block size. Additionally, the transmitting device can determine the parity check matrix to be used for actual LDPC encoding based on the code block size.

[0340] Next, the transmitting device can apply as much padding (or shortening) as the determined amount to determine the code block, and then use the determined parity matrix for LDPC encoding.

[0341] However, as mentioned above, the parity check matrix can be defined according to the range of the input bit size, and methods for determining the parity check matrix based on the input bit size can also be available.

[0342] Meanwhile, it can be understood that, unlike the aforementioned segmentation method, the process of determining the parity check matrix of the LDPC code based on the code block size during the segmentation process requires the application of different methods for determining the range of J, where J is the size of the code block excluding the number of padding bits. For example, in examples where the number of LDPC codeword information bits is set to Kmin, 2*Kmin, 3*Kmin, 5*Kmin (=Kmax), the method used to determine K' can differ depending on whether the value of J is greater than or not greater than 3*Kmin.

[0343] That is, the maximum number of information bits that can be encoded using the parity check matrix of each LDPC code given in the system does not increase uniformly, and when the increase range meets a predetermined condition, it can be understood that there are at least two different methods to determine K' or the parity check matrix, depending on the range of J values ​​which is the size of the maximum code block.

[0344] Specifically, when the number of code blocks is 1, if the number of input bits is less than 3Kmin, the transmitting device can determine K' using the aforementioned method. On the other hand, if the number of input bits is greater than 3Kmin, K' can be determined as Kmax. Therefore, in this case, the transmitting device can fill all remaining bits except for the number of input bits at Kmax with 0.

[0345] On the other hand, when the number of code blocks is 2, different methods can be used to determine the parity check matrix based on the range of J values, which are the size of the code block in addition to the number of padding bits.

[0346] When J is less than 3×Kmin, based on The transmitting device can determine the number K' of information bits to be encoded using LDPC. Details are as described above.

[0347] On the other hand, when J is greater than 3 × Kmin, as mentioned above, K' can be determined as Kmax. The detailed piecewise process can be represented as follows.

[0348]

[0349]

[0350] Fill white space <null>It should be inserted at the end of each code block.

[0351]

[0352] However, in the foregoing embodiments of this disclosure, the following process can be omitted depending on the value of Kmax.

[0353] if J≤3K min

[0354]

[0355] else

[0356] For example, the maximum number of information bits that can be used for LDPC encoding using the parity check matrix of each LDPC code given in the system can be set to four, such as Kmin, 2×Kmin, 3×Kmin, and 12×kmin (=Kmax). Next, when B > 12×Kmin, C > 1 is established. In this case, it is obvious that B / C is always equal to or greater than 6×Kmin. Therefore, the process does not need to consider the case where the J value is less than 3×Kmin.

[0357] The following section describes another process for segmenting based on the range of J values.

[0358] Figure 19 This is a diagram illustrating another segment of the process according to an embodiment of the present disclosure.

[0359] Unlike the above, Figure 19 A method is described for LDPC encoding based on a range of J values ​​without being certain whether the number of code blocks is greater than 1.

[0360] refer to Figure 19 In operation S1910, the transmitting device can determine the number of code blocks. As described above, the transmitting device can determine the number of code blocks based on the number of input bits and the maximum number of LDPC input bits (or information bits), Kmax.

[0361] Furthermore, in operation S1920, the transmitting device may determine J as a temporary value for the code block size before inserting padding bits. In this case, when the number of code blocks is 1, the number of input bits can be J. The process of determining J is the same as described above and will be omitted below.

[0362] Furthermore, in operation S1930, the transmitting device can determine whether the J value is equal to or less than a reference value. In this case, the reference value can refer to the second largest number of LDPC input bits.

[0363] If the J value is equal to or less than the reference value, then in operation S1940, the transmitting device can determine the size of the code block based on the first rule.

[0364] At this point, the first rule could refer to using equations. A method for determining the size of a code block.

[0365] On the other hand, if the J value is greater than the reference value, then in operation S1950, the transmitting device can determine the size of the code block based on the second rule. In this case, the second rule refers to the method of setting Kmax as the size of the code block.

[0366] In this case, operations S1940 and S1950 can be replaced by a process of determining the parity check matrix or the sequence corresponding to it for applying the LDPC encoding or exponential matrix.

[0367] Operations S1940 and S1950 are described by way of example, where the number of LDPC codeword information bits is limited to Kmin, 2*Kmin, 3*Kmin, 4*Kmin, 5*Kmin, and 7*Kmin (=Kmax), with a reference value of 5Kmin. Therefore, when the input bit size is 9Kmin, J is 4.5Kmin, and J is less than 5Kmin, and thus the transmitting device can determine the code block size according to the first rule. On the other hand, when the input bit size is 12Kmin, J is 6Kmin, and J is less than 5Kmin, and thus the transmitting device can determine the code block size according to the second rule.

[0368] To illustrate another example, the number of LDPC codeword information bits is limited to Kmin, 2*Kmin, 3*Kmin, and 12*Kmin (=Kmax), with 3Kmin as a reference value. If the input bit size is 14Kmin, then J is 7Kmin, and J is greater than 3Kmin, and therefore the transmitting device can determine the code block size according to the second rule.

[0369] On the other hand, when the size of the input bits is 2.5Kmin, the number of code blocks is 1, and therefore J is 2.5Kmin, and the transmitting device can determine the size of the code blocks according to the first rule.

[0370] Next, in operation S1960, the transmitting device can determine the number of padding bits based on the size of the code block.

[0371] Furthermore, the transmitting device can configure the code block in S1970 and perform LDPC encoding in operation S1980. At this time, the transmitting device can use a parity check matrix determined based on the code block size to perform LDPC encoding.

[0372] However, when the number of LDPC codeword information bits increases at predetermined intervals, operations S1930 and S1950 can be omitted.

[0373] Figure 20 This is a diagram illustrating another process of segmentation according to an embodiment of the present disclosure.

[0374] and Figure 19 The difference lies in Figure 20 In this process, it is determined whether the number of code blocks is greater than 1. However, this method can be applied when Kmax is twice the reference value. In this case, the reference value can refer to the second largest number of LDPC input bits.

[0375] refer to Figure 20 In operation S2010, the transmitting device can determine the number of code blocks. As described above, the transmitting device can determine the number of code blocks based on the number of input bits and the maximum number Kmax of LDPC input bits (or information bits).

[0376] Furthermore, during operation S2020, the transmitting device can identify whether the number of code blocks is 1.

[0377] At this point, when the number of code blocks is not 1, in operation S2030, the transmitting device can determine the size of the code block based on the second rule. That is, the transmitting device can determine Kmax as the size of the code block.

[0378] The reason is that when Kmax is equal to or greater than twice the reference value and the number of code blocks is equal to or greater than 2, there is no case where the length of the code block is less than the reference value. For example, when the number of LDPC codeword information bits is set to Kmin, 2*Kmin, 3*Kmin, and 12*Kmin (=Kmax), in order for the number of code blocks to be equal to or greater than 2, the number of input bits needs to exceed 12Kmin. In this case, the J value exceeds 6Kmin, and therefore the size of the code block can also be determined as Kmax.

[0379] On the other hand, when the number of code blocks is 1, in operation S2040, the transmitting device can determine whether J is equal to or less than a reference value. J is a temporary value of the size of the code block before inserting padding bits, and the number of code blocks is 1, so the number of input bits can be J. The process of determining J is the same as described above and will be omitted below.

[0380] If the J value is equal to or less than the reference value, the transmitting device can determine the size of the code block based on the first rule in operation S2060.

[0381] At this point, the first rule could refer to using equations. A method for determining the size of a code block.

[0382] On the other hand, if the J value is greater than the reference value, the transmitting device can determine the size of the code block based on the second rule in operation S2050. In this case, the second rule refers to the method of setting Kmax as the size of the code block.

[0383] In this case, operations S2030, S2050, and S2060 can be replaced by a process of determining the parity check matrix or the sequence corresponding to it for applying the LDPC encoding or exponential matrix.

[0384] Another example describing operations S2050 and S2060 involves limiting the number of LDPC codeword information bits to Kmin, 2*Kmin, 3*Kmin, and 12*Kmin (=Kmax), with 3Kmin as a reference value. If the input bit size is 6Kmin, then J is 6Kmin, and J is greater than 3Kmin, therefore the transmitting device can determine the code block size as 12Kmin according to the second rule. On the other hand, when the input bit size is 2.5Kmin, J is 2.5Kmin, and the transmitting device can determine the code block size as 3Kmin according to the first rule.

[0385] Next, in operation S2070, the transmitting device can determine the number of padding bits based on the size of the code block.

[0386] Furthermore, the transmitting device can configure the code block in S2080 and perform LDPC encoding in operation S2090. At this time, the transmitting device can use a parity check matrix determined based on the code block size for LDPC encoding.

[0387] The decoding process can be implemented by reversing the encoding process. For example, first, the receiving device determines the size of the input bits before segmentation from the signal received by the receiver. The non-segmented input bits applied by the system are called transport blocks (or transmission blocks). Next, the receiving device can determine the size of the code block. At this point, based on the maximum number Kmin of input bits (information bits) that can be encoded using the minimum parity check matrix given in the system, the receiving device can determine the size of the code block.

[0388] Furthermore, the receiving device determines the number of padding (shortening) bits based on the code block size. The parity matrix used for LDPC encoding can also be determined based on the code block size, but it can also be determined based on the transport block size. That is, the parity matrix to be used can be limited according to the size of the input bits before segmentation, and the parity matrix can be determined based on the size of the input bits before segmentation.

[0389] In addition, generally, the received signal includes MCS information for transmission and information on the size of a given system resource, and thus the parity check matrix can also be determined based on the system resource size information.

[0390] If the parity check matrix is determined, padding (or shortening) is applied as many as the determined number of padding (or shortening) bits to determine a code block for LDPC decoding, and based on the MCS information and / or the system resource size information and the size of the determined code block, the total number of encoded bits for transmitting one code block is determined for decoding.

[0391] Meanwhile, the parity check matrix proposed by the present disclosure can be represented by other matrices or sequences that mathematically derive the same result. That is, a matrix or sequence changed by an operation using the characteristics of the matrix in the parity check matrix proposed in the present disclosure can be determined to be the same as the matrix proposed in the present disclosure. The input bits of the rate matcher 440 are C = (i0, i1, i2, …, iKldpc-1, p0, p1, p2, …, pNldpc-Kldpc-1) which are the output bits of the LDPC encoder 430. And ik (0 ≤ k < Kldpc) refers to the input bits of the LDPC encoder 430, and pk (0 ≤ k < Nldpc-Kldpc) refers to the LDPC parity bits. The rate matcher 440 includes an interleaver 441 and a puncturing / repeating / zero-removing unit 442.

[0392] The modulator 450 modulates the bit string output from the rate matcher 440 and transmits the modulated bit string to a receiving device (e.g., Figure 5 500).

[0393] Specifically, the modulator 450 can demultiplex the bits output from the rate matcher 440 and map the demultiplexed bits to a constellation.

[0394] That is, the modulator 450 can perform serial-to-parallel conversion on the bits output from the rate matcher 440 and generate units composed of a predetermined number of bits. Here, the number of bits configuring each unit can be equal to the number of bits configuring the modulation symbol mapped to the constellation.

[0395] Next, modulator 450 can map the demultiplexed bits to clusters. That is, modulator 450 can modulate the demultiplexed bits using various modulation schemes such as Quadrature Phase Shift Keying (QPSK), 16-Quadrature Amplitude Modulation (QAM), 64-QAM, 256-QAM, and 1024-QAM to generate modulation symbols and 4096-QAM, and then map the generated modulation symbols to cluster points. In this case, the demultiplexed bit configuration contains units of bits corresponding to the number of modulation symbols, and therefore each unit can be mapped to cluster points sequentially.

[0396] Furthermore, modulator 450 can modulate the signal mapped to the cluster and transmit the modulated signal to receiver 500. For example, modulator 450 can use an OFDM scheme to map the signal mapped to the cluster to an orthogonal frequency division multiplexing (OFDM) frame and transmit the mapped signal to receiver 500 through an allocated channel.

[0397] Simultaneously, the transmitting device 400 can pre-store various parameters for encoding, interleaving, and modulation. Here, the parameters for encoding can be information about the code rate, codeword length, and parity check matrix of the LDPC code. Furthermore, the parameters for interleaving can be information about the interleaving rules, and the parameters for modulation can be information about the modulation scheme. Additionally, the information about puncturing can be the puncturing length. Furthermore, the information about repetition can be the repetition length. When using the parity matrix proposed in this disclosure, the information about the parity check matrix can be stored as the exponent value of the cyclic matrix according to the above equations—Equation 3 or Equation 4.

[0398] In this case, each component of the transmission device 400 can be configured to operate using this parameter.

[0399] Additionally, although not shown, in some cases, the transmitting device 400 may also include a controller (at least one processor) (not shown) for controlling the operation of the transmitting device 400.

[0400] Figure 8 This is a block diagram illustrating the configuration of an encoding device according to an embodiment of the present disclosure. In this configuration, the encoding device 800 can perform LDPC encoding.

[0401] refer to Figure 8 The encoding device 800 includes an LDPC encoder 810. The LDPC encoder 810 can perform LDPC encoding on the input bits based on the parity check matrix to generate LDPC codewords.

[0402] Kldpc bits can form K ldpc Each LDPC information word Used for LDPC encoder 810. LDPC encoder 810 can systematically process K... ldpc Each LDPC information word is LDPC encoded to generate a result consisting of N bits. ldpc LDPC codeword composed of bits The generation process includes determining the codeword such that, as expressed by Equation 1 above, the product of the LDPC codeword and the parity check matrix is ​​a zero vector. The parity check matrix of this disclosure can have the same properties as... Figure 3 The structure is the same as the parity check matrix specified in the middle.

[0403] In this case, the LDPC encoder 810 can use different defined parity check matrices to perform LDPC encoding based on the code rate (i.e., the code rate of the LDPC code).

[0404] For example, when the code rate is 8 / 9, the LDPC encoder 810 can use the parity check matrix defined by the exponent matrix shown in Table 1 above for LDPC encoding, and when the code rate is 2 / 3, it can use the parity check matrix defined by the exponent matrix shown in Table 2 above for LDPC encoding. Furthermore, when the code rate is 4 / 9, the LDPC encoder 810 can use the parity check matrix defined by the exponent matrix table shown in Table 3 above for LDPC encoding.

[0405] Meanwhile, a detailed method for performing LDPC encoding has been described, and therefore detailed overlapping descriptions will be omitted.

[0406] Additionally, the encoding device 800 may include a memory (not shown) for pre-storing information about the code rate, codeword length, and parity check matrix of the LDPC code, and the LDPC encoder 810 may use this information to perform LDPC encoding. When using the parity check matrix proposed in this disclosure, the information about the parity check matrix may store information about the exponent value of the cyclic matrix.

[0407] In the following text, reference will be made to Figure 5 Describe the operation of the receiver in detail.

[0408] Demodulator 510 demodulates the signal received from transmitter 400.

[0409] In detail, demodulator 510 is corresponding to Figure 4 The modulator 400 of the transmitting device 400 is a component that can demodulate the signal received from the transmitting device 400 and generate a value corresponding to the bit transmitted from the transmitting device 400.

[0410] Therefore, the receiving device 500 can pre-store information about the modulation scheme of the modulated signal according to the pattern in the transmitting device 400. Thus, the demodulator 510 can demodulate the signal received from the transmitting device 400 according to this pattern to generate values ​​corresponding to the LDPC codeword bits.

[0411] Meanwhile, the value corresponding to the bit transmitted from transmitting device 400 can be a log likelihood ratio (LLR) value. Specifically, the LLR value can be represented by a value obtained by applying Log to the ratio of the probability that the bit transmitted from transmitting device 300 is 0 to the probability that the bit transmitted from transmitting device 300 is 1. Alternatively, the LLR value can be the bit value itself, and the LLR value can be a representation determined based on the probability that the bit transmitted from transmitting device 300 is 0 and the segment to which the bit transmitted from transmitting device 300 is 1 belongs.

[0412] refer to Figure 5 The demodulator 510 includes a process for multiplexing LLR values ​​(not shown). Specifically, the demodulator 510 is a component corresponding to the bit demultiplexer (not shown) of the transmitting device 400, and can perform operations corresponding to the bit demultiplexer (not shown).

[0413] For this purpose, the receiving device 500 may pre-store information about parameters used by the transmitting device 400 for demultiplexing and block interleaving. Therefore, the multiplexer (not shown) can reverse the demultiplexing and block interleaving operations performed by the bit demultiplexer (not shown) with respect to the LLR value corresponding to the cell word, in order to multiplex the LLR value corresponding to the cell word in the bit cell.

[0414] Rate dematcher 520 can insert LLR values ​​into the LLR values ​​output from demodulator 510. In this case, rate dematcher 520 can insert previously promised LLR values ​​between the LLR values ​​output from demodulator 510.

[0415] Specifically, the rate demodulator 520 is the rate matcher 440 corresponding to the transmitting device 400. Figure 4 The component shown can perform operations corresponding to interlacing 441 and zero removal and perforation / repetition / zero removal 442.

[0416] First, the rate dematcher 520 performs deinterleaving 521 corresponding to the interleaver 441 of the transmitter. The output value of deinterleaving 521 can insert the LLR value corresponding to the zero bit into the position where the zero bit is filled in the LDPC codeword. In this case, the LLR value corresponding to the filled zero bit (i.e., the shortened zero bit) can be ∞ or -∞. However, ∞ or -∞ are theoretical values, but can actually be the maximum or minimum value of the LLR value used in the receiving device 500.

[0417] For this purpose, the receiving device 500 can pre-store information about parameters used by the transmitting device 400 to fill zeros. Therefore, the rate dematcher 520 can determine the position of the filled zeros in the LDPC codeword and insert the LLR value corresponding to the shortened zero into the corresponding position.

[0418] Furthermore, the LLR inserter 520 of the rate dematcher 520 can insert the LLR value corresponding to the punch bit into the position of the punch bit in the LDPC codeword. In this case, the LLR value corresponding to the punch bit can be 0.

[0419] For this purpose, the receiving device 500 can pre-store information about the parameters used by the transmitting device 400 for punching. Therefore, the LLR inserter 522 can insert the corresponding LLR value into the parity position of the punched LDPC bit.

[0420] LLR combiner 523 can combine, that is, sum the LLR values ​​output from LLR inserter 522 and demultiplexer 510. Specifically, LLR combiner 523 is a component corresponding to punch / repeat / zero remover 442 of transmitting device 400, and can perform operations corresponding to repeater or punch / repeat / zero remover 442. First, LLR combiner 523 can combine the LLR value corresponding to the repeat bit with other LLR values. Here, other LLR values ​​can be bits that form the basis for generating the repeat bit in transmitting device 400, that is, the LLR value of the LDPC parity bit selected as the repeat target.

[0421] That is, as described above, the transmitting device 400 selects bits from the LDPC parity bits, repeats the selected bits between the LDPC information bits and the LDPC parity bits, and sends the repeated bits to the receiving device 500.

[0422] As a result, the LLR value of the LDPC parity bit can be composed of the LLR values ​​of repeated LDPC parity bits and the LLR values ​​of non-repeating LDPC parity bits (i.e., LDPC parity bits generated by encoding). Therefore, LLR combiners 523 and 2640 can combine LLR values ​​with the same LDPC parity bits.

[0423] For this purpose, the receiving device 500 can pre-store information about the parameters used by the transmitting device 400 for repetition. Therefore, the LLR combiner 523 can determine the LLR value of the repeated LDPC parity bit and combine the determined LLR value with the LLR value of the LDPC parity bit as the basis for repetition.

[0424] Furthermore, the LLR combiner 523 can combine the LLR value corresponding to the retransmitted bit or incremental redundancy (IR) bit with other LLR values. Here, the other LLR values ​​can be the LLR values ​​of the bits selected for generating the LDPC codeword bits, which are the basis for generating the retransmitted bit or IR bit in the transmitting device 400.

[0425] That is, as described above, when generating a negative acknowledgment (NACK) for HARQ, the transmitting device 400 may send some or all of the codeword bits to the receiving device 500.

[0426] Therefore, the LLR combiner 523 can combine the LLR values ​​of bits received by retransmission or IR with the LLR values ​​of LDPC codeword bits received by the previous frame.

[0427] For this purpose, the receiving device 500 can pre-store information about parameters used by the transmitting device to generate retransmitted bits or IR bits. As a result, the LLR combiner 523 can determine the LLR value of the number of retransmitted bits or IR bits and combine the determined LLR value with the LLR value of the LDPC parity bit, which serves as the basis for generating the retransmitted bits.

[0428] Deinterleaver 524 can deinterleave the LLR values ​​output from LLR combiner 523.

[0429] In detail, the deinterleaver 524 is a component corresponding to the interleaver 441 of the transmitting device 400, and can perform operations corresponding to the interleaver 441.

[0430] For this purpose, the receiving device 500 can pre-store information about the parameters used by the transmitting device 400 for interleaving. As a result, the deinterleaver 524 can perform reverse interleaving operations on the LLR values ​​corresponding to the LDPC codeword bits by the interleaver 441 to deinterleave the LLR values ​​corresponding to the LDPC codeword bits.

[0431] The LDPC decoder 530 can perform LDPC decoding based on the LLR value output from the rate dematcher 520.

[0432] For details, please refer to Figure 4 and Figure 5 The LDPC decoder 530 is a component corresponding to the LDPC encoder 430 of the transmitting device 400, and can perform operations corresponding to the LDPC encoder 430.

[0433] For this purpose, the receiving device 500 can pre-store information about the parameters used by the transmitting device 400 to perform LDPC encoding according to the pattern. As a result, the LDPC decoder 530 can perform LDPC decoding based on the LLR value output from the rate dematcher 520 according to the pattern.

[0434] For example, the LDPC decoder 530 can perform LDPC decoding based on the LLR value output from the rate dematcher 520 using an iterative decoding scheme based on the sum-product algorithm, and output error correction bits based on the LDPC decoding.

[0435] The zero remover 540 can remove zero bits from the bits output from the LDPC decoders 2460 and 2560.

[0436] In detail, the zero remover 540 is a component corresponding to the zero filler 420 of the transmitting device 400, and can perform operations corresponding to the zero filler 420.

[0437] For this purpose, receiving device 500 can pre-store information about parameters used by transmitting device 400 to fill zero bits. As a result, zero remover 540 can remove zero bits filled by zero filler 420 from the bits output from LDPC decoder 530.

[0438] The desegmenter 550 is a component corresponding to the segmenter 410 of the transmitting device 400, and can perform operations corresponding to the segmenter 410.

[0439] For this purpose, receiving device 500 can pre-store information about the parameters used by transmitting device 400 for segmentation. As a result, desegmenter 550 can combine the bits output from zero canceller 540 (i.e., segments of variable-length input bits) to recover the bits before segmentation.

[0440] Figure 9 This is a block diagram illustrating the configuration of a decoding device according to an embodiment of the present disclosure. Reference Figure 9 The decoding device 900 may include an LDPC decoder 910. Simultaneously, the decoding device 900 may also include a memory (not shown) for pre-storing information regarding the code rate, codeword length, and parity matrix of the LDPC code, and the LDPC decoder 910 can use this information to perform LDPC encoding. However, this is merely an example, and the corresponding information could also be provided from the transmitting device.

[0441] The LDPC decoder 910 performs LDPC decoding on LDPC codewords based on the parity check matrix.

[0442] For example, the LDPC decoder 910 can use an iterative decoding algorithm to pass the LLR value corresponding to the LDPC codeword bit for LDPC decoding, thereby generating the information bit.

[0443] Here, the LLR value is the channel value corresponding to the LDPC codeword bit, and it can be represented by various methods.

[0444] For example, the LLR value can be represented by a value obtained by applying Log to the ratio of the probability of a bit being 0 transmitted from the transmitting side through the channel to the probability of a bit being 1 transmitted from the transmitting side through the channel. Furthermore, the LLR value can be the bit value itself determined by soft decision, and the LLR value can be a representation determined based on the portion to which the probability of a bit being 0 or 1 transmitted from the transmitting side belongs.

[0445] In this case, such as Figure 8 As shown, the transmitting side can use the LDPC encoder 810 to generate LDPC codewords.

[0446] Meanwhile, the parity check matrix used in LDPC decoding can have the same properties as... Figure 3 The parity check matrix shown has the same form.

[0447] In this case, refer to Figure 9 The LDPC decoder 910 can perform LDPC decoding using a parity check matrix that is differently defined according to the code rate (i.e., the code rate of the LDPC code).

[0448] For example, when the bit rate is 8 / 9, the LDPC decoder 910 can use the parity check matrix defined in Table 1 above for LDPC decoding, and when the bit rate is 2 / 3, it can use the parity check matrix defined in Table 2 above for LDPC decoding. Furthermore, when the bit rate is 4 / 9, the LDPC decoder 910 can use the parity check matrix defined in Table 3 above for LDPC decoding.

[0449] Figure 10 A structural diagram of an LDPC decoder according to another embodiment of the present disclosure is shown.

[0450] Furthermore, as mentioned above, the LDPC decoder 910 can use an iterative decoding algorithm to perform LDPC decoding. In this case, the LDPC decoder 910 can be configured to have, for example... Figure 10 The structure shown. However, iterative decoding algorithms are already known, and therefore... Figure 10 The detailed configuration shown is just an example.

[0451] refer to Figure 10 The decoding device 1000 includes an input processor 1011, a memory 1012, a variable node arithmetic unit 1013, a controller 1014 (at least one processor), a verification node arithmetic unit 1015, and an output processor 1016.

[0452] Input processor 1011 stores input values. Specifically, input processor 1011 can store the LLR value of a signal received via a radio channel.

[0453] Based on the parity check matrix corresponding to the code rate, the number of values ​​input to the check node 1015, and the address values ​​in the memory 1012, the controller 1014 determines the block size (i.e., codeword length) of the signal received through the radio channel, the number of values ​​input to the variable node arithmetic unit, and the address values ​​in the memory 1012.

[0454] According to embodiments of this disclosure, the index corresponding to the row in the 0th column of the i-th column group can be decoded based on the parity check matrix determined by the index matrix as shown in Tables 1 to 3 above.

[0455] The memory 1012 stores the input and output data of the variable node arithmetic unit 1013 and the check node arithmetic unit 1015.

[0456] Based on the address information and quantity information of the input data received from the controller 1014, the variable node arithmetic unit 1013 receives data from the memory 1012 to perform variable node operations. Next, based on the address information and quantity information of the output data received from the controller 1014, the variable node arithmetic unit 1013 stores the result of the variable node operation in the memory 1012. Furthermore, based on the data received from the input processor 1011 and the memory 1012, the variable node arithmetic unit 1013 inputs the result of the variable node operation to the output processor 1016. (Here, reference has been made to...) Figure 8 It describes the operation of variable nodes.

[0457] Based on the address information and quantity information of the input data received from the controller 1014, the verification node arithmetic unit 1015 receives data from the memory 1012 to perform variable node operations. Next, based on the address information and quantity information of the output data received from the controller 1014, the verification node arithmetic unit 1015 stores the result of the variable node operations in the memory 1012. (Here, reference has been made...) Figure 6 The operation of the verification node is described.

[0458] The output processor 1016 performs a soft determination on whether the information bit on the transmitting side is 0 or 1 based on the data received from the variable node arithmetic unit 1013, and then outputs the result of the soft determination, so that the output value of the output processor 1016 is ultimately the decoded value. In this case, Figure 6 In this context, soft decision-making can be performed based on the sum of all message values ​​input to a variable node (the initial message value and all message values ​​input from the verification node).

[0459] According to embodiments of this disclosure, LDPC codes applicable to variable lengths and variable rates can be supported.

[0460] Although this disclosure has been shown and described with reference to various embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents.< / null> < / null>

Claims

1. A method for quasi-cyclic low-density parity-check (QC-LDPC) channel coding, the method comprising: Determine the number of input bits; The number of code blocks is determined based on the number of input bits and the maximum number of information bits. The size of a code block is determined based on the number of code blocks; The padding bits are determined based on the size of the code block; The code block is determined based on at least a portion of the input bits and the padding bits; The lift size Z is determined based on the size of the code block; The parity check matrix is ​​determined based on the lifting size Z; as well as The code block is encoded at least in part based on the parity check matrix. The parity check matrix consists of a matrix of size 1. A zero matrix, multiple matrices of size identity matrix or multiple identity matrices of size It consists of cyclic permutation matrices, and Each of them has a size of The cyclic permutation matrix is ​​obtained by cyclically shifting the identity matrix based on the modulus lift of the lifting size Z and the values ​​included in the exponent matrix.

2. The method as described in claim 1, in, The parity check matrix is ​​determined based on the following matrix, which indicates the position of 1 in the parity check matrix, and The following matrices indicate the concatenation of A and A' and B and B': 。 3. The method as described in claim 1, wherein, Determining the fill bit includes: The total number of padding bits is determined based on the size of the code block and the number of input bits; and The number of padding bits to be applied to each code block is determined based on the total number of padding bits. The number of code blocks is based on Sure, Wherein, the size of the code block, excluding the number of padding bits, is based on Sure, Wherein, the size of the code block is based on Sure, Wherein, the total number of the fill bits is based on Confirmed, and Wherein, C indicates the number of code blocks, B indicates the number of input bits, Kmax indicates the maximum number of information bits corresponding to the first parity check matrix, J indicates the size of the code block excluding the number of padding bits, K' indicates the size of the code block, F' indicates the total number of padding bits, and Kmin indicates the maximum number of information bits corresponding to the second parity check matrix.

4. A method for decoding a quasi-cyclic low-density parity-check (QC-LDPC) channel, the method comprising: Receive signal; Determine the value corresponding to at least a portion of the codeword from the received signal; The number of input bits is determined from the received signal before segmentation; The number of code blocks is determined based on the number of input bits and the maximum number of information bits. The size of a code block is determined based on the number of code blocks; The lift size Z is determined based on the size of the code block; The parity check matrix is ​​determined based on the lifting size Z; The position of the padding bits in the codeword is determined based on the input bits and the size of the code block. as well as The input bits are determined based on LDPC decoding, at least in part based on the parity check matrix, the positions of the padding bits, and the values ​​corresponding to at least a portion of the codeword. The parity check matrix consists of a matrix of size 1. A zero matrix, multiple matrices of size identity matrix or multiple identity matrices of size It consists of cyclic permutation matrices, and Each of them has a size of The cyclic permutation matrix is ​​obtained by cyclically shifting the identity matrix based on the modulus lift of the lifting size Z and the values ​​included in the exponent matrix.

5. The method as described in claim 4, in, The parity check matrix is ​​determined based on the following matrix, which indicates the position of 1 in the parity check matrix, and The following matrices indicate the concatenation of A and A' and B and B': 。 6. The method as described in claim 4, in, Determining the position of the fill bit includes: The total number of padding bits is determined based on the size of the code block and the number of input bits, and The number of padding bits to be applied to each code block is determined based on the total number of padding bits. The number of code blocks is based on Sure, Wherein, the size of the code block, excluding the number of padding bits, is based on Sure, Wherein, the size of the code block is based on Sure, Wherein, the total number of the fill bits is based on Confirmed, and Wherein, C indicates the number of code blocks, B indicates the number of input bits, Kmax indicates the maximum number of information bits corresponding to the first parity check matrix, J indicates the size of the code block excluding the number of padding bits, K' indicates the size of the code block, F' indicates the total number of padding bits, and Kmin indicates the maximum number of information bits corresponding to the second parity check matrix.

7. An apparatus for quasi-cyclic low-density parity-check (QC-LDPC) channel coding, the apparatus comprising: transceiver; as well as At least one processor, configured as follows: Identify the number of input bits. The number of code blocks is determined based on the number of input bits and the maximum number of information bits. The size of a code block is determined based on the number of code blocks. The padding bits are determined based on the size of the code block. The code block is determined based on at least a portion of the input bits and the padding bits. The lift size Z is determined based on the size of the code block; The parity check matrix is ​​determined based on the increase in size Z, and The code block is encoded at least in part based on the parity check matrix. The parity check matrix consists of a matrix of size 1. A zero matrix, multiple matrices of size identity matrix or multiple identity matrices of size It consists of cyclic permutation matrices, and Each of them has a size of The cyclic permutation matrix is ​​obtained by cyclically shifting the identity matrix based on the modulus lift of the lifting size Z and the values ​​included in the exponent matrix.

8. The device as described in claim 7, in, The parity check matrix is ​​determined based on the following matrix, which indicates the position of 1 in the parity check matrix, and The following matrices indicate the concatenation of A and A' and B and B': 。 9. The device as described in claim 7, in, The at least one processor is further configured to: The total number of padding bits is determined based on the size of the code block and the number of input bits, and The number of padding bits to be applied to each code block is determined based on the total number of padding bits. The number of code blocks is based on Sure, Wherein, the size of the code block, excluding the number of padding bits, is based on Sure, Wherein, the size of the code block is based on Sure, The total number of padding bits is based on Confirmed, and Wherein, C indicates the number of code blocks, B indicates the number of input bits, Kmax indicates the maximum number of information bits corresponding to the first parity check matrix, J indicates the size of the code block excluding the number of padding bits, K' indicates the size of the code block, F' indicates the total number of padding bits, and Kmin indicates the maximum number of information bits corresponding to the second parity check matrix.

10. An apparatus for decoding a quasi-cyclic low-density parity-check (QC-LDPC) channel, the apparatus comprising: transceiver; as well as At least one processor, configured as follows: Signals are received via transceiver. Determine the value corresponding to at least a portion of the codeword from the received signal. The number of input bits is determined from the received signal before segmentation. The number of code blocks is determined based on the number of input bits and the maximum number of information bits. The size of a code block is determined based on the number of code blocks. The lift size Z is determined based on the size of the code block; The parity check matrix is ​​determined based on the increase in size Z. The position of the padding bits in the codeword is determined based on the input bits and the size of the code block, and The input bits are determined based on LDPC decoding, at least in part based on the parity check matrix, the positions of the padding bits, and the values ​​corresponding to at least a portion of the codeword. The parity check matrix consists of a matrix of size 1. A zero matrix, multiple matrices of size identity matrix or multiple identity matrices of size It consists of cyclic permutation matrices, and Each of them has a size of The cyclic permutation matrix is ​​obtained by cyclically shifting the identity matrix based on the modulus lift of the lifting size Z and the values ​​included in the exponent matrix.

11. The device as claimed in claim 10, in, The parity check matrix is ​​determined based on the following matrix, which indicates the position of 1 in the parity check matrix, and The following matrices indicate the concatenation of A and A' and B and B': 。 12. The device as claimed in claim 10, in, The at least one processor is further configured to: The total number of padding bits is determined based on the size of the code block and the number of input bits, and The number of padding bits to be applied to each code block is determined based on the total number of padding bits. The number of code blocks is based on Sure, Wherein, the size of the code block, excluding the number of padding bits, is based on Sure, Wherein, the size of the code block is based on Sure, Wherein, the total number of the fill bits is based on Confirmed, and Wherein, C indicates the number of code blocks, B indicates the number of input bits, Kmax indicates the maximum number of information bits corresponding to the first parity check matrix, J indicates the size of the code block excluding the number of padding bits, K' indicates the size of the code block, F' indicates the total number of padding bits, and Kmin indicates the maximum number of information bits corresponding to the second parity check matrix.

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