Use of a virtual mirror for a vehicle

Abstract

This invention relates to the use of automotive virtual mirrors. A system, method, and computer-readable medium may include techniques for optimal use of automotive virtual mirrors. A gaze detector monitors the driver's eyes to determine whether the driver is looking in the direction of the virtual mirror. If the driver is not looking in the direction of the virtual mirror, all virtual mirrors are placed in a low operating mode. If the driver is looking in the direction of one of the virtual mirrors, the virtual mirror being viewed is placed in a high operating mode and all other virtual mirrors are placed in a low operating mode.

Description

Technical Field

[0001] The examples typically relate to automobiles, and more specifically to the optimal use of virtual mirrors in automobiles. Background Technology

[0002] Mirrors, found on the exterior and interior of cars, are used to help drivers see areas behind and to the sides of the vehicle. Typically, mirrors allow drivers to see objects outside their peripheral vision. Today, traditional rearview and side mirrors may be replaced by virtual mirrors. Attached Figure Description

[0003] Various advantages of the embodiments will become apparent to those skilled in the art from reading the following specification and appended claims and by referring to the following drawings, wherein:

[0004] Figure 1 This is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figures 2A-2D The figure illustrates a parallel processor component according to an embodiment;

[0006] Figures 3A-3B This is a block diagram of a graphics multiprocessor according to an embodiment;

[0007] Figures 4A-4F The figure illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0008] Figure 5 The figure illustrates a graphics processing pipeline according to an embodiment;

[0009] Figures 6A, 6B and 6C illustrate a conventional car with external side mirrors;

[0010] Figure 7A , Figure 7B The illustration shows a conventional car with an interior rearview mirror.

[0011] Figure 8 It is a diagram showing the driver's blind spot and the normal field of vision coverage using conventional side and rearview mirrors for automobiles;

[0012] Figure 9A This is a block diagram illustrating an example vehicle system for optimal power utilization of a virtual mirror in an automobile, according to an embodiment.

[0013] Figure 9B This is a block diagram illustrating an example virtual mirror according to an embodiment;

[0014] Figure 10This is a flowchart illustrating an example method for optimal power usage of a virtual mirror in a car according to an embodiment;

[0015] Figure 11 This is a block diagram of an example of a display with localized backlight capability according to an embodiment;

[0016] Figure 12A This is a block diagram of an example of a data processing device according to an embodiment;

[0017] Figure 12B This is an illustration of an example of distance determination according to an embodiment;

[0018] Figure 13 This is a block diagram illustrating an example of a layered display architecture according to an embodiment;

[0019] Figure 14 This is a block diagram illustrating an example display architecture including multiple display units according to an embodiment; and

[0020] Figure 15 This is a block diagram of an example cloud-assisted media delivery architecture according to an embodiment;

[0021] Figures 16-18 This is a block diagram illustrating an example of a data processing system according to an embodiment;

[0022] Figure 19 This is a block diagram of an example of a graphics processing engine according to an embodiment;

[0023] Figures 20-22 This is a block diagram of an example execution unit according to an embodiment;

[0024] Figure 23 This is a block diagram illustrating an example of a graphical pipeline according to an embodiment;

[0025] Figures 24A-24B This is a block diagram illustrating an example of graphical pipeline programming according to an embodiment;

[0026] Figure 25 This is a block diagram illustrating an example of a graphical software architecture according to an embodiment;

[0027] Figure 26 This is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0028] Figure 27 This is a block diagram of an example system on a chip integrated circuit according to an embodiment. Detailed Implementation

[0029] In the following description, numerous specific details are set forth to provide a more complete understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

[0030] System Overview

[0031] Figure 1 This diagram illustrates a block diagram of a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 communicating via interconnect paths, which may include a memory hub 105. The memory hub 105 may be a separate component within a chipset assembly or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller, which may be included in one or more processors 102, to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0032] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to a memory hub 105 via a bus or other communication link 113. The communication link 113 can be any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication architecture. In one embodiment, the one or more parallel processors 112 form a compute-intensive parallel or vector processing system comprising a large number of processing cores and / or processing clusters, such as multiple integrated core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem capable of outputting pixels to one of one or more display devices 110A coupled via an I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0033] Within the I / O subsystem 111, system storage unit 114 can be connected to I / O hub 107 to provide a storage mechanism for computing system 100. I / O switch 116 can be used to provide an interface mechanism to enable connectivity between I / O hub 107 and other components that can be integrated into the platform, such as network adapter 118 and / or wireless network adapter 119, as well as various other devices that can be added via one or more plug-in devices 120. Network adapter 118 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0034] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 107. Figure 1 The communication paths that interconnect the various components can be implemented using any suitable protocol, such as a PCI-based (Peripheral Component Interconnect) protocol (e.g., PCI-Express) or any other bus or point-to-point communication interface and / or (one or more) protocols (e.g., NV-Link high-speed interconnect or interconnect protocols known in the art).

[0035] In one embodiment, one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while retaining the underlying computing architecture, which is described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, memory hub 105, processor(s) 102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may interconnect with other MCMs to form a modular computing system.

[0036] It should be understood that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processors(one or more) 102, and the number of parallel processors(one or more) 112, can be modified as needed. For example, in some embodiments, system memory 104 is directly connected to processors(one or more) 102 instead of via bridges, while other devices communicate with system memory 104 via memory hub 105 and processors(one or more) 102. In other alternative topologies, parallel processors(one or more) 112 are connected to I / O hub 107 or directly to one of the processors(one or more) 102, instead of being connected to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors(one or more) 102 attached via multiple sockets, which may be coupled to two or more instances of parallel processors(one or more) 112.

[0037] Some specific components shown in this paper are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may be designed for... Figure 1 The components illustrated herein use different terminology for similar components. For example, memory hub 105 may be referred to as the north bridge in some architectures, while I / O hub 107 may be referred to as the south bridge.

[0038] Figure 2A The figure illustrates a parallel processor 200 according to one embodiment. Various components of the parallel processor 200 can be implemented using one or more integrated circuit devices such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). According to the embodiment, the illustrated parallel processor 200 is... Figure 1 One or more variants of the parallel processor 112 shown.

[0039] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 capable of communicating with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via a hub or switch interface, such as a memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar switch 216, wherein the host interface 206 receives commands directed to perform processing operations, and the memory crossbar switch 216 receives commands directed to perform memory operations.

[0040] When host interface 206 receives a command buffer via I / O unit 204, host interface 206 can route the work operations that execute those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is correctly configured and is active before tasks are distributed to the processing clusters of processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, enabling fast preemption and context switching of threads executing on processing array 212. In one embodiment, host software can demonstrate workloads to be scheduled on processing array 212 via one of a plurality of graphics processing doorbells. The workloads can then be automatically distributed on processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0041] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A-214N of processing cluster array 212 can execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to clusters 214A-214N of processing cluster array 212, which may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by scheduler 210 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be allocated to process different types of programs or to perform different types of computations.

[0042] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, such as filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0043] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic to support the performance of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from system memory for processing via I / O unit 204. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) and then written back to system memory.

[0044] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations across multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A-214N can be stored in a buffer to allow intermediate data to be transferred between the clusters 214A-214N for further processing.

[0045] During operation, the processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front end 208. For graphics processing operations, processing tasks may include data to be processed, such as indices of surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data will be processed (e.g., what program will be executed). Scheduler 210 may be configured to retrieve indices corresponding to tasks, or may receive indices from front end 208. Front end 208 may be configured to ensure that processing cluster array 212 is configured to be active before the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.) is initiated.

[0046] Each of one or more instances of parallel processing unit 202 may be coupled to parallel processor memory 222. Parallel processor memory 222 may be accessed via memory crossbar switch 216, which may receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include multiple partition units (e.g., partition units 220A, 220B, up to partition units 220N), each of which may be coupled to a portion (e.g., a memory cell) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and an Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0047] In various embodiments, memory cells 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory. In one embodiment, memory cells 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory cells 224A-224N can vary and can be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps can be stored on memory cells 224A-224N, allowing partitioning cells 220A-220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, a unified memory design that utilizes system memory in conjunction with local cache memory can be advantageous to exclude local instances of parallel processor memory 222.

[0048] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any memory cell 224A-224N within the parallel processor memory 222. The memory crossbar switch 216 can be configured to transfer the output of each cluster 214A-214N to any partition cell 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 via the memory crossbar switch 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar switch 216 has a connection to the memory interface 218 for communication with the I / O unit 204, and a connection to a local instance of the parallel processor memory 222, enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 can use virtual channels to separate traffic flows between clusters 214A-214N and partition units 220A-220N.

[0049] Although a single instance of the parallel processing unit 202 is illustrated within the parallel processor 200, any number of instances of the parallel processing unit 202 may be included. For example, multiple instances of the parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of the parallel processing unit 202 may be configured to interoperate even if they have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, and in one embodiment, some instances of the parallel processing unit 202 may include higher precision floating-point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit 202 or the parallel processor 200 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0050] Figure 2B This is a block diagram of partitioning unit 220 according to one embodiment. In one embodiment, partitioning unit 220 is... Figure 2A An example of one of the partition units 220A-220N. As illustrated, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from memory crossbar switch 216 and ROP 226. Read misses and urgent write-back requests are output from the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory, such as memory cells 224A-224N of FIG. 2 (e.g., within parallel processor memory 222).

[0051] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil printing, z-testing, and blending. ROP 226 then outputs the processed graphics data stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic using one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0052] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2) instead of within partition unit 220. In this embodiment, instead of pixel fragment data, read and write requests for pixel data are transmitted via memory crossbar switch 216. Processed graphics data can be displayed, such as... Figure 1 On one or more display devices 110, the data is routed for further processing by processor(s) 102, or routed for... Figure 2A One of the processing entities within the parallel processor 200 is further processed.

[0053] Figure 2C This is a block diagram of a processing cluster 214 within a parallel processing unit according to one embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. The processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executing on a particular set of input data. In some embodiments, Single Instruction Multiple Data (SIMD) instruction issuing technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, Single Instruction Multiple Threading (SIMT) technology is used to support the parallel execution of a large number of typically synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster. Unlike the SIMD execution regime, in which all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a subset of the functionality of the SIMT processing regime.

[0054] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or texture units 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and the data cross switch 240 can be used to distribute the processed data to one of several possible destinations, including other shading units. The pipeline manager 232 can facilitate the distribution of processed data by specifying the destination for the processed data to be distributed via the data cross switch 240.

[0055] Each graphics multiprocessor 234 within the processing cluster 214 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions complete. The functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0056] Instructions transmitted to processing cluster 214 constitute threads. A group of threads executing on the set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a loop processing the thread group. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0057] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In another embodiment, the graphics multiprocessor 234 may forgo the internal cache and use a cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 may also access an L2 cache within a partition unit (e.g., partition units 220A-220N of FIG. 2), which is shared among all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 202 may be used as global memory. Embodiments where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 may share common instructions and data that can be stored in the L1 cache 308.

[0058] Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG2. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses (more on tile laying) and optional cache line indices. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or the L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to allow valid requests to be interleaved between partition units. Cache line indices can be used to determine whether a request for a cache line is a hit or a miss.

[0059] In graphics and computing applications, processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within graphics multiprocessor 234, and as needed from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs processed tasks to data crossbar switch 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in L2 cache, local parallel processor memory, or system memory via memory crossbar switch 216. PreROP 242 (Pre-Raster Operation Unit) is configured to receive data from graphics multiprocessor 234 and direct the data to ROP units, which may be located within partitioned units (e.g., partitioned units 220A-220N of FIG. 2) as described herein. The preROP 242 unit can perform optimizations for color mixing, organize pixel color data, and perform address translation.

[0060] It should be understood that the core architecture described herein is illustrative, and various variations and modifications are possible. For example, any number of processing units, such as graphics multiprocessors 234, texture units 236, PreROP 242, etc., can be included within processing cluster 214. Furthermore, although only one processing cluster 214 is shown, the parallel processing units as described herein can include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 can be configured to operate independently of other processing clusters 214, using separate and distinct processing units, L1 caches, etc.

[0061] Figure 2DA graphics multiprocessor 234 according to one embodiment is illustrated. In this embodiment, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0062] In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. Instructions are cached in instruction cache 252 and dispatched for execution by instruction unit 254. Instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread in the thread group is assigned to a different execution unit within GPGPU core 262. Instructions can access any address space in the local, shared, or global address space by specifying an address within a unified address space. Address mapping unit 256 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 266.

[0063] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 324. Register file 258 provides temporary storage for operands on data paths connected to functional units of graphics multiprocessor 324 (e.g., GPGPU core 262, load / store unit 266). In one embodiment, register file 258 is partitioned among each functional unit, such that each functional unit is allocated a dedicated portion of register file 258. In another embodiment, register file 258 is partitioned among different warps executed by graphics multiprocessor 324.

[0064] Each GPGPU core 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. The GPGPU cores 262 may be architecturally similar or architecturally different depending on the embodiment. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more GPGPU cores may also include fixed-function or special-function logic.

[0065] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated at compile time by a shader compiler, or automatically generated when executing programs written and compiled for Single Program Multiple Data (SPMD) or SIMT architectures. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0066] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 324 to the register file 258 and shared memory 270. In one embodiment, the memory and cache interconnect 268 is a cross-switch interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 have very low latency. The shared memory 270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data transferred between functional units and texture units 236. The shared memory 270 can also be used as a programmable cache. In addition to automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmably store data within the shared memory.

[0067] Figures 3A-3B The figure illustrates an additional graphics multiprocessor according to an embodiment. The illustrated graphics multiprocessors 325 and 350 are... Figure 2C Variants of the graphics multiprocessor 234. The illustrated graphics multiprocessors 325 and 350 can be configured as streaming multiprocessors (SM) capable of executing a large number of execution threads simultaneously.

[0068] Figure 3A A graphics multiprocessor 325 according to another embodiment is shown. The graphics multiprocessor 325 includes components relative to... Figure 2D The graphics multiprocessor 234 may include multiple additional instances of its execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and one or more texture units 344A-344B. The graphics multiprocessor 325 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0069] Various components can communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more crossbar switches to enable communication between various components of the graphics multiprocessor 325. In another embodiment, interconnect structure 327 is a separate high-speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B can all communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation among components.

[0070] Figure 3B A graphics multiprocessor 350 according to another embodiment is shown. The graphics processor includes multiple sets of execution resources 356A-356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load memory units, such as... Figure 2D and Figure 3A As shown in the diagram. While sharing the instruction cache 354 and shared memory 362, execution resources 356A-356D can work in conjunction with one or more texture units 360A-360D for texture operations. In one embodiment, execution resources 356A-356D can share the instruction cache 354 and shared memory 362, as well as multiple instances of texture and / or data cache memories 358A-358B. Various components can be connected via... Figure 3A The interconnect structure 327 communicates with the similar interconnect structure 352.

[0071] Those skilled in the art will understand that Figure 1 , Figures 2A-2D and Figures 3A-3B The architecture described herein is descriptive and does not limit the scope of this embodiment. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) including multi-core CPUs, one or more parallel processing units such as the parallel processing unit 202 of FIG2, and one or more graphics processors or dedicated processing units without departing from the scope of the embodiments described herein.

[0072] In some embodiments, a parallel processor or GPGPU as described herein can be communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect, such as a high-speed interconnect like PCIe or NVLink. In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0073] Technology for interconnecting GPUs and host processors

[0074] Figure 4A The figure illustrates an exemplary architecture in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, depending on the implementation, the high-speed links 440-443 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the invention are not limited to any particular communication protocol or throughput.

[0075] Additionally, in one embodiment, two or more GPUs 410-413 are interconnected via high-speed links 444-445, which may use the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 4A All communication between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the invention are not limited to any particular type of interconnect technology.

[0076] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memories 401-402 via memory interconnects 430-431, and each GPU 410-413 is communicatively coupled to GPU memories 420-423 via GPU memory interconnects 450-453. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401-402 and GPU memories 420-423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM) and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchical structure).

[0077] As described below, although the various processors 405-406 and GPUs 410-413 can be physically coupled to specific memories 401-402 and 420-423 respectively, a unified memory architecture can be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed across all the various physical memories. For example, processor memories 401-402 can each include 64GB of system memory address space, and GPU memories 420-423 can each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0078] Figure 4B Additional details are illustrated in the figure regarding the interconnect between a multi-core processor 407 and a graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0079] The illustrated processor 407 includes multiple cores 460A-460D, each core having translational backstops 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data, which are not illustrated to avoid obscuring the fundamental principles of the invention (e.g., instruction fetch units, branch prediction units, decoders, execution units, reordering buffers, etc.). Caches 462A-462D may include L1 and L2 caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple sets of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. Processor 407 and graphics accelerator integrated module 446 are connected to system memory 441, which may include processor memories 401-402.

[0080] Consistency is maintained for data and instructions stored in various caches 462A-462D, 456 and system memory 441 via inter-core communication on the coherence bus 464. For example, each cache may have associated cache coherence logic / circuit to communicate via the coherence bus 464 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented on the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well known to those skilled in the art, and will not be described in detail here to avoid obscuring the basic principles of the invention.

[0081] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to coherence bus 464, allowing graphics acceleration module 446 to participate in cache coherence protocols as a core peer. Specifically, interface 435 provides connectivity to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0082] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 431, 432, and N of the graphics acceleration module 446. The graphics processing engines 431, 432, and N may each comprise an independent graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, and N may comprise different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In other words, the graphics acceleration module can be a GPU with multiple graphics processing engines 431-432, and N, or the graphics processing engines 431-432, and N can be individual GPUs integrated into a common package, line card, or chip.

[0083] In one embodiment, accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing system memory 441. MMU 439 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431-432, N. In one embodiment, data stored in cache 438 and graphics memories 433-434, N is consistent with core caches 462A-462D, 456 and system memory 411. As mentioned, this can be accomplished via a proxy circuit 425 representing cache 438 and memories 433-434, N participating in the cache coherence mechanism (e.g., sending updates involving modifications / accesses to cache lines on processor caches 462A-462D, 456 to cache 438 and receiving updates from cache 438).

[0084] A set of registers 445 stores context data for threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages the thread context. For example, context management circuitry 448 can perform save and restore operations to save and restore the context of various threads during context switching (e.g., in the case where the first thread is saved and the second thread is stored, allowing the second thread to be executed by the graphics processing engine). For example, during a context switch, context management circuitry 448 can store the current register value into a specified region in memory (e.g., identified by a context pointer). It can then restore the register value upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0085] In one implementation, the virtual / effective address from graphics processing engine 431 is translated by MMU 439 into an actual / physical address in system memory 411. One embodiment of accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. Graphics accelerator module 446 may be dedicated to a single application executing on processor 407, or it may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which the resources of graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). Resources may be subdivided into “shards” allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0086] Therefore, the accelerator integrated circuit acts as a bridge for the system used by the graphics acceleration module 446 and provides address translation and system memory caching services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0087] Because the hardware resources of graphics processing engines 431-432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is to physically separate the graphics processing engines 431-432, N, so that they appear to the system as independent units.

[0088] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are coupled to each of the graphics processing engines 431-432, N, respectively. Graphics memories 433-434, M store instructions and data processed by each of the graphics processing engines 431-432, N. Graphics memories 433-434, M can be volatile memories such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3DXPoint or Nano-RAM.

[0089] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433-434, M is the data most frequently used by graphics processing engines 431-432, N and preferably not used by cores 460A-460D (at least not frequently used). Similarly, the biasing mechanism attempts to keep the data needed by the cores (and preferably not graphics processing engines 431-432, N) within the core caches 462A-462D, 456 and system memory 411.

[0090] Figure 4C The figure illustrates another embodiment in which the accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via a high-speed link 440 through interfaces 437 and 435 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to... Figure 4B The operation described is the same, but assuming it is close to the coherence bus 462 and caches 462A-462D, 426, it may potentially be at higher throughput.

[0091] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0092] In one embodiment of the dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process within a single operating system. A single application can centralize requests from other applications to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0093] In a dedicated process programming model, the graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize the graphics processing engines 431-432, N to allow access from each operating system. For a single-partition system without a hypervisor, the graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432, N to provide access to each process or application.

[0094] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431-432, N uses a process handle to select a process element. In one embodiment, the process element is stored in system memory 411 and can be addressed using the effective address to actual address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431-432, N (i.e., invoking system software to add the process element to the process element linked list). The lower 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0095] Figure 4D The figure illustrates an exemplary accelerator integration slice 490. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application-effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process element 483 is stored in response to a GPU dispatch 481 from an application 480 executing on processor 407. Process element 483 contains process state for the corresponding application 480. The job descriptor (WD) 484 contained in process element 483 may be a single job requested by the application or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application address space 482.

[0096] The graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all or a subset of processes in the system. Embodiments of the invention include infrastructure for establishing process states and sending WD 484 to the graphics acceleration module 446 to initiate operations in a virtual environment.

[0097] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 446 or an individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, at the moment the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owned partition, and the operating system initializes the accelerator integrated circuit 436 for the owned process.

[0098] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes instructions for the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 can be stored in register 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 446 as illustrated. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can handle interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engines 431-432, N is translated into an actual address by the MMU 439.

[0099] In one embodiment, the same set of registers 445 is copied for each graphics processing engine 431-432, N, and / or graphics acceleration module 446, and can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0100] Table 1 - Registers initialized by the supervisor

[0101] 1 Slice Control Register 2 Real Address (RA) Scheduler Region Pointer 3 Permission masking overwrite register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limits 6 Status Register 7 Logical partition ID 8 Real Address (RA) Manager Accelerator Utilization Record Pointer 9 Storage description register

[0102] Table 2 shows exemplary registers that can be initialized by the operating system.

[0103] Table 2 - Registers initialized by the operating system

[0104] 1 Process and thread identifiers 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) accelerator utilization record pointer 4 Virtual address (VA) stores segment table pointers 5 Access masking 6 Job descriptor

[0105] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information needed by the graphics processing engine 431-432, N to complete its work, or it may be a pointer to a memory location of a command queue that the application has set up to perform the work.

[0106] Figure 4E The figure illustrates additional details of one embodiment of the shared model. This embodiment includes a hypervisor physical address space 498 in which a list of process elements 499 is stored. The hypervisor physical address space 498 is accessible via a hypervisor 496, which virtualizes the graphics acceleration module engine used by the operating system 495.

[0107] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. Two programming models exist where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-oriented sharing.

[0108] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. For the graphics acceleration module 446 to support the virtualization of the hypervisor 496, the graphics acceleration module 446 may meet the following requirements: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 446 must provide context saving and restoration mechanisms. 2) Application job requests must be guaranteed by the graphics acceleration module 446 to be completed within a specified amount of time, including any transition errors, or the graphics acceleration module 446 must provide the ability to preempt job processing. 3) When operating in a shared-processing model, the graphics acceleration module 446 must guarantee fairness between processes.

[0109] In one embodiment, for the shared model, an operating system system call 495 is required using application 480 with the graphics acceleration module 446 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for this system call. The graphics acceleration module 446 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to that set by the application. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before the AMR is passed in the hypervisor call. Before placing the AMR into process element 483, hypervisor 496 may optionally apply the Current Privilege Mask Overwrite Register (AMOR) value. In one embodiment, CSRP is one of the registers 445 for graphics acceleration module 446 that contains the effective address of a region in application address space 482 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. The context save / restore region may be fixed system memory.

[0110] Upon receiving a system call, the operating system 495 can verify that application 480 has been registered and authorized to use the graphics acceleration module 446. The operating system 495 then invokes the hypervisor 496 using the information shown in Table 3.

[0111] Table 3 - OS to Hypervisor Call Parameters

[0112] 1 Working Descriptor (WD) 2 The Authority Mask Register (AMR) value (may be masked). 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interruption Service Number (LISN)

[0113] Upon receiving a call from the hypervisor, the hypervisor 496 verifies that the operating system 495 has been registered and authorized to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements corresponding to the graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0114] Table 4 - Process Element Information

[0115] 1 Working Descriptor (WD) 2 The Authority Mask Register (AMR) value (may be masked). 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interruption Service Number (LISN) 8 Interrupt vector table exported from the parameters called by the management program. 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0116] In one embodiment, the hypervisor initializes multiple accelerator integration slice 490 registers 445.

[0117] like Figure 4F As illustrated, one embodiment of the invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each processor memory 401-402 and GPU memory 420-423, allowing any processor or GPU to access any physical memory—with a virtual address mapped to that memory.

[0118] In one embodiment, bias / coherence management circuitry 494A-494E within one or more MMUs 439A-439E ensures cache coherence between the host processor's (e.g., 405) cache and the GPU 410-413 cache, and implements biasing techniques that indicate the physical memory where certain types of data should be stored. While in Figure 4FThe diagram illustrates several instances of bias / coherence management circuitry 494A-494E, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0119] One embodiment allows GPU-attached memories 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memories 420-423 as system memory without the heavy overhead of cache coherence provides a beneficial operating environment for GPU offload. This arrangement allows host processor 405 software to set up operands and access computation results without the overhead of traditional I / O DMA data copying. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses. Meanwhile, the ability to access GPU-attached memories 420-423 without cache coherence overhead can be critical for the execution time of offloaded computations. For example, in scenarios with heavy streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offload.

[0120] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure comprising 1 or 2 bits for each memory page attached to the GPU (i.e., controlled at the memory page level). The bias table can be implemented within the stolen memory of one or more GPU-attached memories 420-423—with or without a bias cache in GPUs 410-413 (e.g., to cache frequently / recently used bias table entries). Alternatively, the entire bias table can be kept within the GPU.

[0121] In one implementation, the bias table entries associated with each access to the GPU-attached memory 420-423 are accessed before the actual access to the GPU memory, resulting in the following operations: First, local requests from GPUs 410-413 to look up their pages in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from GPUs to look up their pages in the host bias are forwarded to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, a request from processor 405 to look up the requested page in the host processor bias is performed as a normal memory read. Alternatively, requests directed to GPU bias pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, then the GPU can then transfer the page to the host processor bias.

[0122] The page's bias state can be changed through software-based mechanisms, hardware-assisted software-based mechanisms, or—for a finite set of cases—purely hardware-based mechanisms.

[0123] One mechanism for changing the bias state involves an API call (such as OpenCL), which in turn invokes the GPU's device driver. This device driver then sends a message (or queues a command descriptor) to the GPU to guide it in changing the bias state. For certain transitions, a cache dump flush operation is performed on the host machine. The cache dump flush operation is necessary for transitions from the host processor 405 bias to the GPU bias, but not for the reverse transition.

[0124] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that are not cacheable by the host processor 405. To access these pages, the processor 405 may request access from the GPU 410, which, depending on its implementation, may grant access immediately or not. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that GPU-biased pages are those required by the GPU but not by the host processor 405, and vice versa.

[0125] Graphics processing pipeline

[0126] Figure 5 The figure illustrates a graphics processing pipeline 500 according to one embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within the parallel processing subsystem described herein, such as the parallel processor 200 of FIG2, which in one embodiment is... Figure 1Variations of the parallel processor(s) 112. As described herein, various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of parallel processing units (e.g., parallel processing unit 202 of FIG. 2). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3) can be configured to perform one or more functions of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3) and corresponding partitioning units (e.g., partitioning units 220A-220N of FIG. 2). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 in FIG2) via a memory interface 528, which may be an instance of memory interface 218 of FIG2.

[0127] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data, including vertex attributes, to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, lighting, and transformations of the vertex data specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local, or system memory for use in processing vertex data and can be programmed to transform vertex data from object-based coordinate representations to world space coordinate space or normalized device coordinate space.

[0128] The first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., as supported by various graphics processing application programming interfaces (APIs).

[0129] The tessellation control processing unit 508 treats input vertices as control points for the geometric patch. These control points are transformed from the input representation of the patch (e.g., the patch's basis) into a representation suitable for use in the surface evaluation performed by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also compute tessellation factors for the edges of the geometric patch. The tessellation factor is applied to a single edge and quantifies the viewpoint-related level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch surface into multiple geometric primitives, such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0130] A second instance of the primitive assembler 514 receives vertex attributes from the subdivision evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphical primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphical primitives received from the primitive assembler 514 and specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphical primitives into one or more new graphical primitives and compute parameters for rasterizing the new graphical primitives.

[0131] In some embodiments, the geometry processing unit 516 can add or remove elements from the geometry flow. The geometry processing unit 516 outputs parameters and vertices specifying new graphical primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphical primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphical primitives to the rasterizer 522.

[0132] Rasterizer 522 can perform depth culling and other depth-based optimizations. Rasterizer 522 also performs scan transformations on new graphics primitives to generate fragments and outputs these fragments and associated overlay data to fragment / pixel processing unit 524. Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to raster operation unit 526. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. Fragment or pixel shader programs can be configured to shade at sample, pixel, tile, or other granularities depending on the sampling rate configured for the processing unit.

[0133] The raster operation unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, and blending, and outputs pixel data as processed graphic data for storage in a graphics memory (e.g., the parallel processor memory 222 in Figure 2 and / or such as...). Figure 1 The system memory 104 is used to display the data on one or more display devices 110 or to further process the data by one or more processors 102 or one or more parallel processors 112. In some embodiments, the raster operation unit 526 is configured to compress z-or color data written to memory and decompress z-or color data read from memory.

[0134] Best Use of Car Virtual Mirror

[0135] In a car, mirrors are used to help the driver see the area behind, to the right, and to the left of the car. Cars typically have two side mirrors on the exterior (one on the left and one on the right) and a rearview mirror inside the car. Figure 6A illustrates a car 600 with exterior side mirrors 602 and 604. Side mirror 602 is located on the left side of the car. Side mirror 604 is located on the right side of the car. Figures 6B and 6C are examples of what the driver can see when he or she looks through the side mirrors. As shown in Figures 6B and 6C, the driver is able to see the area behind and to the sides of the car when he or she looks through side mirrors 602 and 604.

[0136] Figure 7A The illustration shows an interior view 70 of a car. The interior view 700 includes a rearview mirror 702 for allowing the driver to view the area behind the car. Figure 7BThe illustration shows an example of what a driver can see when he or she looks through the rearview mirror. As shown, the driver is able to see the area behind the car.

[0137] Figure 8 The diagram illustrates an exemplary driving scenario 800 during vehicle operation, showing the driver's normal field of vision coverage and blind spots as seen from the side and rearview mirrors. The driver-operated vehicle 802 is traveling along a highway 804 surrounded by other vehicles 806, 808, 810, 812, 814, 816, and 818. Figure 8 As shown, four cars, 812, 814, 816, and 818, are within the driver's field of vision of car 802, and three of these four cars, 814, 816, and 818, are in front of car 802. The only car visible to the driver of car 802 behind car 802 is car 812. The driver of car 802 has a clear view of car 812 using rearview mirror 702. Figure 8 As shown, vehicle 812 exists within the viewing coverage area 820 of vehicle 802 as seen through the rearview and side mirrors of vehicle 802. Vehicles 806, 808, and 810 are not visible to the driver of vehicle 802 and are therefore considered to be in an area referred to as the blind spot 822 of vehicle 802. A potential accident could occur if vehicle 802 attempts to change lanes by moving to the right or left lane because vehicles 806 and 808 are not visible to the driver of vehicle 802.

[0138] There is a trend towards replacing side and rearview mirrors in automobiles with virtual mirrors. A virtual mirror is a camera that is communication-coupled to a display. Replacing mirrors with a camera and display provides the driver with a wider field of vision, thereby reducing (if not eliminating) blind spots. Virtual mirrors utilize a significant amount of power to encode and decode the images to be displayed. Furthermore, the higher the resolution and the higher the frame rate used for display, the more power is consumed. An embodiment that optimally utilizes virtual mirrors to save power is described below.

[0139] Figure 9A This is a block diagram illustrating a vehicle system 900 for optimal power utilization of a virtual mirror 904 in an automobile according to an embodiment. The system 900 includes a gaze detector 902 and a plurality of virtual mirrors 904 strategically located inside and outside the vehicle, replacing rearview and side mirrors. The virtual mirrors 904 may also be located within the vehicle to eliminate blind spots.

[0140] A gaze detector 902 is a sensor device that measures eye position and eye movement to determine a gaze point or where a person is looking. The gaze detector 902 also senses head movement to determine where a person is looking. In one embodiment, the gaze detector 902 may have an embedded processor and embedded memory to track where the driver is looking. In another embodiment, the gaze detector 902 may be coupled to one or more processors in the vehicle, said processors being coupled to one or more memory devices such that the gaze detector 902 tracks where a person is looking. In one embodiment, the gaze detector 902 is used to determine whether the driver of the vehicle is looking at one of the virtual mirrors 904 in or around the vehicle.

[0141] Virtual mirror 904 is a replacement mirror for rearview and side mirrors in a car. Virtual mirror 904 is used to help the driver see the area behind the car and the areas to the left and right of the car. As previously indicated, each virtual mirror 904 includes a camera 906 communicatively coupled to a display 908. Encoder 910 and decoder 912 are coupled between the camera and the display to encode and decode images from the camera for viewing on the display. A gaze detector 902 is coupled to each virtual mirror 904.

[0142] In another embodiment, each virtual mirror 904 may have its own gaze detector 902. Figure 9B This is a block diagram illustrating an exemplary virtual mirror with a gaze detector according to an embodiment. The gaze detector 902 is coupled to a camera 906 and a display 908. Figure 9B It is also shown that the gaze detector 902 can optionally be coupled to the encoder 910. The gaze detector 902 can control the camera 906, the display 908, and the encoder 910 by sending signals to put the device into a low-power mode or into a full-operation mode, as described below.

[0143] Considering that a driver can only view one virtual mirror 904 at a time, the gaze detector 902 detects whether the driver is looking at a specific virtual mirror 904 at a given time. Only when the driver is looking at the virtual mirror 904 will the virtual mirror 904 capture and display images in real time at full resolution and full frame rate or in full operating mode. If a specific virtual mirror 904 is not being viewed according to the gaze detector 902, the quality of the real-time images captured by the virtual mirror 904 can be reduced to save power. When the driver is not looking at the virtual mirror 904, the resolution and / or frame rate of the display 908 used for the virtual mirror 904 can be reduced. For example, if the driver is looking towards the location of the rearview mirror, the virtual mirror 904 replacing the rearview mirror will operate at full resolution and full frame rate, while all other virtual mirrors 904 will operate in low-power mode. For example, 60 frames per second is a normal frame rate used in the display, and a high-definition resolution could be, for example, 1920×1080 pixels. When the driver is not looking at the virtual mirror 904, the frame rate and / or resolution of the display 908 can be reduced. In one embodiment, the frame rate can be reduced to one-quarter of its original value, thus reducing the frame rate to 15 frames per second. In another embodiment, the resolution can be reduced to one-quarter of its original value, resulting in a resolution of 960 × 540 pixels. Therefore, reducing the display's frame rate and / or resolution to at least one-quarter of its original value saves considerable power. In yet another embodiment, the resolution can be reduced to up to one-sixteenth of its original value, resulting in a resolution of 480 × 270 pixels.

[0144] Low operating mode not only means a lower frame rate and / or resolution for display 908. In one embodiment, the brightness of pixels on display 908 may be reduced. In another embodiment, the resolution and / or frame rate of camera 906 in virtual mirror 904 may be reduced to save power. In an embodiment, the resolution and / or frame rate of encoder 910 may be reduced to save power. Unviewed virtual mirror 904 should be kept in a low-power state rather than being turned off (unless the car is turned off). Drivers constantly observe virtual mirrors 904 while driving and often very quickly shift their gaze from one virtual mirror 904 to another. If virtual mirrors 904 take too long to start up, turning off any virtual mirror 904 while driving could cause irreparable harm.

[0145] Figure 10 This is a flowchart illustrating a method 1000 for optimal power utilization of a virtual mirror 904 in an automobile according to an embodiment. The process begins in block 1002, where it immediately proceeds to block 1004.

[0146] In block 1004, upon vehicle startup, all virtual mirrors 904 are placed in full operational mode. In one embodiment, full operational mode may refer to a frame rate of 60 frames per second and a resolution of 1920×1080 pixels for display 908. In another embodiment, full operational mode may refer to a frame rate of 30 frames per second and a resolution of 1920×1080 pixels for display 908. Similar values ​​for the frame rate and resolution used for camera 906 and encoder 910 may also be used. The process then proceeds to block 1006.

[0147] In box 1006, gaze detector 902 is used to monitor the driver to determine if he or she is looking at virtual mirror 904. The process proceeds to decision box 1008.

[0148] In decision box 1008, it is determined whether the driver is looking in the direction of virtual mirror 904. If the driver is not looking in the direction of virtual mirror 904, the process proceeds to box 1012, where all virtual mirrors 904 are placed in a low operating mode. As previously indicated, the low operating mode can be a reduction of four times the full operating mode of both the frame rate and resolution of display 908, as well as a reduction in the brightness of display 908. In one embodiment, the encoding resolution and frame rate can also be reduced. The resolution and frame rate of camera 906 can also be reduced. The process then returns to box 1006 to continue monitoring the driver to determine whether the driver is looking at virtual mirror 904.

[0149] Returning to decision box 1008, if it is determined that the driver is looking in the direction of virtual mirror 904, the viewed virtual mirror 904 is placed in full operating mode, while all other virtual mirrors 904 are placed in low operating mode. In one embodiment, full operating mode requires all devices in virtual mirror 904 to be returned to full resolution and frame rate. This may include camera 906, encoder 910, and / or display 908. The process then returns to box 1006 to continue monitoring the driver to determine if the driver is looking in the direction of virtual mirror 904. This process of monitoring the driver and adjusting virtual mirror 904 thus continues until the car is turned off.

[0150] Display technology

[0151] Now go to Figure 11The illustration shows a performance-enhanced computing system 1100. In the illustrated example, a processor 1110 is coupled to a display 1120. The processor 1110 typically produces images for display on an LCD panel 1150 of the display 1120. In one example, the processor 1110 includes communication interfaces such as, for example, Video Graphics Array (VGA), DisplayPort (DP) interface, Embedded DisplayPort (eDP) interface, High Definition Multimedia Interface (HDMI), Digital Video Interface (DVI), etc. The processor 1110 may be a graphics processor (e.g., a graphics processing unit / GPU) that processes graphics data and generates images (e.g., video frames, still images) displayed on the LCD panel 1150. Furthermore, the processor 1110 may include one or more image processing pipelines that generate pixel data. The image processing pipelines may conform to an OpenGL architecture or other suitable architecture. Additionally, the processor 1110 may be connected to a host processor (e.g., a central processing unit / CPU) that executes one or more device drivers that control and / or interact with the processor 1110.

[0152] The illustrated display 1120 includes a timing controller (TCON) 1130 that can individually address different pixels in the LCD panel 1150 and update each individual pixel in the LCD panel 1150 in each refresh cycle. In this regard, the LCD panel 1150 may include multiple liquid crystal elements, such as liquid crystals and integrated color filters. Each pixel of the LCD panel 1150 may respectively include a triple liquid crystal element with red, green, and blue color filters. The LCD panel 1150 can arrange pixels in a two-dimensional (2D) array controlled via row drivers 1152 and column drivers 1154 to update the image displayed by the LCD panel 1150. Therefore, the TCON 1130 can drive the row drivers 1152 and column drivers 1154 to address specific pixels of the LCD panel 1150. The TCON 1130 can also adjust the voltage supplied to the liquid crystal elements in the pixel to change the intensity of light passing through each of the three liquid crystal elements, and thus change the color of the pixel displayed on the surface of the LCD panel 1150.

[0153] The backlight 1160 may include multiple light-emitting elements, such as light-emitting diodes (LEDs), arranged at the edges of the LCD panel 1150. Thus, light generated by the LEDs can be diffused through the LCD panel 1150 by a diffuser (not shown). In another example, since each LED diffuses light through one or more corresponding pixels of the LCD panel 1150 located in front of the LED, in one configuration the LEDs are arranged in a 2D array directly behind the LCD panel 1150; this is sometimes referred to as direct backlighting. The light-emitting elements may also include compact fluorescent lamps (CFLs) arranged along one or more edges of the LCD panel 1150. To eliminate multiple edges, the combination of edges can be varied to achieve selective illumination of areas, where a smaller number of lighting elements than the total set are used at lower power.

[0154] The light-emitting element may also include one or more sheets of electroluminescent material placed behind the LCD panel 1150. In this case, light from the surface of the sheet can be dispersed through the pixels of the LCD panel 1150. Alternatively, the sheet can be divided into multiple regions, such as quadrants. In one example, each region is individually controlled to illuminate only a portion of the LCD panel 1150. Other backlighting solutions may also be used.

[0155] The illustrated display 1120 also includes a backlight controller (BLC) 1140 that provides voltage to the light-emitting elements of the backlight 1160. For example, the BLC 1140 may include a pulse-width modulation (PWM) driver (not shown) to generate a PWM signal that activates at least a portion of the light-emitting elements of the backlight 1160. The duty cycle and frequency of the PWM signal can cause the light generated by the light-emitting elements to dim. For example, a 100% duty cycle may correspond to the light-emitting elements being fully on, and a 0% duty cycle may correspond to the light-emitting elements being fully off. Therefore, intermediate duty cycles (e.g., 25%, 50%) typically cause the light-emitting elements to be on for a portion of a cycle proportional to the percentage of the duty cycle. The cycle may be fast enough that the flickering of the light-emitting elements is not noticeable to the human eye. Furthermore, the effect on the user may be that the level of light emitted by the backlight 1160 is lower than when the backlight 1160 is fully activated. The BLC 1140 may be separate from or incorporated into the TCON 1130.

[0156] Alternatively, an emitting display system can be used, in which the LCD panel 1150 is replaced by an emitting display panel (e.g., organic light-emitting diode / OLED), the backlight 1160 is omitted, and the row and column drivers 1152 and 1154 can be used to directly modulate the color and brightness of the pixels, respectively.

[0157] Distance-based display resolution

[0158] Figure 12A The illustration depicts a scenario where a user 1218 interacts with a data processing device 1200 including a display unit 1228. The display processing device 1200 may include, for example, a laptop computer, desktop computer, tablet computer, convertible tablet computer, mobile internet device (MID), personal digital assistant (PDA), wearable device (e.g., head-mounted display / HMD), media player, etc., or any combination thereof. The illustrated data processing device 1200 includes a processor 1224 (e.g., an embedded controller, microcontroller, host processor, graphics processor) coupled to a memory 1222, which may include storage locations addressable by the processor 1224. As will be discussed in more detail, a distance sensor 1210 enables distance-based display resolution relative to the display unit 1228.

[0159] The illustrated memory 1222 includes display data 1226 to be rendered on the display unit 1228. In one example, the processor 1224 performs data transformation on the display data 1226 before presenting it on the display unit 1228. A post-processing engine 1214 can be executed on the processor 1224 to receive the display data 1226 and the output of the proximity sensor 1210. The post-processing engine 1214 can modify the display data 1226 to enhance the readability of screen content on the display unit 1228, reduce power consumption in the data processing device 1200, or any combination thereof.

[0160] In addition to the operating system 1212 and application 1220, the illustrated memory 1222 also stores a display resolution setting 1216. The display resolution setting 1216 specifies the number of pixels of display data 1226 to be rendered on the display unit 1228 along its length and width dimensions. If the display data 1226 generated by application 1220 is incompatible with the format of the display unit 1228, the processor 1224 can configure the scaling of the display data 1226 to match the format of the display unit 1228. In this regard, the display resolution setting 1216 can be associated with and / or incorporated into configuration data that defines other settings for the display unit 1228. Furthermore, the display resolution setting 1216 can be defined based on unit distance or area (e.g., pixels per inch / PPI) or other suitable parameters.

[0161] Application 1220 can generate a user interface, in which user 1218 can interact with the user interface to select display resolution setting 1216 from one or more options provided through the user interface, input display resolution setting 1216 as a requested value, and so on. Therefore, display data 1226 can be resized to fit display resolution setting 1216 before being rendered on display unit 1228.

[0162] The distance sensor 1210 can track the distance between the user 1218 and the display unit 1228, where distance sensing can be triggered by a physical button associated with the data processing device 1200 / display unit 1228, by a user interface provided by the application 1220, and / or by the loading of the operating system 1220, etc. For example, during the boot of the data processing device 1200, the operating system 1212 can implement an automatic process to trigger distance sensing in the background or foreground. Distance sensing can be implemented periodically or continuously.

[0163] Figure 12B An example of a distance sensing scenario is shown. In the illustrated example, distance sensor 1210 uses transceiver 1208 to transmit electromagnetic beam 1202 in the direction of user 1218. Therefore, transceiver 1202 can be positioned on the forward surface of data processing device 1200. Figure 12A Electromagnetic beam 1202 can impact user 1218 and be reflected / scattered from user 1218 as a return electromagnetic beam 1204. The return electromagnetic beam 1204 can be generated by, for example, processor 1224 (…). Figure 12A ) and / or post-processing engine 1214 ( Figure 12A Analysis to determine the relationship between user 1218 and display unit 1228 ( Figure 12A The distance between them is 1206. A distance of 1206 can be used to adjust the display resolution setting to 1216.

[0164] Display layer

[0165] Now go to Figure 13The illustration shows a display system 1300, in which cascaded display layers 1361, 1362, and 1363 are used to achieve spatial / temporal super-resolution in display accessory 1360. In the illustrated example, processor 1310 provides original graphics data 1334 (e.g., video frames, still images) to system 1300 via bus 1320. Cascaded display programs 1331 can be stored in memory 1330, whereby cascaded display programs 1331 may be part of a display driver associated with display accessory 1360. The illustrated memory 1330 also includes the original graphics data 1334 and factored graphics data 1335. In one example, cascaded display programs 1331 include a temporal factor decomposition component 1332 and a spatial factor decomposition component 1333. The temporal factor decomposition component 1332 can perform temporal factor decomposition calculations, and the spatial factor decomposition component can perform spatial factor decomposition calculations. The cascaded display program 1331 can derive graphical data 1335 for rendering factorization on each display layer 1361, 1362, and 1363 based on user configuration and raw graphical data 1334.

[0166] The display accessory 1360 can be implemented as an LCD (Liquid Crystal Display) for applications such as head-mounted displays (HMDs). More specifically, the display accessory 1360 may include a set of LCD panel interface boards, lens accessories, etc. Each panel can operate at, for example, a native resolution of 1280×800 pixels and a refresh rate of 60Hz. Other native resolutions, refresh rates, display panel technologies, and / or layer configurations can be used.

[0167] Multiple display units

[0168] Figure 14 A graphics display system 1400 is illustrated, comprising a set of display units 1430 (1430a-1430n), which can typically be used to output a widescreen (e.g., panoramic) presentation 1440 including cohesive content in the form of cohesion and structured topology. In the illustrated example, a data processing device 1418 includes a processor 1415 that applies logic function 1424 to hardware profile data 1402 received from the set of display units 1430 via a network 1420. Applying logic function 1424 to the hardware profile data 1402 can create a set of automatic topology settings 1406 when the hardware profile data does not match a set of settings in a hardware profile lookup table 1412. The illustrated set of automatic topology settings 1406 is transmitted from the display processing device 1418 to the display units 1430 via the network 1420.

[0169] The processor 1415 can perform and execute the logic function 1424 upon receiving it from the display driver 1410. In this regard, the display driver 1410 may include an automatic topology module 1408 that automatically configures and constructs the topology of the display unit 1432 to create a presentation 1440. In one example, the display driver 1410 is a set of instructions that, when executed by the processor 1415, enable the data processing device 1418 to communicate with the display unit 1430, video card, etc., and perform automatic topology generation operations.

[0170] Data processing device 1418 may include, for example, a server, desktop computer, laptop computer, tablet computer, convertible tablet computer, MID, PDA, wearable device, media player, etc. Therefore, display processing device 1418 may include hardware control module 1416, storage device 1414, random access memory (RAM, not shown), controller card including one or more video controller cards, etc. In one example, display units 1430 are flat panel displays (e.g., liquid crystal, active matrix, plasma, etc.), HMDs, video projection devices, etc., that coordinate with each other to produce presentation 1440. Furthermore, presentation 1440 can be generated based on media files stored in storage device 1414, where media files may include, for example, movies, video clips, animations, advertisements, etc., or any combination thereof.

[0171] The term "topology" can be considered as the number, scaling, shape, and / or other configuration parameters of the first display unit 1430a, the second display unit 1430b, the third display unit 1430n, etc. Therefore, the topology of the display units 1430 allows the presentation 1440 to be consistently visually rendered, ensuring that the various parts of the presentation 1440 are proportional to and compatible with the original dimensions and extent of the media played through the display units 1430. Thus, the topology can constitute spatial relationships and / or geometric properties unaffected by continuous changes in the shape or size of the content rendered in the presentation 1440. In one example, the automatic topology module 1408 includes a timing module 1426, a control module 1428, a signal monitoring module 1432, and a signal display module 1434. The timing module 1426 can designate a specific display unit in the group of display units 1430 as a sample display unit. In this case, the timing module 1426 can designate the remaining display units 1430 as additional display units. In one example, timing module 1426 automatically sets the shape factor to be compatible with hardware profile data 1402, where rendering 1440 is automatically initiated by graphic signal sequence 1422.

[0172] In one example, control module 1428 modifies the set of automatic topology settings 1406. Additionally, signal monitoring module 1432 can automatically monitor the graphic signal sequence 1422 and trigger storage device 1414 to associate the set of automatic topology settings 1406 with hardware profile lookup table 1412. Furthermore, signal monitoring module 1432 can automatically detect changes in the set of display units 1430 based on a set of change criteria and automatically generate a new topology profile corresponding to the changes in the set of display units 1430. Therefore, the new topology profile can be applied to the set of display units 1430. If the graphic signal sequence 1422 does not meet a set of criteria, signal monitoring module 1432 can also trigger signal display module 1434 to reapply the set of automatic topology settings 1406. If hardware profile data 1402 does not support automatic topology display of graphic signal sequence 1422, data processing device 1418 can report an error and log the error in error log 1413.

[0173] Cloud-assisted media delivery

[0174] Now go to Figure 15 The cloud gaming system 1500 includes clients 1540 coupled to server 1520 via network 1510. Clients 1540 may typically be consumers of graphical content (e.g., games, virtual reality / VR, augmented reality / AR) hosted, processed, and rendered on server 1520. The illustrated server 1520 may be scalable, having the ability to serve graphical content to multiple clients simultaneously (e.g., by utilizing parallel and amortized processing and rendering resources). In one example, the scalability of server 1520 is limited by the capacity of network 1510. Therefore, there may be a threshold number of clients beyond which service is degraded for all clients.

[0175] In one example, server 1520 includes a graphics processor (e.g., GPU) 1530, a host processor (e.g., CPU) 1524, and a network interface card (NIC) 1522. NIC 1522 can receive requests for graphics content from client 1540. Requests from client 1540 can cause graphics content to be retrieved from memory via an application running on host processor 1524. Host processor 1524 can perform high-level operations, such as determining the position, collision, and motion of objects in a given scene. Based on these high-level operations, host processor 1524 can generate rendering commands that combine scene data and are executed by graphics processor 1530. Rendering commands can cause graphics processor 1530 to define scene geometry, shading, lighting, motion, textures, camera parameters, etc., for rendering via client 1540.

[0176] More specifically, the illustrated graphics processor 1530 includes a graphics renderer 1532, which performs the rendering process according to rendering commands generated by the host processor 1524. The output of the graphics renderer 1532 may be a stream of raw video frames provided to the frame capturer 1534. The illustrated frame capturer 1534 is coupled to an encoder 1536, which can compress / format the raw video stream for transmission over the network 1510. The encoder 1536 may use a variety of video compression algorithms, such as, for example, the H.264 standard from the International Telecommunication Union Telecommunication Standardization Sector (ITUT), the MPEG4 Advanced Video Coding (AVC) standard from the International Organization for Standardization / International Electrotechnical Commission (ISO / IEC), and so on.

[0177] The illustrated client 1540 can be a desktop computer, laptop computer, tablet computer, convertible tablet computer, wearable device, MID, PDA, media player, etc., and includes a NIC 1542 to receive video streams transmitted from server 1520. NIC 1522 may include the physical layer and the software layer foundation for the network interface in client 1540 to facilitate communication over network 1510. Client 1540 may also include a decoder 1544, which employs the same formatting / compression scheme as encoder 1536. Therefore, the decompressed video stream can be provided from decoder 1544 to video renderer 1546. The illustrated video renderer 1546 is coupled to display 1548, which visually presents graphical content.

[0178] As already mentioned, graphical content can include game content. In this regard, client 1540 can implement real-time interactive streaming, which involves collecting user input from input device 1550 and delivering the user input to server 1520 via network 1510. This real-time interactive component of cloud gaming may pose challenges regarding latency.

[0179] Additional System Overview Example

[0180] Figure 16 This is a block diagram of a processing system 1600 according to one embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0181] Embodiments of system 1600 may include or be incorporated within a server-based gaming platform, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1600 is a mobile phone, smartphone, tablet computing device, or mobile internet device. Data processing system 1600 may also include, be coupled to, or be integrated within a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0182] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 for processing instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a particular instruction set 1609. In some embodiments, the instruction set 1609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Words (VLIW). Multiple processor cores 1607 may each process different instruction sets 1609, which may include instructions that facilitate the emulation of other instruction sets. Processor cores 1607 may also include other processing devices, such as digital signal processors (DSPs).

[0183] In some embodiments, processor 1602 includes cache memory 1604. Depending on the architecture, processor 1602 may have a single internal cache or multi-level internal caches. In some embodiments, cache memory is shared among various components of processor 1602. In some embodiments, processor 1602 also uses external caches (e.g., a Level 3 (L3) cache or an ultimate level cache (LLC)) (not shown), which can be shared among processor cores 1607 using known cache coherence techniques. Processor 1602 also includes a register file 1606, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general-purpose registers, while others may be specific to the design of processor 1602.

[0184] In some embodiments, processor 1602 is coupled to processor bus 1610 to transmit communication signals such as address, data, or control signals between processor 1602 and other components in system 1600. In one embodiment, system 1600 uses an exemplary “central” system architecture that includes a memory controller central hub 1616 and an input / output (I / O) controller central hub 1630. Memory controller central hub 1616 facilitates communication between memory devices and other components of system 1600, while I / O controller central hub (ICH) 1630 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller central hub 1616 is integrated within the processor.

[0185] Memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance for use as processing memory. In one embodiment, memory device 1620 may operate as system memory for system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute an application or process. Memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may communicate with one or more graphics processors 1608 in processor 1602 to perform graphics and media operations.

[0186] In some embodiments, ICH 1630 enables peripheral devices to connect to memory device 1620 and processor 1602 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard disk drive, flash memory, etc.), and a conventional I / O controller 1640 for coupling conventional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices such as a keyboard and mouse 1644 combination. A network controller 1634 may also be coupled to ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1610. It will be appreciated that the illustrated system 1600 is exemplary and not limiting, as other types of data processing systems with different configurations may also be used. For example, the I / O controller hub 1630 can be integrated into one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 can be integrated into a separate external graphics processor, such as an external graphics processor 1612.

[0187] Figure 17 This is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A-1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Elements have the same reference numerals (or names) as those in any other figures herein. Figure 17 Those components may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 1700 may include additional cores, up to and including additional cores 1702N, indicated by the dashed box. Each of processor cores 1702A-1702N includes one or more internal cache units 1704A-1704N. In some embodiments, each processor core may also access one or more shared cache units 1706.

[0188] Internal cache units 1704A-1704N and shared cache unit 1706 represent the cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache in each processor core and one or more levels of shared intermediate cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, wherein the highest-level cache preceding external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the individual cache units 1706 and 1704A-1704N.

[0189] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1710 provides management functionality for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 to manage access to various external memory devices (not shown).

[0190] In some embodiments, one or more of the processor cores 1702A-1702N include support for simultaneous multithreading. In such an embodiment, the system agent core 1710 includes components for coordinating and operating the cores 1702A-1702N during multithreaded processing. The system agent core 1710 may additionally include a power control unit (PCU) which includes logic and components for regulating the power states of the processor cores 1702A-1702N and the graphics processor 1708.

[0191] In some embodiments, processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, graphics processor 1708 is coupled to the shared cache unit 1706 and a system proxy core 1710 including one or more integrated memory controllers 1714. In some embodiments, display controller 1711 is coupled to graphics processor 1708 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 1711 may be a separate module coupled to graphics processor via at least one interconnect, or it may be integrated within graphics processor 1708 or system proxy core 1710.

[0192] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other techniques including those well known in the art, may be used. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via I / O link 1713.

[0193] Exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702-1702N and the graphics processor 1708 uses the embedded memory module 1718 as a shared last-level cache.

[0194] In some embodiments, processor cores 1702A-1702N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 1702A-1702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 1702A-N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1702A-1702N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, processor 1700 may be implemented on one or more chips or as a SoC integrated circuit having the components shown, among other components.

[0195] Figure 18This is a block diagram of a graphics processing unit 1800, which may be a discrete graphics processing unit or a graphics processing unit integrated with multiple processing cores. In some embodiments, the graphics processing unit communicates via a memory-mapped I / O interface to registers on the graphics processing unit and using commands placed in processor memory. In some embodiments, the graphics processing unit 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0196] In some embodiments, the graphics processor 1800 further includes a display controller 1802 to drive display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlay planes for the display and combination of multi-layer video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 to encode media into one or more media encoding formats, decode from one or more media encoding formats, or transcode between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and SMPTE 421M / VC-1, as well as Joint Picture Experts Group (JPEG) formats such as JPEG and Animated JPEG (MJPEG).

[0197] In some embodiments, the graphics processor 1800 includes a block image transfer (BLIT) engine 1804 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in one embodiment, one or more components of the graphics processing engine (GPE) 1810 are used to perform 2D graphics operations. In some embodiments, the graphics processing engine 1810 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0198] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering 3D images and scenes using processing functions acting on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 1812 includes programmable and fixed-function elements that perform various tasks within those elements and / or produce execution threads to the 3D / media subsystem 1815. While the 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 specifically designed to perform media operations such as video post-processing and image enhancement.

[0199] In some embodiments, the media pipeline 1816 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterleaving, and video encoding acceleration, in place of or on behalf of the video codec engine 1806. In some embodiments, the media pipeline 1816 further includes thread-producing units to produce threads for execution on the 3D / media subsystem 1815. The produced threads perform computations on media operations for one or more graphics execution units included in the 3D / media subsystem 1815.

[0200] In some embodiments, the 3D / media subsystem 1815 includes logic for executing threads produced by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0201] 3D / Media Processing

[0202] Figure 19 This is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, GPE 1910 is... Figure 18 A version of GPE 1810 shown. Elements having the same reference numerals (or names) as those in any other figures herein. Figure 19 The components may operate or function in any manner similar to those described elsewhere in this document, but are not limited thereto.

[0203] In some embodiments, GPE 1910 is coupled to command fluidizer 1903, which provides a command stream to GPE 3D and media pipelines 1912, 1916. In some embodiments, command fluidizer 1903 is coupled to memory, which may be system memory or one or more internal cache memories and shared cache memories. In some embodiments, command fluidizer 1903 receives commands from memory and sends the commands to 3D pipeline 1912 and / or media pipeline 1916. The command is an instruction retrieved from a ring buffer that stores commands for 3D and media pipelines 1912, 1916. In one embodiment, the ring buffer may additionally include a batch command buffer that stores a batch of multiple commands. 3D and media pipelines 1912, 1916 process commands by performing operations via logic within the respective pipeline or by dispatching one or more execution threads to execution unit array 1914. In some embodiments, the execution unit array 1914 is scalable, such that the array includes a variable number of execution units based on the target power and performance level of the GPE 1910.

[0204] In some embodiments, the sampling engine 1930 is coupled to memory (e.g., cache memory or system memory) and the execution unit array 1914. In some embodiments, the sampling engine 1930 provides a memory access mechanism for the execution unit array 1914, which allows the execution array 1914 to read graphics and media data from memory. In some embodiments, the sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0205] In some embodiments, the specialized media sampling logic in the sampling engine 1930 includes a denoising / deinterlacing module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / deinterlacing module 1932 includes logic for performing one or more denoising or deinterlacing algorithms on the decoded video data. The deinterlacing logic combines alternating fields of interlaced video content into a single video frame. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising and deinterlacing logics are motion-adaptive and use spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / deinterlacing module 1932 includes dedicated motion detection logic (e.g., within the motion estimation engine 1934).

[0206] In some embodiments, the motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions such as motion vector estimation and prediction on video data. The motion estimation engine determines motion vectors that describe the transformations of image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on video at the macroblock level, operations that may otherwise be computationally too intensive to be performed by a general-purpose processor. In some embodiments, the motion estimation engine 1934 is typically used in graphics processor components to assist in video decoding and processing functions that are sensitive to or adapted to the direction or magnitude of motion within video data.

[0207] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to enhance the visual quality of the generated images and videos. In some embodiments, the scaling and filtering module 1936 processes image and video data during sampling operations before providing data to the execution unit array 1914.

[0208] In some embodiments, the GPE 1910 includes a data port 1944, which provides additional mechanisms for the graphics subsystem to access memory. In some embodiments, the data port 1944 facilitates memory access to operations including render target writes, constant buffer reads, temporary memory space read / writes, and media surface access. In some embodiments, the data port 1944 includes cache memory space for caching memory accesses. The cache memory may be a single data cache or may be divided into multiple caches (e.g., render buffer cache, constant buffer cache, etc.) for multiple subsystems accessing memory via the data port. In some embodiments, threads executing on execution units in the execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect coupled to each subsystem of the GPE 1910.

[0209] Execution unit

[0210] Figure 20 This is a block diagram of another embodiment of the graphics processor 2000. Elements having the same reference numerals (or names) as those in any other figures herein. Figure 20 The components may operate or function in any manner similar to those described elsewhere in this document, but are not limited thereto.

[0211] In some embodiments, the graphics processor 2000 includes a ring interconnect 2002, a pipelined front end 2004, a media engine 2037, and graphics cores 2080A-2080N. In some embodiments, the ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0212] In some embodiments, the graphics processor 2000 receives batch commands via a ring interconnect 2002. Incoming commands are interpreted by a command streamer 2003 in a pipeline front-end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2080A-2080N. For 3D geometry processing commands, the command streamer 2003 supplies commands to a geometry pipeline 2036. For at least some media processing commands, the command streamer 2003 supplies commands to a video front-end 2034 coupled to a media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2033 for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080A.

[0213] In some embodiments, the graphics processor 2000 includes scalable thread execution resource feature modular cores 2080A-2080N (sometimes referred to as core shards), each having a plurality of sub-cores 2050A-2050N and 2060A-2060N (sometimes referred to as core sub-shards). In some embodiments, the graphics processor 2000 may have any number of graphics cores 2080A to 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes a plurality of graphics cores 2080A-2080N, each including a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. Each sub-core in the set of first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. Each sub-core in the set of second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In some embodiments, each sub-core 2050A-2050N and 2060A-2060N shares a set of shared resources 2070A-2070N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0214] Figure 21 The figure illustrates thread execution logic 2100 of an array of processing elements employed in some embodiments of GPE. Elements having the same reference numerals (or names) as those in any other figures herein. Figure 21 The components may operate or function in any manner similar to those described elsewhere in this document, but are not limited thereto.

[0215] In some embodiments, thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array including multiple execution units 2108A-2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the included components are interconnected via an interconnect structure linking each component. In some embodiments, thread execution logic 2100 includes one or more connections to a memory such as system memory or cache memory via one or more of the instruction cache 2106, data port 2114, sampler 2110, and execution unit arrays 2108A-2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple concurrent threads and processing multiple data elements in parallel for each thread. In some embodiments, the execution unit arrays 2108A-2108N include any number of individual execution units.

[0216] In some embodiments, the execution unit arrays 2108A-2108N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2108A-2108N execute instruction sets that include native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct 3D and OpenGL) with minimal transformations. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders).

[0217] Each execution unit in the execution unit arrays 2108A-2108N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels used for instructions. An execution channel is a logical execution unit for data element access, masking, and flow control within an instruction. The number of channels can be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2108A-2108N support both integer and floating-point data types.

[0218] The execution unit instruction set includes Single Instruction Multiple Data (SIMD) instructions. Various data elements can be stored in registers as packed data types, and the execution unit will process these elements based on their data size. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad-word (QW) size data elements), eight separate 32-bit packed data elements (double-word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or 32 separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0219] One or more internal instruction caches (e.g., 2106) are included in thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0220] During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 2100 via thread production and dispatch logic. In some embodiments, thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics and media pipeline and instantiates the requested thread on one or more execution units 2108A-2108N. For example, the geometry pipeline (e.g., Figure 20 2036) dispatches vertex processing, tessellation, or geometry processing threads to thread execution logic 2100 ( Figure 21 In some embodiments, thread dispatcher 2104 may also handle runtime thread spawning requests from the shader program.

[0221] Once the geometric object group has been processed and rasterized into pixel data, pixel shader 2102 is dispatched to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, depth buffer, stencil buffer, etc.). In some embodiments, pixel shader 2102 computes values ​​of various vertex attributes to be interpolated onto the rasterized object. In some embodiments, pixel shader 2102 then executes a pixel shader program provided by an application programming interface (API). To execute the pixel shader program, pixel shader 2102 dispatches a thread to an execution unit (e.g., 2108A) via thread dispatcher 2104. In some embodiments, pixel shader 2102 uses texture sampling logic in sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and input geometry data compute pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0222] In some embodiments, data port 2114 provides a memory access mechanism for thread execution logic 2100, outputting processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data for memory access via the data port.

[0223] Figure 22 This is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having multiple instruction formats. Solid line block diagrams show components typically included in the execution unit instructions, while dashed lines represent optional components or components included only in a subset of the instructions. In some embodiments, the instruction format 2200 described and illustrated are macro instructions, as they are instructions supplied to the execution unit—as opposed to micro-operations generated from instruction decoding once the instruction is processed.

[0224] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit format 2210. A 64-bit compact instruction format 2230 may be available for some instructions, depending on the selected instructions, instruction options, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted to 64-bit format 2230. The native instructions available in 64-bit format 2230 vary depending on the embodiment. In some embodiments, instructions are compressed in part using a set of index values ​​in index field 2213. The execution unit hardware references a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instructions in 128-bit format 2210.

[0225] For each format, instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel on multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation on each color channel representing a texture element or image element. By default, the execution unit executes each instruction on all data channels of the operand. In some embodiments, instruction control field 2214 enables control over certain execution options, such as channel selection (e.g., prediction) and data channel order (e.g., allocation). For 128-bit instructions 2210, execution size field 2216 limits the number of data channels to be executed in parallel. In some embodiments, execution size field 2216 is not available for use in the 64-bit compact instruction format 2230.

[0226] Some execution unit instructions have up to three operands, including two source operands src0 2220 and src1 2222, and a destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0227] In some embodiments, the 128-bit instruction format 2210 includes access / addressing mode information 2226 specifying, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are directly provided by bits in the instruction 2210.

[0228] In some embodiments, the 128-bit instruction format 2210 includes an access / addressing mode field 2226, which specifies the addressing mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, instruction 2210 may use byte-aligned addressing for both source and destination operands, and when in a second mode, instruction 2210 may use 16-byte aligned addressing for all source and destination operands.

[0229] In one embodiment, the addressing mode portion of the access / addressing mode field 2226 determines whether the instruction uses direct or indirect addressing. When using direct register addressing mode, the bits in instruction 2210 directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0230] In some embodiments, instructions are grouped based on the 2212-bit field of the opcode to simplify opcode decoding 2240. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares five most significant bits (MSB), where the move (mov) instruction is of the form 0000xxxxb and the logic instruction is of the form 0001xxxxb. The flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions of the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) of the form 0011xxxxb (e.g., 0x30). Parallel math instruction group 2248 includes component-based arithmetic instructions (e.g., addition, multiplication (mul)) in the form of 0100xxxxb (e.g., 0x40). Parallel math group 2248 performs arithmetic operations in parallel on the data path. Vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic operations on vector operands, such as dot product calculations.

[0231] Graphics Pipeline

[0232] Figure 23 This is a block diagram of another embodiment of the graphics processor 2300. Elements having the same reference numerals (or names) as those in any other figures herein. Figure 23 The components may operate or function in any manner similar to those described elsewhere in this document, but are not limited thereto.

[0233] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a rendering output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by registers written to one or more control registers (not shown) or by commands issued to the graphics processor 2300 via a ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are interpreted by a command streamer 2303, which supplies instructions to the various components of the graphics pipeline 2320 or the media pipeline 2330.

[0234] In some embodiments, command fluidizer 2303 guides the operation of vertex acquirer 2305, which reads vertex data from memory and executes vertex processing commands provided by command fluidizer 2303. In some embodiments, vertex acquirer 2305 provides vertex data to vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex acquirer 2305 and vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A and 2352B via thread dispatcher 2331.

[0235] In some embodiments, execution units 2352A and 2352B are arrays of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 2352A and 2352B have an attached L1 cache 2351, which is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or partitioned into a single cache containing data and instructions in different partitions.

[0236] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable shell shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides back-end evaluation of the tessellation output. A tessellation unit 2313 operates in the direction of the shell shader 2311 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model provided as input to the graphics pipeline 2320. In some embodiments, the tessellation components 2311, 2313, and 2317 can be bypassed if tessellation is not used.

[0237] In some embodiments, the complete geometry object can be processed by the geometry shader 2319 via one or more threads dispatched to execution units 2352A, 2352B, or it can proceed directly to the trimmer 2329. In some embodiments, the geometry shader operates on the entire geometry object, rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0238] Prior to rasterization, clipper 2329 processes vertex data. Clipper 2329 may be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, rasterizer 2373 (e.g., a depth testing component) in the render output pipeline 2370 dispatches pixel shaders to transform geometric objects into their per-pixel representation. In some embodiments, pixel shader logic is included in thread execution logic 2350. In some embodiments, an application may bypass rasterizer 2373 and access unrasterized vertex data via outflow unit 2323.

[0239] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, execution units 2352A, 2352B and associated cache(s) 2351, texture and media sampler(s) 2354, and texture / sampler cache(s) 2358 are interconnected via data port 2356 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, sampler(s), cache(s) 2351, 2358, and execution units 2352A, 2352B each have a separate memory access path.

[0240] In some embodiments, the rendering output pipeline 2370 includes a rasterizer 2373 that transforms vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit that performs fixed-function triangle and line rasterization. Associated renderer cache 2378 and depth cache 2379 are also available in some embodiments. Pixel operation component 2377 performs pixel-based operations on the data, but in some cases, pixel operations associated with 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 2341, or replaced at display time by the display controller 2343 using an overlay display plane. In some embodiments, a shared L3 cache 2375 is available to all graphics components, allowing data to be shared without using main system memory.

[0241] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front-end 2334. In some embodiments, the video front-end 2334 receives pipeline commands from a command streamer 2303. In some embodiments, the media pipeline 2330 includes a separate command streamer. In some embodiments, the video front-end 2334 processes media commands before sending them to the media engine 2337. In some embodiments, the media engine 2337 includes thread production functionality to produce threads for dispatch to thread execution logic 2350 via a thread dispatcher 2331.

[0242] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and coupled to the graphics processor via a ring interconnect 2302 or some other interconnect bus or structure. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which may be a system-integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0243] In some embodiments, the graphics pipeline 2320 and media pipeline 2330 may be configured to perform operations based on multiple graphics and media programming interfaces and not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct3D library from Microsoft, or both OpenGL and D3D may be supported. Support may also be provided for the open-source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a pipeline mapping from future APIs to the graphics processor pipeline is possible.

[0244] Graphical Pipeline Programming

[0245] Figure 24A This is a block diagram illustrating a graphics processor command format 2400 according to some embodiments. Figure 24B This is a block diagram illustrating a graphics processor command sequence 2410 according to an embodiment. Figure 24A Solid lines in the diagram show components that are typically included in the graphics command, while dashed lines indicate optional components or components that are only included in a subset of the graphics command. Figure 24A An exemplary graphics processor command format 2400 may include data fields for identifying the target client 2402 of the command, a command operation code (opcode) 2404, and related data 2406 for the command. In some commands, a sub-opcode 2405 and a command size 2408 are also included.

[0246] In some embodiments, client 2402 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a client unit receives a command, it reads opcode 2404 and sub-opcode 2405—if present—to determine the operation to be performed. The client unit uses information in data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands based on the command opcode. In some embodiments, commands are aligned via multiple double words.

[0247] Figure 24B The flowchart illustrates an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the illustrated command sequence to set up, execute, and terminate a set of graphics operations. The example command sequence is shown and described for illustrative purposes only, as the embodiments are not limited to these specific commands or the command sequence. Moreover, commands can be issued as a batch of commands in a command sequence, such that the graphics processor will process the command sequence at least partially simultaneously.

[0248] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline dump clearing command 2412 to cause any active graphics pipeline to complete its current pending commands. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate simultaneously. Pipeline dump clearing is performed to cause any pending commands to be completed by the active graphics pipeline. In response to pipeline dump clearing, the command parser for the graphics processor suspends command processing until the active graphics engine completes its pending operations and the relevant read cache is invalidated. Optionally, any data marked as "dirty" in the renderer cache may be cleared during memory dumping. In some embodiments, pipeline dump clearing command 2412 may be used before placing the graphics processor in a low-power state or for pipeline synchronization.

[0249] In some embodiments, a pipeline selection command 2413 is used when a sequence of commands requires the graphics processor to explicitly switch between pipelines. In some embodiments, only one pipeline selection command 2413 is required in the execution context before a pipeline command is issued—unless the context requires issuing commands for two pipelines. In some embodiments, a pipeline dump clearing command 2412 is required immediately preceding the pipeline switch via pipeline selection command 2413.

[0250] In some embodiments, pipeline control command 2414 configures the graphics pipeline for operation and is used to program the 3D pipeline 2422 and the media pipeline 2424. In some embodiments, pipeline control command 2414 configures the pipeline state for the active pipeline. In one embodiment, pipeline control command 2414 is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing batch commands.

[0251] In some embodiments, the return buffer state command 2416 is used to configure a set of return buffers for a given pipeline to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers to which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 2416 includes selecting the size and number of return buffers for a set of pipeline operations.

[0252] The remaining commands in the command sequence differ based on the active pipeline used for the operation. Based on pipeline determination 2420, a customized command sequence is made for either the 3D pipeline 2422 that begins with 3D pipeline state 2430 or the media pipeline 2424 that begins with media pipeline state 2440.

[0253] Commands for 3D pipeline state 2430 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API being used. In some embodiments, 3D pipeline state 2430 commands can also selectively disable or bypass certain pipeline elements—if these elements will not be used.

[0254] In some embodiments, 3D primitive 2432 commands are used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters passed to the graphics processor via 3D primitive 2432 commands are forwarded to the vertex extraction function in the graphics pipeline. The vertex extraction function uses the 3D primitive 2432 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 2432 commands are used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution unit.

[0255] In some embodiments, the 3D pipeline 2422 is triggered by executing command 2434 or an event. In some embodiments, register writes trigger command execution. In some embodiments, execution is triggered by a "go" or "kick" command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution to clear the command sequence via a graphics pipeline dump. The 3D pipeline performs geometry processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized, and the pixel engine shades the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for these operations.

[0256] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Typically, the specific use and programming of the media pipeline 2424 depends on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly associated with the rendering of graphics primitives.

[0257] In some embodiments, the media pipeline 2424 is configured in a manner similar to that of the 3D pipeline 2422. Prior to the media object command 2442, a set of media pipeline status commands 2440 are dispatched or placed in a command queue. In some embodiments, the media pipeline status commands 2440 include data configuring media pipeline elements that will be used to process media objects. This includes data configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline status commands 2440 also support the use of one or more pointers to "indirect" status elements that contain batch status settings.

[0258] In some embodiments, media object command 2442 supplies a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 2442. Once the pipeline states are configured and media object command 2442 is queued, media pipeline 2424 is triggered via execution command 2444 or an equivalent execution event (e.g., register write). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0259] Graphical software architecture

[0260] Figure 25The figure illustrates an exemplary graphics software architecture for a data processing system 2500 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, the processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. The graphics application 2510 and the operating system 2520 each execute in the system memory 2550 of the data processing system.

[0261] In some embodiments, the 3D graphics application 2510 includes one or more shader programs, which include shader instructions 2512. The shader language instructions may be a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2514 in machine language suitable for execution by a general-purpose processor core 2534. The application also includes graphics objects 2516 defined by vertex data.

[0262] In some embodiments, the operating system 2520 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary Unix-like operating system, or an open-source Unix-like operating system using a variant of the Linux kernel. When the Direct3D API is used, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a lower-level shader language. Compilation can be just-in-time (JIT) compilation or application-enabled shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 2510.

[0263] In some embodiments, the user-mode graphics driver 2526 includes a back-end shader compiler 2527 for translating shader instructions 2512 into a hardware-specific representation. When the OpenGL API is used, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functionality 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0264] IP Core Implementation

[0265] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within a processor. When read by a machine, the instructions can cause the machine to manufacture logic to perform the techniques described herein. This representation, referred to as an "IP core," is a reusable unit of logic for an integrated circuit that can be stored on a tangible machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model can be supplied to various customers or manufacturing facilities that load it onto manufacturing machines that produce the integrated circuit. The integrated circuit can be manufactured such that the circuit performs the operations described in association with any of the embodiments described herein.

[0266] Figure 26 This is a block diagram illustrating an IP core development system 2600, according to an embodiment, that can be used to fabricate integrated circuits to perform operations. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). Design facility 2630 can generate software simulation 2610 of the IP core design using a high-level programming language (e.g., C / C++). Software simulation 2610 can be used to design, test, and verify the behavior of the IP core. Register transfer level (RTL) designs can then be created or synthesized from the simulation model 2600. RTL design 2615 is an abstraction of the behavior of an integrated circuit, modeling the flow of digital signals between hardware registers that include associated logic performed using modeled digital signals. In addition to RTL design 2615, low-level designs at the logic level or transistor level can also be created, designed, or synthesized. Therefore, specific details of the initial design and simulation can vary.

[0267] The RTL design 2615 or its equivalent can be further synthesized by the design facility into a hardware model 2620, which may be a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to validate the IP core design. The IP core design can be stored in non-volatile memory 2640 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2665. Alternatively, the IP core design can be transmitted via a wired connection 2650 or a wireless connection 2660 (e.g., via the Internet). The manufacturing facility 2665 can then manufacture an integrated circuit at least partially based on the IP core design. The manufactured integrated circuit can be configured to perform operation according to at least one embodiment described herein.

[0268] Figure 27This is a block diagram illustrating an exemplary system on a chip integrated circuit 2700 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit includes one or more application processors 2705 (e.g., a CPU), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which may be a modular IP core from the same or more different design facilities. The integrated circuit includes peripheral or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, and an I... 2 S / I 2 C controller 2740. Additionally, the integrated circuit may include a display device 2745, which is coupled to one or more High Definition Multimedia Interface (HDMI) controllers 2750 and Mobile Industrial Processor Interface (MIPI) display interfaces 2755. Storage may be provided by a flash memory subsystem 2760 including flash memory and a flash memory controller. A memory interface for accessing SDRAM or SRAM memory devices may be provided via a memory controller 2765. Some integrated circuits also include an embedded security engine 2770.

[0269] Additionally, the processor in the integrated circuit 2700 may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0270] Advantageously, any of the above systems, processors, graphics processors, devices and / or methods can be integrated with or utilize the configuration of any (e.g., or a portion thereof) of the various embodiments described herein, including those described, for example, in the following additional notes and examples.

[0271] Additional notes and examples

[0272] Example 1 may include an automotive system including a gaze detector; and at least one virtual mirror coupled to the gaze detector; wherein the gaze detector continuously monitors the driver of the vehicle to determine whether the driver is looking in the direction of the virtual mirror; and if the driver is not looking in the direction of the virtual mirror, the virtual mirror is placed in a low-operation mode.

[0273] Example 2 may include the automotive system of Example 1, wherein if the driver is looking in the direction of the virtual mirror, the virtual mirror is placed in a high operating mode.

[0274] Example 3 may include the automotive system of Example 1, wherein the at least one virtual mirror comprises a plurality of virtual mirrors coupled to the gaze detector, wherein if the driver is not looking in the direction of one of the plurality of virtual mirrors, each of the plurality of virtual mirrors is placed in a low operating mode.

[0275] Example 4 may include the vehicle system of Example 3, wherein if the driver is looking in the direction of one of the plurality of virtual mirrors, the virtual mirror being viewed is placed in a high operating mode and each of the remaining virtual mirrors is placed in a low operating mode.

[0276] Example 5 may include the automotive system of Example 3, wherein each virtual mirror includes a camera communicatively coupled to a display, the camera capturing images of the environment surrounding the vehicle in real time, and the display showing the captured images.

[0277] Example 6 may include the automotive system of Example 5, wherein an encoder and a decoder are coupled between the camera and the display of each virtual mirror.

[0278] Example 7 may include the automotive system of Example 6, wherein the low operating mode includes a lower resolution of at least one of the display, camera, and encoder.

[0279] Example 8 may include the automotive system of Example 6, wherein the low operating mode includes a low frame rate of at least one of the display, camera, and encoder.

[0280] Example 9 may include the automotive system of Example 6, wherein the high operating mode includes the resolution and frame rate of the display, camera, and encoder operating at full capacity.

[0281] Example 10 may include the automotive system of Example 9, wherein the full capacity includes a frame rate of 60 frames per second and a high-definition resolution of 1920×1080 pixels.

[0282] Example 11 may include the automotive systems of Examples 1, 3 and 4, wherein placing the virtual mirror in a low operating mode includes placing the virtual mirror in a power-saving mode.

[0283] Example 12 may include a method for optimizing the performance of a car virtual mirror, comprising: monitoring the driver’s eyes via a gaze detector to determine whether the driver is looking in the direction of the virtual mirror; and if the driver is not looking in the direction of the virtual mirror, placing all virtual mirrors in a low operating mode.

[0284] Example 13 may include the method of Example 12, wherein if the driver is looking in the direction of the virtual mirror, the virtual mirror being viewed is placed in a high operating mode and all other virtual mirrors are placed in a low operating mode.

[0285] Example 14 may include the methods of Examples 12-13, wherein the low operating mode includes a lower resolution of at least one of the virtual mirror's display, camera, and encoder.

[0286] Example 15 may include the methods of Examples 12-13, wherein the low operating mode includes a low frame rate of at least one of the virtual mirror’s display, camera, and encoder.

[0287] Example 16 may include the method of Example 13, wherein the high operating mode includes the resolution and frame rate of the virtual mirror operating at full capacity.

[0288] Example 17 may include the method of Example 16, wherein the full capacity includes a frame rate of 60 frames per second and a high-definition resolution of 1920×1080 pixels.

[0289] Example 18 may include the method of Example 17, wherein the low operating mode is at least one-quarter of the full capacity in terms of frame rate and resolution.

[0290] Example 19 may include the method of Example 16, wherein the virtual mirror includes a camera, an encoder, a decoder, and a display, and full-capacity operation includes enabling the camera, the encoder, and the display to operate at full frame rate and full resolution.

[0291] Example 20 may include a system for optimal power performance of a virtual mirror in a vehicle, including a gaze detector that monitors the driver’s eye and head movements to determine whether the driver is looking in the direction of the virtual mirror; and if the driver is not looking in the direction of the virtual mirror, the gaze detector sends a signal to all virtual mirrors to put them into a low operating mode; and if the driver is looking in the direction of the virtual mirror, the gaze detector sends a signal to the virtual mirror being viewed to put it into a high operating mode, and the gaze detector sends a signal to all other virtual mirrors to put them into a low operating mode.

[0292] Example 21 may include the system of Example 20, wherein the virtual mirror includes a display, a camera, and an encoder, and the low operating mode includes a lower resolution of at least one of the display, the camera, and the encoder of the virtual mirror.

[0293] Example 22 may include the system of Example 21, wherein the low operating mode includes a low frame rate of at least one of the virtual mirror’s display, camera, and encoder.

[0294] Example 23 may include the system of Example 21, wherein placing all virtual mirrors in a low operating mode includes reducing the resolution of the display.

[0295] Example 24 may include the system of Example 21, wherein placing all virtual mirrors in a low operating mode includes reducing the frame rate of the display.

[0296] Example 25 may include the system of Example 21, wherein placing all virtual mirrors in a low operating mode includes reducing the resolution of the camera.

[0297] Example 26 may include the system of Example 21, wherein placing all virtual mirrors in a low operating mode includes reducing the frame rate of the camera.

[0298] Example 27 may include the system of Example 21, wherein placing all virtual mirrors in a low operating mode includes reducing the resolution of the encoder.

[0299] Example 28 may include the system of Example 21, wherein placing all virtual mirrors in a low operating mode includes reducing the frame rate of the encoder.

[0300] Example 29 may include the system of Example 21, wherein each virtual mirror includes a display, a camera, and an encoder, and the high operating mode includes the resolution and frame rate of the display, camera, and encoder of each virtual mirror operating at full capacity.

[0301] Example 30 may include the system of Example 29, wherein the full capacity includes a frame rate of at least 60 frames per second and a high-definition resolution of at least 1920×1080 pixels.

[0302] Example 31 may include the system of Example 29, wherein the low operating mode is at least one-quarter of the full capacity.

[0303] Example 32 may include the system of Example 20, wherein the virtual mirror includes a camera, an encoder, a decoder, and a display, and full-capacity operation includes enabling the camera, the encoder, and the display to operate at full frame rate and full resolution.

[0304] Example 33 may include at least one computer-readable medium including a set of instructions that, when executed by a computing device, cause the computing device to monitor the driver's eyes via a gaze detector to determine whether the driver is looking in the direction of the virtual mirrors; and if the driver is not looking in the direction of the virtual mirrors, to put all virtual mirrors into a low-operation mode.

[0305] Example 34 may include at least one computer-readable medium of Example 33, wherein, if the driver is looking in the direction of the virtual mirror, when the set of instructions is executed by the computing device, the computing device causes the virtual mirror being viewed to be placed in a high operating mode and all other virtual mirrors to be placed in a low operating mode.

[0306] Example 35 may include at least one computer-readable medium of Examples 33-34, wherein the low operating mode includes a lower resolution of at least one of the virtual mirror’s display, camera, and encoder.

[0307] Example 36 may include at least one computer-readable medium of Examples 33-34, wherein the low operating mode includes a low frame rate of at least one of the virtual mirror’s display, camera, and encoder.

[0308] Example 37 may include at least one computer-readable medium of Example 34, wherein the high operating mode includes the resolution and frame rate of the virtual mirror operating at full capacity.

[0309] Example 38 may include at least one computer-readable medium of Example 37, wherein the full capacity includes a frame rate of 60 frames per second and a high-definition resolution of 1920×1080 pixels.

[0310] Example 39 may include at least one computer-readable medium of Example 38, wherein the low operating mode is at least one-quarter of the full capacity in terms of frame rate and resolution.

[0311] Example 40 may include at least one computer-readable medium of Example 37, wherein the virtual mirror includes a camera, an encoder, a decoder, and a display, and full-capacity operation includes enabling the camera, the encoder, and the display to operate at full frame rate and full resolution.

[0312] Example 41 may include a system for optimal power performance of virtual mirrors in a vehicle, including means for monitoring the driver’s eye and head movements to determine whether the driver is looking in the direction of the virtual mirror; means for placing all virtual mirrors in a low operating mode if the driver is not looking in the direction of the virtual mirror; and means for placing the virtual mirror being viewed in a high operating mode if the driver is looking in the direction of the virtual mirror, and means for placing all other virtual mirrors in a low operating mode.

[0313] Example 42 may include the system of Example 41, wherein the low operating mode includes a lower resolution of at least one of the virtual mirror’s display, camera, and encoder.

[0314] Example 43 may include the system of Example 41, wherein the low operating mode includes a low frame rate of at least one of the virtual mirror’s display, camera, and encoder.

[0315] Example 44 may include the system of Example 41, wherein the means for placing all virtual mirrors in a low operating mode includes means for reducing the resolution of the display for each virtual mirror.

[0316] Example 45 may include the system of Example 41, wherein the means for placing all virtual mirrors in a low operating mode includes means for reducing the frame rate of the display for each virtual mirror.

[0317] Example 46 may include the system of Example 41, wherein the means for placing all virtual mirrors in a low operating mode includes means for reducing the resolution of the camera for each virtual mirror.

[0318] Example 47 may include the system of Example 41, wherein the means for placing all virtual mirrors in a low operating mode includes means for reducing the frame rate of the camera for each virtual mirror.

[0319] Example 48 may include the system of Example 41, wherein the means for placing all virtual mirrors in a low operating mode includes means for reducing the resolution of the encoder for each virtual mirror.

[0320] Example 49 may include the system of Example 41, wherein the means for placing all virtual mirrors in a low operating mode includes means for reducing the frame rate of the encoder for each virtual mirror.

[0321] Example 50 may include the system of Example 41, wherein the high operating mode includes the resolution and frame rate of the display, camera, and encoder of the virtual mirror operating at full capacity.

[0322] Example 51 may include the system of Example 50, wherein the full capacity includes a frame rate of at least 60 frames per second and a high-definition resolution of at least 1920×1080 pixels.

[0323] Example 52 may include the system of Example 50, wherein the low operating mode is at least one-quarter of the full capacity.

[0324] Example 53 may include the system of Example 41, wherein the virtual mirror includes a camera, an encoder, a decoder, and a display, and includes means for enabling the camera, the encoder, and the display to operate at full frame rate and full resolution in full-capacity operation.

[0325] Example 54 may include an automotive system comprising: a gaze detector including an embedded processor and a memory device; and a plurality of virtual mirrors, each virtual mirror being coupled to the gaze detector; wherein the gaze detector continuously monitors the driver of the vehicle to determine whether the driver is looking in the direction of one of the plurality of virtual mirrors; and if the driver is not looking in the direction of one of the plurality of virtual mirrors, each of the plurality of virtual mirrors is placed in a low operating mode.

[0326] Example 55 may include the automotive system of Example 54, wherein if the driver is looking in the direction of one of the plurality of virtual mirrors, the virtual mirror being viewed is placed in a high operating mode and each of the remaining virtual mirrors is placed in a low operating mode.

[0327] Example 56 may include the automotive system of Example 54, wherein each virtual mirror includes a camera that is communicatively coupled to a display.

[0328] Example 57 may include the automotive system of Example 56, wherein an encoder and a decoder are coupled between the camera and the display of each virtual mirror.

[0329] Example 58 may include the automotive system of Example 57, wherein the low operating mode includes a lower resolution of at least one of the display, camera, and encoder.

[0330] Example 59 may include the automotive system of Example 57, wherein the low operating mode includes a lower frame rate of at least one of the display, camera, and encoder.

[0331] Example 60 may include the automotive system of Example 57, wherein a high operating mode includes the resolution and frame rate of the display, camera, and encoder operating at full capacity.

[0332] Example 61 may include the automotive system of Example 60, wherein the full capacity includes a frame rate of 60 frames per second and a high-definition resolution of 1920×1080 pixels.

[0333] Example 62 may include at least one computer-readable medium comprising a set of instructions which, when executed by a computing system, cause the computing system to perform a method according to any one of Examples 12-19.

[0334] The term “coupling” may be used herein to refer to any type of direct or indirect relationship between the components under discussion and may be applied to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Additionally, unless otherwise indicated, the terms “first,” “second,” etc., may be used herein merely to facilitate discussion and do not carry any particular temporal or chronological significance. Furthermore, it should be understood that the indefinite article “a” or “an” carries the meaning of “one or more” or “at least one.”

[0335] As used in this application and claims, a list of items connected by the term "one or more of..." can refer to any combination of the listed items. For example, the phrase "one or more of A, B, or C" can mean A, B, C; A and B; A and C; B and C; or A, B, and C.

[0336] The embodiments have been described above with reference to specific examples. However, those skilled in the art will understand that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the foregoing description and drawings are to be considered illustrative rather than restrictive.

Claims

1. A vehicle system, comprising: gaze detector; as well as At least one virtual mirror coupled to the gaze detector, wherein the virtual mirror includes a display and a camera; The encoder and decoder are coupled between the camera and the display; The gaze detector continuously monitors the driver's eye position, eye movements, and head movements to determine whether the driver is looking in the direction of the virtual mirror; and If the driver is looking in the direction of the virtual mirror, then the virtual mirror is placed in a high operating mode; If the driver is not looking in the direction of the virtual mirror, the virtual mirror is placed in a low operating mode; High operating mode is a mode in which the display, camera, encoder, and decoder operate at full resolution and / or frame rate; Low operating mode is a mode in which the display, camera, encoder, and decoder operate at a reduced resolution and / or frame rate compared to full resolution and / or frame rate, and / or the display operates at a reduced brightness compared to high operating mode. The display has a backlight and a liquid crystal display (LCD) panel, wherein the backlight includes a plurality of light-emitting elements arranged at the edges of the LCD panel, wherein selective illumination of the area can be achieved by combining the edges.

2. The vehicle system of claim 1, wherein, The at least one virtual mirror includes a plurality of virtual mirrors coupled to the gaze detector, wherein if the driver is not looking in the direction of one of the plurality of virtual mirrors, each of the plurality of virtual mirrors is placed in a low operating mode.

3. The vehicle system of claim 2, wherein, If the driver is looking in the direction of one of the multiple virtual mirrors, the virtual mirror being viewed is set to a high operating mode and each of the remaining virtual mirrors is set to a low operating mode.

4. The vehicle system of claim 2, wherein, The camera will capture images of the environment around the car in real time, and the display will show the captured images.

5. The vehicle system of claim 1, wherein, The high operating mode includes the resolution and frame rate of the display, camera, and encoder operating at full capacity.

6. The vehicle system of claim 5, wherein, The full capacity includes a frame rate of 60 frames per second and a high-definition resolution of 1920×1080 pixels.

7. The automobile system of any one of claims 1, 2, and 3, wherein, Placing the virtual mirror in a low-operation mode includes placing the virtual mirror in a power-saving mode.

8. A method for achieving optimal performance for a virtual car mirror, comprising: A gaze detector is used to monitor the driver's eye position, eye movement, and head movement to determine whether the driver is looking in the direction of the virtual mirror; as well as If the driver is looking in the direction of the virtual mirror, then the virtual mirror is placed in a high operating mode; If the driver is not looking in the direction of the virtual mirror, all virtual mirrors will be placed in low operating mode. High operating mode is a mode in which the display, camera, encoder, and decoder operate at full resolution and / or frame rate; The low operating mode is a mode in which the display, camera, encoder, and decoder operate at a reduced resolution and / or frame rate compared to full resolution and / or frame rate, and / or the display operates at a reduced brightness compared to the high operating mode. The display has a backlight and a liquid crystal display (LCD) panel, wherein the backlight includes a plurality of light-emitting elements arranged at the edges of the LCD panel, wherein selective illumination of the area can be achieved by combining the edges.

9. The method of claim 8, wherein, If the driver is looking in the direction of the virtual mirror, the virtual mirror being viewed will be set to high operating mode and all other virtual mirrors will be set to low operating mode.

10. The method of claim 8, wherein, The high-performance operating mode includes the resolution and frame rate of the virtual mirror operating at full capacity.

11. The method of claim 10, wherein, The full capacity includes a frame rate of 60 frames per second and a high-definition resolution of 1920×1080 pixels.

12. The method of claim 11, wherein, Low operating mode offers at least a quarter of the full capacity in terms of frame rate and resolution.

13. The method of claim 10, wherein, Operating at full capacity includes enabling the camera, encoder, and display to operate at full frame rate and full resolution.

14. A system for optimal power performance of a virtual mirror in an automobile, comprising: A gaze detector monitors the driver's eye position, eye movement, and head movement to determine whether the driver is looking in the direction of the virtual mirror; as well as If the driver is looking in the direction of the virtual mirror, then the virtual mirror is placed in a high operating mode; If the driver is not looking in the direction of the virtual mirror, the gaze detector will send a signal to all virtual mirrors to put them into a low operating mode; as well as If the driver is looking in the direction of the virtual mirror, the gaze detector will send a signal to the virtual mirror being viewed to put it into a high operating mode, and the gaze detector will send a signal to all other virtual mirrors to put them into a low operating mode. High operating mode is a mode in which the display, camera, encoder, and decoder operate at full resolution and / or frame rate; The low operating mode is a mode in which the display, camera, encoder, and decoder operate at a reduced resolution and / or frame rate compared to full resolution and / or frame rate, and / or the display operates at a reduced brightness compared to the high operating mode. The display has a backlight and a liquid crystal display (LCD) panel, wherein the backlight includes a plurality of light-emitting elements arranged at the edges of the LCD panel, wherein selective illumination of the area can be achieved by combining the edges.

15. A device for optimal performance of a virtual mirror for automobiles, comprising: A device for monitoring the driver’s eye position, eye movement and head movement via a gaze detector to determine whether the driver is looking in the direction of a virtual mirror; as well as A device for placing the virtual mirror into a high operating mode if the driver is looking in the direction of the virtual mirror; A device for setting all virtual mirrors to a low operating mode if the driver is not looking in the direction of the virtual mirrors; High operating mode is a mode in which the display, camera, encoder, and decoder operate at full resolution and / or frame rate; The low operating mode is a mode in which the display, camera, encoder, and decoder operate at a reduced resolution and / or frame rate compared to full resolution and / or frame rate, and / or the display operates at a reduced brightness compared to the high operating mode. The display has a backlight and a liquid crystal display (LCD) panel, wherein the backlight includes a plurality of light-emitting elements arranged at the edges of the LCD panel, wherein selective illumination of the area can be achieved by combining the edges.

16. The device of claim 15, wherein, If the driver is looking in the direction of the virtual mirror, the virtual mirror being viewed will be set to high operating mode and all other virtual mirrors will be set to low operating mode.

17. The device of claim 15, wherein, The high-performance operating mode includes the resolution and frame rate of the virtual mirror operating at full capacity.

18. The device of claim 17, wherein, The full capacity includes a frame rate of 60 frames per second and a high-definition resolution of 1920×1080 pixels.

19. The device of claim 18, wherein, Low operating mode offers at least a quarter of the full capacity in terms of frame rate and resolution.

20. The device of claim 17, wherein, Operating at full capacity includes enabling the camera, encoder, and display to operate at full frame rate and full resolution.

21. A computer-readable medium having instructions thereon that, when executed, cause a computer device to perform the method according to any one of claims 8-13.

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