HDR enhancement using time multiplexing

Abstract

This application discloses HDR enhancement using temporal multiplexing. Systems, devices, and methods may include a performance-enhanced computing system comprising: a sensor for measuring luminance values corresponding to light focused onto the sensor at multiple pixel locations; a memory comprising a set of instructions; and a processor. The processor executes the set of instructions, causing the system to: generate a multi-segment tone mapping curve; generate a set of tone mapping values corresponding to the multi-segment tone mapping curve for storing equally spaced input values between zero and one in a lookup table; and process the luminance values using the lookup table to apply the tone mapping curve to the luminance values of the pixels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a U.S. patent application claiming the benefit of priority to Indian Patent Application No. 201741014415 filed on April 24, 2017. Technical Field

[0003] Embodiments relate generally to graphics processing architectures and more particularly to HDR enhancement using time-multiplexed processing in graphics processing architectures. Background Art

[0004] In a computer display setting, a source platform (e.g., a game console, a computer, a camera, a video recording device) can encode (e.g., compress) a video signal, such as a movie or a three-dimensional (3D) game, for wireless transmission to a display. Each frame in the video signal can contain high dynamic range (HDR) content that is dynamically generated as each frame of the video is produced. Video containing a series of HDR images typically requires significant processing resources to generate a real-time video stream using conventional processing. If each HDR image is generated using HDR enhancement using time multiplexing as disclosed herein with respect to the present invention, the difficulties associated with generating a real-time HDR video stream can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various advantages of the embodiments will become apparent to those skilled in the art from a reading of the following description and appended claims, and from a reference to the following drawings, in which:

[0006] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0007] Figures 2A to 2D A parallel processor component according to an embodiment is shown;

[0008] Figure 3A to Figure 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0009] Figures 4A to 4F An exemplary architecture is presented in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0010] Figure 5 Demonstrating a graphics processing pipeline according to an embodiment;

[0011] Figure 6A is a presentation of an example of a high dynamic range (HDR) image generated using multiple images according to an embodiment;

[0012] Figure 6B shows a timeline identifying shutter times used to generate scanned images 611 to 613 according to an embodiment of the present invention;

[0013] Figure 6C shows a processing architecture 700 using HDR enhancement using time multiplexing processing according to an embodiment of the present invention;

[0014] Figure 6D Demonstrating the use of interleaved scanning to obtain an HDR image from a sensor according to an embodiment;

[0015] Figure 6E is a conceptual block diagram of a processing system for generating an HDR image for display using an enhanced alpha channel according to an embodiment;

[0016] Figure 6F Demonstrates two-bit alpha channel image fusion according to an embodiment of the present invention;

[0017] Figure 6G is a conceptual block diagram of a processing system for generating an HDR image for display using matching dynamic range and color gamut according to an embodiment;

[0018] Figure 6H An example tone mapping is shown for transforming an input image to match dynamic range and color gamut when generating an HDR image for display, according to an embodiment;

[0019] Figure 6I An example tone mapping is shown for transforming an input image to match dynamic range and color gamut when generating an HDR image for display, according to an embodiment;

[0020] Figure 6J A flowchart illustrating a process for generating a tone map for transforming an input image to match dynamic range and color gamut when generating an HDR image for display is shown in accordance with an embodiment.

[0021] Figure 7 is a conceptual block diagram of a processing system for generating an HDR image enhanced with temporal multiplexing, according to an embodiment;

[0022] Figure 8 is a flowchart of an example of a method of selecting an encoding amount based on a brightness level according to an embodiment;

[0023] Figure 9 is a block diagram of an example of a computing system according to an embodiment;

[0024] Figure 10 is a display of an example of a semiconductor packaging device according to an embodiment;

[0025] Figure 11is a block diagram of an example of a display with local backlight capability according to an embodiment;

[0026] Figure 12A is a block diagram of an example of a data processing apparatus according to an embodiment;

[0027] Figure 12B is a demonstration of an example of distance determination according to an embodiment;

[0028] Figure 13 is a block diagram of an example of a layered display architecture according to an embodiment;

[0029] Figure 14 is a block diagram of an example of a display architecture according to an embodiment, the display architecture including a plurality of display units;

[0030] Figure 15 is a block diagram of an example of a cloud-assisted media delivery architecture according to an embodiment;

[0031] Figures 16 to 18 is a block diagram of an example of an overview of a data processing system according to an embodiment;

[0032] Figure 19 is a block diagram of an example of a graphics processing engine according to an embodiment;

[0033] Figures 20 to 22 is a block diagram of an example of an execution unit according to an embodiment;

[0034] Figure 23 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0035] FIG. 24A to FIG. 24B is a block diagram of an example of a graphics pipeline according to an embodiment;

[0036] Figure 25 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0037] Figure 26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0038] Figure 27 is a block diagram of an example of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0039] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the present invention.

[0040] System Overview

[0041] Figure 1 is a block diagram illustrating a computing system 100 that is configured to implement one or more aspects of the embodiments described herein. Computing system 100 includes a processing subsystem 101 having one or more processors 102 and system memory 104, the processors and the system memory communicating via an interconnect path that may include a memory hub 105. Memory hub 105 may be a separate component within a chipset component or may be integrated within one or more processors 102. Memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. I / O subsystem 111 includes an I / O hub 107 that may enable computing system 100 to receive input from one or more input devices 108. Additionally, I / O hub 107 may enable a display controller that may be included in one or more processors 102 to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I / O hub 107 may include local, internal, or embedded display devices.

[0042] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 that are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, the PCI Express bus), or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computationally focused parallel or vector processing system that includes a large number of processing cores and / or processing clusters (such as, for example, many-integrated-core (MIC) processors). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 110B.

[0043] Within the I / O subsystem 111, a system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that can be integrated into the platform, as well as various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0044] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI Express bus) or any other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect, or interconnect protocols known in the art).

[0045] In one embodiment, one or more parallel processors 112 include circuits optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 include circuits optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of computing system 100 may be integrated on a single integrated circuit along with one or more other system elements. For example, one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0046] It will be appreciated that the computing system 100 shown herein is illustrative and that various variations and modifications are possible. The connection topology, including the number and banks of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, may be modified as desired. For example, in some embodiments, the system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 112.

[0047] Some specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be different from those described in the preceding text. Figure 1 Different terminology may be used for components that are similar to those shown in FIG. For example, in some architectures, memory hub 105 may be referred to as a northbridge, while I / O hub 107 may be referred to as a southbridge.

[0048] Figure 2A A parallel processor 200 according to an embodiment is shown. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is Figure 1 A variation of one or more parallel processors 112 is shown in .

[0049] In one embodiment, parallel processor 200 includes parallel processing unit (PPU) 202. The PPU includes an I / O unit 204 that enables communication with other devices, including other instances of PPU 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 connects to other devices using a hub or switch interface (e.g., memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within PPU 202, I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, wherein host interface 206 receives commands related to performing processing operations and memory crossbar 216 receives commands related to performing memory operations.

[0050] When host interface 206 receives command buffers via I / O unit 204, it can direct work operations for executing those commands to front-end 208. In one embodiment, front-end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before tasks are distributed to its processing clusters. In one embodiment, scheduler 210 is implemented via firmware logic executing on a microcontroller. A microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 212. In one embodiment, host software can identify workloads for scheduling on processing array 212 via one of multiple image processing doorbells. The workload can then be automatically distributed across processing array 212 by scheduler 210 logic within the scheduler microcontroller.

[0051] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A-214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to assign work to the clusters 214A-214N of the processing cluster array 212, which may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by the scheduler 210, or may be assisted in part by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 may be assigned to process different types of programs, or to perform different types of computations.

[0052] Processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0053] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processors 200 are configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing units 202 may pass data from system memory via I / O units 204 for processing. During processing, the passed data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0054] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A to 214N in processing cluster array 212. In some embodiments, multiple portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. Intermediate data generated by one or more of clusters 214A to 214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A to 214N for further processing.

[0055] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include an index of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data), as well as state parameters and commands defining how the data is to be processed (e.g., what program to execute). The scheduler 210 may be configured to obtain an index corresponding to a task, or may receive these indexes from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured in a valid state before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0056] Each of the one or more instances of parallel processing units 202 can be coupled to parallel processor memory 222. Parallel processor memory 222 can be accessed via memory crossbar 216, which can receive memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar 216 can access parallel processor memory 222 via memory interface 218. Memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N), each of which can be coupled to a portion of parallel processor memory 222 (e.g., memory cells). In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0057] In various embodiments, memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (GRAM), such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory units 224A-224N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of memory units 224A-224N may vary and may be selected from a variety of conventional designs. Render targets (e.g., frame buffers or texture maps) may be stored across memory units 224A-224N, allowing partition units 220A-220N to write to multiple portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be eliminated to facilitate utilizing a unified memory design for system memory in conjunction with local cache memory.

[0058] In one embodiment, any of the clusters 214A-214N in the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to pass the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with a memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 for communication with the I / O unit 204 and a connection to a local instance of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0059] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if these different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems comprising one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0060] Figure 2B is a block diagram of the partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A2. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). L2 cache 221 is a read / write cache that is configured to execute load and store operations received from memory crossbar switch 216 and ROP 226. Read misses and urgent write-back requests are output by L2 cache 221 to frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via frame buffer interface 225 for processing. In one embodiment, frame buffer interface 225 interfaces with one of the memory units in parallel processor memory, such as memory units 224A to 224N of FIG. 2 (e.g., within parallel processor memory 222).

[0061] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, and the like. ROP 226 then outputs the processed graphics data that is stored in graphics memory. In some embodiments, ROP 226 includes compression logic that compresses depth or color data written to memory and decompresses depth or color data read from memory. The compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 226 may vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a tile-by-tile basis.

[0062] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A through 214N of FIG. 2 ) rather than within partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted via memory crossbar 216. The processed graphics data may be displayed on a display device (e.g., Figure 1 100 ), is routed for further processing by the processor(s) 102 , or is routed for processing by the processor(s) 102 . Figure 2A The processing is further processed by one of the processing entities within the parallel processor 200.

[0063] Figure 2C2 is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of FIG. The processing cluster 214 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a set of specific input data. In some embodiments, when multiple independent instruction units are not provided, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads. In other embodiments, when a common instruction unit is used, a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, and the common instruction unit is configured to issue instructions to a group of processing engines within each of the processing clusters. Unlike the SIMD execution regime (wherein all processing engines typically execute the same instruction), SIMT execution allows different threads to more easily pass through a given thread program along divergent execution paths. It will be understood by those skilled in the art that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0064] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an illustrative example of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar 240 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). The pipeline manager 232 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 240.

[0065] Each graphics multiprocessor 234 within a processing cluster 214 can include an identical set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). The function execution logic can be configured in a pipelined manner, in which new instructions can be issued before previous instructions are completed. The function execution logic supports a wide variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can be present.

[0066] Instructions transmitted to processing cluster 214 constitute threads. A group of threads executed across a set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during the cycle in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0067] In one embodiment, the graphics multiprocessor 234 includes internal cache memory to perform load and store operations. In one embodiment, the graphics multiprocessor 234 can forgo the internal cache and use cache memory within the processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 also has access to an L2 cache within a partition unit (e.g., partition units 220A through 220N in FIG. 2 ), which is shared across all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 202 can be used as global memory. Multiple embodiments (where a processing cluster 214 includes multiple instances of the graphics multiprocessor 234) can share common instructions and data, which can be stored in the L1 cache 308.

[0068] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of Figure 2. The MMU 245 includes: a set of page table entries (PTEs) for mapping virtual addresses of tiles (more on tiling) to physical addresses; and optionally a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. The physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving among the partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0069] In graphics and compute applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (e.g., a pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units, which may be co-located with partition units (e.g., partition units 220A through 220N of FIG. 2 ), as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0070] It will be appreciated that the core architecture described herein is illustrative and that various variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. Furthermore, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 cache, etc.

[0071] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0072] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into distinct memory addresses that can be accessed by the load / store unit 266.

[0073] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of these functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between the different warps executed by the graphics multiprocessor 324.

[0074] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) that executes instructions for the graphics multiprocessor 324. Depending on the embodiment, the GPGPU cores 262 may be architecturally similar or architecturally different. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or may implement variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (e.g., copying rectangles or pixel blending operations). In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0075] In one embodiment, GPGPU core 262 includes SIMD logic that can execute a single instruction to multiple groups of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. The SIMD instructions for GPGPU core can be generated by the shader compiler at compile time, or can be automatically generated when executing a program written and compiled for single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0076] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, resulting in very low-latency data transfer between the GPGPU core 262 and the register file 258. Shared memory 270 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 236. Shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU core 262 can programmatically store data in the shared memory in addition to the automatically cached data stored in the cache memory 272.

[0077] Figure 3A to Figure 3B Additional graphics multiprocessors are shown according to embodiments. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0078] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 is Figure 2DThe graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0079] Various components can communicate via interconnect fabric 327. In one embodiment, interconnect fabric 327 includes one or more crossbar switches to enable communication between the various components of graphics multiprocessor 325. In one embodiment, interconnect fabric 327 is a separate high-speed network fabric layer upon which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect fabric 327. For example, GPGPU cores 336A-336B, 337A-337B, and 338A-338B can each communicate with shared memory 346 via interconnect fabric 327. Interconnect fabric 327 can arbitrate communications within graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0080] Figure 3B FIG3 shows a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A to 356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores and load storage units, such as Figure 2D and Figure 3A 360A-360D to perform texture operations while sharing the instruction cache 354 and shared memory 362. In one embodiment, the execution resources 356A-356D can share multiple instances of the instruction cache 354 and shared memory 362 as well as texture and / or data cache memories 358A-358B. The various components can be accessed via a similar Figure 3A The interconnect structure 327 and the interconnect structure 352 communicate.

[0081] Those skilled in the art will understand that Figure 1 、 Figures 2A to 2D as well as Figures 3A to 3BThe architecture described in is illustrative and non-limiting with respect to the scope of the present embodiments. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (e.g., parallel processing unit 202 of FIG. 2 ), and one or more graphics processors or special-purpose processing units, without departing from the scope of the embodiments described herein.

[0082] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0083] Technologies for GPU to host processor interconnection

[0084] Figure 4A An exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440 to 443 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the present invention are not limited to any particular communication protocol or throughput.

[0085] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4AAll communications between the various system components shown in can be accomplished using the same protocols / links (eg, via a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0086] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or nano RAM. In one embodiment, a portion of the memory can be volatile memory and another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0087] As described below, although the various processors 405-406 and GPUs 410-413 may each be physically coupled to a specific memory 401-402, 420-423, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (yielding a total of 256GB of addressable memory in this example).

[0088] Figure 4B 4 shows additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0089] The processor 407 shown includes multiple cores 460A to 460D, each having a translation lookaside buffer 461A to 461D and one or more caches 462A to 462D. These cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the basic principles of the present invention (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). Caches 462A to 462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple groups of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 to 402 .

[0090] The coherence of data and instructions stored in the various caches 462A-462D, 456, and system memory 441 is maintained via inter-core communication over a coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the present invention.

[0091] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0092] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431 to 432, N, or the graphics processing engines 431 to 432, N may be individual GPUs integrated on a common package, line card, or chip.

[0093] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for translating virtual / effective cache to physical / real addresses. In one implementation, a cache 438 stores commands and data for efficient access by the graphics processing engines 431 to 432, N. In one embodiment, data stored in the cache 438 and graphics memory 433 to 434, N is kept consistent with the core caches 462A to 462D, 456 and the system memory 411. As mentioned, this may be accomplished via proxy circuitry 425 that participates in the cache coherence mechanism on behalf of cache 438 and memories 433-434, N (e.g., sending updates to and receiving updates from cache 438 relating to modifications / accesses to cache lines on processor caches 462A-462D, 456).

[0094] A set of registers 445 stores context data for threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations during context switches to save and restore the contexts of various threads (e.g., where a first thread is saved and a second thread is restored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 448 may store current register values to a designated area in memory (e.g., identified by a context pointer). It may then restore these register values upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0095] In one implementation, virtual / effective addresses from the graphics processing engine 431 are translated into real / physical addresses in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which multiple applications or virtual machines (VMs) share the resources of the graphics processing engines 431 to 432, N. These resources can be subdivided into "slices" that are allocated to the different VMs and / or applications based on their associated processing requirements and priorities.

[0096] Thus, the accelerator integrated circuit acts as a bridge to the system of the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management of the graphics processing engine.

[0097] Because the hardware resources of graphics processing engines 431-432, N are explicitly mapped into the real address space seen by host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of accelerator integrated circuit 436 is to physically separate graphics processing engines 431-432, N so that they appear to the system as independent units.

[0098] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Random Access Memory (Nano-Ram).

[0099] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433-434, M is the data that will be used most frequently by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by cores (and preferably not by graphics processing engines 431-432, N) within the caches 462A-462D, 456 of these cores and system memory 411.

[0100] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly to the accelerator integrated circuit 436 via interfaces 437 and 435 (again, these interfaces may utilize any form of bus or interface protocol) over a high-speed link 440. The accelerator integrated circuit 436 may perform operations related to the graphics processing engine 431-432, N. Figure 4B The same operations are described, but at potentially higher throughput given their close proximity to the coherency bus 462 and caches 462A-462D, 426.

[0101] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0102] In one embodiment of a dedicated process model, graphics processing engines 431 to 432, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431 to 432, N, thereby providing virtualization within a VM / partition.

[0103] In a dedicated process programming model, graphics processing engines 431 to 432, N can be shared by multiple VM / application partitions. This shared model requires a hypervisor to virtualize graphics processing engines 431 to 432, N to allow access by each operating system. For a single-partition system without a hypervisor, graphics processing engines 431 to 432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 to 432, N to provide access to each process or application.

[0104] For the shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431 to 432, N use a process handle to select a process element. In one embodiment, process elements are stored in system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431 to 432, N (that is, calling system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0105] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 436. An application effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process elements 483 are stored in response to a GPU call 481 from an application 480 executing on a processor 407. Process elements 483 contain the process state of the corresponding application 480. A work descriptor (WD) 484 contained in a process element 483 may be a single job requested by the application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application's address space 482.

[0106] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all processes or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0107] In one implementation, a dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 446 or individual graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0108] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 can be stored in registers 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 446, as shown. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing the segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can process interrupt events 492 received from the graphics acceleration module 446. When executing graphics operations, the effective addresses 493 generated by the graphics processing engines 431-432, N are converted by the MMU 439 into real addresses.

[0109] In one embodiment, a set of identical registers 445 is replicated for each graphics processing engine 431 to 432, N, and / or graphics acceleration module 446, and these registers can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integration slice 490. Example registers that can be initialized by a hypervisor are shown in Table 1.

[0110] Table 1 - Registers initialized by the hypervisor

[0111] 1 Slice Control Register 2 Real address (RA) dispatched process area pointer 3 Authority Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) hypervisor accelerator utilizing record pointers 9 Storage Description Register

[0112] Example registers that may be initialized by the operating system are shown in Table 2.

[0113] Table 2 - Registers initialized by the operating system

[0114] 1 Process and thread identifiers 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission mask 6 Job Descriptor

[0115] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information needed by the graphics processing engine 431-432, N to do its work, or it may be a pointer to a memory location where the application has set up a command queue for work to be done.

[0116] Figure 4E 4. Additional details of one embodiment of the sharing model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine for an operating system 495.

[0117] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced sharing and graphics directed shared.

[0118] In this model, hypervisor 496 owns graphics acceleration module 446 and makes its functionality available to all operating systems 495. For graphics acceleration module 446 to support virtualization by hypervisor 496, it must adhere to the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or graphics acceleration module 446 must provide a context save and restore mechanism. 2) Application job requests must be guaranteed to complete within a specified amount of time (including any transition failures), or graphics acceleration module 446 must provide the ability to preempt processing of jobs. 3) When operating in a shared-directed programming model, graphics acceleration module 446 must ensure fairness between processes.

[0119] In one embodiment, for a shared model, an application 480 is required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure used to describe work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 436 and graphics acceleration module 446 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Optionally, the hypervisor 496 may apply the current permission mask overwrite register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area can be pinned system memory.

[0120] Upon receiving the system call, the operating system 495 may verify that the application 480 is registered and has been given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0121] Table 3 – OS to Hypervisor call parameters

[0122] 1 Work Descriptor (WD) 2 Access Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0123] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has been registered and granted permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements of the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

[0124] Table 4 - Process element information

[0125] 1 Work Descriptor (WD) 2 Access Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 Status register (SR) value 10 Logical Partition ID (LPID) 11 Real Address (RA) hypervisor accelerator utilizing record pointers 12 Memory Descriptor Register (SDR)

[0126] In one embodiment, the hypervisor initializes the plurality of accelerator integration slice 490 registers 445 .

[0127] like Figure 4F As shown in FIG, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. This allows the entire virtual / effective memory space (sometimes referred to as the effective address space) to be distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access any physical memory using virtual addresses mapped to that memory.

[0128] In one embodiment, bias / coherency management circuitry 494A-494E within one or more of MMUs 439A-439E ensures cache coherency between the caches of the host processor (e.g., 405) and GPUs 410-413 and implements biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4F Multiple examples of bias / coherence management circuits 494A- 494E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436.

[0129] One embodiment allows GPU-attached memory 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without the typical performance drawbacks associated with full system cache coherence. The ability to access GPU-attached memory 420-423 as system memory without the burdensome cache coherence overhead provides a beneficial operating environment for GPU offload. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead can be critical to the execution time of offloaded computations. In situations with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setup, result access, and GPU computation all play a role in determining the effectiveness of GPU offload.

[0130] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, a page-granular structure comprising 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented using stolen memory ranges of one or more GPU-attached memories 420 to 423, with or without a bias cache in GPUs 410 to 413 (e.g., for caching frequently used / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0131] In one implementation, the bias table entry associated with each access to GPU attached memory 420-423 is accessed before the actual GPU memory access, resulting in the following operations. First, local requests from GPUs 410-413 that find their pages in the GPU bias (these local requests find their pages in the GPU bias) are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPUs that find their pages in the host bias are forwarded to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, requests from processor 405 that find the requested page in the host processor bias complete similarly to normal memory read requests. Alternatively, requests for GPU biased pages can be forwarded to GPUs 410-413. Then, if the GPU is not currently using the page, it can transfer the page to the host processor bias.

[0132] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of circumstances, a purely hardware-based mechanism.

[0133] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, instructing it to change the bias state and, for some transitions, performs a cache flushing operation in the host. The cache flushing operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0134] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not be granted immediately, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU bias pages are those pages that are needed by the GPU but not by host processor 405 (and vice versa).

[0135] Graphics processing pipeline

[0136] Figure 5 2. A graphics processing pipeline 500 is shown according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG. 2, which in one embodiment is Figure 1 2 . Various parallel processing systems may implement graphics processing pipeline 500 via one or more instances of parallel processing units (e.g., parallel processing unit 202 of FIG. 2 ) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functionality of one or more of vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment / pixel processing unit 524. The functionality of data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operations unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A through 220N of FIG. 2 ). Graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 in FIG. 2 ) via memory interface 528, which may be an example of memory interface 218 in FIG. 2 .

[0137] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes vertex shader programs to illuminate and transform vertex data as specified by the vertex shader programs. The vertex processing unit 504 reads data stored in cache, local, or system memory for use in processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0138] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc., which are supported by various graphics processing application programming interfaces (APIs).

[0139] The tessellation control processing unit 508 treats the input vertices as control points for the geometry patch. The control points are converted from an input representation from the patch (e.g., the basis of the patch) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometry patch. The tessellation factors are applied to individual edges and quantize the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as lines, triangles, or quadrilaterals, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0140] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform the graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and calculate parameters for rasterizing the new graphics primitives.

[0141] In some embodiments, the geometry processing unit 516 may add or delete elements from the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for use in processing geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0142] The rasterizer 522 can perform depth sorting and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. The fragment / pixel processing unit 524 transforms fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels that are output to the raster operations unit 526. The fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity depending on the sampling rate configured for the processing unit.

[0143] Raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 and / or Figure 1 The raster operations unit 526 may be configured to compress the z or color data written to memory and to decompress the z or color data read from memory.

[0144] HDR enhancement using time multiplexing

[0145] Now go to Figure 6A, shows a high dynamic range (HDR) image 601 (e.g., a still picture, a video frame). HDR image 601, which may also be referred to as an enhanced dynamic range (EDR) and / or wide dynamic range (WDR) image, may typically be part of visual content presented to a user in conjunction with a three-dimensional (3D) game, a virtual reality (VR) environment, an augmented reality (AR) environment, and the like. For example, HDR image 601 may be transmitted from a source device via a wireless link (e.g., Bluetooth, WiFi) to a head-mounted display (HMD) system being worn by a user to provide a real-time, immersive VR experience. In another example, HDR image 601 may be transmitted via a wired link (e.g., Universal Serial Bus / USB) to a fixed display system being viewed by a user to playback a movie. Image 601 may be considered to be formatted in HDR to the extent that it reproduces a greater dynamic range of luminance than is possible using standard digital imaging or photography techniques. Thus, HDR image 601 may have a luminance range similar to that experienced by the human visual system, which constantly adjusts to the wide range of luminances present in the environment. The brain can continuously interpret this information so that the user / viewer can see in a wide range of lighting conditions.

[0146] In the illustrated example, an HDR image 601 is generated by a sensor device 602 using a CCD array, a camera, or any other image acquisition device. When generating the HDR image 601, the sensor device 602 generates a plurality of scanned images 611 to 613, each of which is acquired with a different exposure level. These scanned images 611 to 613 are illustrated as a set of three images, including an underexposed image, a well-exposed image 612, and an overexposed image 611. While the illustrated example embodiment utilizes a set of three images, those skilled in the art will recognize that any number of scanned images may be used without departing from the present invention. Furthermore, the three-image set may include an underexposed image 613 and an overexposed image 611, each of which has the same exposure, which can be measured in f-stops from the well-exposed image 612. Of course, according to the present invention, the set of images combined to generate the HDR image 601 may use images with any exposure variance.

[0147] Figure 6BA timeline identifying shutter times used to generate scanned images 611 through 613 is shown, in accordance with an embodiment of the present invention. Exposure of the image begins at time t0 620 and continues until sensor 602 is disabled after time t3 623. The sensor is collecting charge from incoming incident light at each of the pixel locations within image 601. At time t1 621, pixel values are scanned from sensor 602, resulting in underexposed image 611. The sensor continues collecting pixel data until time t3 622, at which point the pixel values are scanned again to produce well-exposed image 612. Again, sensor 602 continues collecting pixel data until time t3, at which point the sensor is scanned again, resulting in overexposed image 623. As the last of these three images, sensor 602 can be disabled and reset to prepare for collecting a later set of images.

[0148] This timing for scanning pixel data produces this result because sensors typically have fixed-aperture lenses, and image exposure is achieved by extending the time the shutter is open, or in the case of CCD arrays, by extending the time the sensor is enabled to collect charge corresponding to incident light. The longer the sensor collects data, the slower the device's shutter speed. Collecting these three images in this manner allows the images to overlap in time and reduces any motion observed in the resulting image if the subject moves during the time the sensor collects data.

[0149] Figure 6C A processing architecture 630 is shown for HDR enhancement using time-multiplexing processing as described herein. In the example shown, sensor optics 631 focus light corresponding to the scene being viewed onto sensor 602, generating illumination 632 to be observed across sensor 602. Sensor 602 collects charge associated with the intensity of the light focused on sensor 602. Multiple images can be scanned from the sensor with different shutter times, generating images with pixel values corresponding to the observed CCD acquisition levels. Using these scanned detection images 633, shutter times 621 to 623 can be determined for the scene as currently illuminated.

[0150] Scanning detection images 633 is used to determine shutter times 621 to 623 by calculating exposure estimates for each of these images 634 using the intensity values of the image pixels. Exposure estimates can be calculated by determining the average of the intensity values for all pixels; determining the number or percentage of pixels exceeding a predetermined intensity level for each of detection images 633; and determining the number or percentage of pixel intensity values that have reached a maximum or saturation level by receiving more charge corresponding to light intensity than is measured for a given resolution. All of these metrics approximate the exposure of the image obtained from sensor 602. Higher calculated values for the image are associated with individual exposure levels. Thus, desired shutter times can be determined by measuring the time required to generate a particular level of the calculated metrics from detection images 633. As long as HDR image 601 is obtained immediately after the shutter times are determined and before the illumination level of the observed scene changes, these determined shutter times generate desired exposure images for generating HDR images using temporal multiplexing as discussed herein. The sensor 602 is reset and re-enabled to acquire 635 the scanned images 611 to 613 by scanning and saving these images 611 to 613 at the appropriate times t1 621 , t2 622 and t3 623 as discussed above. These three scanned images can then be combined to produce the HDR image 601 .

[0151] Figure 6D 6. HDR images are obtained from a sensor using interlaced scanning according to another embodiment. Any HDR image 601 can be generated by combining two or more images taken with different exposures that cover a wider dynamic range possible from the sensor 602. Figure 6D In an alternative embodiment, each of the two images is scanned from the sensor 602 using alternating, staggered rows of pixels. In the first image, the even rows 651 are scanned at a first exposure. The second image can be scanned from the odd rows 652 with a second exposure. The first image 653 and the second image 654 are as described above with respect to FIG. Figure 6A Once the HDR image is generated, the process may continue by obtaining a third image using the even rows 651 using the second exposure and then obtaining a fourth image using the first exposure.

[0152] This alternating generation of component images can be repeated with a first exposure used with even rows 651 and a second exposure used with even rows. By using alternating scanning, a smaller number of pixels need to be scanned, and the second exposure can be started more quickly. Sampling the image more quickly reduces the effects of object motion within the acquired image.

[0153] Figure 6DAlso shown are pixels from a portion 650 of the acquired image 601, where the image is shown as rows of pixels. Even rows 651 are identified as rows 0, 2, 4, 6, etc. 651, and odd rows 652 are 1, 3, 5, 7, etc. While the disclosed embodiment uses only two alternating row samples, one of ordinary skill will recognize that any number of sample rows may be utilized without departing from the invention.

[0154] Figure 6E 6 is a conceptual block diagram of a processing system for generating HDR images for display using an enhanced alpha channel, according to an embodiment. This processing system merges multiple image planes 662 through 664 into an HDR output image 665 in an alpha blending module 661. Input images include an HDR UI image 662 and an HDR video image 663; the alpha channel 664 is used to blend the other input images together. The HDU UI image 662 can be used to display user interface information to the viewer, such as text and progress and health bars; according to one embodiment, the HDR video image 663 can be used to display a scene from a video game in which the viewer is present.

[0155] In a typical display processing system, these input images are 32-bit images, where ten bits are allocated to each of the three R, G, and B image channels, and two bits are allocated to the alpha channel. If additional detail is required for blending, the image needs to use a 64-bit image, doubling the required memory and associated bandwidth requirements. The present invention reduces these memory resources by using a 40-bit image, which allocates ten bits to the red channel, ten bits to the green channel, ten bits to the blue channel, and eight bits to the alpha channel. The red, green, and blue channels can be adequately displayed using the 10-bit resolution used by the HDR output image 665.

[0156] The alpha blending module 661 merges the HDR UI image 662 and the HDR video image 663 to produce an HDR output image 665 that uses the alpha channel 664 to define the surface as to how the other two images will be combined.

[0157] Figure 6F Two-bit alpha channel image blending according to an embodiment of the present invention is shown. In this example embodiment, a first image 666 is blended with a second image 667 to produce an output image 669 using a two-bit alpha channel 668. With two bits for the alpha channel, only four values can work when encoding the blend (00, 01, 10, 11). For example, this can correspond to a blend where one image has the following transparency:

[0158] a.00: completely transparent;

[0159] b.01: 67% transparent;

[0160] c.10: 33% transparent; and

[0161] d.11: Completely opaque.

[0162] The second image can have the opposite amount of transparency, e.g. Figure 6F As shown in . With more bits in the alpha channel, higher transparency granularity can be achieved. Additionally, the specific transparency levels used in the above examples can be varied as needed.

[0163] Figure 6G This is a conceptual block diagram of a processing system for generating an HDR image for display using matching dynamic range and color gamut, according to an embodiment. When multiple images are combined to produce a composite image, image characteristics such as dynamic range and color gamut may not match for each of the input images to be combined. The enhanced correction and composition processing system 670 corrects for these mismatches before image merging occurs.

[0164] The enhanced correction and compositing processing system 670 reduces any issues with dynamic range and color gamut by mapping each input to a common image and color space before compositing the input images. Figure 6F In the example above, an 8-bit SDR image will be merged with a 10-bit HDR image. For each of these images, the dynamic range of the image will be mapped to a common dynamic range. For each pixel value in the SDR image and the HDR image, it will be mapped to a new value in the common dynamic range. A lookup table can be generated to maintain this mapping and then used to generate pixel values for each pixel in the input image in the common dynamic range. For each image type, mapping 671, 675 is required to transform the dynamic range to the common dynamic range. Separate gamut corrections 672, 676 can also be applied in a similar manner to map the images to a common color space.

[0165] Figure 6H An example tone mapping curve 783 is shown for transforming an input image to match the dynamic range and color gamut when generating an HDR image for display, according to an embodiment. An example mapping from an input image to a transformed image is shown in FIG. Input pixel values 681 are shown along the x-axis of the curve. Output pixel values 682 are shown along the y-axis. The tone mapping curve 683 shows the image stored above in FIG. Figure 6F, which allows the enhancement correction and compositing processing system 670 to transform the input image into a common color and image space. A separate tone mapping curve 683 is used for each image type prepared for compositing, where a specific curve is defined to appropriately transform each image type (e.g., SDR images, HDR images, UI graphics, etc.) into a common color and image space. A brute force tone mapping 684 is also shown to illustrate a linear mapping, which can be achieved by a formula that directly maps one dynamic range to another (which can be expressed as a set of mathematical operations rather than a lookup table).

[0166] Once all input images are processed into a common color and image space, the compositor 677 may combine the images into an output image 665. In one possible embodiment, the compositor 677 may include a Figure 6E The alpha fusion module 661 discussed here is in addition to other known image merging methods.

[0167] Figure 6I Example tone mapping is shown for transforming an input image to a matching dynamic range and color gamut when generating an HDR image for display, in accordance with an embodiment. Tone mapping is an important step when displaying source content of a different dynamic range than that of the display panel. Tone mapping is also required when fusing multiple high dynamic range images with different maximum brightness. Typically, multi-segment curves are used to compress the source dynamic range to fit the dynamic range of the output display device. However, generating a tone mapping curve in which the connections between the segments are smooth can present computational challenges. Unless the tone mapping curve 686 includes a sufficient amount of smoothing, the generated tone mapping curve 686 may have sharp corners between the segments that may cause noticeable visual artifacts on the output image. The tone mapping calculations applied to the output image may be performed within a graphics processing engine or within a display engine of a typical GPU, as described above with reference to FIG. Figure 5 described.

[0168] A special polynomial can be used to smoothly connect two segments of curve 686. The tone mapping calculation can define three or more pivot points on the tone mapping curve. The pivot points correspond to the desired output curve values at various predefined input values. The calculation described below can connect the pivot points by smoothing the curve segments. The smoothed curve is generated using a polynomial equation. The polynomial takes the general form:

[0169] Equation 1y=a*x+b+c*x -1 +d*x -2

[0170] Equation 1ay=ac*x -2 -2*d*x -3

[0171] The values of a, b, c, and d are four unknown constants. x is the input pixel value, and y is the tone-mapped pixel value. y(x) represents the line segment of the tone-mapped curve. y' represents the first derivative of y with respect to x. y' defines the slope of the curve y at the input x.

[0172] If the starting slope (y') and starting value (y) of a line segment are the same as similar values of the previous line segment, then the two pivot points can be smoothly connected. Substituting the starting / ending slope / value of the line segment into Equation 1 and Equation 1a, four linear equations with unknowns a, b, c, and d can form the desired tone mapping curve. Standard techniques can be used to solve the four linear equations to obtain the four constants a, b, c, and d. The calculated constants can then be used in Equation 1 to form the missing point between the two line segments.

[0173] The above steps can be repeated to connect other segments of the tone mapping curve 686. These segments correspond to areas between other pivot points along the tone mapping curve 686. These calculations can utilize any number of pivot points. When only three or four pivot points are utilized, an alternative smoothing equation can be of the form:

[0174] Equation 2y=a*x 2 +b*x+c->applies to 3 pivot points

[0175] Equation 3y=a+b*e -cx -> Applicable to 3 pivot points

[0176] Equation 4y=a*e bx +c*e dx -> Applicable to 4 pivot points

[0177] Substituting the known values into the above equations yields equations with unknown constants. Solving these equations yields the values of these constants. Equations 3 and 4 require solving nonlinear equations and exponential calculations, which may not be desirable for real-time computing. For many cases, Equations 1 and 2 may be sufficient.

[0178] All of these equations create a curve 687 that starts with a sharper slope and gradually stabilizes to a certain maximum value. However, these equations may produce undesirable fluctuations along the tone mapping curve 686. Implementations can explicitly limit these fluctuations, especially those with a downward slope, while generating curve 687. If some flat areas are generated due to the above-mentioned fluctuation limiting, a moving window average filter can further smooth curve 686 at the end of the generation. The window size can be determined based on accuracy and computational requirements. A moving average filter with a window size of three to five samples may be typical. An example may be a three-segment curve with thirty-three sample points. Here, when using Equation 1 as described above, the line segments are connected with linear interpolation 687.

[0179] Figure 6J A flow chart is presented of a process for generating a tone map according to an embodiment, wherein the tone map is used to transform an input image to match the dynamic range and color gamut when generating an HDR image for display. The presented process can be implemented as one or more modules in a set of logic instructions stored in a non-transitory machine or computer readable storage medium such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), in fixed function hardware logic using circuit technology such as application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS), or transistor-transistor logic (TTL) technology, or any combination thereof.

[0180] A tone mapping curve can generally be created with the goal of reproducing content of any dynamic range as close as possible to the content creator's intent on a display / monitor of any dynamic range, and adjusting the dynamic range so that artifacts are imperceptible. To achieve this, the content's static metadata, Maximum Content Light Level (Max CLL), Maximum Frame Average Light Level (Max FALL), and the display's maximum and minimum displayable luminance levels, can be used in the tone mapping calculations described herein.

[0181] Figure 6J The four-step process dynamically creates a five-segment transfer function for a given source content and display parameters. If the content parameters change, this transfer function can be dynamically rebuilt to achieve the optimal viewing experience.

[0182] This process begins at block 690, which generates a tone mapping curve using known parameters. To ensure that black content is displayed with the same level of detail on displays with different dynamic ranges, the input values can be mapped to matching output values to maintain an approximately 1:1 ratio. For example, block 690 can set initial values as shown in Table 5 below:

[0183] Table 5 - Initial values

[0184] X Y X0＝0 Y0=minimum DL X1 = 100 nits Y1=100 nits X5 = Maximum CLL Y5=maximum DL

[0185] Illustrated decision block 691 checks whether the current image requires tone mapping.If the maximum luminance of the display is greater than the maximum luminance of the content, then tone mapping is not required and block 692 sets x2=x3=x4=x5=y2=y3=y4=Max DL.

[0186] If decision block 691 determines that tone mapping is required and if the content has a higher luminance than the maximum luminance of the display, then x2 to x4 and y2 to y4 are calculated. In one example, in block 693, the points x2 to x4 are distributed between 100 nits (x2) and the maximum CLL (x5). To ensure that only highlights are compressed, block 693 maps the top 2 / 5 of the source content to the top 5% of the display luminance. If less compression is required, such as when the luminance of the content is a smaller amount than the luminance of the display, block 696 sets the condition for adjusting less compression in this line segment. Block 693 then sets:

[0187] x4=3 / 5*x5

[0188] y4=0.95*y5

[0189] Block 694 ensures that low tones and mid tones are not compressed by adding a pivot point at x2. The pivot point can be set to 1 / 5 of the difference between x5 and x1. The corresponding y2 point is assigned 70% of the brightness range between y1 and y4. To ensure that there is no sudden difference between the brightness ranges at the (x4, y4) point, block 695 adds a pivot point at (x3, y3). Block 695 sets x3 to 2 / 5 of the difference between x5 and x1 (plus x1), with y3 set to 70% of the code between y4 and y2.

[0190] To ensure that there are no artifacts due to tone mapping greater than 1:1 in any portion of the transfer function, block 696 performs the following operations along curve 686 ( Figure 6I ) at each point and if this check is true, set y=x. Otherwise, the previously calculated point is calculated as follows:

[0191] If y2>x2; then y2=x2.

[0192] If y3>x3; then y3=x3.

[0193] If y4>x4; then y4=x4.

[0194] Table 6 below shows example calculations of x2 to x4 and y2 to y4:

[0195] Table 6 - Example calculations

[0196]

[0197] Block 697 utilizes the tone mapping curve calculated above and maps these values to a lookup table (LUT) at equally spaced points. Block 698 applies a five-tap synchronous filter to soften the edges and ensure that there are no hard edges that produce visual artifacts. The coefficients of the synchronous filter correspond to: [0.094711194, 0.247492276, 0.31559306, 0.247492276, 0.094711194]. LUT entries 1, 2, the last entry, and the second to last entry may not be filtered. In one example, a pre-filtered value is used. If the center + 2 inputs of the filter are equal to the maximum DL, block 697 does not filter the LUT and uses the pre-filtered value as is.

[0198] To ensure that each of the color components is adjusted by the same factor to prevent possible color shifts, block 699 calculates a common dynamic range adjustment factor and applies the factor to all color components. The dynamic range adjustment factor can be calculated by dividing the previously calculated value by the equally spaced input values. Once the adjustment factor is applied to the LUT, the output image can be processed by the LUT to tone map the image for display to the user.

[0199] Figure 7 6 is a conceptual block diagram of a processing system for generating HDR images enhanced with time multiplexing, according to an embodiment. As discussed above, the sensor module 641 collects pixel intensity values corresponding to the brightness of light focused on the sensor 641. During the initial exposure measurement period of processing, pixel values are extracted from the sensor 641 by the readout interlacer 642. The readout interlacer 642 passes the pixels to the exposure estimator 643, which calculates an estimated exposure for each detection image obtained from the readout interlacer 642. The exposure estimator 643 then uses the exposure estimates it generates to determine shutter times t0 621 to t3 623. The determined shutter times t0 621 to t3 623 are returned to the readout interlacer 642 for use in acquiring scanned images 611 to 613.

[0200] The readout interleaver scanner 642 resets the sensor to begin a new image acquisition period starting at t0. The readout interleaver scanner 642 then scans out an underexposed image 621, a well-exposed image 622, and an overexposed image 623 by scanning out sensor pixel values at times t1 621, t2 622, and t3 623, respectively. The readout interleaver scanner 642 stores each of the three scanned images in its own image buffer 761 to 763. The above embodiment of the readout interleaver scanner 642 implements the above-described Figures 6A to 6C The readout interleaver 642 can also utilize the time multiplexing described above. Figure 6D An interleaved scan using two image buffers 645 to 646 is described.

[0201] Once all scanned images 611-613 are stored in image buffers 645-647, an HDR image merger module 644 combines the multiple images to produce an HDR image enhanced in accordance with the present invention using temporal multiplexing 601. This HDR image 601 can be passed to downstream stages of the 3D graphics processing pipeline for additional processing.

[0202] In the process of combining multiple images, the HDR image merger module 644 can implement the above-mentioned Figure 6F The hue and color mapping in the disclosed module 731 and as described above with respect to Figure 6E The disclosed compositing using alpha channel fusion. Utilizing these additional modules 731 - 732 allows for the use of additional modules within the programmable graphics processing pipeline 500 to improve the visual quality of the HDR image 601 .

[0203] In embodiments where a series of HDR images are to be generated, such as for generating video images, one of ordinary skill in the art will recognize that the readout scanner 642 can perform its functions in a single pass. Once a set of scanned images is obtained, the images can be passed to an exposure estimator 643 to determine the shutter time to be used in the next frame for video generation, while also storing the scanned content in image buffers 645 to 647 for use in generating HDR images to be used as video frames. In this arrangement, the scanned images 611 to 613 of each HDR image 601 are simultaneously used to estimate the exposure of the next image frame. The above modules operate in a parallel processing manner to efficiently generate a series of HDR images 601.

[0204] Figure 8The method 800 of operating a semiconductor packaging device may be implemented as one or more modules in a set of logic instructions stored in a non-transitory machine or computer readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as, for example, a PLA, FPGA, CPLD, etc., in fixed-function hardware logic using circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof.

[0205] For example, the computer program code for performing the operations shown in method 800 may be written in any combination of one or more programming languages, including object-oriented programming languages such as JAVA, SMALLTALK, C++, and conventional procedural programming languages such as the "C" programming language or similar programming languages. Additionally, the logic instructions may include assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, state setting data, configuration data for an integrated circuit system, state information that personalizes the electronic circuit system, and / or other structural components native to the hardware (e.g., a host processor, a central processing unit / CPU, a microcontroller, etc.).

[0206] The illustrated configurable logic block 801 provides for enabling the sensor 641 to collect illuminance data corresponding to light focused on the sensor 641. Block 802 scans out pixel values for a first sampling time t1, which are used by block 802 to estimate the exposure level of the scanned image in block 803. A decision block determines whether the estimated exposure of the scanned image corresponds to a predetermined exposure level to be used in the generated HDR image 601. If so, time t1 is saved by block 805 for use in acquiring an image set for generating the HDR image 601, before using decision block 806 to determine whether the image scan has ended when the scanned image has reached a maximum desired saturation level. If decision block 804 determines that the estimated exposure level is not of interest, processing continues directly to decision block 806.

[0207] If the decision block 806 determines that the estimated exposure is not saturated, the process returns to block 802 to generate another detection scan image at time t2, and so on. This process continues until the decision block 806 ends this detection cycle and continues to block 811 to reset the sensor 641 to begin the image acquisition process at the desired exposure level. Block 812 scans out the image at the desired time t i The pixel intensity values at 621 to 623 are calculated, and block 813 stores the scanned images 611 to 613 in image buffers 761 to 763. A decision block determines whether all scanned images have been acquired, and if not, the process returns to block 812 to store the scanned images at time t i+1The next scan image is acquired. Once all scan images are acquired and stored in the image buffers 761 to 763, decision block 814 may pass the processing to block 815 to generate the HDR image 601. Block 822 retrieves the scan images 611 to 613 from the image buffers 645 to 647 to combine them using any desired HDR processing to generate the desired image. Block 822 for combining the images may also include a process for mapping the HDR image 601 to a Figures 6F to 6G Correction steps for the common color and image spaces disclosed in .

[0208] This HDR image 601 can be passed to any additional stage in the 3D graphics processing pipeline for transmission to a display device. If a video image is generated, the entire HDR process 800 can begin again for the next HDR image to be processed. Although the above method shows how Figures 6A to 6C The time multiplexing process discussed in the above is also possible, but the readout interleaver 642 can be used in Figure 6D The method disclosed in Figure 6D The interleaved scanning process is used for the scanning process discussed above with reference to blocks 802 and 812 .

[0209] Figure 9 A performance-enhanced computing system 900 is shown. In the example shown, a host processor 902 includes an integrated memory controller (IMC) 904 that communicates with system memory 906 (e.g., DRAM). Host processor 902 can be coupled to a graphics processor 908 (e.g., via a peripheral component interconnect / PCI bus) and an input / output (IO) module 910. IO module 910 can be coupled to a network controller 912 (e.g., wireless and / or wired), a display 914 (e.g., a fixed or head-mounted liquid crystal display / LCD, a light-emitting diode / LED display, etc. for visually presenting a three-dimensional / 3D scene), and a mass storage device 918 (e.g., flash memory, an optical disk, a solid-state drive / SSD). The illustrated graphics processor 908 includes a media pipeline 920 and is coupled to graphics memory 916 (e.g., dedicated graphics RAM).

[0210] Additionally, the system memory 906 and / or the mass storage device 918 may include a set of instructions 922 (e.g., device driver instructions) that, when executed by the host processor 902 and / or the graphics processor 908, cause the system 900 to implement the method 800 already discussed. Figure 8 Thus, execution of instructions 922 may cause system 900 to generate an HDR image enhanced with time multiplexing as disclosed herein.

[0211] Figure 10A semiconductor package device 1000 (e.g., a chip) is shown, comprising a substrate 1002 (e.g., silicon, sapphire, gallium arsenide) and logic 1004 (e.g., a transistor array and other integrated circuit / IC components) coupled to the substrate 1002. The logic 1004, which may be implemented, for example, using configurable logic and / or fixed-function hardware logic, may generally implement the method 800 already discussed ( Figure 8 Thus, the logic 1004 may generate an HDR image enhanced with time multiplexing, as disclosed herein.

[0212] Display Technology

[0213] Now turn Figure 11 , showing a performance-enhanced computing system 1100. In the example shown, a processor 1110 is coupled to a display 1120. The processor 1110 generally generates an image to be displayed on an LCD panel 1150 of the display 1120. In one example, the processor 1110 includes a communication interface, such as, for example, a video graphics array (VGA), a display port (DP) interface, an embedded display port (eDP) interface, a high-definition multimedia interface (HDMI), a digital visual interface (DVI), and the like. The processor 1110 can be a graphics processor (e.g., a graphics processing unit / GPU) that processes graphics data and generates an image (e.g., a video frame, a still image) displayed on the LCD panel 1150. In addition, the processor 1110 can include one or more image processing pipelines that generate pixel data. The image processing pipelines can conform to the OPENGL architecture or other suitable architectures. In addition, the processor 1110 can be connected to a host processor (e.g., a central processing unit / CPU), wherein the host processor executes one or more device drivers that control the processor 1100 and / or interact with the processor 1110.

[0214] The illustrated display 1120 includes a timing controller (TCON) 1130 that can individually address different pixels on an LCD panel 1150 and update each individual pixel on the LCD panel 1150 on a refresh cycle-by-refresh basis. In this regard, the LCD panel 1150 can include multiple liquid crystal elements, such as, for example, liquid crystals and integrated color filters. Each pixel of the LCD panel 1150 can include a triplet of liquid crystal elements each having a red, green, and blue filter. The LCD panel 1150 can arrange the pixels in a two-dimensional (2D) array, which is controlled by row drivers 1152 and column drivers 1154 to update the image being displayed by the LCD panel 1150. Thus, the TCON 1130 can drive the row drivers 1152 and column drivers 1154 to address specific pixels of the LCD panel 1150. The TCON 1130 can also adjust the voltage supplied to the liquid crystal elements in the pixel to change the intensity of light passing through each of the three liquid crystal elements, thereby changing the color of the pixel displayed on the surface of the LCD panel 1150.

[0215] The backlight 1160 may include a plurality of light-emitting elements, such as, for example, light-emitting diodes (LEDs), arranged at the edges of the LCD panel 1150. Accordingly, the light generated by the LEDs may be dispersed through the LCD panel 1150 by a diffuser (not shown). In another example, the LEDs are arranged in a 2D array directly behind the LCD panel 1150 in a configuration sometimes referred to as direct backlighting because each LED disperses light through one or more corresponding pixels of the LCD panel 1150 positioned in front of the LED. The light-emitting elements may also include compact fluorescent lamps (CFLs) arranged along one or more edges of the LCD panel 1150. To eliminate multiple edges, the combination of edges may be modified to achieve selective illumination of an area, using less power than the entire set of lighting elements.

[0216] The light-emitting element may also include one or more sheets of electroluminescent material placed behind LCD panel 1150. In such cases, light from the surface of the sheet can be dispersed through the pixels of LCD panel 1150. Furthermore, the sheet can be divided into multiple regions, such as, for example, quadrants. In one example, each region is individually controlled to illuminate only a portion of LCD panel 1150. Other backlighting solutions may also be used.

[0217] The illustrated display 1120 also includes a backlight controller (BLC) 1140 that provides voltage to the light-emitting elements of backlight 1160. For example, BLC 1140 may include a pulse-width modulation (PWM) driver (not shown) to generate a PWM signal that activates at least a portion of the light-emitting elements of backlight 1160. The duty cycle and frequency of the PWM signal can dim the light generated by the light-emitting elements. For example, a 100% duty cycle may correspond to a light-emitting element being fully on, while a 0% duty cycle may correspond to a light-emitting element being fully off. Thus, intermediate duty cycles (e.g., 25%, 50%) typically cause the light-emitting elements to be on for a portion of the cycle proportional to the percentage of the duty cycle. This cycle can be fast enough so that the flickering of the light-emitting elements is imperceptible to the human eye. Furthermore, the impact to the user may be that the light level emitted by backlight 1160 is lower than when backlight 1160 is fully activated. BLC 1140 may be separate from TCON 1130 or may be incorporated into TCON 1130.

[0218] Alternatively, an emissive display system may be used, where the LCD panel 1150 would be replaced by an emissive display panel (e.g., organic light emitting diode / OLED), the backlight 1160 would be omitted, and the row driver 1152 and column driver 1154 could be used to directly modulate pixel color and brightness, respectively.

[0219] Distance-based display resolution

[0220] Figure 12A A scenario is shown in which a user 1218 interacts with a data processing device 1200 including a display unit 1228. Display processing device 1200 may include, for example, a laptop computer, a desktop computer, a tablet computer, a convertible tablet, a mobile internet device (MID), a personal digital assistant (PDA), a wearable device (e.g., a head-mounted display / HMD), a media player, or the like, or any combination thereof. Data processing device 1200 is shown including a processor 1224 (e.g., an embedded controller, a microcontroller, a host processor, a graphics processor) coupled to a memory 1222, which may include storage locations addressable by processor 1224. As will be discussed in greater detail, distance sensor 1210 may enable distance-based display resolution relative to display unit 1228.

[0221] Memory 1222 is shown including display data 1226 to be rendered on a display unit 1228. In one example, processor 1224 performs data conversion on display data 1226 before presenting the display data 1226 on display unit 1228. Post-processing engine 1214 may execute on processor 1224 to receive display data 1226 and the output of distance sensor 1210. Post-processing engine 1214 may modify display data 1226 to enhance readability of screen content on display unit 1228, reduce power consumption in data processing device 1200, or the like, or any combination thereof.

[0222] Memory 1222 is shown storing, in addition to operating system 1212 and applications 1220, display resolution settings 1216. Display resolution settings 1216 may specify the number of pixels of display data 1226 to be presented on display unit 1228 along the length and width dimensions. If display data 1226, as generated by application 1220, is incompatible with the format of display unit 1228, processor 1224 may configure the scaling of display data 1226 to match the format of display unit 1228. In this regard, display resolution settings 1216 may be associated with and / or incorporated into configuration data defining other settings for display unit 1228. Furthermore, display resolution settings 1216 may be defined in terms of unit distance or area (e.g., pixels per inch / PPI), or other suitable parameters.

[0223] The application 1220 can generate a user interface, where the user 1218 can interact with the user interface to select a display resolution setting 1216 from one or more options provided through the user interface, enter the display resolution setting 1216 as a requested value, etc. Thus, the display data 1226 can be resized to fit the display resolution setting 1216 before being rendered on the display unit 1228.

[0224] The distance sensor 1210 can track the distance between the user 1218 and the display unit 1228, wherein the distance sensing can be triggered by a physical button associated with the data processing device 1200 / display unit 1228, by a user interface provided by the loading of the application 1220 and / or the operating system 1220, etc. For example, during the booting of the data processing device 1200, the operating system 1212 can execute an automatic process to trigger distance sensing in the background or foreground. The distance sensing can be performed periodically or continuously.

[0225] Figure 12BAn example of a distance sensing scenario is shown. In the example shown, the distance sensor 1210 uses a transceiver 1208 to transmit an electromagnetic beam 1202 in the direction of a user 1218. Thus, the transceiver 1202 may be located at the data processing device 1200 ( Figure 12A ). The electromagnetic beam 1202 may impact the user 1218 and may be reflected / scattered from the user 1218 as a return electromagnetic beam 1204. The return electromagnetic beam 1204 may be processed by, for example, a processor 1224 ( Figure 12A ) and / or post-processing engine 1214 ( Figure 12A ) analysis to determine whether the user 1218 is in contact with the display unit 1228 ( Figure 12A ) between the two images 1206. The distance 1206 can be used to adjust the display resolution setting 1216.

[0226] Display Layer

[0227] Now turn Figure 13 , a display system 1300 is shown in which cascaded display layers 1361, 1362, and 1363 are used to implement spatial / temporal super-resolution in a display component 1360. In the example shown, a processor 1310 provides raw graphics data 1334 (e.g., video frames, still images) to the system 1300 via a bus 1320. A cascaded display program 1331 can be stored in a memory 1330, where the cascaded display program 1331 can be part of a display driver associated with the display component 1360. The illustrated memory 1330 also includes raw graphics data 1334 and decomposed graphics data 1335. In one example, the cascaded display program 1331 includes a temporal decomposition component 1332 and a spatial decomposition component 1333. The temporal decomposition component 1332 can perform temporal decomposition calculations, while the spatial decomposition component can perform spatial decomposition calculations. The cascaded display program 331 may derive decomposed graphics data 1335 for presentation on each display layer 1361 , 1362 , and 1363 based on the user configuration and the original graphics data 1334 .

[0228] Display assembly 1360 may be implemented as an LCD (liquid crystal display) for use in, for example, head-mounted display (HMD) applications. More specifically, display assembly 1360 may include a stack of LCD panels, an interface board, lens attachments, and the like. Each panel may operate at, for example, a native resolution of 1280*1280 and a 60 Hz refresh rate. Other native resolutions, refresh rates, display panel technologies, and / or layer configurations may be used.

[0229] Multiple display units

[0230] Figure 14A graphical display system 1400 is shown that includes a set of display units 1430 (1430a-1430n) that can generally be used to output a widescreen (e.g., panoramic) presentation 1440 that includes coordinated content in a cohesive and structured topological form. In the illustrated example, a data processing device 1418 includes a processor 1415 that applies a logic function 1424 to hardware profile data 1402 received from the set of display units 1430 via a network 1420. When no match is found between the hardware profile data and a set of settings in a hardware profile lookup table 1412, applying the logic function 1424 to the hardware profile data 1402 creates a set of automatic topology settings 1406. The illustrated set of automatic topology settings 1406 is transmitted from the display processing device 1418 via the network 1420 to the display units 1430.

[0231] The processor 1415 may execute and run the logic function 1424 after receiving it from the display driver 1410. In this regard, the display driver 1410 may include an automatic topology module 1408 that automatically configures and builds a topology for the display unit 1432 to create the presentation 1440. In one example, the display driver 1410 is a set of instructions that, when executed by the processor 1415, causes the data processing device 1418 to communicate with the display unit 1430, a video card, etc., and perform automatic topology generation operations.

[0232] Data processing device 1418 may include, for example, a server, a desktop computer, a laptop computer, a tablet computer, a convertible tablet computer, a MID, a PDA, a wearable device, a media player, and the like. Thus, display processing device 1418 may include hardware control module 1416, storage device 1414, random access memory (RAM, not shown), controller cards including one or more video controller cards, and the like. In one example, display unit 1430 is a flat panel display (e.g., liquid crystal, active matrix, plasma, etc.), an HMD, a video projection device, and the like that cooperates with each other to generate presentation 1440. Furthermore, presentation 1440 may be generated based on media files stored in storage device 1414, where the media files may include, for example, movies, video clips, animations, advertisements, and the like, or any combination thereof.

[0233] The term "topology" can be considered to refer to the number, scale, shape, and / or other configuration parameters of first display unit 1430a, second display unit 1430b, third display unit 1430n, and so on. Accordingly, the topology of display unit 1430 can enable presentation 1440 to be visually presented consistently, such that the various segments of presentation 1440 are proportional to and compatible with the original scale and extent of the media being played through display unit 1430. Thus, topology can constitute spatial relationships and / or geometric properties that are unaffected by continuous changes in the shape or size of the content rendered in presentation 1440. In one example, automatic topology module 1408 includes a timing module 1426, a control module 1428, a signal monitor module 1432, and a signal display module 1434. Timing module 1426 can designate a particular display unit in a group of display units 1430 as a sample display unit. In such cases, timing module 1426 can designate the remaining display units 1430 as additional display units. In one example, the timing module 1426 automatically sets the form factor to be compatible with the hardware profile data 1402 , where the presentation 1440 is automatically initiated by the sequence of graphical signals 1422 .

[0234] In one example, control module 1428 modifies set of automatic topology settings 1406. Furthermore, signal monitor module 1432 can automatically monitor sequence of graphical signals 1422 and trigger storage device 1414 to associate set of automatic topology settings 1406 with hardware profile lookup table 1412. Furthermore, signal monitor module 1432 can automatically detect changes in set of display units 1430 based on a set of change criteria and automatically generate a new topology profile corresponding to the changes in set of display units 1430. Thus, the new topology profile can be applied to set of display units 1430. Signal monitor module 1432 can also trigger signal display module 1434 to reapply set of automatic topology settings 1406 if sequence of graphical signals 1422 fails to meet the set of criteria. If hardware profile data 1402 does not support automatic topology display of sequence of graphical signals 1422, data processing device 1418 can report an error and record the error in error log 1413.

[0235] Cloud-assisted media delivery

[0236] Now turn Figure 15, the cloud gaming system 1500 includes a client 1540 coupled to a server 1520 via a network 1510. The client 1540 can generally be a consumer of graphics (e.g., games, virtual reality / VR, augmented reality / AR) content that is hosted, processed, and rendered on the server 1520. The scalable server 1520 shown has the capacity to provide graphics content to multiple clients simultaneously (e.g., by utilizing parallel and shared processing and rendering resources). In one example, the scalability of the server 1520 is limited by the capacity of the network 1510. Accordingly, there can be a threshold number of clients, above which the service to all clients is degraded.

[0237] In one example, server 1520 includes a graphics processor (e.g., GPU) 1530, a host processor (e.g., CPU) 1524, and a network interface card (NIC) 1552. NIC 1522 can receive requests for graphics content from clients 1540. Requests from clients 1540 can cause graphics content to be retrieved from memory via applications executing on host processor 1524. Host processor 1524 can perform high-level operations such as, for example, determining the position, collision, and motion of objects in a given scene. Based on these high-level operations, host processor 1524 can generate rendering commands that are combined with scene data and executed by graphics processor 1530. The rendering commands can cause graphics processor 1530 to define scene geometry, shading, lighting, motion, textures, camera parameters, etc. for a scene to be rendered via client 1540.

[0238] More specifically, the illustrated graphics processor 1530 includes a graphics renderer 1532 that performs a rendering process based on rendering commands generated by the host processor 1524. The output of the graphics renderer 1532 may be a stream of raw video frames that is provided to a frame capturer 1534. The illustrated frame capturer 1534 is coupled to an encoder 1536 that may compress / format the raw video stream for transmission over the network 1510. The encoder 1536 may use various video compression algorithms, such as, for example, the H.264 standard from the International Telecommunication Union Telecommunication Standardization Sector (ITUT), the MPEG-4 Advanced Video Coding (AVC) standard from the International Organization for Standardization / International Electrotechnical Commission (ISO / IEC), and the like.

[0239] 15. The illustrated client 1540 (which may be a desktop computer, laptop computer, tablet computer, convertible computer, wearable device, MID, PDA, media player, etc.) includes a NIC 1542 to receive the transmitted video stream from the server 1520. The NIC 1522 may comprise the physical layer and the software layer basis of the network interface in the client 1540 to facilitate communication over the network 1510. The client 1540 may also include a decoder 1544 that employs the same formatting / compression scheme as the encoder 1536. Thus, the decompressed video stream may be provided from the decoder 1544 to a video renderer 1546. The illustrated video renderer 1546 is coupled to a display 1548 that visually presents the graphical content.

[0240] As already noted, the graphical content may include gaming content. In this regard, the client 1540 may perform real-time interactive streaming, which involves collecting user input from the input device 1550 and delivering the user input to the server 1520 via the network 1510. This real-time interactive portion of cloud gaming can present challenges with respect to latency.

[0241] Additional System Overview Examples

[0242] Figure 16 16 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and can be a single-processor desktop computer system, a multi-processor workstation system, or a server system with a large number of processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform included in a system-on-chip (SoC) for use in a mobile device, a handheld device, or an embedded device.

[0243] Embodiments of system 1600 may include or be included in the following: a server-based gaming platform, a gaming console (including gaming and media consoles), a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, system 1600 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. Data processing system 1600 may also include, be coupled with, or be integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual display device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphics interface generated by one or more graphics processors 1608.

[0244] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 for processing instructions that, when executed, perform operations of the system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 can each process a different instruction set 1609, which may include instructions for facilitating emulation of other instruction sets. The processor cores 1607 may also include other processing devices, such as a digital signal processor (DSP).

[0245] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC) (not shown), which may be shared between the processor cores 1607 using known cache coherence techniques. A register file 1606 is additionally included in the processor 1602, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1602.

[0246] In some embodiments, processor 1602 is coupled to a processor bus 1610 to transmit communication signals (e.g., address, data, or control signals) between processor 1602 and other components in system 1600. In one embodiment, system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an input / output (I / O) controller hub 1630. Memory controller hub 1616 facilitates communication between memory devices and other components of system 1600, while I / O controller hub (ICH) 1630 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 1616 is integrated within the processor.

[0247] Memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with suitable performance to function as process memory. In one embodiment, memory device 1620 may operate as system memory for system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute applications or processes. Memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may be coupled to graphics processor 1608 in processor 1602 to perform graphics and media operations.

[0248] In some embodiments, ICH 1630 enables peripheral devices to be connected to memory device 1620 and processor 1602 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices (e.g., a keyboard and mouse 1644 combination). A network controller 1634 may also be coupled to ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1610. It will be appreciated that the illustrated system 1600 is exemplary and non-limiting, as other types of data processing systems configured in different ways may also be used. For example, the I / O controller hub 1630 may be integrated within the one or more processors 1602 , or the memory controller hub 1616 and the I / O controller hub 1630 may be integrated within a discrete external graphics processor, such as the external graphics processor 1612 .

[0249] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A through 1702N, an integrated memory controller 1714 , and an integrated graphics processor 1708 . Figure 17Those elements in the same figure as those in any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Processor 1700 may include additional cores up to and including additional core 1702N represented by a dashed box. Each of processor cores 1702A to 1702N includes one or more internal cache units 1704A to 1704N. In some embodiments, each processor core may also have access to one or more shared cache units 1706.

[0250] Internal cache units 1704A to 1704N and shared cache unit 1706 represent a cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level cache (e.g., level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache), with the highest level of cache preceding external memory being categorized as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A to 1704N.

[0251] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express buses). The system agent core 1710 provides management functions for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714, which are used to manage access to various external memory devices (not shown).

[0252] In some embodiments, one or more of the processor cores 1702A through 1702N include support for simultaneous multi-threaded processing. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A through 1702N during multi-threaded processing. The system agent core 1710 may also include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1702A through 1702N and the graphics processor 1708.

[0253] In some embodiments, processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, graphics processor 1708 is coupled to a set of shared cache units 1706 and a system agent core 1710, including one or more integrated memory controllers 1714. In some embodiments, a display controller 1711 is coupled to graphics processor 1708 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 1711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within graphics processor 1708 or system agent core 1710.

[0254] In some embodiments, a ring-based interconnect 1712 is used to couple the internal components of the processor 1700. However, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via an I / O link 1713.

[0255] Exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1718 (such as an eDRAM module). In some embodiments, each of processor cores 1702 through 1702N and graphics processor 1708 use embedded memory module 1718 as a shared last-level cache.

[0256] In some embodiments, processor cores 1702A to 1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1702A to 1702N are heterogeneous with respect to instruction set architecture (ISA), wherein one or more of processor cores 1702A to 1702N execute a first instruction set, while at least one of the other cores executes a subset or different instruction set of the first instruction set. In one embodiment, processor cores 1702A to 1702N are heterogeneous with respect to microarchitecture, wherein one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. In addition, processor 1700 can be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0257] Figure 181 is a block diagram of a graphics processor 1800, which can be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, graphics processor 1800 includes a memory interface 1814 for accessing memory. Memory interface 1814 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0258] In some embodiments, the graphics processor 1800 also includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0259] In some embodiments, graphics processor 1800 includes a block image transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1810. In some embodiments, graphics processing engine 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0260] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1812 includes programmable and fixed-function elements that perform various tasks within elements and / or spawned execution threads for 3D / media subsystem 1815. While 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 specifically for performing media operations, such as video post-processing and image enhancement.

[0261] In some embodiments, media pipeline 1816 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encoding acceleration, instead of or on behalf of video codec engine 1806. In some embodiments, media pipeline 1816 further includes a thread generation unit to generate threads for execution on 3D / media subsystem 1815. The generated threads perform computations for the media operations on one or more graphics execution units included in 3D / media subsystem 1815.

[0262] In some embodiments, 3D / media subsystem 1815 includes logic for executing threads generated by 3D pipeline 1812 and media pipeline 1816. In one embodiment, the pipelines send thread execution requests to 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching each request to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0263] 3D / Media Processing

[0264] Figure 19 is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, GPE 1910 is Figure 18 A version of GPE 1810 is shown in . Figure 19 Elements in the drawings having the same reference numbers (or names) as elements of any other figures herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0265] In some embodiments, GPE 1910 is coupled to a command streamer 1903, which provides a command stream to the GPE's 3D pipeline 1912 and media pipeline 1916. In some embodiments, command streamer 1903 is coupled to a memory, which may be system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, command streamer 1903 receives commands from memory and sends them to 3D pipeline 1912 and / or media pipeline 1916. The commands are instructions retrieved from a circular buffer storing instructions for 3D pipeline 1912 and media pipeline 1916. In one embodiment, the circular buffer may further include a batch command buffer for storing batches of multiple commands. 3D pipeline 1912 and media pipeline 1916 process the commands by executing operations via logic within their respective pipelines or by dispatching one or more execution threads to execution unit array 1914. In some embodiments, execution unit array 1914 is scalable such that the array includes a variable number of execution units based on the target power and performance level of GPE 1910 .

[0266] In some embodiments, sampling engine 1930 is coupled to memory (e.g., cache memory or system memory) and execution unit array 1914. In some embodiments, sampling engine 1930 provides a memory access mechanism for execution unit array 1914 that allows execution array 1914 to read graphics and media data from memory. In some embodiments, sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0267] In some embodiments, specialized media sampling logic within the sampling engine 1930 includes a denoising / deinterlacing module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / deinterlacing module 1932 includes logic for performing one or more of a denoising or deinterlacing algorithm on the decoded video data. The deinterlacing logic combines alternating fields of interlaced video content into a single frame of video. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising and deinterlacing logic is motion adaptive and uses spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / deinterlacing module 1932 includes specialized motion detection logic (e.g., within the motion estimation engine 1934).

[0268] In some embodiments, the motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions (such as motion vector estimation and prediction) on video data. The motion estimation engine determines motion vectors that describe the transformation of image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on macroblock-level video that may otherwise be too computationally intensive to perform using a general-purpose processor. In some embodiments, the motion estimation engine 1934 is generally available to the graphics processor component to assist with video decoding and processing functions that are sensitive or adaptive to the direction or magnitude of motion within the video data.

[0269] In some embodiments, image scaling and filtering module 1936 performs image processing operations to improve the visual quality of generated images and videos. In some embodiments, scaling and filtering module 1936 processes image and video data during sampling operations before providing the data to execution unit array 1914.

[0270] In some embodiments, GPE 1910 includes a data port 1944 that provides an additional mechanism for the graphics subsystem to access memory. In some embodiments, data port 1944 facilitates memory access for operations including render target writes, constant buffer reads, temporary memory space reads / writes, and media surface accesses. In some embodiments, data port 1944 includes a cache memory space for caching accesses to memory. The cache memory can be a single data cache or separated into multiple caches (e.g., a render buffer cache, a constant buffer cache, etc.) for multiple subsystems that access memory via the data port. In some embodiments, threads executing on execution units in execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect that couples each subsystem of GPE 1910.

[0271] Execution Unit

[0272] Figure 20 is a block diagram of another embodiment of a graphics processor 2000 . Figure 20 Elements in the drawings having the same reference numbers (or names) as elements of any other figures herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0273] In some embodiments, graphics processor 2000 includes ring interconnect 2002, pipeline front end 2004, media engine 2037, and graphics cores 2080A through 2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of multiple processors integrated into a multi-core processing system.

[0274] In some embodiments, the graphics processor 2000 receives batches of commands via a ring interconnect 2002. The incoming commands are translated by a command streamer 2003 in a pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2080A through 2080N. For 3D geometry processing commands, the command streamer 2003 supplies the commands to a geometry pipeline 2036. For at least some media processing commands, the command streamer 2003 supplies the commands to a video front end 2034, which is coupled to a media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate execution threads, which are used for thread execution resources provided by at least one graphics core 2080A.

[0275] In some embodiments, graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A through 2080N (sometimes referred to as core slices), each of which has multiple sub-cores 2050A through 2050N and 2060A through 2060N (sometimes referred to as core subslices). In some embodiments, graphics processor 2000 can have any number of graphics cores 2080A through 2080N. In some embodiments, graphics processor 2000 includes graphics core 2080A, which has at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2050A). In some embodiments, graphics processor 2000 includes multiple graphics cores 2080A through 2080N, each of which includes a set of first sub-cores 2050A through 2050N and a set of second sub-cores 2060A through 2060N. Each sub-core in the set of first sub-cores 2050A to 2050N includes at least a first set of execution units 2052A to 2052N and a media / texture sampler 2054A to 2054N. Each sub-core in the set of second sub-cores 2060A to 2060N includes at least a second set of execution units 2062A to 2062N and a sampler 2064A to 2064N. In some embodiments, each sub-core 2050A to 2050N, 2060A-2060N shares a set of shared resources 2070A to 2070N. In some embodiments, these shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0276] Figure 21 Threaded execution logic 2100 is shown, including an array of processing elements employed in some embodiments of a GPE. Figure 21 Those elements in FIG. 1 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0277] In some embodiments, thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array, including multiple execution units 2108A to 2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, these included components are interconnected via an interconnect structure that links to each of these components. In some embodiments, thread execution logic 2100 includes one or more connections to a memory (e.g., system memory or cache memory) via the instruction cache 2106, the data port 2114, the sampler 2110, and one of the execution unit arrays 2108A to 2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, execution unit arrays 2108A to 2108N include any number of individual execution units.

[0278] In some embodiments, execution unit arrays 2108A through 2108N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2108A through 2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, allowing shader programs from graphics libraries (e.g., Direct 3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders).

[0279] Each execution unit in execution unit arrays 2108A through 2108N operates on an array of data elements. The number of data elements is the "execution size," or the number of lanes used for an instruction. An execution lane is a logical execution unit used for data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2108A through 2108N support integer and floating point data types.

[0280] The execution unit instruction set includes single instruction multiple data (SIMD). Various data elements can be stored in registers as compressed data types, and the execution unit will process these elements based on the data size of various elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four independent 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight independent 32-bit compressed data elements (data elements of double word length (DW) size), sixteen independent 16-bit compressed data elements (data elements of word length (W) size), or thirty-two independent 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0281] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0282] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 2100 via the thread generation and dispatch logic. In some embodiments, the thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics pipeline and the media pipeline and instantiates the requested threads on one or more execution units 2108A to 2108N. For example, the geometry pipeline (e.g., Figure 20 2036) dispatches vertex processing, tessellation, or geometry processing threads to thread execution logic 2100 ( Figure 21 In some embodiments, thread dispatcher 2104 may also process runtime thread generation requests from executing shader programs.

[0283] Once a set of geometric objects has been processed and rasterized into pixel data, the pixel shader 2102 is called to further calculate output information and cause the results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, the pixel shader 2102 calculates the values of each vertex attribute, which is interpolated across the rasterized objects. In some embodiments, the pixel shader 2102 then executes a pixel shader program supplied by an application programming interface (API). To execute the pixel shader program, the pixel shader 2102 dispatches threads to execution units (e.g., 2108A) via a thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses texture sampling logic in a sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations performed on the texture data and the input geometry calculate pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0284] In some embodiments, the data port 2114 provides a memory access mechanism for the thread execution logic 2100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data via the data port for memory access.

[0285] Figure 22 is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid-line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2200 described and illustrated are macroinstructions, as they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0286] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit format 2210. A 64-bit compact instruction format 2230 may be used for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 2230. The native instructions available in the 64-bit format 2230 vary depending on the embodiment. In some embodiments, instructions are partially compacted using a set of index values in the index field 2213. The execution unit hardware references a set of compression tables based on these index values and uses the compression table output to reconstruct the native instruction in 128-bit format 2210.

[0287] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit executes a simultaneous addition operation across each color channel representing a texture element or picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., mixing). For 128-bit instructions 2210, the execution size field 2216 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2216 is not available for 64-bit compact instruction format 2230.

[0288] Some execution unit instructions have up to three operands, including two source operands src0 2220 and src1 2222, and one destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., src2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed by the instruction.

[0289] In some embodiments, the 128-bit instruction format 2210 includes access / address mode information 2226 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction 2210.

[0290] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode defines the data access alignment of the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction 2210 may use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction 2210 may use 16-byte aligned addressing for all source operands and destination operands.

[0291] In one embodiment, the address mode portion of the access / address mode field 2226 determines whether the instruction will use direct or indirect addressing. When direct register addressing mode is used, bits in the instruction 2210 directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0292] In some embodiments, instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares the five most significant bits (MSBs), wherein the move (mov) instruction takes the form of 0000xxxxb, while the logic instruction takes the form of 0001xxxxb. The flow control instruction group 2244 (e.g., call (call), jump (jmp)) includes instructions taking the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) taking the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across the data lanes. The vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands.

[0293] Graphics pipeline

[0294] Figure 23 is a block diagram of another embodiment of a graphics processor 2300 . Figure 23 Elements in the drawings having the same reference numbers (or names) as elements of any other figures herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0295] In some embodiments, graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 2300 via ring interconnect 2302. In some embodiments, ring interconnect 2302 couples graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 2302 are translated by command stream converter 2303, which supplies instructions to individual components of graphics pipeline 2320 or media pipeline 2330.

[0296] In some embodiments, command stream converter 2303 directs the operation of vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 2303. In some embodiments, vertex fetcher 2305 provides vertex data to vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 2305 and vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A, 2352B via thread dispatcher 2331.

[0297] In some embodiments, execution units 2352A, 2352B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 2352A, 2352B have an additional L1 cache 2351 specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0298] In some embodiments, graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides back-end evaluation of the tessellation output. Tessellation controller 2313 operates under the direction of hull shader 2311 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model provided as input to graphics pipeline 2320. In some embodiments, tessellation components 2311, 2313, and 2317 can be bypassed if tessellation is not used.

[0299] In some embodiments, the complete geometric object can be processed by the geometry shader 2319 via one or more threads dispatched to the execution units 2352A, 2352B, or can proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on entire geometric objects (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 can be programmed by the geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0300] Before rasterization, the clipper 2329 processes the vertex data. The clipper 2329 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, the rasterizer 2373 (e.g., a depth test component) in the render output pipeline 2370 dispatches a pixel shader to convert geometric objects into their pixel-by-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, the application can bypass the rasterizer 2373 and access the unrasterized vertex data via the outflow unit 2323.

[0301] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, execution units 2352A, 2352B and associated cache(s) 2351, texture and media samplers 2354, and texture / sampler cache 2358 are interconnected via data ports 2356 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2354, caches 2351, 2358, and execution units 2352A, 2352B each have separate memory access paths.

[0302] In some embodiments, the render output pipeline 2370 includes a rasterizer 2373 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated render cache 2378 and depth cache 2379 are also available in some embodiments. A pixel operation component 2377 performs pixel-based operations on data, although in some examples, pixel operations associated with 2D operations (e.g., bit-block image transfers and blending) are performed by the 2D engine 2341 or, at display time, by a display controller 2343 using an overlaid display plane. In some embodiments, a shared L3 cache 2375 is available to all graphics components, allowing data to be shared without using main system memory.

[0303] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from the command stream converter 2303. In some embodiments, the media pipeline 2330 includes a separate command stream converter. In some embodiments, the video front end 2334 processes the media commands before sending them to the media engine 2337. In some embodiments, the media engine 2337 includes a thread generation function for generating threads for dispatching to the thread execution logic 2350 via the thread dispatcher 2331.

[0304] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via a ring interconnect 2302, or some other interconnect bus or structure. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which can be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0305] In some embodiments, graphics pipeline 2320 and media pipeline 2330 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the driver software of the graphics processor converts API dispatch specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from Khronos Group and the Direct 3D library from Microsoft, or support can be provided for both OpenGL and D3D. Support can also be provided for the open source computer vision library (OpenCV). If a mapping can be performed from the pipeline called from the future API to the pipeline of the graphics processor, future APIs with compatible 3D pipelines will also be supported.

[0306] Graphics pipeline programming

[0307] Figure 24A is a block diagram illustrating a schematic processor command format 2400 according to some embodiments. Figure 24B is a block diagram illustrating a schematic diagram of a processor command sequence 2410 according to an embodiment. Figure 24A The solid-line boxes in show components that are typically included in a graphics command, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Figure 24A The exemplary graphics processor command format 2400 includes data fields for identifying the target client 2402 of the command, a command operation code (opcode) 2404, and command-related data 2406. In some commands, a sub-opcode 2405 and a command size 2408 are also included.

[0308] In some embodiments, client 2402 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads an opcode 2404 and, if present, a sub-opcode 2405 to determine the operation to be performed. The client unit uses the information in data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, commands are aligned via multiples of double word length.

[0309] Figure 24B The flowchart in FIG. 24 illustrates an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these specific commands or this command sequence. Furthermore, the commands may be issued as a batch of commands in a command sequence such that the graphics processor processes the command sequence at least partially simultaneously.

[0310] In some embodiments, graphics processor command sequence 2410 may begin with a pipeline flush command 2412 to cause any active graphics pipeline to complete its currently pending commands. In some embodiments, 3D pipeline 2422 and media pipeline 2424 are not operating simultaneously. A pipeline flush is performed to cause any pending commands in the active graphics pipeline to complete. In response to a pipeline flush, the graphics processor's command parser suspends command processing until the active graphics engines complete pending operations and the associated read cache is invalidated. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, pipeline flush command 2412 may be used for pipeline synchronization or before placing the graphics processor in a low-power state.

[0311] In some embodiments, pipeline select command 2413 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, pipeline select command 2413 is only required once per execution context before issuing pipeline commands, unless the context is issuing commands for both pipelines. In some embodiments, a pipeline flush command 2412 is required immediately before a pipeline switch via pipeline select command 2413.

[0312] In some embodiments, pipeline control commands 2414 configure the graphics pipeline for operation and are used to program 3D pipeline 2422 and media pipeline 2424. In some embodiments, pipeline control commands 2414 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 2414 are used for pipeline synchronization and for flushing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0313] In some embodiments, return buffer state commands 2416 are used to configure a set of return buffers for the corresponding pipeline to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers to which these operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 2416 includes selecting the size and number of return buffers to use for the set of pipeline operations.

[0314] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline determination 2420 , the command sequence is customized according to the 3D pipeline 2422 , which begins at 3D pipeline state 2430 , and the media pipeline 2424 , which begins at media pipeline state 2440 .

[0315] The commands for 3D pipeline state 2430 include 3D state setup commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, 3D pipeline state 2430 commands can also selectively disable or bypass specific pipeline elements if those elements are not to be used.

[0316] In some embodiments, the 3D primitive 2432 command is used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2432 are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2432 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 2432 command is used to perform vertex operations on the 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches the shader execution thread to the graphics processor execution unit.

[0317] In some embodiments, the 3D pipeline 2422 is triggered via an execute 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0318] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the specific purpose and programming of the media pipeline 2424 depends on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and the media decoding can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0319] In some embodiments, the media pipeline 2424 is configured in a similar manner to the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into the command queue before the media object commands 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline (such as encoding or decoding mode). In some embodiments, the media pipeline state commands 2440 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0320] In some embodiments, media object commands 2442 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 2442. Once the pipeline state is configured and media object commands 2442 are queued, media pipeline 2424 is triggered via execute commands 2444 or equivalent execute events (e.g., register writes). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0321] Graphics software architecture

[0322] Figure 25 An exemplary graphics software architecture for a data processing system 2500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. Graphics application 2510 and operating system 2520 each execute in system memory 2550 of the data processing system.

[0323] In some embodiments, the 3D graphics application 2510 includes one or more shader programs that include shader instructions 2512. The shader language instructions can be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in a machine language suitable for execution by a general-purpose processor core 2534. The application also includes geometric objects 2516 defined by vertex data.

[0324] In some embodiments, operating system 2520 is from Microsoft Corporation Operating system, proprietary UNIX-like operating system using a variant of the Linux kernel, or open source UNIX-like operating system. When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a low-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can execute shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 2510, high-level shaders are compiled into low-level shaders.

[0325] In some embodiments, the user-mode graphics driver 2526 includes a back-end shader compiler 2527 that converts shader instructions 2512 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functions 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0326] IP core implementation

[0327] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit (e.g., a processor). For example, a machine-readable medium may include instructions representing the various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. This type of representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model can be supplied to each customer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit can be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0328] Figure 26 26 is a block diagram showing an IP core development system 2600 according to an embodiment, which can be used to manufacture integrated circuits to perform operations. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). The design facility 2630 can use a high-level programming language (e.g., C / C++) to generate a software simulation 2610 for the IP core design. The software simulation 2610 can be used to design, test, and verify the behavior of the IP core. The register transfer level (RTL) design can then be created or synthesized by the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of the integrated circuit (including the associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2615, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. As a result, the specific details of the initial design and simulation can vary.

[0329] The RTL design 2615 or equivalent may be further synthesized by the design facility into a hardware model 2620, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. Non-volatile memory 2640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) may be used to store the IP core design for delivery to a third-party manufacturing facility 2665. Alternatively, the IP core design may be transmitted (e.g., via the Internet) via a wired connection 2650 or a wireless connection 2660. The manufacturing facility 2665 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0330] Figure 27 27 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2700, which may be fabricated using one or more IP cores, according to an embodiment. The exemplary integrated circuit includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, an I / O controller 2740, and a SPI / SDIO controller 2741. 2 S / I 2 The integrated circuit may include a display device 2745 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 2750 and a Mobile Industry Processor Interface (MIPI) display interface 2755. Storage may be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits may also include an embedded security engine 2770.

[0331] Additionally, other logic and circuitry may be included in the processor of integrated circuit 2700 , including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0332] In one example, the processor 1110 ( Figure 11 ) outputs the HDR enhanced image to the display 1120 ( Figure 11 ), such as Figures 6A to 10 and as described in the following examples. Similar examples can be found in Figure 23 Found in the graphics processor 2300.

[0333] Additional Notes and Examples

[0334] Example 1 may include a performance-enhanced computing system comprising: a sensor for measuring brightness values corresponding to light focused onto the sensor at multiple pixel locations; a memory comprising a set of instructions; and a processor, wherein the instructions, when executed by the processor, cause the system to: periodically scan multiple detection images from the sensor while the sensor remains enabled; determine multiple shutter times using multiple exposure estimates for each of the detection images; and scan multiple acquisition images from the sensor for storage into multiple image buffers, wherein the acquisition images include at least underexposed images, well-exposed images, and overexposed images.

[0335] Example 2 may include the system of Example 1, wherein the instructions further cause the system to combine the acquired images into a single high dynamic range (HDR) image.

[0336] Example 3 may include the system of Example 1, wherein the instructions further enable the sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before starting the scanning of the multiple acquisition images, wherein the scanning of the multiple acquisition images is scanned at each of the multiple shutter times.

[0337] Example 4 may include the system of Example 3, wherein the plurality of detection images used to generate the plurality of shutter times correspond to a plurality of acquisition images from a previous HDR image.

[0338] Example 5 may include the system of any of Examples 1 to 4, wherein determining the exposure estimate for each of the detection images includes counting a number of pixel values greater than a plurality of predetermined thresholds.

[0339] Example 6 may include the system of Example 5, wherein the plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

[0340] Example 7 may include a semiconductor package device comprising: a substrate; and logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-function hardware logic, the logic being configured to: periodically scan a plurality of detection images from the sensor while the sensor remains enabled; determine a plurality of shutter times using a plurality of exposure estimates for each of the detection images; and scan a plurality of acquisition images from the sensor for storage into a plurality of image buffers, wherein the acquisition images include at least an underexposed image, a well-exposed image, and an overexposed image.

[0341] Example 8 may include the apparatus of Example 7, wherein the method further comprises combining the acquired images into a single high dynamic range (HDR) image.

[0342] Example 9 may include the device of Example 7, wherein the logic further enables the sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before starting the scanning of the multiple acquisition images, the multiple acquisition images being scanned at each of the multiple shutter times.

[0343] Example 10 may include the apparatus of Example 9, wherein the plurality of detection images used to generate the plurality of shutter times correspond to a plurality of acquisition images from a previous HDR image.

[0344] Example 11 may include the apparatus of any of Examples 7 to 10, wherein determining the exposure estimate for each of the detection images comprises counting a number of pixel values greater than a plurality of predetermined thresholds.

[0345] Example 12 may include the device of Example 11, wherein the plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

[0346] Example 13 may include a method of operating a semiconductor packaging device, the method comprising: periodically scanning a plurality of detection images from the sensor while the sensor remains enabled; determining a plurality of shutter times using a plurality of exposure estimates for each of the detection images; and scanning a plurality of acquisition images from the sensor for storage into a plurality of image buffers, wherein the acquisition images include at least an underexposed image, a well-exposed image, and an overexposed image.

[0347] Example 14 may include the method of Example 13, wherein the method further comprises combining the acquired images into a single high dynamic range (HDR) image.

[0348] Example 15 may include a method as described in Example 13, wherein the method further includes: enabling the sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before starting the scanning of the multiple acquisition images, and scanning the multiple acquisition images with each of the multiple shutter times.

[0349] Example 16 may include the method of Example 15, wherein the plurality of detection images used to generate the plurality of shutter times correspond to a plurality of acquisition images from a previous HDR image.

[0350] Example 17 may include the method of any of Examples 13 to 16, wherein determining the exposure estimate for each of the detection images includes counting a number of pixel values greater than a plurality of predetermined thresholds.

[0351] Example 18 may include the method of Example 17, wherein the plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

[0352] Example 19 may include at least one computer-readable storage medium comprising a set of instructions that, when executed by a computing system, cause the computing system to: periodically scan a plurality of detection images from the sensor while the sensor remains enabled; determine a plurality of shutter times using a plurality of exposure estimates for each of the detection images; and scan a plurality of acquisition images from the sensor for storage into a plurality of image buffers, wherein the acquisition images include at least an underexposed image, a well-exposed image, and an overexposed image.

[0353] Example 20 may include at least one computer-readable storage medium as described in Example 19, wherein the set of instructions, when executed by the computing system, causes the computing system to: further combine the acquired images into a single high dynamic range (HDR) image.

[0354] Example 21 may include at least one computer-readable storage medium as described in Example 19, wherein the set of instructions, when executed by the computing system, causes the computing system to: further enable the sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before starting the scanning of the multiple acquisition images, the multiple acquisition images being scanned at each of the multiple shutter times.

[0355] Example 22 may include at least one computer-readable storage medium as described in Example 21, wherein the multiple detection images used to generate the multiple shutter times correspond to multiple acquisition images from a previous HDR image.

[0356] Example 23 may include at least one computer-readable storage medium as described in any of Examples 19 to 22, wherein determining the exposure estimate for each of the detection images includes: counting the number of pixel values greater than multiple predetermined thresholds.

[0357] Example 24 may include the at least one computer-readable storage medium of Example 23, wherein the plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

[0358] Example 25 may include a semiconductor packaging device comprising: a device for periodically scanning multiple detection images from the sensor while the sensor remains enabled; a device for determining multiple shutter times using multiple exposure estimates for each of the detection images; and a device for scanning multiple acquisition images from the sensor for storage in multiple image buffers, wherein the acquisition images include at least underexposed images, well-exposed images, and overexposed images.

[0359] Example 26 may include the apparatus of Example 25, further comprising: means for combining the acquired images into a single high dynamic range (HDR) image.

[0360] Example 27 may include an apparatus as described in Example 25, further comprising: a device for enabling the sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before starting the scanning of the multiple acquisition images, and the scanning of the multiple acquisition images will be scanned at each of the multiple shutter times.

[0361] Example 28 may include the apparatus of Example 27, wherein the plurality of detection images used to generate the plurality of shutter times correspond to a plurality of acquisition images from a previous HDR image.

[0362] Example 29 may include an apparatus as described in any of Examples 25 to 28, further comprising: means for counting the number of pixel values greater than a plurality of predetermined thresholds.

[0363] Example 30 may include the device of Example 29, wherein the plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

[0364] Example 31 may include a system comprising: a sensor for measuring luminance values corresponding to light focused onto the sensor at multiple pixel locations in a captured image, the luminance values having a dynamic range; a memory comprising a set of instructions; and a processor, wherein the instructions, when executed by the processor, cause the system to: generate a multi-segment tone mapping curve; generate a set of tone mapping values corresponding to the multi-segment tone mapping curve for storing equally spaced input values between zero and one in a lookup table; and use the lookup table to process the luminance values to apply the tone mapping curve to the luminance values of the pixels.

[0365] Example 32 may include a system as described in Example 31, wherein generating the multi-segment tone mapping curve includes: setting initial values for a set of end pivot points on the multi-segment tone mapping curve; calculating additional pivot points on the multi-segment tone mapping curve between the set of end points to compress the dynamic range of the luminance values to a desired dynamic range; mapping the tone mapping curve to values in the lookup table at equally spaced positions; and applying a multi-tap synchronization filter to the values in the lookup table.

[0366] Example 33 may include the system of Example 32, wherein the multi-tap synchronous filter comprises an exponential curve fit function.

[0367] Example 34 may include the system of Example 33, wherein, when the dynamic range is greater than a desired dynamic range, generating the tone mapping curve produces a one-to-one line in which no tone mapping is applied to the luma values.

[0368] Example 35 may include the system of Example 34, wherein the desired dynamic range corresponds to a dynamic range of an output display device used to display the captured image.

[0369] Example 36 may include the system of Example 31, wherein the sensor comprises a digital imaging device.

[0370] Example 37 may include a device comprising: a substrate; and logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-function hardware logic, the logic being configured to: generate a multi-segment tone mapping curve; generate a set of tone mapping values corresponding to the multi-segment tone mapping curve for storing equally spaced input values between zero and one in a lookup table; and process the luminance value using the lookup table to apply the tone mapping curve to the luminance value of the pixel.

[0371] Example 38 may include an apparatus as described in Example 37, wherein generating the multi-segment tone mapping curve comprises: setting initial values for a set of end pivot points on the multi-segment tone mapping curve; calculating additional pivot points on the multi-segment tone mapping curve between the set of end points to compress the dynamic range of the luminance values to a desired dynamic range; mapping the tone mapping curve to values in the lookup table at equally spaced positions; and applying a multi-tap synchronization filter to the values within the lookup table.

[0372] Example 39 may include the apparatus of Example 38, wherein the multi-tap synchronous filter comprises an exponential curve fit function.

[0373] Example 40 may include the apparatus of Example 39, wherein, when the dynamic range is greater than a desired dynamic range, generating the tone mapping curve produces a one-to-one line that does not apply tone mapping to the luminance values.

[0374] Example 41 may include the apparatus of Example 40, wherein the desired dynamic range corresponds to a dynamic range of an output display device for displaying the captured image.

[0375] Example 42 may include the apparatus of Example 37, wherein the sensor comprises a digital imaging device.

[0376] Example 43 may include a method comprising: generating a multi-segment tone mapping curve; generating a set of tone mapping values corresponding to the multi-segment tone mapping curve for storing equally spaced input values between zero and one in a lookup table; and using the lookup table to process the luminance value to apply the tone mapping curve to the luminance value of the pixel.

[0377] Example 44 may include a method as described in Example 43, wherein generating the multi-segment tone mapping curve includes: setting initial values for a set of end pivot points on the multi-segment tone mapping curve; calculating additional pivot points on the multi-segment tone mapping curve between the end point groups to compress the dynamic range of the luminance values to a desired dynamic range; mapping the tone mapping curve to values in the lookup table at equally spaced positions; and applying a multi-tap synchronization filter to the values in the lookup table.

[0378] Example 45 may include the method of Example 44, wherein the multi-tap synchronous filter comprises an exponential curve fit function.

[0379] Example 46 may include the method of Example 45, wherein, when the dynamic range is greater than a desired dynamic range, generating the tone mapping curve produces a one-to-one line that does not apply tone mapping to the luma values.

[0380] Example 47 may include the method of Example 46, wherein the desired dynamic range corresponds to a dynamic range of an output display device used to display the captured image.

[0381] Example 48 may include the method of Example 43, wherein the sensor comprises a digital imaging device.

[0382] Example 49 may include at least one computer-readable storage medium comprising a set of instructions that, when executed by a computing system, cause the computing system to: generate a multi-segment tone mapping curve; generate a set of tone mapping values corresponding to the multi-segment tone mapping curve for storing equally spaced input values between zero and one in a lookup table; and use the lookup table to process the luminance value to apply the tone mapping curve to the luminance value of the pixel.

[0383] Example 50 may include at least one computer-readable storage medium as described in Example 49, wherein generating the multi-segment tone mapping curve includes: setting initial values for a set of end pivot points on the multi-segment tone mapping curve; calculating additional pivot points on the multi-segment tone mapping curve between the end point groups to compress the dynamic range of the luminance values to a desired dynamic range; mapping the tone mapping curve to values in the lookup table at equally spaced positions; and applying a multi-tap synchronization filter to the values in the lookup table.

[0384] Example 51 may include the at least one computer-readable storage medium of Example 50, wherein the multi-tap synchronous filter comprises an exponential curve fitting function.

[0385] Example 52 may include at least one computer-readable storage medium as described in Example 51, wherein, when the dynamic range is greater than a desired dynamic range, generating the tone mapping curve produces a one-to-one line that does not apply tone mapping to the luminance values.

[0386] Example 53 may include at least one computer-readable storage medium as described in Example 52, wherein the desired dynamic range corresponds to a dynamic range of an output display device used to display the acquired image.

[0387] Example 54 may include the at least one computer-readable storage medium of Example 49, wherein the sensor comprises a digital imaging device.

[0388] The term "coupled" may be used herein to refer to any type of relationship, direct or indirect, between the components in question and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Furthermore, the terms "first," "second," and the like may be used herein merely to facilitate discussion and, unless otherwise indicated, do not convey any particular temporal or sequential significance. Furthermore, it should be understood that the indefinite articles "a" or "an" carry the meaning of "one or more" or "at least one."

[0389] As used in this application and in the claims, a list of items described by the term "one or more" may mean any combination of the listed items. For example, the phrase "at least one of A, B, and C" means A, B, C; A and B; A and C; B and C; or A, B, and C.

[0390] The embodiments have been described above with reference to specific embodiments. However, those skilled in the art will appreciate that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. The foregoing description and drawings are therefore to be considered in an illustrative rather than a restrictive manner.

Claims

1. A performance-enhanced computing system comprising: a sensor for measuring brightness values corresponding to light focused onto the sensor at a plurality of pixel locations; Memory, including a set of instructions; as well as a processor, wherein the instructions, when executed by the processor, cause the system to: while the sensor remains enabled, periodically scanning a plurality of detection images from the sensor; determining a plurality of shutter times using a plurality of exposure estimates for each of the detection images; scanning a plurality of acquired images from the sensor for storage into a plurality of image buffers; and combining the plurality of acquired images into a single high dynamic range HDR image, wherein a tone mapping curve is used to map each of the plurality of acquired images to a common color and image space, wherein the tone mapping curve comprises pixel values stored in a lookup table, The multiple collected images include at least underexposed images, well-exposed images, and overexposed images.

2. The system of claim 1, wherein: The instructions further enable the sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before starting the scanning of the multiple acquisition images, wherein the scanning of the multiple acquisition images is scanned at each of the multiple shutter times.

3. The system of claim 2, wherein: The plurality of detection images used to generate the plurality of shutter times correspond to a plurality of acquisition images from a previous HDR image.

4. The system according to any one of claims 1 to 3, wherein: Determining an exposure estimate for each of the inspection images includes counting a number of pixel values greater than a plurality of predetermined thresholds.

5. The system of claim 4, wherein: The plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

6. A semiconductor packaging device comprising: substrate; as well as Logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-function hardware logic, the logic configured to: while the sensor remains enabled, periodically scanning a plurality of detection images from the sensor; determining a plurality of shutter times using a plurality of exposure estimates for each of the test images; scanning a plurality of acquired images from the sensor for storage into a plurality of image buffers; and combining the plurality of acquired images into a single high dynamic range HDR image, wherein a tone mapping curve is used to map each of the plurality of acquired images to a common color and image space, wherein the tone mapping curve comprises pixel values stored in a lookup table, The multiple collected images include at least underexposed images, well-exposed images, and overexposed images.

7. The apparatus of claim 6, wherein: The logic further enables the sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before commencing the scanning of the plurality of acquisition images, the plurality of acquisition images being scanned at each of the plurality of shutter times.

8. The apparatus of claim 7, wherein: The plurality of detection images used to generate the plurality of shutter times correspond to a plurality of acquisition images from a previous HDR image.

9. The apparatus according to any one of claims 6 to 8, wherein Determining an exposure estimate for each of the inspection images includes counting a number of pixel values greater than a plurality of predetermined thresholds.

10. The apparatus of claim 9, wherein: The plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

11. A method of operating a semiconductor packaging apparatus, the method comprising: while the sensor remains enabled, periodically scanning a plurality of detection images from the sensor; determining a plurality of shutter times using a plurality of exposure estimates for each of the test images; scanning a plurality of acquired images from the sensor for storage into a plurality of image buffers; as well as combining the plurality of acquired images into a single high dynamic range HDR image, wherein a tone mapping curve is used to map each of the plurality of acquired images to a common color and image space, wherein the tone mapping curve comprises pixel values stored in a lookup table, The multiple collected images include at least underexposed images, well-exposed images, and overexposed images.

12. The method of claim 11, wherein: The method further includes enabling a sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before starting the scanning of the plurality of acquisition images, the plurality of acquisition images being scanned at each of the plurality of shutter times.

13. The method of claim 12, wherein: The plurality of detection images used to generate the plurality of shutter times correspond to a plurality of acquisition images from a previous HDR image.

14. The method according to any one of claims 11 to 13, wherein The determining the exposure estimate for each of the detection images includes counting a number of pixel values greater than a plurality of predetermined thresholds.

15. The method of claim 14, wherein: The plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

16. A semiconductor packaging device comprising: means for periodically scanning a plurality of detection images from said sensor while the sensor remains enabled; means for determining a plurality of shutter times using a plurality of exposure estimates for each of the test images; means for scanning a plurality of acquired images from said sensor for storage into a plurality of image buffers; as well as means for combining said plurality of acquired images into a single high dynamic range HDR image, wherein a tone mapping curve is used to map each of the plurality of acquired images to a common color and image space, wherein the tone mapping curve comprises pixel values stored in a lookup table, The multiple collected images include at least underexposed images, well-exposed images, and overexposed images.

17. The apparatus of claim 16, further comprising: Means for enabling a sensor to begin collecting image pixel data corresponding to the brightness of light focused on the sensor before commencing the scanning of the plurality of acquisition images to be scanned at each of the plurality of shutter times.

18. The apparatus of claim 17, wherein: The plurality of detection images used to generate the plurality of shutter times will correspond to a plurality of acquisition images from a previous HDR image.

19. The apparatus of any one of claims 16 to 18, further comprising: Means for counting the number of pixel values greater than a plurality of predetermined thresholds.

20. The apparatus of claim 19, wherein: The plurality of predetermined thresholds includes a saturation threshold corresponding to a maximum pixel value generated by the sensor.

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