Solid state storage device with asymmetric channels

Abstract

Solid state storage devices with asymmetric channels are disclosed. A solid state storage device of the present application includes a control component coupled to NVM chips through a plurality of channels; each channel is coupled to one or more NVM chips, the NVM chips include one or more logical units, each of the plurality of logical units provides a physical block for a large block, the number of logical units provided by the NVM chips coupled to one or more first channels is greater than the number of logical units provided by the NVM chips coupled to one or more second channels.

Description

TECHNICAL FIELD

[0001] The present application relates to solid state storage devices, and in particular, to data organization in solid state storage devices with asymmetric channels. BACKGROUND

[0002] Figure 1 A block diagram of a solid state storage device is shown. The solid state storage device 102 is coupled to a host for providing storage capability to the host. The host and the solid state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device through the above-mentioned ways, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc. are common NVMs.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is configured to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and is also configured to perform storage management, host logical address to flash physical address mapping, wear leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data of the DRAM 110. The DRAM can store the FTL table and / or buffered IO command data.

[0006] The control component 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive results of command execution output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] A memory target is one or more logical units (LUNs) of a shared CE (Chip Enable) signal within a NAND flash package. A NAND flash package can include one or more dies. Typically, a logical unit (LUN) corresponds to a single die. A logical unit can include multiple planes. Multiple planes within a logical unit can be accessed in parallel, while multiple logical units within a NAND flash chip can execute commands and report status independently of one another. The meaning of target, logical unit, LUN, and plane are provided in the "Open NAND Flash Interface Specification (Revision 3.0)", which is part of the prior art.

[0008] Data is typically stored and read on a storage medium in pages. Data is erased in blocks. A block (also referred to as a physical block) contains multiple pages. A block contains multiple pages. A page (referred to as a physical page) on a storage medium has a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0009] In a solid state storage device, a FTL (Flash Translation Layer) is utilized to maintain mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of the solid state storage device as perceived by upper layer software such as an operating system. Physical addresses are addresses used to access physical storage units of the solid state storage device. In the related art, address mapping can also be implemented in an intermediate address form. For example, a logical address is mapped to an intermediate address, and the intermediate address is further mapped to a physical address.

[0010] A table structure that stores mapping information from logical addresses to physical addresses is referred to as an FTL table. The FTL table is important metadata in the solid state storage device. Typically, a data item of the FTL table records an address mapping relationship in the solid state storage device in units of data pages.

[0011] The FTL table includes a plurality of FTL table entries (or table items). In one case, a corresponding relationship between one logical page address and one physical page is recorded in each FTL table entry. In another case, a corresponding relationship between a plurality of continuous logical page addresses and a plurality of continuous physical pages is recorded in each FTL table entry. In yet another case, a corresponding relationship between a logical block address and a physical block address is recorded in each FTL table entry. In still another case, a mapping relationship between logical block addresses and physical block addresses, and / or a mapping relationship between logical page addresses and physical page addresses is recorded in the FTL table.

[0012] A chunk includes physical blocks from each of a plurality of logical units (LUNs), also referred to as logical unit groups. Each logical unit can provide one physical block for a chunk. For example, in Figure 2 In the diagram of a chunk shown, a chunk is constructed over every 16 logical units (LUNs). Each chunk includes 16 physical blocks from each of the 16 logical units (LUNs). In Figure 2 In the example of FIG. 2, chunk 0 includes physical block 0 from each of the 16 logical units (LUNs), and chunk 1 includes physical block 1 from each of the logical units (LUNs). Chunks can also be constructed in a variety of other ways.

[0013] For example, a stripe of pages is constructed in a chunk, and physical pages of the same physical address within each logical unit (LUN) constitute a "stripe of pages". Figure 2 In the example of FIG. 3, physical page P0-0, physical page P0-1,..., and physical page P0-x constitute a stripe of pages 0, where physical page P0-0, physical page P0-1,..., physical page P0-14 are used to store user data, and physical page P0-x is used to store check data calculated from all user data within the stripe. Similarly, physical page P1-0, physical page P1-1,..., and physical page P1-x constitute a stripe of pages 1, where physical page P1-0, physical page P1-1,..., physical page P1-14 are used to store user data, and physical page P1-x is used to store check data calculated from all user data within the stripe. Figure 2In some embodiments, physical pages P2-0, P2-1, …, and P2-x form a stripe 2. The physical pages used to store the parity data can be located anywhere in the stripe. As another example, in the related description of the Chinese patent application No. 201710752321.0, another configuration of the chunk is provided. SUMMARY

[0014] To provide a specified storage capacity, in some cases, a solid state storage device uses asymmetric channels. Each of the multiple channels coupling the NVM chips is provided with a different number of NVM chips, dies, LUNs, and / or storage capacity. The asymmetric channels cause a difference in the amount of data to be transmitted by each channel when reading data randomly, and some channels become a performance bottleneck. Embodiments according to the present application attempt to solve one or more of the above-mentioned technical problems, as well as other technical problems.

[0015] According to a first aspect of the present application, there is provided a first solid state storage device according to the first aspect of the present application, comprising a control component coupled to NVM chips through a plurality of channels; each channel is coupled to one or more NVM chips, the NVM chips comprise one or more logical units, each of the plurality of logical units provides a physical block for a chunk, the number of logical units provided by the NVM chips coupled to one or more first channels is greater than the number of logical units provided by the NVM chips coupled to one or more second channels.

[0016] According to the first solid state storage device of the first aspect of the present application, there is provided a second solid state storage device according to the first aspect of the present application, the parity block of the chunk is provided by the NVM chips coupled to the first channels.

[0017] According to the first or second solid state storage device of the first aspect of the present application, there is provided a third solid state storage device according to the first aspect of the present application, the parity block of the first chunk is provided by the NVM chips coupled to the second channels, and one or more physical blocks provided by the first channels for the first chunk are not used.

[0018] According to the third solid state storage device of the first aspect of the present application, there is provided a fourth solid state storage device according to the first aspect of the present application, the one or more physical blocks provided by the first channels for the first chunk are marked as bad blocks.

[0019] According to the third or fourth solid state storage device of the first aspect of the present application, there is provided a fifth solid state storage device according to the first aspect of the present application, the bad blocks are naturally generated or marked as bad blocks by artificially marking the available physical blocks.

[0020] According to one of the third to fifth solid state storage devices of the first aspect of the present application, there is provided a sixth solid state storage device according to the first aspect of the present application, if there is one or more naturally occurring bad blocks in the physical blocks provided by the first channel for the first large block, there is no need to artificially mark available physical blocks as bad blocks.

[0021] According to one of the third to fifth solid state storage devices of the first aspect of the present application, there is provided a seventh solid state storage device according to the first aspect of the present application, if there is no naturally occurring bad block in the physical blocks provided by the first channel for the first large block, one or more available physical blocks are artificially marked as bad blocks.

[0022] According to one of the first to seventh solid state storage devices of the first aspect of the present application, there is provided an eighth solid state storage device according to the first aspect of the present application, the location of the check block of the large block is recorded in the metadata of the large block.

[0023] According to one of the first to eighth solid state storage devices of the first aspect of the present application, there is provided a ninth solid state storage device according to the first aspect of the present application, one or more physical blocks of the NVM chip of the first channel meet the conditions for constructing the first large block, but are not used to construct the first large block.

[0024] According to one of the first to ninth solid state storage devices of the first aspect of the present application, there is provided a tenth solid state storage device according to the first aspect of the present application, the logical unit includes a plurality of planes, and the first logical unit that provides the most good physical blocks for the first large block is selected as the first logical unit that provides the check block for the first large block among a plurality of logical units that provide physical blocks for the first large block.

[0025] According to the tenth solid state storage device of the first aspect of the present application, there is provided an eleventh solid state storage device according to the first aspect of the present application, if the first logical unit does not belong to the first channel, the physical blocks provided by the first channel for the first large block are set as bad blocks.

[0026] According to the first solid state storage device of the first aspect of the present application, there is provided a twelfth solid state storage device according to the first aspect of the present application, the check block of the first large block is provided by the NVM chip coupled by the first channel; the check block of the second large block is provided by the NVM chip coupled by the second channel; and one or more physical blocks provided by the NVM chip of the first channel for the second large block are not used.

[0027] According to one of the first to twelfth solid state storage devices of the first aspect of the present application, there is provided a thirteenth solid state storage device according to the first aspect of the present application, the number of NVM chips coupled by one or more first channels is greater than the number of NVM chips coupled by one or more second channels.

[0028] According to one of the first to thirteenth solid state storage devices of the first aspect of the present application, there is provided a fourteenth solid state storage device according to the first aspect of the present application, the one or more channel-coupled NVM chips having different numbers of logical units.

[0029] According to the first to third methods of selecting a check block for a large block of the second aspect of the present application, there is provided a fourth method of selecting a check block for a large block according to the second aspect of the present application, selecting one or more physical blocks provided by the first logical unit for the first large block as the check block for the first large block.

[0030] According to the first to third methods of selecting a check block for a large block of the second aspect of the present application, there is provided a fourth method of selecting a check block for a large block according to the second aspect of the present application, selecting one or more physical blocks provided by the first logical unit for the first large block as the check block for the first large block.

[0031] According to the first to third methods of selecting a check block for a large block of the second aspect of the present application, there is provided a fourth method of selecting a check block for a large block according to the second aspect of the present application, selecting one or more physical blocks provided by the first logical unit for the first large block as the check block for the first large block.

[0032] According to the first to third methods of selecting a check block for a large block of the second aspect of the present application, there is provided a fourth method of selecting a check block for a large block according to the second aspect of the present application, selecting one or more physical blocks provided by the first logical unit for the first large block as the check block for the first large block.

[0033] According to the first to third methods of selecting a check block for a large block of the second aspect of the present application, there is provided a fourth method of selecting a check block for a large block according to the second aspect of the present application, selecting one or more physical blocks provided by the first logical unit for the first large block as the check block for the first large block.

[0034] According to the first to third methods of selecting a check block for a large block of the second aspect of the present application, there is provided a fourth method of selecting a check block for a large block according to the second aspect of the present application, selecting one or more physical blocks provided by the first logical unit for the first large block as the check block for the first large block.

[0035] According to the first to third methods for selecting a check block for a large block of the second aspect of the present application, the seventh method for selecting a check block for a large block according to the second aspect of the present application is provided, if there is no bad block in one or more physical blocks provided by the first logical unit for the first large block, at least one of the one or more physical blocks provided by the first logical unit for the first large block is marked as a bad block.

[0036] According to the first to third methods for selecting a check block for a large block of the second aspect of the present application, the eighth method for selecting a check block for a large block according to the second aspect of the present application is provided, if the number of physical blocks that can be used as data blocks of the first large block in the first channel physical block is greater than the number of physical blocks that can be used as data blocks of the first large block in the second channel, one or more physical blocks that can be used as data blocks of the first large block in the first channel physical block are marked as bad blocks.

[0037] According to the eighth method for selecting a check block for a large block of the second aspect of the present application, the ninth method for selecting a check block for a large block according to the second aspect of the present application is provided, after marking the bad blocks, the number of physical blocks that can be used as data blocks of the first large block in the first channel physical block is not greater than the number of physical blocks that can be used as data blocks of the first large block in the second channel.

[0038] According to the first method for selecting a check block for a large block of the second aspect of the present application, the tenth method for selecting a check block for a large block according to the second aspect of the present application is provided, when writing data to the large block, no data is written to the marked bad blocks.

[0039] According to the first method for selecting a check block for a large block of the second aspect of the present application, the eleventh method for selecting a check block for a large block according to the second aspect of the present application is provided, when performing error checking on the large block, the marked bad blocks are avoided.

[0040] According to the third aspect of the present application, the first method for selecting a check block for a large block according to the third aspect of the present application is provided, comprising: obtaining the number of good blocks provided by each logical unit on one or more channels for the first large block; if the number of good blocks provided by the first logical unit on the first channel of the one or more channels for the first large block is equal to the maximum number of good blocks that can be provided by each of all logical units providing physical blocks for the first large block, and the number of logical units of the first channel is greater than the number of logical units of the second channel of the one or more channels; selecting the first logical unit to provide a check block for the first large block.

[0041] According to the first method for selecting a check block for a large block of the third aspect of the present application, the second method for selecting a check block for a large block according to the third aspect of the present application is provided, if the number of good blocks provided by the first logical unit for the large block is less than the maximum number of good blocks, selecting a logical unit of another channel different from the first channel to provide a check block for the first large block.

[0042] According to the second method for selecting a check block for a large block according to the third aspect of the present application, the third method for selecting a check block for a large block according to the third aspect of the present application is provided, and further comprising: if the number of good blocks that the first channel can provide for the first large block is greater than the number of good blocks that the second channel can provide for the first large block, marking one or more good blocks of the first channel that can be provided for the first large block as bad blocks.

[0043] According to the third method for selecting a check block for a large block according to the third aspect of the present application, the fourth method for selecting a check block for a large block according to the third aspect of the present application is provided, and further comprising: marking one or more good blocks of the first channel that can be provided for the first large block as bad blocks, so that the number of good blocks that the first channel provides for the first large block is not greater than the number of good blocks that the second channel provides for the first large block.

[0044] According to one of the first to fourth methods for selecting a check block for a large block according to the third aspect of the present application, the fifth method for selecting a check block for a large block according to the third aspect of the present application is provided, and the number of good blocks that the logical unit provides for a large block depends on the number of good blocks in the physical blocks provided for the specified large block in each plane of the logical unit.

[0045] According to one of the first to fifth methods for selecting a check block for a large block according to the third aspect of the present application, the sixth method for selecting a check block for a large block according to the third aspect of the present application is provided, and the physical blocks that the logical unit provides for a large block have the same block address.

[0046] According to the fourth aspect of the present application, the first method for selecting a check block for a large block according to the fourth aspect of the present application is provided, comprising one of the first to eleventh methods for selecting a check block for a large block according to the second aspect of the present application, and one of the first to sixth methods for selecting a check block for a large block according to the third aspect of the present application.

[0047] According to the fifth aspect of the present application, a program comprising program code is provided, which, when loaded into a storage device and executed on the storage device, causes the storage device to perform one of the methods for selecting a check block for a large block according to the second aspect, the third aspect or the fourth aspect of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0049] Figure 1 is a block diagram of a solid-state storage device in the related art;

[0050] Figure 2 is a diagram of a chunk in the related art;

[0051] Figure 3 is a block diagram of a solid state storage device according to an embodiment of the present application;

[0052] Figure 4 illustrates data organization according to an embodiment of the present application;

[0053] Figure 5 is a flowchart of selecting a check chunk for a chunk according to another embodiment of the present application;

[0054] Figure 6A is a block diagram of a solid state storage device according to yet another embodiment of the present application;

[0055] Figure 6B is a block diagram of a solid state storage device according to another embodiment of the present application;

[0056] Figure 6C is a block diagram of a solid state storage device according to still another embodiment of the present application;

[0057] Figure 6D is a block diagram of a solid state storage device according to yet still another embodiment of the present application;

[0058] Figure 6E is a block diagram of a solid state storage device according to yet another embodiment of the present application;

[0059] Figure 6F is a block diagram of a solid state storage device according to another embodiment of the present application;

[0060] Figure 7 illustrates a diagram of a chunk according to yet another embodiment of the present application;

[0061] Figure 8A illustrates a chunk according to yet another embodiment of the present application;

[0062] Figure 8B illustrates a chunk according to yet still another embodiment of the present application; and

[0063] Figure 9 is a flowchart of selecting a check chunk for a chunk according to yet another embodiment of the present application. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present application will be apparently and completely described below with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person skilled in the art without any creative work fall within the scope of protection of the present application.

[0065] Figure 3 is a block diagram of a solid state storage device according to an embodiment of the application. The control component (see also Figure 1 , control component 104) of the solid state storage device is coupled to the NVM chips (NVM) through one or more channels. Figure 3 In the figure, channels are indicated by "CH" followed by a reference number. Each channel can be coupled to one or two NVM chips. Figure 3 In the figure, reference "QDP" followed by a sequence number indicates one of the NVM chips. "QDP" implies that the indicated NVM chip comprises four dies. Reference "DDP" followed by a sequence number also indicates one of the NVM chips. "DDP" implies that the indicated NVM chip comprises two dies. And by way of example, according to an embodiment of the application, each die provides one LUN. Figure 3

[0066] Figure 3 In an embodiment of the application, eight channels are shown, where each of CH 0-CH 6 is provided with one NVM chip comprising four dies (QDP 0-QDP 6, respectively). Channel CH 7 is provided with two NVM chips, one comprising four dies (QDP 7) and the other comprising two dies (DDP 8).

[0067] Figure 3 In an embodiment of the application, a chunk is constructed. The dies of the NVM chips are divided into two groups, where the LUNs provided by the dies in each group are used to construct the same chunk. The physical blocks belonging to the same chunk come from the LUNs of the same group. Die 0 and die 1 of each of the NVM chips (QDP 0-QDP 7) and die 0 of the NVM chip (DDP 8) form one group, which is used to construct a chunk. Die 2 and die 3 of each of the NVM chips (QDP 0-QDP 7) and die 1 of the NVM chip (DDP 8) form another group, which is used to construct a chunk.

[0068] Figure 3 In an embodiment of the application, channels CH 0-CH 6 have the same NVM chip configuration, while the NVM chip configuration of channel CH 7 is different from channels CH 0-CH 6.

[0069] ​Solid-state storage devices (SSDs) have a specified storage capacity. The storage capacity determines the number and / or type of NVM chips (SDP, DDP, QDP, or ODP, containing 1, 2, 4, or 8 dies per chip, respectively) that the SSD must have. For example, to accommodate 52 dies in an SSD, 12 QDP chips and 4 SDP chips can be used. To accommodate 20 dies in an SSD, 10 DDP chips can be used.

[0070] Solid-state storage devices have a specified number of channels in their control unit. It is difficult to constrain the relationship between the number of channels and the number of NVM chips. This results in, for example... Figure 3 The embodiments shown depict scenarios where each channel has a different NVM chip configuration.

[0071] Because the NVM chips on the same channel share some of the signal lines (e.g., data lines) provided by the channel, the NVM chip configuration of the channel affects the channel's performance. Figure 3 For example, if the maximum data transmission bandwidth of a channel is BW, then in channels CH0 to CH6, the maximum bandwidth usable by each die is BW / 4 (because each channel has 4 dies), while in channel CH7, the maximum bandwidth usable by each die is BW / 6 (because channel CH7 has 6 dies). This results in the underutilization of the performance of each die in channel CH7. According to embodiments of this application, an attempt is made to at least solve this problem.

[0072] According to embodiments of this application, by carefully selecting the location of the check block that provides storage check data in the large block, the user data stored in the large block is more advantageously distributed across multiple channels of the solid-state storage device, thereby improving the performance of the solid-state storage device.

[0073] Figure 4 Data organization according to embodiments of this application is illustrated.

[0074] Combination Figure 3 and Figure 4 According to an embodiment of this application, the 34 dies of the solid-state storage device provide 34 LUNs, and 17 LUNs are grouped together to build a bulk. Figure 4 In this configuration, LUNs 0-16 are supplied sequentially by dies 0 and 1 of each of QDPs 0-QDP 7, and die 0 of DDP 8. LUN 14 is supplied by die 0 of QDP 7, LUN 15 by die 1 of QDP 7, and LUN 16 by die 0 of DDP 8. LUNs 0 to 16 are used to construct bulks 0 to n. LUNs 17-33 are supplied sequentially by dies 1 and 2 of each of QDPs 0-QDP 7, and die 1 of DDP 8.

[0075] According to an embodiment of Figure 4 , for chunk 0 to chunk n, the parity chunk is provided by the LUN (LUN 14~LUN 16) located in channel CH 7 as much as possible. For example, the parity chunk B0 storing the parity data of chunk 0 is located in LUN 16, and the parity chunk B1 of chunk 1 is located in LUN 15. According to an embodiment of Figure 4 , in some cases, the parity chunk for a chunk is provided by a LUN of a channel other than channel CH 7, for example, the parity chunk Bn of chunk n is located in LUN 1.

[0076] Some physical chunks of the NVM chip are bad chunks. For example, the physical chunk BB1 of chunk 1 from LUN 14. The bad chunk is marked so as not to be used to store data. For chunk n, since the parity chunk Bn is located in LUN 1 instead of one of LUN 14~LUN 16 of channel CH 7, it is possible that channel CH 7 provides the physical chunk for storing user data for chunk n, and causes that when continuously reading the data stored in the three physical chunks, the bandwidth of channel CH 7 is occupied and the performance of LUN 14~LUN 16 cannot be fully utilized. To solve this problem, although the physical chunks provided by LUN 14~LUN 16 for chunk n are all available (not bad chunks), at least one of the physical chunks provided by LUN 14~LUN 16 for chunk n is marked as a bad chunk. Figure 4 In the embodiment, the physical chunk provided by LUN 16 for chunk n is marked as a bad chunk, denoted as MB.

[0077] According to an embodiment of Figure 4 , for any chunk C, among the multiple physical chunks provided by LUN 14~LUN 16 of channel CH 7 for chunk C, either one of the physical chunks is used to store parity data, or at least one of the physical chunks is a bad chunk (either naturally generated or artificially marked as a bad chunk), so as to ensure that the physical chunks used to store user data for chunk C provided by LUN 14~LUN 16 of channel CH 7 are not more than two. Further, when reading data from chunk C, the data read from channel CH 7 comes from not more than two physical chunks, so that the maximum bandwidth of channel CH 7 does not become the performance bottleneck of LUN 14~LUN 16, or the maximum bandwidth of channel 7 has little effect on the overall performance of LUN 14~LUN 16.

[0078] It is understood that, according to embodiments of this application, the number of LUNs constituting a block is not limited to 17, but can be other numbers. The fault-tolerant configuration (RAID configuration) used in the block is not limited to 16+1 (16 copies of user data and 1 copy of parity data), but can also be 15+2 or 30+1, etc. The NVM chip used in the channel is not limited to QDP or DDP, but can encapsulate other numbers of dies in the NVM chip.

[0079] Figure 5 This is a flowchart of selecting a verification block for a large block according to an embodiment of this application.

[0080] Implement according to each large block Figure 5 The process of an embodiment is to determine the location of the check block used for the large block. Optionally, the location of the check block used for the large block is also recorded in the metadata of the large block, so that the location of the check block can be obtained from the metadata when data is written to the large block or when the check block needs to be used.

[0081] For large block C, to determine the location of its check block, it is necessary to obtain information about the number of channels on the solid-state storage device compared to other channels (see [link]). Figure 3 (Channel CH 7). Then, obtain one or more LUNs provided by the die of channel CH 7 for block C, and the physical block provided by the one or more LUNs for block C (510). If one of the one or more LUNs (denoted as LUN x) can serve as a check block for block C (520) (for example, the physical block is available), then the check block for block C is successfully determined in the die of channel CH 7, and it is recorded that LUN x provides a check block for block C.

[0082] If none of the physical blocks provided by the one or more LUNs for block C are suitable as parity blocks (e.g., these physical blocks are all bad and unusable), then a parity block is selected from the LUNs provided by the dies of other channels in the solid-state storage device (530), and the location of the determined parity block is recorded in the metadata of block C. Additionally, among the physical blocks provided by the die of channel CH 7 for block C, a physical block belonging to one of the LUNs of channel CH 7 is marked as a bad block (540), thereby reducing the number of LUNs provided by channel CH 7 for storing user data for block C. For example, each of the three LUNs of channel CH 7 provides physical blocks for block C. If at least one of these three physical blocks is a naturally occurring bad block, then there is no need to manually mark the usable physical blocks of these three physical blocks as bad blocks; if there are no naturally occurring bad blocks among these three physical blocks, then at least one of these three physical blocks is manually marked as a bad block.

[0083] When writing data to large block C, avoid marked bad blocks. When performing error checking on large block C, also avoid marked bad blocks.

[0084] Figure 6A is a block diagram of a solid state storage device according to yet another embodiment of the present application. The control component (see also Figure 1 , control component 104) of the solid state storage device is coupled to the NVM chips (NVM) through one or more channels. As an example, according to Figure 6A embodiments, each die provides one LUN.

[0085] Figure 6A In the embodiment of , eight channels are shown, where each of CH 0 ~ CH 6 is configured with one NVM chip (denoted as QDP 0 ~ QDP 6 respectively) containing four dies. While channel CH 7 is configured with two NVM chips (denoted as QDP 7 ~ QDP 8 respectively) each containing four dies. Thus, the solid state storage device uses a single model of NVM chip (containing four dies) to reduce the complexity of parts procurement and management, and also to reduce the probability of introducing errors in the development and manufacturing process of the solid state storage device due to the diversity of NVM chip models.

[0086] Figure 6A In the embodiment of , the chunks are constructed. For example, the dies of the NVM chips are divided into two groups, and the LUNs provided by the dies in each group are used to construct the same chunk. The physical blocks belonging to the same chunk come from the LUNs in the same group. Die 0 and die 1 of each of the NVM chips (QDP 0 ~ QDP 7) and die 0 of the NVM chip (QDP 8) are a group, which are used to construct a chunk. Die 2 and die 3 of each of the NVM chips (QDP 0 ~ QDP 7) and die 1 of the NVM chip (QDP 8) are another group, which are used to construct a chunk. And all the physical blocks of die 2 and die 3 of the NVM chip (QDP 8) are artificially marked as bad blocks. Thus, it is ensured that the chunk provided by die 2 and die 3 of the NVM chip (QDP 8) will not be used when accessing the chunk.

[0087] According to the embodiment of Figure 5 for selecting the check block for a chunk is applied to the embodiment of Figure 6AThe solid-state storage device of this embodiment. Therefore, for each block, physical blocks in the LUNs provided by the dies of channel CH7 (excluding dies 2 and 3 of NVM chip QDP 8) are selected as parity blocks as much as possible. And when the dies of channel CH7 are not suitable for providing parity blocks, parity blocks are selected from dies of other channels, and among the physical blocks provided by the dies of channel CH7 for the block (excluding physical blocks of dies 2 and 3 of NVM chip QDP 8), physical blocks belonging to one of the LUNs of channel CH7 (excluding LUNs of dies 2 and 3 of NVM chip QDP 8) are marked as bad blocks (540), thereby reducing the number of LUNs provided by channel CH7 for storing user data in the block C.

[0088] Figure 6B This is a block diagram of a solid-state storage device according to another embodiment of this application.

[0089] Figure 6B In the embodiment shown, eight channels are illustrated, where each of channels CH0 to CH6 is equipped with an NVM chip containing two dies (denoted as DDP0 to DDP6 respectively). Channel CH7 is equipped with two NVM chips containing two dies each (denoted as DDP7 to DDP8 respectively). Thus, the solid-state storage device uses a single type of NVM chip (containing two dies), with each die providing one LUN.

[0090] Figure 6B In this embodiment, dies 0 and 1 of each of the NVM chips (DDP 0 to DDP 7), and die 0 of the NVM chip (DDP 8), are grouped together to construct large blocks. All physical blocks of die 1 of the NVM chip (DDP 8) are artificially marked as bad blocks. This ensures that when accessing large blocks, the large blocks provided by die 1 of the NVM chip (DDP 8) are not used.

[0091] Furthermore, by selecting the location of the parity block for the large block, it is ensured that for any large block, at most two of the three dies of channel CH 7 (dies 0 and 1 of NVM chip DDP 6, and die 0 of NVM chip DDP7) provide data blocks for the large block. At least one physical block provided by the three dies of channel CH 7 for the large block is either used to store the large block's parity data or is marked as a bad block (whether naturally bad or manually marked bad).

[0092] Figure 6C This is a block diagram of a solid-state storage device according to another embodiment of the present application.

[0093] Figure 6CIn the embodiment of FIG. 1, eight channels are shown, where each of channels CH 0-CH 6 is provided with two NVM chips (labeled DDP 0-DDP 13, respectively) that each contain two dies. Channel CH 7 is provided with one NVM chip (labeled DDP 14) that contains two dies and one NVM chip (labeled QDP 0) that contains four dies.

[0094] Figure 6C In the embodiment of FIG. 1, die 0 of each of NVM chips (DDP 0-DDP 14) and die 0 and die 1 of NVM chip (QDP 0) are grouped together to form a large block. Die 1 of each of NVM chips (DDP 0-DDP 14) and die 2 and die 3 of NVM chip (QDP 0) are grouped together to form a large block.

[0095] and by selecting the location of the check block for a large block, it is ensured that for any large block, at most two of the three dies (die 0 of NVM chip DDP 14 and die 0 and die 1 of NVM chip QDP 0, or die 1 of NVM chip DDP 14 and die 2 and die 3 of NVM chip QDP 0) of channel CH 7 that provide a physical block for the large block provide a data block for the large block. The three dies of channel CH 7 that provide a physical block for a large block either provide at least one physical block for the large block or are used to store check data for the large block or are marked as bad blocks (whether naturally bad blocks or artificially marked bad blocks).

[0096] Figure 6D is a block diagram of a solid state storage device according to yet another embodiment of the application.

[0097] Figure 6D In the embodiment of FIG. 1, eight channels are shown, where each of channels CH 0-CH 5 is provided with one NVM chip (labeled DDP 0-DDP 5, respectively) that contains two dies. Each of channels CH 6 and CH 7 is provided with two NVM chips (labeled DDP 6-DDP 9) that each contain two dies.

[0098] Figure 6D In the embodiment of FIG. 1, die 0 and die 1 of each of NVM chips (DDP 0, DDP 2, DDP 4, and DDP 6) and die 0 of NVM chip (DDP 9) are grouped together to form a large block. Die 0 and die 1 of each of NVM chips (DDP 1, DDP 3, DDP 5, and DDP 7) and die 0 of NVM chip (DDP 8) are grouped together to form a large block. Die 1 of NVM chips DDP 9 and DDP 8 are marked as bad blocks and do not participate in large block formation.

[0099] By selecting the location of the parity block for a large block, it is ensured that for any large block, at most 2 out of the 3 dies (die 0 and die 1 of NVM chip DDP 6 and die 0 of NVM chip DDP 9) of channel CH 6 that provide the physical blocks for the large block provide data blocks for the large block. The three dies of channel CH 6 that provide the physical blocks for a large block provide at least one physical block for the large block, or are used to store parity data for the large block, or are marked as bad blocks (whether naturally bad blocks or artificially marked bad blocks). And it is ensured that for any large block, at most 2 out of the 3 dies (die 0 and die 1 of NVM chip DDP 7 and die 0 of NVM chip DDP 8) of channel CH 7 that provide the physical blocks for the large block provide data blocks for the large block.

[0100] Figure 6E is a block diagram of a solid state storage device according to yet another embodiment of the present application.

[0101] Figure 6E In an embodiment of, 8 channels are shown, where each of channels CH 0 ~ CH 3 is provided with 2 NVM chips (denoted as QDP 0 ~ QDP 7) each containing 4 dies. And each of channels CH 4 ~ CH 7 is provided with 1 NVM chip (denoted as QDP 8 ~ QDP 11) containing 4 dies and 1 NVM chip (denoted as SDP 0 ~ SDP 3) containing 1 die.

[0102] Figure 6E In an embodiment of, all dies of NVM chips (QDP 0, QDP 2 and QDP 8) and all dies of SDP 0 are grouped to construct large blocks; all dies of NVM chips (QDP 1, QDP 3 and QDP 9) and all dies of SDP 1 are grouped to construct large blocks; all dies of NVM chips (QDP 4, QDP 6 and QDP 10) and all dies of SDP 2 are grouped to construct large blocks; and all dies of NVM chips (QDP 5, QDP 7 and QDP 11) and all dies of SDP 3 are grouped to construct large blocks.

[0103] As an example, by selecting the location of the parity block for a large block, it is ensured that for any large block, the dies of the SDP chips provide the parity blocks for the large block. Or for any large block, the dies of the NVM chips of channels CH 4 ~ CH 7 that provide the physical blocks for the large block do not exceed 4 dies (e.g., the parity blocks are provided in the physical blocks provided by the NVM chips of channels CH 4 ~ CH 7 for the large block, or at least one of the physical blocks provided by the NVM chips of channels CH 4 ~ CH 7 for the large block is marked as a bad block).

[0104] Figure 6F is a block diagram of a solid state storage device according to yet another embodiment of the present application.

[0105] Figure 6F In an embodiment of the present application, 12 channels are shown, each of which is provided with one NVM chip containing 8 dies (denoted as ODP 0~ODP 11), and one NVM chip containing 2 dies (denoted as DDP 0~DDP 11).

[0106] Figure 6F In an embodiment of the present application, as an example, dies 0-3 of ODP 0, ODP 1 and OPD 6, and die 0 of DDP 0 form a group (denoted as group 0) for constructing a large block; dies 0-3 of ODP 2, ODP 3 and OPD 7, and die 0 of DDP 2 form a group (denoted as group 1) for constructing a large block; dies 4-7 of ODP 0, ODP 1 and OPD 6, and die 1 of DDP 0 form a group (denoted as group 2) for constructing a large block.

[0107] As an example, by selecting the location of the check block for a large block, it is ensured that for any large block, the check block for the large block is provided by a die of a DDP (DDP 0) chip. Alternatively, for a large block in group 0, the channel CH 0 containing the DDP chip provides the check block for the large block, or one or more of the physical blocks in channel CH 0 provided for the large block are marked as bad blocks. Similarly, for a large block in group 1, the channel CH 2 containing the DDP chip (DDP 2) provides the check block for the large block, or one or more of the physical blocks in channel CH 2 provided for the large block are marked as bad blocks.

[0108] Figure 7 A schematic diagram of a large block according to yet another embodiment of the present application is shown.

[0109] According to an embodiment of the present application, Figure 7 In an embodiment of the present application, a large block is constructed by 17 LUNs. Each logical unit (LUN) includes a plurality of planes. As an example, LUN 2 includes 4 planes (plane 0, plane 1, plane 2 and plane 3). Each plane in a LUN can perform read and write operations simultaneously, thereby improving the parallelism of operations.

[0110] In an embodiment of the present application, Figure 7In the example, the lower 2 bits of the physical block address are used to address the plane. For instance, the physical block address within a LUN is 12 bits, where the lowest 2 bits are used to address one of the four planes within the LUN, and the higher 10 bits are used to address the physical block. For clarity, the higher 10 bits of the physical block address are called the "block address," and the lower 2 bits are called the "plane address." Thus, physical blocks with the same "block address" within each logical unit constitute a "large block." It should be noted that sometimes the 12-bit address along with the "plane address" is also called the "block address." In this case, physical blocks with block addresses 0, 1, 2, and 3 in each LUN belong to the same block stripe.

[0111] See Figure 7 Physical blocks B0 with address 0 in each plane from LUN0 to LUN16 constitute large block 0. Physical blocks B0 in each plane from LUN0 to LUN15 are used to store user data, while physical blocks B0 in the four planes of LUN16 are used to store check data calculated based on the user data in the block stripe.

[0112] Similarly, Figure 7 In the LUN0-LUN16, physical block B2 with block address 2 constitutes large block 2.

[0113] Sometimes bad blocks exist in NVM chips, which can cause the number of physical blocks provided by the various LUNs that make up a large block to differ.

[0114] Figure 8A A large block according to yet another embodiment of this application is shown. The large block is constructed on LUN 0 to LUN 4. Each of LUN 0 to LUN 4 includes four planes, labeled P0, P1, P2 and P3 respectively. Figure 8A Each square in the array represents a physical block and has the same physical block address. Figure 8A All the blocks together form the large block 800. The physical blocks marked by shaded areas are bad blocks and cannot be written to.

[0115] according to Figure 8A In the illustrated embodiment, LUN 4 is selected to provide the parity block for block 800. All planes of LUN 4 that provide physical blocks for block 800 serve as parity blocks for block 800. LUN 4 is selected to provide the parity block for block 800 because, among LUNs 0-LUN 4, the planes of LUN 4 that provide physical blocks for block 800 have the largest number of available blocks. In other words, the LUN with the most good blocks (or the fewest bad blocks) among the multiple LUNs constituting block 800 is selected to provide the parity block.

[0116] Figure 8B This application still demonstrates another embodiment of the present application. Figure 8BAll the blocks constitute block 810. The physical blocks marked with shaded areas are bad blocks and cannot be written to. LUN 0, LUN 1, and LUN 4 each provide three good blocks for block 810, and any one of LUN 0, LUN 1, or LUN 4 can be selected to provide a check block for block 810. For example, LUN 0 is chosen to provide the check block for block 810.

[0117] Figure 9 This is a flowchart for selecting a large block for verification according to another embodiment of this application.

[0118] See also Figure 7 , Figure 8A and Figure 8B ,according to Figure 9 In this embodiment, the LUN of the NVM chip in the solid-state storage device comprises multiple planes. Implementation is based on... Figure 9 The process of an embodiment is to determine the location of the check block for the large block.

[0119] according to Figure 9 In one embodiment, the control unit of the solid-state storage device couples multiple NVM chips through multiple channels. The number of NVM chips coupled to each channel differs, or the number of dies / LUNs coupled differs. Some channels (denoted as channel CHn) have a greater number of NVM chips / dies / LUNs coupled than others. Priority is given to providing large blocks of parity data from the NVM chips / dies / LUNs coupled to channel(one or more) of channel CHn, such that large blocks of parity data are stored in the NVM chips / dies / LUNs coupled to channel CHn, while smaller blocks of user data are stored, thereby reducing the amount of data to be transferred when large blocks are accessed.

[0120] See Figure 9 By identifying the number of NVM chips / dies / LUNs coupled to each channel of the solid-state storage device, one or more channels (denoted as channel CHn) are identified as the ones to be prioritized for providing parity blocks. For example, one or more channels (CHn) with the largest number of coupled NVM chips / dies / LUNs are selected. For a specified block C, the number of good blocks that the LUN on each of one or more channels (CHn) can provide for block C is obtained (910). If the number of good blocks that the LUN (denoted as Ln) on one of the one or more channels (CHn) can provide for block C is equal to the maximum number of good blocks that each of all LUNs that provide physical blocks for block C can provide (920), then LUN (Ln) is selected to provide parity blocks for block C (950), and the location of the parity block in the block's metadata is marked as the physical block provided by the LUN (Ln) of channel (CHn).

[0121] The number of good blocks provided by a LUN for a large block depends on the number of good blocks of the physical blocks provided by the LUN for the large block. For example, for a LUN including 4 planes (see Figure 7 ), the physical blocks provided by the LUN for a specified large block are either good blocks or bad blocks in each plane. Alternatively, the number of good blocks of the physical blocks with the same block address from each of the multiple planes determines the number of good blocks of the physical blocks provided by the LUN for the large block. See Figure 8A , among the multiple LUNs constituting the large block 800, the LUN 4 provides the largest number of good blocks for the large block 800; among the multiple LUNs constituting the large block 810, the LUN 0, the LUN 1 and the LUN 4 provide the largest number of good blocks for the large block 810.

[0122] Referring back to Figure 9 , at step 920, if the number of good blocks provided by any LUN of the one or more channels (CHn) for the large block C is less than the largest number of good blocks provided by each of all the LUNs providing physical blocks for the large block C, then a LUN (denoted as LUNx) providing a check block for the large block C is selected from the LUNs of the dies on other channels than the one or more channels (CHn) (930), the LUNx being capable of providing the largest number of good blocks for the large block C. And one or more physical blocks provided by the LUN of the one or more channels (CHn) for the large block C are marked as bad blocks (whether naturally bad blocks or artificially marked bad blocks) (940). Thus, for any large block, the number of LUNs providing data blocks for the large block among the LUNs providing physical blocks for the large block on the one or more channels (CHn) is less than the number of LUNs on the channels (CHn).

[0123] According to embodiments of the present application, data is written to large blocks consecutively, so that the data consecutively written to the solid state storage device is distributed consecutively on the large blocks. When responding to random read of data, the read data is randomly distributed in the NVM chips of the solid state storage device. Thus, when responding to random read of data, the parallelism of the NVM chips / dies / LUNs can be fully exploited. When responding to consecutive read of data, the data to be read out is distributed in multiple physical blocks of a large block, and even if the data is read out from multiple or all physical blocks of the large block simultaneously, the channels (CHn) will not become a performance bottleneck due to the check data set on the channels (CHn) because of too much data to be read out.

[0124] According to embodiments of the present application, there is also provided a solid state storage device including a controller and a non-volatile memory chip, wherein the controller performs any of the processing methods provided by embodiments of the present application.

[0125] According to the embodiments of the present application, a program stored on a readable medium, when executed by a controller of a solid state storage device, causes the solid state storage device to perform any of the processing methods provided by the embodiments of the present application.

[0126] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to encompass within their scope all possible variations and modifications of the preferred embodiments. It is apparent that those skilled in the art can, without departing from the spirit or scope of the application, make various changes and modifications of the application. Thus, the application is intended to encompass all such changes and modifications as fall within the scope of the claims, together with all equivalents thereof.

Claims

1. A solid-state storage device, characterized in that, This includes a control unit coupled to an NVM chip via multiple channels; each channel couples to one or more NVM chips, and the NVM chip includes one or more logic units, each of which provides a physical block for a larger block. For any large block, the number of logic units provided by one or more first-channel coupled NVM chips is greater than the number of logic units provided by one or more second-channel coupled NVM chips; The first large verification block is provided by the NVM chip coupled to the first channel; If the first channel provides one or more naturally generated bad blocks in the physical blocks of the first large block, then there is no need to manually mark the available physical blocks as bad blocks; If there are no naturally generated bad blocks in the physical blocks provided by the first channel for the first large block, then one or more available physical blocks will be manually marked as bad blocks; By marking bad blocks, the number of physical blocks in the first channel that can be used as the first large data block is not greater than the number of physical blocks in the second channel that can be used as the first large data block.

2. The solid-state storage device as described in claim 1, characterized in that, One or more physical blocks of the NVM chip in the first channel meet the conditions for constructing the first large block, but are not used to construct the first large block.

3. The solid-state storage device as described in claim 1, characterized in that, The logic unit comprises multiple planes. Among the multiple logic units that provide physical blocks for the first block, the first logic unit that provides the most good physical blocks for the first block is selected to provide the check block for the first block.

4. The solid-state storage device as described in claim 3, characterized in that, If the first logical unit does not belong to the first channel, the physical block provided by the first channel for the first large block is set as a bad block.

5. The solid-state storage device as described in any one of claims 1 to 4, characterized in that, The number of NVM chips coupled to one or more first channels is greater than the number of NVM chips coupled to one or more second channels.

6. The solid-state storage device as described in any one of claims 1 to 4, characterized in that, Multiple NVM chips coupled to one or more channels have different numbers of logic units.

7. The solid-state storage device as described in claim 1, characterized in that, The first large verification block is provided by the NVM chip coupled to the first channel; The second large verification block is provided by the NVM chip coupled to the second channel; as well as One or more physical blocks provided by the NVM chip in the first channel for the second block are not used.

8. A method for selecting a check block for a large block, characterized in that, include: For any large block, the first channel that provides the most logical units from multiple channels selects the first logical unit that provides the check block for the first large block, and selects the physical block provided by the first logical unit for the first large block as the check block for the first large block; If the first channel provides one or more naturally generated bad blocks in the physical blocks of the first large block, then there is no need to manually mark the available physical blocks as bad blocks; If there are no naturally generated bad blocks in one or more physical blocks provided by the first logic unit for the first large block, then at least one of the one or more physical blocks provided by the first logic unit for the first large block will be manually marked as a bad block. By marking bad blocks, the number of physical blocks in the first channel that can be used as the first large data block is not greater than the number of physical blocks in the second channel that can be used as the first large data block.

9. The method for selecting a check block for a large block as described in claim 8, characterized in that, Select one or more physical blocks provided by the first logical unit for the first large block as the check blocks of the first large block.

10. The method for selecting a check block for a large block as described in claim 8 or 9, characterized in that, The location of the identified check block is recorded in the metadata of the large block.

11. The method for selecting a check block for a large block as described in claim 8, characterized in that, If one or more physical blocks provided by the first logic unit for the first large block are bad blocks, mark the first large block to use one or more other physical blocks provided by the first logic unit for the first large block.

12. The method for selecting a check block for a large block as described in claim 8, characterized in that, By marking bad blocks, the number of physical blocks in the first channel that can be used as the first large data block is not greater than the number of physical blocks in the second channel that can be used as the first large data block.

13. The method for selecting a check block for a large block as described in claim 8, characterized in that, When writing data to large blocks, do not write data to marked bad blocks.

14. The method for selecting a check block for a large block as described in claim 8, characterized in that, When performing error checking on large blocks, avoid marked bad blocks.

15. A method for selecting a check block for a large block, characterized in that, include: For any large block, obtain the number of good blocks provided by each logical unit on one or more channels for the first large block; If the number of good blocks provided by the first logic unit on the first channel of one or more channels for the first large block is equal to the maximum number of good blocks that each of all logic units that provide physical blocks for the first large block can provide for the first large block, and the number of logic units in the first channel is greater than the number of logic units in the second channel of one or more channels; The first logical unit is selected to provide a check block for the first large block; If the number of good blocks provided by the first logic unit for the large block is less than the maximum number of good blocks, a logic unit from another channel different from the first channel is selected to provide a check block for the first large block; If the number of good blocks that the first channel can provide for the first large block is greater than the number of good blocks that the second channel can provide for the first large block, mark one or more good blocks that the first channel can provide for the first large block as bad blocks; If the first channel provides one or more naturally generated bad blocks in the physical blocks of the first large block, then there is no need to manually mark the available physical blocks as bad blocks; If there are no naturally generated bad blocks in the physical blocks provided by the first channel for the first large block, then one or more available physical blocks will be manually marked as bad blocks; By marking bad blocks, the number of physical blocks in the first channel that can be used as the first large data block is not greater than the number of physical blocks in the second channel that can be used as the first large data block.

16. The method for selecting a check block for a large block as described in claim 15, characterized in that, Also includes: If the number of good blocks that the first channel can provide for the first large block is greater than the number of good blocks that the second channel can provide for the first large block, mark one or more good blocks that the first channel can provide for the first large block as bad blocks.

17. The method for selecting a check block for a large block as described in claim 15, characterized in that, Also includes: Mark one or more good blocks that the first channel can provide for the first large block as bad blocks, such that the number of good blocks provided by the first channel for the first large block is no greater than the number of good blocks provided by the second channel for the first large block.

18. The method for selecting a check block for a large block as described in any one of claims 15 to 17, characterized in that, The number of good blocks a logic unit provides for a large block depends on the number of good blocks in the physical blocks provided for a given large block in each plane of the logic unit.

19. The method for selecting a check block for a large block as described in any one of claims 15 to 17, characterized in that, The logical unit provides physical blocks with the same block address as the large block.

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