Method and bus node for controlling a serial data bus system

Abstract

The present invention relates to a bus node, which can implement the method for allocating bus addresses to bus nodes of a serial data bus system according to the present invention. The method for allocating bus addresses to bus nodes of a serial data bus system is implemented in an allocation period by means of a bus shunt resistor (R2) in each bus node (SL1, SL2, SL3) of the data bus system. After the implementation of the method for allocating bus addresses to bus nodes of a serial data bus system in an allocation period, an operation period follows. The bus node has such a bus shunt resistor (R2). The bus node is characterized in that it has a bus shunt jumper switch (S4), which is opened before the bus address is allocated to the bus node in the allocation period, the bus shunt jumper switch is closed after the bus address is allocated to the bus node in the allocation period, and the bus shunt jumper switch is closed in the operation period.

Description

[0001] This application claims the benefit of German application number DE 10 2017 128 923.2 filed on December 5, 2017 and European application number EP 17210861.5 filed on December 28, 2017, which are hereby incorporated by reference in their respective entireties. Technical Field

[0002] The invention relates to a method for controlling a serial data bus system and to a bus node for such a data bus system.

[0003] The invention generally relates to a self-testable serial data bus system and to a method for allocating bus node addresses within such a serial data bus with a chain of bus nodes or to a method and a device in connection with the addressing preparation of bus nodes. Background Art

[0004] Various methods for address assignment in LIN bus systems are known from the prior art, see for example DE-B-10 2010 026 431, DE-B-10 147 512, EP-B-1 490 772 and US Pat. No. 9,331,866.

[0005] All these documents have in common that the number of bus nodes (hereinafter referred to as addressed bus nodes) that can be addressed by the bus master is limited, because each bus node introduces a specified current into the bus during the automatic addressing process. Here, in each addressed bus node, a shunt resistor (bus shunt) is inserted into the single-wire data bus, on which the current causes a voltage drop on its path to the bus master, in which the current sink is effective during the address allocation process. The addressed bus node closest to the bus master records a higher voltage drop as an addressed bus node arranged away from the bus master. The voltage on the bus shunt is compared with a threshold value. If the threshold value is exceeded, the relevant bus node that exceeds the threshold value on its bus shunt can be considered that it is not recognized by the bus master as the last bus node in the addressing bus node chain. It then cuts off its current source and waits for the next initialization run.

[0006] The addressed bus node, which is the last bus node in the bus node chain counting from the bus master, does not switch off its power supply. After a predetermined initialization time has elapsed, the bus node can be considered to be the last bus node to be addressed in the addressed bus node chain. It then accepts the bus node address transmitted by the bus master and does not participate in further initialization processes until the received bus node address is declared invalid by a reset command or another reset condition.

[0007] The problem is that, first, the bus shunt resistance must be as small as possible. Second, it must be possible to address as many addressable bus nodes as possible. Third, the addressing system must be able to operate with a negative ground offset. Fourth, the voltage level on the bus shunt must be maximized, which requires the largest possible addressing current. Fifth, the total current that must be absorbed by the bus master during the address assignment process must not exceed a predefined value, which is currently 40 mA for the LIN bus.

[0008] DE-B-10 2010 026 431 discloses a method according to which the individual addressed bus nodes do not operate with a constant addressing current as in DE-B-10 147 512 and EP-B-1 490 772, but the addressing current rises continuously or in a trapezoidal manner until the threshold value of the previous bus node is exceeded. This has many disadvantages: First, this leads to a long rise time when there are many addressed bus nodes. However, the time for automatic addressing is limited. It is therefore necessary to shorten the time until the addressed bus node farthest from the bus master and not yet addressed is addressed. DE-B-10 2010 026 431 therefore does not completely solve the problem of being able to address many addressed bus nodes and being able to further reduce the resistance value of the bus shunt resistor sufficiently. In addition, the technical teaching disclosed in DE-B-10 2010 026 431 does not lead to self-testing capabilities.

[0009] Another disadvantage of DE-B-10 2010 026 431 is that, for reasons of robustness, a certain level range must also be opened here in order to prevent the master from being overloaded or addressing errors. In order to reduce the bus shunt resistance and to create comfort with the LIN bus, it is therefore beneficial to maximize the DC component in the addressing current. However, according to the technical teaching disclosed in DE-B-10 2010 026 431, this value fluctuates around the addressing current level value. As a result, the available addressing current level is unnecessarily reduced.

[0010] DE-B-10 256 631, EP-B-1 603 282, US-B-7 590 140, EP-B-1 490 772 and EP-B-1 298 851 disclose bus node addressing methods which require a bus shunt resistor (R2) within each automatically addressed bus node (SL1, SL2, SL3). This resistor has the disadvantage that it deteriorates the EMC behavior compared to standard-compliant LIN bus nodes. Summary of the invention

[0011] The object of the present invention is therefore to provide a solution which does not have the above-mentioned disadvantages of the prior art and has further advantages.

[0012] Automatic addressing methods for serial data bus systems in particular require that a current measuring device (usually in the form of a shunt resistor) be connected to the bus, specifically for each addressable addressable bus node (see, for example, EP-B-1 490 772, EP-A-2 571 200 and EP-A-2 654 246). The current measuring device is only required during the addressing phase. It is therefore advantageous that the current measuring device no longer plays a role in the normal operation of the data bus system.

[0013] In the sense of the present invention, a "bus line" refers to both a single-core bus and a dual-core bus, the latter of which can be designed and operated differentially. A "bus node" refers to the connection hardware of a bus participant, via which the bus participant is connected to the bus line. A bus node thus also includes, for example, a bus transceiver, but in particular the pull-up resistors (which can also be understood as static current sources) that are usually present, and, if necessary, switches (if necessary with a control unit), with which the bus participants can connect the bus to ground. As long as the bus node is not a standard bus node, but an addressable addressable bus node, within the scope of the present invention, the bus node also includes hardware for feeding in an addressing current with an associated current measuring unit and a current detection unit, as will be described later.

[0014] According to a further aspect, the invention relates to a method for controlling a serial data bus system, wherein in the method:

[0015] - in the addressing phase, an address is assigned to each addressed bus node when the jumper switch is open;

[0016] During the operating phase, the current measuring device of each addressed bus node is bridged by closing the bridge switch.

[0017] According to the invention, a jumper switch is therefore provided for each current measuring device, which jumper switch, like the current measuring device, advantageously belongs to the addressed bus node and is controlled by the addressed bus node depending on whether the relevant addressed bus node has been addressed. If the addressed bus node has not yet been addressed, the jumper switch is open. The addressed bus node that has already been addressed controls the jumper switch so that it is now closed and thus jumpers the current measuring device.

[0018] In a first embodiment of the invention, it can be provided that the addressing phase has a plurality of addressing cycles, wherein each addressing cycle assigns an address to an unaddressed or not yet addressed addressing bus node, and the addressed bus node addressed within an addressing cycle no longer participates from that point on in the subsequent address assignment for other not yet addressed addressing bus participants, wherein the current measuring device assigned to the addressed addressing bus node in the addressing phase is bridged by closing a bridge switch connected in parallel with the current measuring device.

[0019] According to the invention, it is thus possible to close the jumper switch as soon as the addressed bus node has received its address. If, therefore, multiple addressed bus nodes to be addressed are addressed in the addressing phase, and thus multiple addressing cycles are running in the addressing phase, one of the jumper switches that is still open can be closed after each addressing cycle. Alternatively, it is possible for the individual current measuring devices to be bridged or short-circuited individually only after the end of the addressing phase. Thus, during the addressing phase, all current measuring devices are "active", which is advantageous because then the same "situation" always exists on the bus line during the addressing phase, i.e., all current measuring devices are always connected to the bus line.

[0020] In another advantageous design of the present invention, it can be provided that, in the addressing phase, each unaddressed or not yet addressed addressed bus node feeds an addressing current flowing to the bus master into the bus line, and the addressing current flows through the current measuring device of the relevant unaddressed or not yet addressed addressed bus node.

[0021] In relation to the aforementioned aspects of the invention, the invention also covers an addressed bus node for a serial data bus system with a bus master connected to a bus line and with a plurality of bus nodes connected successively to the bus line, some of the bus nodes being addressed bus nodes and other bus nodes being designed as standard bus nodes with predefined addresses, wherein the addressed bus node is configured to have its address assigned by the bus master and has:

[0022] - a current measuring device that can be connected to the bus line;

[0023] - a jumper switch connected in parallel with the current measuring device;

[0024] - an addressing current source for feeding an addressing current into the bus line to the bus master; and

[0025] a control unit for controlling the jumper switch, wherein the control unit controls the jumper switch to an open state in an addressing phase of the data bus system for address assignment and controls the jumper switch to a closed state in an operating phase of the data bus system after the addressing phase.

[0026] An alternative to the addressing bus node according to the invention can be that the current measuring device detects in particular the addressing current fed into the bus line by the addressing current source. Such an addressing bus node is thus suitable, for example, for an addressing method in which the addressing current is immediately detected, which each addressed bus node which has not yet been addressed feeds into the bus line. The current flowing on the bus line at the level of the addressed bus node thus also contains as a part the addressing current fed in by the relevant addressed bus node. Such an addressing method will be described in more detail below.

[0027] A variant of the invention relates to a method for controlling a serial data bus system, wherein the data bus system is provided with:

[0028] bus lines;

[0029] a bus master connected to the bus line; and

[0030] A plurality of bus nodes serially connected to the bus line; wherein the plurality of bus nodes:

[0031] having at least two addressable bus nodes which receive addresses in an addressing phase; and

[0032] There is no or at least one standard bus node with a defined address;

[0033] The method comprises: an addressing phase for assigning an address to at least one of the two addressable bus nodes, and an operating phase for operating the data bus system after the end of the addressing phase;

[0034] wherein in an addressing phase at least two of the plurality of bus nodes feed a respective current into the bus line which flows to the bus master, and wherein the plurality of bus nodes:

[0035] A first bus node is connected to the bus line at a position upstream of and closest to the bus master,

[0036] having a last bus node connected to the bus line at a position upstream of and farthest from the bus master; and

[0037] There is no or at least one intermediate bus node which is connected to the bus line between the first bus node and the last bus node;

[0038] Each of the at least two addressable bus nodes receives an address assigned by the bus master during an addressing phase and has a current measuring circuit accessible into the bus line and a controllable jumper switch connected in parallel with the current measuring circuit, and

[0039] Each of the standard bus nodes, if any, has a respective address which is determined before the addressing phase is carried out,

[0040] - wherein in the method:

[0041] In the addressing phase, in the open state of the jumper switch, an address is assigned to each addressable bus node; and in the operating phase, the current measuring circuit of each addressed addressable bus node is bypassed by closing the jumper switch.

[0042] In a variant of the method, the addressing phase has a plurality of addressing cycles and, for each addressing cycle:

[0043] Assigning an address to each of the addressable bus nodes that has not yet been assigned an address; and

[0044] After the address assignment, this addressable bus node no longer participates in the subsequent address assignment for other addressable bus nodes that have not yet been addressed in the remainder of the addressing phase, and, after the address assignment, the current measuring circuit is bypassed for this addressable bus node by closing a jumper switch connected in parallel with the current measuring circuit.

[0045] In another embodiment of the present invention, during the addressing phase, each addressable bus node that has not yet been assigned an address during the addressing phase feeds its own addressing current flowing to the bus master into the bus line, wherein the corresponding addressing current flows through the current measuring circuit of the corresponding addressable bus node that has not yet been assigned an address.

[0046] Finally, a variant of the invention provides an addressable bus node for a serial data bus system, wherein the bus system has:

[0047] bus lines;

[0048] a bus master connected to the bus line; and

[0049] A plurality of bus nodes serially connected to a bus line, wherein the plurality of bus nodes:

[0050] having at least two addressable bus nodes which receive addresses assigned by the bus master in an addressing phase; and

[0051] There are no or at least one standard bus node with a correspondingly assigned address; the addressable bus nodes having:

[0052] A current measurement circuit that can be connected to the bus line;

[0053] a jumper switch connected in parallel with the current measuring circuit;

[0054] an addressing current source for feeding an addressing current flowing into the bus master into the bus line; and

[0055] a control unit for controlling the jumper switch;

[0056] The control unit controls the jumper switch to be in an open state during an addressing phase of the data bus system for assigning addresses, and controls the jumper switch to be in a closed state during an operating phase of the data bus system after the addressing phase.

[0057] In such an addressable bus node, a current measuring circuit can detect the addressing current fed into the bus line by the addressing current source.

[0058] The present invention also recommends a method for allocating addresses in a serial data bus system, wherein the data bus system has a bus master and a bus node, and wherein on the one hand, the bus master is connected to the bus line and on the other hand, the bus nodes are connected to the bus line one after another. At least some of the bus nodes feed the current flowing to the bus master into the bus line respectively. One of the bus nodes is the first bus node connected to the bus line closest to the bus master, and the other bus nodes upstream of the first bus node are connected to the bus line. In other words, one of the bus nodes is the last bus node connected to the bus line farthest from the bus master, and the other bus nodes downstream of the last bus node are connected to the bus between the bus node and the bus master. At least two of the bus nodes are addressed bus nodes, wherein the bus master assigns the addresses to the addressed bus nodes accordingly in the addressing phase, and the other bus nodes can be standard bus nodes with addresses that have been determined before the execution of the addressing phase.

[0059] For serial data bus systems, such as the LIN bus, a motivation for a modified automatic addressing will be briefly presented below, specifically using the LIN bus as an example.

[0060] The bus current during LIN bus operation must be below a maximum value. If this maximum value is exceeded, this indicates a short circuit to ground on the bus, which must be detected.

[0061] During normal operation of the LIN bus, a so-called base current flows in the bus. This base current serves, for example, to stabilize the bus and to make the bus less sensitive to, for example, electromagnetic interference influences.

[0062] During automatic addressing of the LIN bus nodes, they feed in the addressing current. Depending on how many bus nodes to be addressed are connected to the bus, the maximum bus current load could be exceeded if the addressing current were fed in via all bus nodes. Automatic addressing would then no longer be possible.

[0063] For LIN bus applications, in the past people therefore resorted to inserting a so-called preselection phase, in which not all bus nodes are addressed, but only a group of bus nodes, the size of the group being selected so that the maximum current load of the bus is not exceeded when all bus nodes of this group are fed with addressing current.

[0064] In LIN applications, shunt resistors in the bus are disadvantageous. Efforts are made to select these resistors as small as possible, for example in order to reduce losses or to avoid other network problems.

[0065] However, if the resistors are now designed to be smaller, the voltage drop will also be reduced, ie the measurement signal which must then be amplified is reduced. This involves additional hardware.

[0066] In order to increase the measurement signal, or rather increase it without amplification, the addressing current is increased. This increases the risk that the automatic addressing will run into the maximum current limit of the bus.

[0067] According to the invention, the addressable participant has a bus node with a transceiver, i.e., it has hardware connected to the bus line and additionally has a unit for feeding in an addressing current and for measuring the addressing current on the bus line. From the perspective of the bus master, the current feeding is located on the bus line after a shunt resistor which is also located on the bus line.

[0068] It is assumed that the bus system has a mixed structure of addressable bus nodes and non-addressable standard bus nodes. Standard bus nodes have fixed addresses and do not participate in the automatic addressing process. In order to stabilize the bus line and to observe a uniform generation of the bus potential along the length of the bus line, all bus nodes, that is, both standard bus nodes and addressed bus nodes, input a quiescent current into the bus line or can feed this quiescent current. During the automatic addressing phase, not every standard bus node and / or addressed bus node must forcibly feed this bus current. Each addressed bus node first detects the basic current as the sum of all quiescent currents fed in by the standard bus nodes and the addressed bus nodes behind it. The maximum bus current is now specified, which is a certain degree lower than the current value below, at which the bus master recognizes an error situation (e.g. a bus short circuit) and pulls the bus to ground.

[0069] The addressed bus nodes now all respectively feed in an addressing current, but this is not fed in suddenly. The bus node located furthest away from the bus master measures "its" own addressing current and other currents that can be fed in by bus nodes that are connected further away from the bus master than the observed bus node of the bus line.

[0070] Thus, while the addressing currents of all addressed bus nodes that have not yet been addressed slowly increase, one of the addressed bus nodes close to the bus master detects that "a predetermined maximum bus current has been reached". This addressed bus node then causes its addressing current source to decrease, more precisely, preferably more quickly than it had previously increased it. The other addressed bus nodes that have not yet been addressed cause their addressing current sources to continue to increase until another addressed bus node close to the bus master detects that "the maximum bus current may have been reached". This addressed bus node then also reduces its addressing current source.

[0071] This leads to a "chain reaction" until at the end only the last addressed bus node, that is, the addressed bus node that has not yet been addressed and is arranged farthest from the bus master, has caused its addressing current source to rise to a certain extent until the maximum bus current is measured by itself. The addressed bus node thus "knows" that it is now identified. This is because, after the addressing cycle ends, the node is the only node whose addressing current source provides the addressing current. If the address is now placed on the bus line, the addressed bus node will accept the address as its own address. Alternatively, in advance, the address can be sent from the bus master to all the addressed bus nodes that have not yet been addressed, so that now one of the addressed bus nodes accepts the address as its own address, and other addressed bus nodes that have not yet been addressed will abandon the bus address.

[0072] For a hybrid structure, the above method works particularly advantageously when the standard bus nodes are located only behind the addressed bus nodes that are arranged farthest from the bus master. Because the addressed bus node can then detect the sum of the quiescent currents fed by these standard bus nodes as the total quiescent current. If the standard bus node is arranged between the bus master and the first addressed bus node, this addressed bus node and the other addressed bus nodes arranged behind it do not know how large the basic current consisting of the quiescent current is, because they cannot measure the quiescent current of the standard bus node. This situation can be overcome in that each addressed bus node receives information about "how many standard bus nodes are located between the addressed bus node group and the bus master".

[0073] On the contrary, a mixed structure designed in such a way that standard bus nodes and addressed bus nodes alternately follow one another can be tolerated. If then the last bus node arranged furthest from the bus master is an addressed bus node, then only this bus node will necessarily receive information about how many standard bus nodes are connected to the bus line before it.

[0074] The method according to the invention is used for assigning addresses to addressed bus nodes, wherein according to the method,

[0075] - the bus nodes feed a quiescent current into the bus line or have the possibility of feeding a quiescent current into the bus line or - alternatively - some standard bus nodes and / or some addressed bus nodes feed a quiescent current into the bus line, while other standard bus nodes and / or addressed bus nodes do not feed a quiescent current into the bus line;

[0076] - Each addressed bus node which has not yet been addressed feeds an addressing current into the bus line;

[0077] - each addressed bus node which has not yet been addressed detects the bus current flowing through it by means of a current measuring device as the sum of the quiescent currents of all bus nodes arranged upstream (i.e. the quiescent currents of both the addressed bus nodes or the quiescent currents of the addressed bus nodes which have not yet been addressed and the standard bus nodes which, if applicable, also each feed a quiescent current into the bus line) and its own addressing current and the addressing currents of all addressed bus nodes which have not yet been addressed and are arranged upstream;

[0078] - determining a maximum permissible maximum addressing current during the addressing phase, which together with the sum of all fed-in quiescent currents results in a maximum permissible maximum bus current which is less than the bus current flowing into the bus master in which, for example, an error situation, a bus short circuit, is detected in the bus master (in other words, the maximum addressing current is determined as the difference between the bus current flowing into the bus master in which an error situation (e.g. a bus line short circuit) is detected and the sum of the quiescent currents of all bus nodes (which may be standard bus nodes and / or addressed bus nodes) which each feed a quiescent current into the bus line);

[0079] - in the addressing phase, a plurality of addressing cycles, each lasting a predetermined duration, are executed in order to identify each addressed bus node which has not yet been addressed, wherein an addressed bus node identified in an addressing cycle no longer participates in a subsequent addressing process in that it behaves, for example, like a standard bus node;

[0080] - For each addressing cycle,

[0081] - at the beginning, each addressed bus node which has not yet been addressed feeds an addressing current into the bus line which increases at a rising rate,

[0082] - during the addressing phase, each addressed bus node which has not yet been addressed measures the bus current flowing through it and compares it with the maximum bus current and, if the maximum bus current is exceeded, reduces the addressing current it feeds into the bus line at a decreasing rate, or, each addressed bus node which has not yet been addressed measures the addressing current it feeds into the bus line and compares it with the maximum addressing current and, if the maximum addressing current is exceeded, reduces the addressing current it feeds into the bus line at a decreasing rate, and

[0083] - at the end of the addressing cycle, there remains a single addressed bus node which has not yet been addressed, which feeds the maximum addressing current into the bus line and is thereby identified; and

[0084] - Assigning an address to the identified addressed bus node.

[0085] According to the invention, each addressed bus node that has not yet been addressed detects its own addressing current fed into the bus line. Each addressed bus node knows the maximum addressing current that is allowed. The addressed bus node close to the bus master will detect during the addressing phase or during the addressing cycle that the total current on the bus line is greater than the total current of those addressed bus nodes that are connected to the bus line away from the bus master and are still addressed. If now all the addressed bus nodes that have not yet been addressed each feed a rising bus current into the bus line, then one of the preceding addressed bus nodes, i.e., close to the bus master, in particular the first addressed bus node that has not yet been addressed, first "notices" that it must reduce the addressing current fed by it so that the maximum addressing current on the bus line is not reached or even exceeded. The addressed bus node that has not yet been addressed near the bus master eventually leads its addressing current to zero, and this process continues through the next addressed bus node that has not yet been addressed, until finally only one addressed bus node that has not yet been addressed feeds its entire addressing current into the bus line, and no bus line conducts a bus current greater than the maximum addressing current. Thus, at the end of the addressing cycle, there is only one single addressed bus node that has not yet been addressed and is in the aforementioned operating state. This now identified addressed bus node can now be assigned an address.

[0086] A major advantage of the method according to the invention is that at the beginning of the addressing phase the maximum permissible addressing current which can be fed into each addressed bus node which has not yet been addressed is determined. This addressing current is the same for all addressed bus nodes. The comparison of the current flowing in the bus line with the maximum addressing current is the same for each addressed bus node, which further simplifies the method according to the invention.

[0087] In an advantageous embodiment of the invention, provision can be made for as many addressing cycles to be carried out as there are addressable bus nodes connected to the bus line to be addressed.

[0088] A special case can be generated when only one addressed bus node has not yet been addressed. That is, then either another addressing cycle can be carried out, at the end of which it is indicated that precisely this addressed bus node that has not yet been addressed has been identified and can be addressed. However, it is also possible that when only one addressed bus node has not yet been addressed, no further addressing cycle is carried out, so that the bus master assigns its address to this last addressed bus node that has not yet been addressed, instead of this last addressed bus node that has not yet been addressed feeding an addressing current into the bus line.

[0089] In another advantageous embodiment of the invention, it can be provided that the addresses are assigned to the addressed bus nodes identified in the addressing cycle by assigning addresses to all not yet addressed bus nodes before or at the beginning of the addressing cycle or by assigning addresses at the end of the addressing cycle.

[0090] As already mentioned above, in each addressed bus node that has not yet been addressed, the addressing current is increased at a certain rate of increase, and the addressing current is reduced at a certain rate of decrease. In principle, it is applicable that the rate of decrease is selected to be greater than the rate of increase, wherein each addressed bus node that has not yet been addressed reduces its addressing current fed into the bus line at the rate of decrease when the maximum bus current or the maximum addressing current is exceeded, and each addressed bus node that has not yet been addressed feeds its addressing current into the bus line at the rate of increase until the said exceeding. The rate of increase and the rate of decrease are preferably defined by a first time constant (for the rate of increase) and a second time constant (for the rate of decrease). The smaller the time constant, the greater the corresponding rate of increase or rate of decrease. If during the addressing cycle an addressed bus node that has not yet been addressed notices that it must reduce its addressing current in order to maintain the maximum addressing current on the bus line, this is done significantly faster than the further increase of the addressing current fed into the bus line by other addressed bus nodes that have not yet been addressed. This is because, when one of the addressed bus nodes that has not yet been addressed reduces its addressing current, the other addressed bus nodes that have not yet been addressed may not have noticed anything yet, because they detect a bus current that is significantly smaller or smaller than the maximum addressing current due to the fact that they measure the other total currents on the bus line. As a result, these addressed bus nodes that have not yet been addressed still feed in their addressing current until the first of these other addressed bus nodes that have not yet been addressed also notices that the maximum addressing current load has been reached, so that as a result, it also reduces its addressing current. This complete process is expedient to reduce the addressing current at a significantly greater rate of reduction than the rate at which the addressing current rises. The first time constant, i.e., the rate of increase, is preferably at least 2 or 5 or 10 or 20 or 50 or 100 or 200 or 500 or 1000 times greater than the second time constant, i.e., the rate of reduction.

[0091] As an alternative or in addition to the foregoing, the first and / or second time constant can respectively depend on the size of the bus current drawn by the addressed bus node that has not yet been addressed, or depend on the size of the addressing current fed into the addressed bus node by the addressed bus node that has not yet been addressed, or be selected accordingly.

[0092] In a further advantageous design of the present invention, it can be advantageous if the first and / or second time constant is different depending on whether the bus current drawn by an addressed bus node that has not yet been addressed or the addressing current fed into the bus line by an addressed bus node that has not yet been addressed is greater than or equal to a threshold value or less than the threshold value, or alternatively is greater than a threshold value or less than or equal to the threshold value.

[0093] In the aforementioned alternative for selecting two time constants, it can also be provided that the first time constant will be greater or larger when starting from a threshold value or above the threshold value than when it is at or below the threshold value, and / or that the second time constant will be smaller or smaller when starting from a threshold value or below the threshold value than when it is at or above the threshold value.

[0094] As a result of the aforementioned variant scheme for selecting the time constant and for selecting the magnitude of the rate of decrease and the rate of increase relative to each other, it has thus been shown that the larger the maximum addressing current that is smaller than the maximum bus current is selected, the greater the multiple by which the second time constant or its maximum value is smaller than the first time constant or its maximum value.

[0095] In a further advantageous embodiment of the invention, in order to ascertain whether the address assignment has been carried out correctly, provision can be made for a check at the end of the last addressing cycle by means of a query on the part of the bus master to determine whether there is at least one addressed bus node which has not yet been addressed.

[0096] Furthermore, for the aforementioned purpose it can be advantageously provided that at the end of each addressing cycle, or at the end of at least some addressing cycles, and given knowledge of the number of addressed bus nodes to be addressed, and in particular at the end of the last addressing cycle, each addressed bus node which has not yet been addressed sends a corresponding notification to the bus master via an address assignment which has not yet taken place.

[0097] In a further embodiment of the invention, a plurality of addressing cycles can be carried out in the addressing phase until it is determined in an addressing cycle, in particular by the bus master, that no addressed bus node feeds an addressing current into the bus line or that the maximum addressing current is not fed into the bus line in any case.

[0098] In order to reduce possible errors in address allocation, it is also advantageous to check at the end of the addressing cycle whether there is an addressed bus node to be assigned an address which has not been previously addressed and / or to check at the end of the addressing cycle whether the addressed bus node identified for address allocation already has an assigned address.

[0099] If, alternatively, the number of bus nodes to be addressed and thus the number of addressing cycles to be performed is known before the start of the addressing phase, it is possible to check after the end of the addressing phase whether each addressed bus node has been assigned an address.

[0100] In a further advantageous embodiment of the invention, provision can be made for the relevant not yet addressed bus node to be identified as soon as it is determined during the addressing cycle, and thus possibly before the end of a predetermined duration of the addressing cycle, that "an as yet unaddressed addressed bus node feeds the maximum addressing current into the bus line". This has the advantage that interference influences, for example electromagnetic interference, which may still occur later during the addressing cycle can no longer influence the already completed identification process of the not yet addressed addressed bus node.

[0101] For carrying out the method according to the invention it can be advantageous if all standard bus nodes having addresses which have been determined before the addressing phase is carried out are connected to the bus line upstream of all addressed bus nodes.

[0102] Alternatively, it is possible that at least one standard bus node with an address which has been determined before the addressing phase is connected to the bus line downstream of an addressed bus node, which receives information about the number of standard bus nodes which are arranged downstream of the addressed bus node and thus knows the possible maximum value of the sum of the quiescent currents fed into the bus line by the standard bus node.

[0103] The invention also provides an addressable bus node for a serial data bus system, which has a bus master connected to the bus line and has a plurality of bus nodes connected successively to the bus line, some of which are addressable bus nodes and other bus nodes are designed as standard bus nodes with predefined addresses, wherein the addressable bus node is configured to have its address assigned by the bus master and has:

[0104] -Current measuring device;

[0105] an addressing current source for feeding an addressing current into the bus line and via the bus line to the bus master, specifically when detected by a current measuring device; and

[0106] a quiescent current source for feeding a quiescent current into the bus line and via the bus line to the bus master, wherein the quiescent current source may be identical to the addressing current source; and

[0107] - a control unit for increasing the addressing current provided by the addressing current source with a possibly variable rate of increase until a predeterminable maximum current is possibly exceeded, and for reducing the addressing current provided by the addressing current source with a possibly variable rate of reduction, in particular to zero, when the maximum value is possibly exceeded once.

[0108] In an advantageous embodiment of the invention, it can be provided that the current measuring device detects an addressing current of an addressing current source to be fed into the bus line and that the control unit compares the addressing current with a predefinable maximum addressing current.

[0109] In an advantageous further development of the invention, it can be provided that a current measuring device can be integrated into the bus line and detects the bus current, and the control unit compares the bus current with a predefinable maximum bus current.

[0110] According to the invention, it can be provided that the rate of increase is defined by a first time constant and the rate of decrease is defined by a second time constant, the first time constant being at least 2 or 5 or 10 or 20 or 50 or 100 or 200 or 500 or 1000 times greater than the second time constant.

[0111] In an advantageous embodiment of the invention, it can be provided that the first and / or second time constant is selected depending on the magnitude of the bus current drawn by an as-yet-addressed bus node or depending on the magnitude of the addressing current fed into the addressed bus node by an as-yet-addressed bus node.

[0112] In a further advantageous design of the present invention, it can be provided that the first and / or second time constant is different depending on whether the bus current obtained by an addressed bus node that has not yet been addressed or the addressing current fed into the bus line by an addressed bus node that has not yet been addressed is greater than or equal to a threshold value or less than the threshold value, or optionally is greater than a threshold value or less than or equal to the threshold value.

[0113] In an automatic addressing method for automatically assigning addresses to addressed bus nodes of a serial data bus system, it is advantageous if each addressed bus node to which an address is assigned can detect the bus current at its connection point to the bus line flowing through it by means of measurement technology, wherein the connection point bus current also contains its own addressing current fed in by the addressed bus node concerned. However, this presupposes that each bus node is correctly connected to the bus line when the serial data bus system is constructed, that is, is connected in the correct "orientation" to the bus line.

[0114] A further aspect of the invention therefore relates to a method for feeding an addressing current into a bus line of a serial data bus system, more precisely via an addressed bus node, wherein the data bus system has, in addition to a bus master and addressed bus nodes and optionally standard bus nodes, a bus line to which the bus master is connected on the one hand and to which the bus nodes are connected successively on the other hand. It applies within the scope of the invention that the bus line can have a single-core bus or a dual-core bus, which optionally operates differentially, i.e. with differential signals.

[0115] The method according to the invention is therefore used to detect the correct feeding of addressing currents into the bus lines of a serial data bus system by a bus node thereof, wherein according to the method

[0116] - the bus nodes feed a quiescent current into the bus line or have the possibility of feeding a quiescent current into the bus line or - alternatively - some standard bus nodes and / or some addressed bus nodes feed a quiescent current into the bus line, while other standard bus nodes and / or addressed bus nodes do not feed a quiescent current into the bus line;

[0117] - Each addressed bus node which has not yet been addressed feeds an addressing current into the bus line;

[0118] - each addressed bus node which has not yet been addressed detects the bus current flowing through it by means of a current measuring device as the sum of the quiescent currents of all bus nodes arranged upstream (i.e. the quiescent currents of both the addressed bus node or the quiescent currents of the respective addressed bus node which has not yet been addressed and the standard bus nodes which, if applicable, also each feed a quiescent current into the bus line) and its own addressing current and the addressing currents of all addressed bus nodes arranged upstream which have not yet been addressed;

[0119] - during the addressing phase, identifying individual bus nodes among these bus nodes by evaluating the addressing current fed into the addressed bus nodes which have not yet been addressed;

[0120] - an addressed bus node which has not yet been addressed feeds an addressing current into the bus line selectively at one of the two nodes, wherein the current measuring device is arranged between the two nodes; and

[0121] -For an addressed bus node that has not yet been addressed or in this addressed bus node that has not yet been addressed, the following node is selected for feeding the addressing current, for which the current measuring device detects the addressing current, or for which the current measuring device detects a test current, which is selectively fed into one of these nodes or successively into each node in order to obtain the following node, for which the current measuring device detects the test current.

[0122] By adopting the method of the present invention, it is ensured according to the present invention on the one hand that, independently of the exchange of the inputs and outputs of the addressed bus node, via which the bus node is connected to the serial data bus, the addressing current is always fed in such a way that the fed-in addressing current flowing towards the bus master in any case also flows through a current measuring device connected to the bus line or is detected by this current measuring device.

[0123] According to a first variant of the invention, each addressed bus node or at least some of the addressed bus nodes has two addressed current sources, which are each in operative connection with the bus line via a node. The current measuring device is now located between the two nodes, or the current measuring device itself is in operative connection with the bus line, more precisely with the section of the bus line located between the two nodes.

[0124] It is advantageous in terms of hardware costs if, according to another variant of this aspect of the invention, each addressed bus node or at least some of the addressed bus nodes has a unique addressing current source. According to this variant of the invention, it is then applicable that:

[0125] the addressing current flows into an input of a switching unit, which has two outputs, one of which is operatively connected to a node and the other of which is operatively connected to another node;

[0126] The switching unit transitions to a first switching position or is preset to the first switching position, in which the input of the switching unit is connected to one of its outputs;

[0127] - when an addressing current or a test current is fed in this first switch position of the switching unit, checking whether the current measuring device detects the addressing current or, alternatively, the test current;

[0128] - if the current measuring device detects an addressing current, or alternatively a test current, maintaining the first switch position;

[0129] If this is not the case, the switching unit switches to a second switching position in which the input of the switching unit is connected to its other output.

[0130] In connection with the detection according to the invention of the correct feeding of addressing currents via bus nodes of a serial data bus system, the invention also proposes an addressed bus node for a serial data bus system with a bus master connected to the bus line and with a plurality of bus nodes connected successively to the bus line, some of the bus nodes being addressed bus nodes and other bus nodes being designed as standard bus nodes with predefined addresses, wherein the addressed bus node is designed to have its address assigned by the bus master and has:

[0131] -Current measuring device;

[0132] an addressing current source for feeding an addressing current into the bus line and via the bus line to the bus master, specifically when detected by a current measuring device; and

[0133] a quiescent current source for feeding a quiescent current into the bus line and via the bus line to the bus master, wherein the quiescent current source may be identical to the addressing current source;

[0134] - a control unit for controlling at least an addressing current source in order to feed the addressing current into the bus line selectively via one of the two nodes;

[0135] - wherein the current measuring device is arranged between two nodes;

[0136] wherein the control unit has an analysis unit for detecting one of the two nodes for which the current measuring device detects the current when the addressing current or the test current is fed in; and

[0137] In this case, an addressing current is fed into the bus line via those nodes for which the current measuring device has already detected the addressing current or—as an alternative—has previously detected a test current.

[0138] According to a first variant of the addressable bus node of the present invention, the addressable bus node has a switching unit, which has an input terminal connected to an addressing current source and has two output terminals, one of which is connected to a node and the other is connected to another node, wherein the input terminal of the switching unit can be selectively connected to one of its output terminals or to the other of its output terminals, wherein the switching unit can transition to a switching position at the request of the control unit, in which switching position a current measuring device detects an addressing current flowing through the switching unit, or detects a test current.

[0139] According to another variant of the addressable bus node of the present invention, the addressable bus node has: a first and a second addressing current source, one of which is connected to one node and the other is connected to another node; a monitoring unit for obtaining at which of the two nodes the current measuring device detects the current when feeding in an addressing current or a test current, wherein the addressing current is to be fed into the bus line by the addressing current source connected to the node for which the current measuring device has already detected the current in advance when feeding in the addressing current or - alternatively - feeding in the test current.

[0140] For the purpose of orientation, the following directions on the data bus are first defined here: the viewing direction from a bus node means that all objects on the data bus between the bus node and the bus master are located before the bus node in question and are therefore located downstream of the bus node in question with respect to the direction of the current flowing to the bus master, and all objects between the bus node in question and the end of the data bus are located after the bus node and are therefore located upstream of the bus node in question with respect to the direction of the current. This definition applies throughout the present application.

[0141] In the following, an exemplary method for automatic address assignment is first described with reference to a standard-compliant LIN bus system. Starting from the end of this paragraph, the present invention will be described.

[0142] In contrast to the methods and devices of DE-B-10 147 512, EP-B-1 490 772 and US-B-9 331 866, according to the invention the resistance value of the bus shunt resistor can be reduced to a certain extent, so that compliance with the standard can be achieved again. The Local Intranet Network (LIN), also called LIN bus, is a serial communication system for networking sensors and actuators, i.e. a fieldbus. LIN is used where the bandwidth and diversity of CAN are not required. A typical application example is networking inside doors or seats of a car. The relevant standard is ISO-Standard 17987-1, "Road vehicles-Local interconnect network (LIN)-Part 1-7".

[0143] The basic idea of ​​the invention presented here by way of example is now to use the addressing current source for self-testing, thereby meeting the requirements of ISO 26262. For this purpose, in contrast to the technical teaching of DE-B-10 2010 026 431, the bus current flowing from the subsequent addressed bus node through the respective bus node is not measured, but rather the total current (i1, i2, i3) leaving the respective addressed bus node is measured, which total current consists of the addressing current and the bus current flowing from the subsequent, i.e. upstream, addressed bus node through the respective addressed bus node, which addressing current is fed into the data line in the respective addressed bus node by the addressing current source (Iq1, Iq2, Iq3) of the respective addressed bus node. This means in terms of construction that the bus shunt resistor (R2) of the corresponding bus node (SL1, SL2, SL3) is respectively arranged in front of the corresponding automatic addressing current source (Iq1, Iq2, Iq3), so that the own addressing current of the corresponding bus node must flow through the bus shunt resistor (R2) in order to reach the bus master (ECU), where it is connected to ground.

[0144] Furthermore, another aspect of the invention proposed here is that, contrary to all the aforementioned documents, during the address allocation process, from the output of each addressed bus node, the associated bus node (SL j ) of a substantially constant output current (i j ) is fed into the previous data bus towards the bus master (ECU).

[0145] A problem is the possible existence of standard bus nodes (CS1, CS2) which do not have automatic addressing capability in the sense of the present invention, i.e. have a pre-determined address. It is basically assumed within the scope of the present invention that a mixed construction is not carried out using addressable bus nodes with automatic addressing capability according to other automatic addressing methods. Standard bus nodes (CS1, CS2) without automatic addressing capability use their bus current sources (S1, R3, d1) to feed the bus current, the bus node basic current, into the data bus towards the bus master (ECU). These are preferably bus nodes (CS1, CS2) which exist only once in the data bus and can therefore be easily distinguished from each other visually by the installer based on their appearance, for example, during the assembly of a car. As a result, when these bus nodes are assembled, for example, in a car, no automatic addressing is required during their assembly. Each of these standard bus nodes (CS1, CS2) feeds a basic (static) current component into the data bus by means of a pull-up current source (S1, R3, d1) according to the LIN standard. These standard bus nodes (CS1, CS2) therefore jointly draw a maximum base current which can be estimated by addressable bus nodes with automatic addressing capability, referred to below as automatic addressable bus nodes, from the number of standard bus nodes without automatic addressing capability.

[0146] There are two extreme configurations with the aid of which the resulting problems can be described. In both extreme configurations, the number of standard bus nodes is maximized and the number of automatically addressable bus nodes with automatic addressing capability is minimized.

[0147] Configuration A:

[0148] In configuration A, all n standard bus nodes without automatic addressing capability are located behind, for example, only two automatically addressable bus nodes, which have automatic addressing capability according to the invention described here, as viewed from the bus master (ECU). The maximum number n of standard bus nodes behind two automatically addressable bus nodes with automatic addressing capability is then (n+2). max / I k Here, I max It is the maximum current value that the bus master (ECU) can have in the automatic addressing phase according to the ISO standard. Preferably, the maximum current value I max It is selected to be slightly smaller than the actual maximum current value of the bus master (ECU) in order to accommodate manufacturing fluctuations and operating parameter fluctuations. k ​is the upper limit of the bus node basic current value, which the entirety of all standard bus nodes without automatic addressing capability feeds into the data bus. Preferably, each standard bus node without automatic addressing feeds approximately the same bus node basic (quiescent) current into the data bus. Thus, at the input of the second automatically addressable bus node with automatic addressing capability, the standard bus node generates a maximum basic current I G =n*I k For automatic addressing via automatically addressable bus nodes with automatic addressing, a current range I is reserved for the maximum addressing current of each automatically addressable bus node. amax =2*I k . This current range for the maximum addressing current of each automatically addressing bus node can then be used for automatic addressing. To this end, these automatically addressing bus nodes can measure the basic current flowing through their corresponding bus shunt resistor (R2) in the pre-stage A, and then obtain the current range of the maximum addressing current of each automatically addressing bus node, which is then used for automatic addressing. This maximizes the voltage drops across the bus shunt resistor (R2). They can therefore be minimized. This is in contrast to DE-B-10 2010 026 431, which does not solve this problem.

[0149] Configuration B:

[0150] In configuration B, all n standard bus nodes without automatic addressing capability are located, as viewed from the bus master (ECU), in front of, for example, only two automatically addressing bus nodes which have automatic addressing capability according to the invention presented here. However, in contrast to configuration A, the automatically addressing bus node now has no information about the number of standard bus nodes that are located in front of it in the direction of the bus master (ECU), i.e. downstream of it. There is therefore the risk that, in combination with the basic current of all preceding bus nodes in the data bus that reaches the bus master, the maximum addressing current used by the automatically addressing bus node is too high, which can lead to false notifications. However, the maximum number n of standard bus nodes that can be located behind two automatically addressing bus nodes with automatic addressing capability is (n+2) max / I k Here, I max It is also the maximum current value that the bus master (ECU) can have during the automatic addressing phase. Preferably, the maximum current value I max Here, too, it is selected to be slightly smaller than the actual maximum current value of the bus master (ECU) in order to compensate for manufacturing fluctuations and operating parameter fluctuations. k ​is the upper limit value of the bus node basic current value, which the entirety of all standard bus nodes feeds into the data bus. Preferably, each standard bus node also feeds substantially the same bus node basic current into the data bus. At the input of the bus master (ECU), the standard bus node then generates a maximum basic current I G =n*I k For automatic addressing by the automatically addressing bus nodes behind them with automatic addressing, the addressing current (I a ), leaving only the current range 2*I k . However, subsequent automatically addressable bus nodes with automatic addressing capability cannot obtain information through this current range. Although this current range can be used for automatic addressing, the automatically addressable bus nodes with automatic addressing capability must now be notified by the bus master (ECU). This can happen as follows: the bus master notifies all bus nodes of the number of standard bus nodes by means of a message directed to all bus nodes, or notifies a suitable addressing current value in advance by means of such an instruction. It is thus possible to maximize the addressing current to the corresponding automatically addressable bus node.

[0151] Configuration C:

[0152] Configuration C is a mix of Configuration A and Configuration B.

[0153] The standard bus nodes are then located in the serial data bus before, i.e. downstream, and after, i.e. upstream, the automatically addressable bus nodes with automatic addressing capability. In this case, the bus master (ECU) only needs to communicate the number n of standard bus nodes located before the automatically addressable bus node. The automatically addressable bus nodes can thus refer to the subsequent bus nodes by measuring the basic current flowing through their bus shunt resistors and by comparing this basic current with n times the basic bus node current I k The total basic current is obtained by summing up the values ​​of . Alternatively, the bus master (ECU) can also transmit another value from which the basic bus current can be calculated. Based on this, each automatically addressing bus node can then calculate the maximum addressing current I amax and adjust it to maximum.

[0154] Before assigning bus node addresses, the bus master (ECU) therefore preferably signals all bus nodes "which of the above configurations exists, how many standard bus nodes without automatic addressing capability are present in the system, and / or how large the expected basic bus current is."

[0155] With the start of automatic addressing, the bus master (ECU) directs the data line to ground via a switch (SB) or the like. The current sink used for this purpose can absorb a maximum current value of Imax When the bus current flowing into the bus master (ECU) exceeds this value, the bus master (ECU) may identify a short circuit and generate a corresponding signal notification and error report. Therefore, in normal operation, the maximum current value I must not be exceeded. max .

[0156] Depending on the number of standard bus nodes and the maximum permissible bus current I specified in the standard max , so each bus node can calculate the maximum addressing current I still allowed by its corresponding addressing current source (Iq1, Iq2, Iq3) amax , without exceeding the maximum permissible addressing current (I max ). Preferably, this value is set in the corresponding automatically addressable bus node with automatic addressing capability by the number n received by the standard bus node without automatic addressing capability. In this case, preferably, a safety margin is also taken into account, so that the actually adjusted automatic addressing current I of the automatic addressing current source of the automatically addressable bus node (SL1, SL2, SL3) amax Less than the actual maximum allowable auto-addressing current.

[0157] Now it must be ensured that the maximum permissible bus current I max In contrast to DE-B-10 2010 026 431, in an automatically addressing bus node the base current and the addressing current from the subsequent bus node are not detected and the own addressing current source is not deactivated in the event of a deviation from the base current.

[0158] Specifically, the total current (i1, i2, i3) is detected, which leaves the respective automatically addressed bus node via the data bus towards the bus master (ECU). This total current consists of the bus current fed in from the subsequent automatically addressed bus node and, if applicable, the standard bus node plus the addressing current fed in itself.

[0159] For this purpose, the respective automatically addressed bus node (Sl1, SL2, SL3) measures the output bus current (i1, i2, i3) which comes from the subsequent automatically addressed bus node (Sl2, Sl3), flows through the bus shunt (R2) of the respective automatically addressed bus node (Sl1, SL2, SL3) and leaves it again at the output of the respective bus node towards the bus master (ECU). The respective automatically addressed bus node (SL1, SL2, SL3) now controls its own addressing current source (Iq1, Iq2, Iq3) so that the sum of the input bus current of the subsequent bus node (Sl2, Sl3) and the addressing current of its own addressing current source (Iq1, Iq2, Iq3) is equal to the predetermined total current (I s ). Addressing current (Ia ) is adjusted so that the maximum bus current I max The magnitude of the output bus current (i1, i2, i3) cannot be exceeded. As a result, the bus current (i1, i2, i3) leaving the respective bus node (SL1, SL2, S13) remains constant and does not rise above a maximum value through the respective bus node (SL1, SL2, S13). Overloading of the bus master current sink during the address assignment process is thereby avoided.

[0160] In this method, each automatically addressed bus node participating in the address assignment process thus detects an additional current which is different from the basic current. This additional current is composed of the own addressing current of the respective bus node and the addressing current of the bus nodes (addressed bus nodes and, if applicable, standard bus nodes) following the respective automatically addressed bus node (SL1, SL2, SL3).

[0161] In order to prevent the output current (i1, i2, i3) from overshooting and exceeding I max , the corresponding bus node adjusts its output current (i1, i2, i3) toward the bus master (ECU) so that it is always equal to the addressing current I amax The basic current is added to the prescribed maximum value. For this purpose, the addressing current sources (Iq1, Iq2, Iq3) are controllably designed within each automatically addressing bus node (SL1, S12, S13) with automatic addressing capability. The addressing current of the corresponding addressing current source (Iq1, Iq2, Iq3) then depends on the previously determined maximum value (I amax ), and on the other hand, depending on a control signal, the control signal is determined by means of a control path (F) and a measuring device (R2, D1) from an output current (i1, i2, i3) in the direction of a bus master (ECU) from a corresponding bus node (SL2).

[0162] The control path thus starts with a measuring device, preferably a bus shunt resistor (R2), which is arranged upstream of a bus node which, as viewed from the bus master (ECU), is connected to the data bus upstream of the respective bus node (SL1, SL2, SL3). There, the bus current is converted from the respective bus node to the bus master (ECU) into a voltage value. This voltage value is detected by a measuring device, such as an operational amplifier (D1), and, if necessary, after a filter (F), is converted into a control value, with which the respective automatic addressing current source (Iq1, Iq2, Iq3) can then be controlled, so that the bus current (i1, i2, i3) to the bus master (ECU) remains constant during this addressing phase.

[0163] In this case, within the respective bus node (SL1, SL2, S13), given a suitable design of the necessary control loop, a control variable, i.e. a control value, preferably as an output signal of the filter (F) is present. For simplicity, it is assumed here, for example, that the control variable is directly proportional to the respective output current (i1, i2, i3) of the respective automatically addressable bus node (S11, S12, S13) towards the bus master (ECU).

[0164] If the adjustment value always exceeds the predetermined threshold value (SW) after the predetermined initialization time has elapsed, the own addressing current source (Iq1, Iq2, Iq3) then supplies the predetermined output current to the bus master (ECU), and the corresponding automatically addressed bus node is the last bus node in the chain of automatically addressed bus nodes as viewed by the bus master (ECU). The relevant automatically addressed bus node then accepts the bus node address to be assigned, which was previously or subsequently transmitted by the bus master (ECU) to all automatically addressed bus nodes (SL1, SL2, S13), as its now valid bus node address, and no longer participates in the subsequent initialization process, unless the resulting bus node address is declared invalid by a reset command or another reset condition. Other automatically addressed bus nodes that do not yet have a valid bus node address participate in the subsequent initialization process.

[0165] Preferably, the output current value of the automatically addressing current source (Iq1, Iq2, Iq3) is controlled within the automatically addressing bus node (SL1, SL2, SL3), wherein filtering is performed by means of a filter (F). The control loop is preferably formed as a PI controller. This filtering is necessary so that no overshoot occurs when the addressing current is generated by all automatically addressing bus nodes (SL1, S12, S13) at the bus master (ECU). If this occurs, the maximum permissible bus current I max , the bus master (ECU) would detect a short circuit, which is to be avoided.

[0166] It is therefore advantageous and preferred if at least one low-pass filter (F) is accommodated in the control loop of each automatically addressable bus node (SL1, SL2, S13).

[0167] In another preferred embodiment of the present invention, the filter (F) is designed to be nonlinear. A first control time constant (τ) of the nonlinear filter (F) for increasing the addressing current of the corresponding addressing current source (Iq1, Iq2, Iq3) of the corresponding bus node (SL1, S12, S13) is 1) should preferably be greater than a second control time constant (τ) of the nonlinear filter (F) for reducing the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) of the respective bus node (SL1, SL2, SL3). 2 ). It has been shown that, when there are m automatically addressing bus nodes, the second time constant (τ) provided for reducing the addressing current of the corresponding addressing current source (Iq1, Iq2, Iq3) 2 ) shall be a first time constant (τ) defining the increase of the addressing current of the corresponding addressing current source (Iq1, Iq2, Iq3). 1 ). This results in the addressing current of the respective addressing current source (Iq1, Iq2, Iq3) of the respective bus node (SL1, SL2, S13) decreasing faster than increasing. As a result, the subsequent automatically addressed bus nodes adjust their addressing current downward faster than it is adjusted upward by other automatically addressed bus nodes. This ensures that the bus current remains constant during the addressing phase, but at least always below the maximum bus current value I max The simulation shows that the first time constant (τ 1 ) should be the second time constant (τ 2 ), preferably 10 times larger, preferably 100 times larger, the addressing current sources (Iq1, Iq2, Iq3) of the corresponding automatic addressing bus nodes (SL1, Sl2, Sl3) are adjusted upward with the first time constant, and the addressing current sources (Iq1, Iq2, Iq3) of the corresponding automatic addressing bus nodes (SL1, SL2, Sl3) are adjusted downward with the second time constant.

[0168] However, in conventional LIN buses, as already mentioned, there are also standard LIN bus nodes without automatic addressing capability according to the invention. These bus nodes supply a constant continuous current to the bus master (ECU) during the addressing phase. In contrast to other methods involving a base current, the threshold for identifying the last bus position of an automatically addressed bus node, which is to set the bus node address in the associated initialization process, can now be set very high.

[0169] After the automatically addressable bus node with automatic addressing capability has obtained a valid bus node address in this way, it uses its addressing current source, preferably like a bus node basic current source, and then acts like a bus node without automatic addressing capability. In the accompanying drawings, as a possible alternative, although separate bus node basic current sources (S1, R3, d1) in the automatically addressable bus nodes (SL1, SL2, SL3) are drawn. But they can be omitted. After the effective bus node address is assigned, this state of the automatically addressable bus node is preferably changed only by resetting the automatically addressable bus node or by canceling the validity of these bus node addresses. Therefore, in the next initialization process, the last automatically addressable bus node is observed from the bus master (ECU) to obtain a valid bus node address, and from then on it acts like a standard bus node, that is, it no longer participates in the subsequent automatic addressing process. In addition, the automatically addressable bus node that has not yet obtained a valid bus node address acts like an automatically addressable bus node. The initialization process is terminated. The bus master then triggers another initialization process, during which the automatically addressed bus node which was previously the second to last observed by the bus master (ECU) and which is now the last automatically addressed bus node observed by the bus master (acting as it does) receives a valid bus node address, etc. The initialization process is repeatedly triggered by the bus master (ECU) and in this initialization process a valid bus node address is assigned to the automatically addressed bus node which was observed by the bus master to act as it did last, which lasts for a period of time until all automatically addressed bus nodes have received a valid bus node address from the bus master (ECU). In order to determine this, the bus master (ECU) preferably checks after each initialization process whether the addressed automatically addressed bus node which should have received a valid bus node address responds. Preferably, the addressed automatically addressed bus node then sends a random number to the bus master (ECU) at the request of the bus master (ECU). If - for whatever reason - two automatically addressed bus nodes are valid, a bus conflict occurs. These bus conflicts can be detected by the bus nodes and signaled to the bus master (ECU). In some cases, the bus master (ECU) can also directly determine the bus conflict when the response can be predetermined. The bus master (ECU) can thus either directly or indirectly recognize the bus conflict and, if necessary, repeat the initialization of the relevant bus node address. For this purpose, it is advantageous if the bus master (ECU) can send a cancel command for the last assigned bus node address to all bus nodes.

[0170] During address assignment, the bus current flowing through the bus shunt resistor (R2) can now be checked for different conditions:

[0171] a) If the voltage drop across the bus shunt resistor (R2) is above the maximum voltage drop threshold, there is a short circuit in the subsequent data bus section behind the supply voltage. In this case, the relevant bus node preferably switches off all current sources in order to avoid damage to the system. However, the bus master (ECU) then usually also detects such a short circuit.

[0172] b) If the voltage drop across the bus shunt resistor is 0 V, the measurement input is usually short-circuited.

[0173] c) if the voltage drop across the bus shunt resistor (R2) is below the maximum voltage drop threshold but above the second voltage drop threshold, the bus shunt resistor may be disconnected from the subsequent bus nodes, the measurement input is still connected to the subsequent bus nodes, which pull the measurement line towards the supply voltage;

[0174] d) If the voltage drop across the bus shunt resistor (R2) is within the range of the voltage drop of the base current, the own addressing current source (Iq1, Iq2, Iq3) of the relevant bus node is not operational, although it is the last bus node. The bus node can signal this situation to the bus master (ECU), for example, in the following way: it induces a bus conflict in that it accepts the bus node address to be assigned as a valid bus node address. This then leads to two automatically addressed bus nodes responding to the bus master during the check for correct bus node addressing, and the bus master can then detect this situation. Therefore, a method for assigning bus node addresses within a serial data bus with a chain of bus nodes (SL1, SL2, SL3) and with a bus master (ECU) is proposed, in which method the bus nodes (SL1, SL2, SL3) can be automatically addressed bus nodes or standard bus nodes, and the data bus has a bus master (ECU). Each bus node (SL2, SL3) has a previous bus node (SL1, SL2) if it is not the first bus node (SL1). Each bus node (SL2, SL3) is connected to its previous bus node (SL1, SL2) via a data bus if it is not the first bus node (SL1). The first bus node (SL1) is connected to a bus master (ECU) via a data bus. Each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its previous bus node (SL1, Sl2) via a bus node output terminal if it is not the first bus node (SL1). The first bus node (SL1) sends a bus node output current (i1) to the bus master (ECU) via a bus node output terminal. Each bus node (SL1, SL2) receives a bus node input current (i2, i3) from its subsequent bus node (SL2, Sl3) via a bus node input terminal if it is not the last bus node (SL3). The method comprises the following steps:

[0175] Determine the maximum addressing current (I amax );

[0176] For each automatically addressed bus node of the bus nodes (SL1, S12, SL3) which does not yet have a valid bus node address, an initialization sequence is carried out in the following steps until all automatically addressed bus nodes of the bus nodes (S11, S12, S13) have a valid bus node address:

[0177] ○Signaling the bus node address to be assigned to all automatically addressable bus nodes;

[0178] o The following steps are performed by all automatically addressable bus nodes (SL1, SL2, SL3), which are referred to below as relevant automatically addressable bus nodes (SLj):

[0179] ■ receiving the automatic addressing command by the bus master (ECU) via the relevant automatic addressing bus node (SLj);

[0180] ■ receiving the bus node address to be assigned by the bus master (ECU) via the associated automatically addressable bus node (SLj);

[0181] ■ Switching off any existing bus node basic current sources (S1, R3, d1) within the corresponding automatically addressed bus node (SLj);

[0182] ■ receiving, by the bus master (ECU) via the associated automatically-addressed bus node (SLj), a start signal for assigning a bus node address to be assigned, and starting a timer via the associated automatically-addressed bus node (SLj);

[0183] ■ The bus input current (i (j+1) ) is fed into the bus node output of the associated automatically addressed bus node (SLj) as the bus output current (i j )

[0184] ■ The bus node output current (i j ) value;

[0185] ■ With the aid of the control mechanism (F), the bus node output current (i j ) detects the value and generates the adjustment signal (rw j );

[0186] ■According to the generated adjustment signal (rw j ), with the aid of the regulated automatic addressing current source (Iqj), the bus node output current (i j ) is adjusted to a predetermined total current value (I ref ), the addressing current of the automatic addressing current source is the bus output current (i j )

[0187] ■ Among them, the first time constant (τ 1) increasing the addressing current of the regulated automatic addressing current source (Iqj) of the associated automatic addressing bus node (SLj);

[0188] ■ Among them, the second time constant (τ 2 ) reduces the addressing current of the regulated automatic addressing current source (Iqj) of the associated automatic addressing bus node (SLj); and

[0189] ■ Among them, the second time constant (τ 2 ) is less than the first time constant (τ 1 );

[0190] ■ comparing the regulation value (rj) of the relevant automatically addressed bus node (SLj) with the threshold value (SWj) of the relevant automatically addressed bus node (SLj);

[0191] ■After starting the timer, at the first time point t 1 Freezing the regulation of the addressing current source (Iqj) of the associated automatically addressed bus node (SLj);

[0192] The bus node address to be assigned is accepted by the bus master (ECU) as a valid bus node address of the associated automatically addressed bus node (SLj) if a minimum time has elapsed since the start of the timer and if a comparison of the regulation value (rj) with the threshold value (SWj) shows that the addressing current of the addressing current source (Iqj) of the associated automatically addressed bus node (SLj) is above the current threshold value in magnitude and, at a first point in time t 1 The second time point t 2 The relevant automatically addressable bus node (SLj) is configured as a standard bus node without automatic addressing capability, which has the bus node address to be assigned as the bus node address of the relevant automatically addressable bus node (SLj), whereby the automatically addressable bus node (SLj) temporarily no longer participates in the subsequent initialization sequence.

[0193] ○ Checking of successful address assignment by the bus master (ECU);

[0194] o If necessary, the validity of the last assigned bus node address is cancelled, whereby the associated automatically addressed bus node (SLj) behaves again like an automatically addressed bus node (SLj) without a valid bus node address;

[0195] ○ Check whether all automatically addressed bus nodes have obtained valid bus node addresses;

[0196] o If not all automatically addressed bus nodes have received a valid bus node address, another initialization sequence is performed.

[0197] In a variant of the proposed method, the first time constant (τ 1 ) is the second time constant (τ 2 ) is more than 10 times, preferably more than 100 times. In another variant of the method, the first time constant (τ) within the associated automatic addressing bus node (SLj) 1 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j ) is detected by means of the measuring device (R2, D1, D3). For example, it is advantageous when the first time constant (τ 1 ), the total current flowing through the bus shunt resistor is still small and short, so that the addressing current source of the corresponding automatically addressable bus node increases the current quickly, while the addressing current of the automatically addressable current source increases slowly afterwards. It is therefore conceivable that the first time constant (τ 1 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j ) is detected by means of a measuring device (R2, D1, D3), so that the first time constant (τ 1 ) has a first value below the threshold value and a second value above the threshold value. It is also conceivable that a second time constant (τ) within the relevant automatic addressing bus node (SLj) 2 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j ) detected by means of a measuring device (R2, D1, D3).

[0198] In order to now be able to detect the exchange of LIN inputs and LIN outputs, a variant of the method preferably includes checking the associated automatically addressed bus node (SL j ) of the bus node output current (i j ) and if the relevant automatically addressed bus node (SL j ) of the bus node output current (i j ) is unreliable, take action.

[0199] In another embodiment, the feed point of the addressing current can be redefined as a countermeasure if the relevant automatic addressing bus node (SL j ) of the bus node output current (i j ) is unreliable.

[0200] In addition to this compensatory measure, the bus master (ECU) can also signal the error on request via the data bus if the relevant automatically addressed bus node (SL j ) of the bus node output current (i j ) is unreliable.

[0201] In a further development, a further measure necessary for the stability of the control loop may be to carry out a detection of the associated automatically addressed bus node (SL) by means of a measuring device (R2, D1, D3). j ) of the bus node output current (i j ) value. Preferably, if the relevant automatic addressing bus node (SL j ) of the bus node output current (i j ) is credible, the first symbol is used to detect the relevant automatic addressing bus node (SL) by means of the measuring device (R2, D1, D3). j ) of the bus node output current (i j ) value; if the relevant automatically addressed bus node (SL j ) of the bus node output current (i j ) is untrustworthy, the associated automatically addressed bus node (SL) is detected with a second sign opposite to the first sign by means of a measuring device (R2, D1, D3). j ) of the bus node output current (i j ) value.

[0202] A further methodological measure may be that if the relevant automatically addressable bus node (SL j ) of the bus node output current (i j ) is unreliable, the predetermined error address is used as the relevant automatic addressing bus node (SL j ) of the bus master (ECU). This is predetermined in the design or is specified by the bus master (ECU) for example in a broadcast message.

[0203] A data bus system is proposed, which has bus nodes (SL1, SL2, SL3) for a serial data bus, each of which has a bus shunt resistor (R2) connected to the data bus. The bus nodes should also have an addressing current source (Iq1, Iq2, Iq3) for detecting the bus position of the bus node in the data bus, which addressing current source can be adjusted to additionally feed an addressing current into the data bus, so that the total current (i1, i2, i3) flowing through the bus shunt resistor (R2) of the bus node (SL1, SL2, SL3) is equal to a predetermined or calculated or otherwise determined total current (I ref). The control is carried out via the control loop (R2, D1, D3, F, Iq1, Iq2, Iq3). The addressing current flows through the bus shunt resistor (R2) of the associated automatic addressing bus node. A variant of the proposed bus node has a device (R2, D1) for detecting the current flowing through the bus shunt resistor (R2), which can include detecting measured values. The detection current flowing through the bus shunt resistor (R2) can be used for self-testing, so that the above-mentioned errors (e.g. a bus shunt resistor break) can be detected.

[0204] In another variant of the device, the device has a detection device (DET) which checks the plausibility of internal signals (ds1, ds3) of the bus node (SLx). Reference is made here to the description of the drawings.

[0205] Finally, other checks on the normality of the data bus system may also be performed, as described in WO-A-2005 / 050924.

[0206] The bus node (SLx) or the subdevice (DET) of the bus node (Slx) is preferably designed so that it takes measures if the detection device (DET) does not determine plausible internal signals within the bus node. See the following figure description for possible measures.

[0207] The bus node of the present invention has, for example, a partial device (MUX) which is capable of changing the feed point of the addressing current of the addressing current source (Iqx). Alternatively, instead of the addressing current source (Iqx) and the multiplier (MUX), the bus node (SLx) of the present invention may also have a first addressing current source (Iqx1) and a second addressing current source (Iqx2), wherein the first addressing current source (Iqx1) feeds its current into a node connected to the first terminal of the bus shunt resistor (R2) when it feeds current, wherein the second addressing current source (Iqx2) feeds its current into a node connected to the second terminal of the bus shunt resistor (R2) when it feeds current. In order to enable automatic addressing, only one of the two addressing current sources (Iqx1, Iqx2) feeds the addressing current, while the other addressing current source preferably does not feed current. The two addressing current sources ( Iqx1 , Iqx2 ) therefore preferably feed their current in such a way that the addressing current preferably flows via the bus shunt resistor ( R2 ) towards the bus master (ECU).

[0208] In another particularly preferred variant of the automatically addressable bus node, the addressing current sources (Iq1, Iq2, Iq3) which feed the addressing current are switched with a first time constant (τ 1 ) increases the addressing current and increases the addressing current by a time less than or greater than the first time constant (τ 1 )’s second time constant (τ2 )Reduce the addressing current.

[0209] In order to improve the EMV capability, it is proposed to implement the method described above for assigning bus node addresses within a serial data bus having a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU). However, the subsequent principles for improving the EMV properties can also be applied to automatic addressing methods, which are known, for example, from the documents DE-B-10 256631, EP-B-1 603 282, US-B-7 590 140, EP-B-1 490 772 and EP-B-1 298 851.

[0210] Here, the bus nodes (SL1, SL2, SL3) can be automatically addressed bus nodes or standard bus nodes. The data bus has a bus master (ECU). Each bus node (SL2, SL3) has a previous bus node (SL1, SL2) if it is not the first bus node (SL1). Each bus node (SL2, SL3) is connected to its previous bus node (SL1, SL2) via the data bus if it is not the first bus node (SL1). The first bus node (SL1) is connected to the bus master (ECU) via the data bus. Each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its previous bus node (SL1, Sl2) via the bus node output terminal if it is not the first bus node (SL1). The first bus node (SL1) sends a bus node output current (i1) to the bus master (ECU) via the bus node output terminal. Each bus node (SL1, SL2) receives a bus node input current (i2, i3) from its subsequent bus node (SL2, S13) via the bus node input, if it is not the last bus node (SL3).

[0211] According to the invention, a method for assigning bus node addresses within a serial data bus formed by a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU) comprises the following steps:

[0212] The bus shunt resistor (R2) assigned to each automatically addressable bus node (SL1, SL2, SL3) is connected to the serial data bus by opening a bus shunt jumper switch (S4) within the corresponding automatically addressable bus node (SL1, SL2, SL3), the bus shunt resistor being part of the corresponding automatically addressable bus node (SL1, SL2, SL3), the bus shunt jumper switch being assigned to the assigned bus shunt resistor (R2). Obviously, the connection is only made if the bus shunt jumper switch (S4) of the corresponding bus shunt resistor (R2) has not yet been opened. It is assumed within the scope of the present application that the corresponding bus shunt resistor (R2) of the automatically addressable bus node (SL1, SL2, SL3) is bridged by the corresponding bus shunt jumper switch (S4) at the beginning of the addressing sequence and is thus removed from the data bus;

[0213] · acquiring a bus node address for at least one automatically addressed bus node (SL1, SL2, SL3) and assigning the bus node address to the newly addressed automatically addressed bus node (SL1, SL2, SL3) by means of an assigned bus shunt resistor (R2) which is not bridged by its assigned bus shunt jumper switch (S4);

[0214] By closing the bus shunt jumper switch (S4) assigned to the assigned bus shunt resistor (R2) of the re-addressed automatically-addressed bus node (SL1, SL2, SL3), the assigned bus shunt resistor (R2) of the re-addressed automatically-addressed bus node (SL1, SL2, SL3) is jumped, wherein the re-addressed automatically-addressed bus node (SL1, SL2, SL3), after assigning the bus node address to the re-addressed automatically-addressed bus node (SL1, SL2, SL3) and closing its assigned bus shunt jumper switch (S4), acts like a standard bus node until the following event: the action of the re-addressed automatically-addressed bus node (SL1, SL2, SL3) is canceled. Such an event can be, for example, a broadcast command "open the bus shunt jumper switch (S4)" sent to all automatically-addressed bus nodes, or a reset of the bus system, or a voltage drop of the supply voltage. The opening of the bus splitter jumper switch (S4) preferably results in the assigned bus node address of the associated automatically addressed bus node (SL1, SL2, SL3) becoming invalid;

[0215] If necessary, repeatedly acquire and assign a bus node address for at least one other automatically addressable bus node (SL1, SL2, SL3) and, if necessary, bridge the assigned bus shunt resistor (R2) of the other newly addressed automatically addressable bus node (SL1, SL2, SL3) by means of an assigned bus shunt jumper switch (S4) until, if necessary, all automatically addressable bus nodes (SL1, SL2, SL3) have received the bus node address. Of course, the process can also be interrupted without all automatically addressable bus nodes (SL1, SL2, SL3) having received the bus node address. However, this is usually not helpful;

[0216] In order to be able to implement the aforementioned method, a bus node of the present invention is proposed, which can implement a method for assigning bus node addresses to bus nodes of a serial data bus system, wherein the method for assigning bus node addresses to bus nodes of the serial data bus system is implemented in an assignment period by means of a bus shunt resistor (R2) in each bus node (SL1, SL2, SL3), wherein the method for assigning bus node addresses to bus nodes of the serial data bus system in the assignment period is followed by an operating period. For this purpose, the bus node has such a bus shunt resistor (R2). According to the present invention, it has a bus shunt jumper switch (S4), which is open before the bus node address is assigned to the bus node in the assignment period, the bus shunt jumper switch is closed after the bus node address is assigned to the bus node in the assignment period, and the bus shunt jumper switch is closed in the operating period.

[0217] The proposed method and the proposed bus node enable automatic addressing according to one of the above-mentioned methods (bus-shunt-method=BSM-automatic addressing), which are disclosed, for example, in the documents DE 10 256 631 B4, EP 1 603 282 B1, US 7 590 140 B2, EP 1 490 772 B1, EP 1 298 851 B1 and the as yet unpublished German patent application DE 10 2017 122 364.9. By means of the shunt jumper switch (S4), the resistance is reduced to a minimum value in normal operation after automatic addressing, and in addressing operation, this resistance value enables good and robust automatic addressing.

[0218] But the advantages are not limited to this. BRIEF DESCRIPTION OF THE DRAWINGS

[0219] Figure 1A simplified, schematic representation of a bus system according to the invention is provided, in which the total current is measured by measuring the total current at the bus outputs of the respective automatically addressable bus nodes (SL1, SL2, SL3) across a shunt resistor;

[0220] Figures 2 to 4 Curves showing output currents (i1, i2, i3) of bus nodes (SL1, SL2, SL3) and currents of addressing current sources (Iq1, Iq2, Iq3) for different control time constants;

[0221] Figure 5 A schematically simplified representation of a bus system of type A with two standard bus nodes (CS1, CS2) which do not have automatic addressing capability;

[0222] Figure 6 A schematically simplified representation of a bus system of type B with two standard bus nodes (CS1, CS2) which do not have automatic addressing capability;

[0223] Figure 7 A schematically simplified representation of a bus system of type C with two standard bus nodes (CS1, CS2) which do not have automatic addressing capability;

[0224] Figure 8 shows the flipping condition of the second bus node (SL2);

[0225] Fig. 9 Shows the situation after the swapping of LIN inputs and outputs has been detected and countermeasures have been taken Figure 8 situation;

[0226] Fig.10 Shown in detailed form Figure 8 and 9 The second automatically addressable bus node (SL2) now serves as the xth automatically addressable bus node (SLx);

[0227] Fig.11 Shown in detailed form Figure 8 and 9 The second automatically addressable bus node (SL2) now functions as the x-th automatically addressable bus node (SLx), specifically in the first of two possible cases, in a state of being connected to the bus;

[0228] Fig.12 Corresponding to Figure 5, which schematically and in a simplified manner shows a bus system of type A with two standard bus nodes (CS1, CS2) without automatic addressing capability and automatically addressable bus nodes (SL1, SL2, SL3), each of which has a bus current splitter jumper switch (S4) and a receiver (Rec);

[0229] Fig.13 A bus node with connected applications is shown. DETAILED DESCRIPTION

[0230] Figure 1 The bus system according to the invention is shown in a simplified and schematic manner.

[0231] At the beginning of automatic addressing, the bus master (ECU) informs all automatically addressed bus nodes that bus node addresses are to be assigned. The subsequent address assignment is divided into several address assignment phases, wherein in each address assignment phase, exactly one initialization run is performed, preferably exactly one automatically addressed bus node, i.e., the last one of the automatically addressed bus nodes (SL1, SL2, SL3), and the bus master (ECU) obtains the valid bus node address of the bus master (ECU) in the bus node chain that does not yet have a bus node address. The bus master preferably transmits the number of standard bus nodes to all automatically addressed bus nodes by means of a so-called broadcast command, which standard bus nodes are located before the automatically addressed bus nodes (Sl1, Sl2, Sl3), i.e., between them and the bus master (ECU) or the maximum addressing level. Of course, the maximum addressing level I amax The bus nodes can also be programmed, since the bus topology is usually determined by the construction rather than by the operation and is therefore predictable. Here, it is determined how large the total current (I ref ) flows through the bus shunt resistor (R2).

[0232] At the beginning of each address allocation phase, the bus master (ECU) turns off its switch (SB) again for a predetermined addressing time T A . This current sink (SB) of the bus master (ECU) is usually actually a relatively complex structure, which can also detect bus short circuits and is only reproduced in a simplified manner here. In this way, the bus master (ECU) provides a current sink for the addressing current of the automatic addressing current source and the bus node basic current of the bus node in the subsequent address allocation phase. The automatically addressable automatic addressing bus nodes (SL1), (SL2) and (SL3) register that the data bus is connected to ground and open their corresponding switches S1 and S2. As a result, the automatic addressing bus nodes (SL1, SL2, SL3) no longer feed the bus node basic current into the data bus.

[0233] After a first time period (dt1) has elapsed, the automatically addressed bus node determines the basic current flowing through the corresponding bus shunt resistor (R2) by measuring the voltage drop across the bus shunt resistor (R2). This voltage drop can be temporarily stored, for example, as an offset voltage value in a sample and hold circuit and then deducted from the voltage drop across the bus shunt resistor (R2) measured later by a subtraction circuit. This ensures that only bus currents that differ from the corresponding basic current are used for address assignment and control of the addressing current sources (Iq1, Iq2, Iq3).

[0234] This phase ends after a second time period (dt2) has elapsed.

[0235] All automatically addressed bus nodes which do not yet have a valid bus node address detect a current which is different from a base current flowing through their respective bus shunt resistor (R2) and subsequently control their respective addressed current sources (Iq1, Iq2, Iq3) based on the bus current measurement value thus obtained so that the current flowing through their respective bus shunt resistor (R2) is equal to the previously determined or predefined total current (I ref ). For this purpose, the respective automatically addressable bus node has a measuring device (R2, D1, D3) in order to obtain the actual total current in the form of the respective bus node output current (i1, i2, i3) towards the bus master (ECU). In this case, the voltage drop across the bus shunt resistor (R2) is detected and, preferably after deducting the voltage value for the bus basic current, is subsequently processed as a total current signal. As already mentioned, the total current signal thus generated is filtered in a preferably nonlinear filter (F1) to form a control signal. This control signal is compared with a reference value (Ref) by means of a differential amplifier stage, which corresponds to a difference between the respective bus node output current (i1, i2, i3) and the reference current (I ref ) in terms of its effect. Therefore, when setting or calculating the reference current (I ref ), in practice this reference value (Ref) is usually determined. This comparison can be carried out before and after filtering in the filter (F). This preferably involves a difference calculation. A further filtering (not shown in the drawing) can also be carried out after this comparison. The control values ​​(rw1, rw2, rw3) obtained in this way then control the corresponding addressing current sources (Iq1, Iq2, Iq3) of the corresponding automatically addressing bus nodes (SL1, SL2, SL3).

[0236] Since the total current at the output of the corresponding automatically addressed bus nodes (SL1, S12, S13) should always be constant, ultimately only the last automatically addressed bus node (SL3) supplies current to the data bus, while all other addressing current sources (Iq1, Iq2) of the other automatically addressed bus nodes (SL1, S12) are adjusted downward by the controllers (R2, D1, D3, F) of the other automatically addressed bus nodes (SL1, S12). This results in the adjustment value (rw3) of the last bus node (SL3) differing from the adjustment values ​​(rw1, rw2) of the other bus nodes (SL1, S12) in that it adjusts the addressing current source (Iq3) of its bus node (SL3) completely upward, while the adjustment values ​​(rw1, rw2) of the previous bus nodes (SL1, SL2) have such values: these values ​​adjust their addressing current sources (Iq1, Iq2) downward. Each bus node (SL1, SL2, SL3) can therefore compare the manipulated value (rw1, rw2, rw3) with a preferably approximately equal threshold value (SW).

[0237] This phase ends after a third time period (dt3) has elapsed.

[0238] The end of this addressing phase is preferably characterized by the disconnection of the current sink switch (SB). As a result, the data bus is again connected to the supply voltage. The bus nodes (SL1, SL2, SL3) then preferably freeze the state of their respective set values ​​(rw1, rw2, rw3) and analyze it in comparison with the threshold value (SW), and then determine on the basis of this whether they are the last automatically addressed bus node (here SL3) in the bus node chain (SL1, SL2, SL3) or the previous automatically addressed bus node (SL1, S12). If they are the last bus node (SL3), they receive the bus node address to be assigned, which was signaled by the bus master (ECU) at the beginning, in which case they preferably have stored the bus node address in a suitable memory after receiving it. The automatically addressed bus node (SL3) then no longer participates in the other addressing phases of the initialization mode of operation. This means that the automatically addressed bus node (SL3) then no longer feeds the addressing current into the data bus via its addressing current source (Iq3). Of course, it then also no longer accepts other bus node addresses provided by the bus master (ECU), since it does have a valid bus node address, and behaves like a standard bus node until its valid bus node address becomes invalid, for example when the operating voltage falls below an operating voltage threshold, or the bus node address of the automatically addressed bus node becomes invalid, for example due to an instruction from the bus master or due to another signal.

[0239] The bus master preferably checks at the end of each initialization run whether the address assignment has been successfully performed.

[0240] Next comes the addressing phase of the subsequent initialization operation form, in which the next, now the last, not yet addressed automatic addressing bus node (SL2) obtains its valid bus node address in the same way. The process proceeds similarly. Then, just like the automatic addressing bus node (SL3) that was initially provided with a valid bus node address, the automatic addressing bus node (SL2) no longer participates in the other addressing phases of the subsequent initialization operation form. Then it behaves like a standard bus node. This means that it no longer feeds addressing current into the data bus through its addressing current source (Iq2). Of course, it then also no longer accepts other bus node addresses to be assigned provided by the bus master (ECU), because it then does have a valid bus node address. This continues until all automatic addressing bus nodes have obtained valid bus node addresses.

[0241] Figure 2 The graph shows the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2) and the output current (i3) of the third bus node (SL3). The graph also shows the current (I1_internal) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_internal) of the addressing current source (Iq2) of the second bus node (SL2) and the current (I3_internal) of the addressing current source (Iq3) of the third bus node (SL3). In this case, the time constants for the upward regulation of the addressing current source and the downward regulation of the addressing current source are approximately equal. Overshoot occurs. It can be clearly seen that the current (I1_internal) of the addressing current source (Iq1) of the first bus node (SL1) and the current (I2_internal) of the addressing current source (Iq2) of the second bus node (SL2) are regulated downward by the controllers of these automatically addressing bus nodes, while the current (I3_internal) of the addressing current source (Iq3) of the third bus node (SL3) is controlled to a reference value. The time for oscillation is determined only by the first time constant (τ 1 ) decision, which differs from DE-B-10 2010 026 431.

[0242] Figure 3The graph shows the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2) and the output current (i3) of the third bus node (SL3). The figure also shows the current (I1_internal) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_internal) of the addressing current source (Iq2) of the second bus node (SL2) and the current (I3_internal) of the addressing current source (Iq3) of the third bus node (SL3). In this case, the time constant for the upward regulation of the addressing current source is approximately ten times longer than the time constant for the downward regulation of the addressing current source. Minimal overshoot occurs.

[0243] Figure 4 The graph shows the output current (i1) of the first bus node (SL1), the output current (i2) of the second bus node (SL2) and the output current (i3) of the third bus node (SL3). The graph also shows the current (I1_internal) of the addressing current source (Iq1) of the first bus node (SL1), the current (I2_internal) of the addressing current source (Iq2) of the second bus node (SL2) and the current (I3_internal) of the addressing current source (Iq3) of the third bus node (SL3). In this case, the time constant for the upward regulation of the addressing current source is approximately one hundred times longer than the time constant for the downward regulation of the addressing current source. No overshoot occurs.

[0244] Figure 5 A bus system of type A is shown schematically and in a simplified manner with two standard bus nodes ( CS1 , CS2 ) which do not have automatic addressing capability.

[0245] Figure 6 A bus system of type B with two standard bus nodes ( CS1 , CS2 ) which do not have automatic addressing capability is shown schematically and in a simplified manner.

[0246] Figure 7 A bus system of type C is shown in a schematically simplified manner with two standard bus nodes ( CS1 , CS2 ) which do not have automatic addressing capability.

[0247] Figure 8The twisted situation of the second bus node (SL2) is shown. For the second bus node (SL2), the LIN bus input and the LIN bus output are swapped in this example. This operating situation should be recognized. The swap causes the bus shunt current (i2R) flowing through the bus shunt resistor (R2) of the twisted second bus node (SL2) to be fed into its bus shunt resistor (R2) in the opposite direction compared to the normal position. This bus shunt current (i2R) flowing through the bus shunt resistor (R2) in this example only includes the bus node output current (i3) of the subsequent, third automatically addressed bus node (SL3) or, in other cases, a subsequent bus node. This bus node output current (i3) of the third automatically addressed bus node (SL3) therefore now causes a negative voltage drop (V R2 ). This can be detected by the first differential amplifier (D1) of the second reversed automatic addressing bus node (SL2) in this example. When the output level of the output terminal (ds1) of the differential amplifier (D1) is as small as possible, the output terminal (ds1) thereof is negatively charged due to the negative voltage drop (V R2 ). This output level of the output (ds1) of the differential amplifier (D1) which is as small as possible can be the maximum value of the negative output value in terms of magnitude, or the minimum value of the positive output value in terms of magnitude. This is usually near 0V, depending on the construction of the first differential amplifier (D1) and its voltage supply. As a result, the output (ds1) of the first differential amplifier (D1) is usually below the level of the reference value (Ref). This causes a large positive signal at the output (ds3) of the third differential amplifier (D3), and thus at least after the start-up of the nonlinear filter (F) of the twisted automatic addressing bus node (SL2), the addressing current is maximized by the regulated addressing current source (iq2) of the second automatic addressing bus node (SL2) which is twisted here in this exemplary error case. The control loop thus increases the addressing current fed into the data bus by the addressing current source (Iq2). Here, the following problem now arises: the addressing current does not flow through its own bus shunt resistor (R2) as specified. The provided control loop is thus interrupted. The current transient caused by the bus node output current (i3) of the subsequent third automatically-addressed bus node (SL3) thus does not cause a positive current transient in the bus shunt resistor (R2) as specified, but rather a negative current transient. The other automatically-addressed bus nodes (SL2) located after the twisted second automatically-addressed bus node (SL2) further bias negatively the voltage drop across the bus shunt resistor (R2) of the twisted second automatically-addressed bus node (SL2).

[0248] However, the second automatically addressable bus node (SL2) can be reversed by means of the voltage drop (V R2 )——It has a voltage magnitude |V R2 |=|i2R|*|R2|——Identify: the voltage drop (V) between the addressing current transient generated by its regulated addressing current source (Iq2) and its bus shunt resistor (R2) R2 ) is not proportional to the transient state normally associated with the bus. In addition, a sign error occurs. Thus, if the x-th automatically addressed bus node (SLx) detects a negative voltage drop (V R2 ), and its addressed current source (Iq2) is to provide a positive current, the associated automatically addressed bus node (SL2) can recognize this situation and take countermeasures.

[0249] In particular, the relevant x-th automatically addressed bus node (SLx) must prevent: in this error situation, the addressing current of its regulated addressing current source (Iqx) continues to rise, and thus the bus node output current (ix) of the relevant x-th automatically addressed bus node (SLx) continues to rise, because the bus node output current (ix) will exceed the maximum LIN bus current (condition: i1 = <40mA), and the bus node output current is the sum of the bus input current and the addressing current of its regulated addressing current source (Iqx).

[0250] In the simplest case, the xth automatically addressed bus node (SLx) switches off its addressing current source (Iqx) and accepts a predetermined error address as the bus node address. After automatic addressing, the bus master (ECU) can send a test request for the bus node using this error address as the bus node address and then reply to this test request with a standardized response.

[0251] In the simplest case, the bus master (ECU) can then signal a bus error to all bus nodes and / or users. However, the bus master (ECU) can also send a command to the bus node with the incorrect address, which then firstly changes the feed point of its addressing current, for example by means of a multiplier (MUX), and secondly exchanges the polarity of the inputs or alternatively the outputs of the first differential amplifier (D1). The bus master (ECU) then carries out a new address assignment. The bus master preferably only signals an error if the address assignment is still incorrect. If necessary, it disconnects the bus node that is still involved by means of a command to the incorrect address (broadcast command), since in this case another error is obviously present.

[0252] Fig. 9Shown in:

[0253] a. Identify the LIN input and output swap,

[0254] b. Switching of the feeding point of the automatic addressing current of the addressing current source (Iq2) of the second automatic addressing bus node (SL2) which is here exemplary reversed, and

[0255] c. Swap the polarity of the input terminals of the first differential amplifier (D1) or, alternatively, swap the output terminals

[0256] What happened afterwards.

[0257] Fig.10 Shown in detailed form Figure 8 and 9 The second automatically addressable bus node (SL2) is now the x-th automatically addressable bus node. Here x is a positive, integer natural number representing the position of the bus node in the LIN bus chain. This is the x-th automatically addressable bus node (SLx), which is able to:

[0258] First, identify the exchange of its LIN input and its LIN output;

[0259] Second, in this case, as an exemplary countermeasure, the feeding point of the addressing current for its regulated addressing current source (Iqx) is arranged before or after its bus shunt resistor (R2), so that automatic addressing can be performed according to the direction in which the bus node is connected.

[0260] to this end, Fig.10 The x-th automatically addressable bus node (SLx) shown by way of example in the figure has a detection device (DET) which is able to determine the exchange of the LIN input of the x-th automatically addressable bus node (SLx) with the LIN output of the x-th automatically addressable bus node (SLx). To this end, the exemplary detection device (DET) checks the plausibility of the internal signals of the x-th automatically addressable bus node (SLx). If the internal signals of the x-th automatically addressable bus node (SLx) allow reliable conclusions to be drawn about the exchange of the LIN input of the x-th automatically addressable bus node (SLx) with the LIN output of the x-th automatically addressable bus node (SLx), the detection device may take various exemplary measures:

[0261] a. Signal the error to the user;

[0262] b. Signaling an error to the bus master (ECU) by responding to a diagnostic query (broadcast message);

[0263] c. Using the wrong address as the bus node address;

[0264] d. Reconfigure the internal topology to eliminate the error;

[0265] e. Reset parameters for some internal devices such as current sources to eliminate errors;

[0266] Other measures may be considered.

[0267] exist Fig.10 In the example, it is specified to reconfigure the internal topology in order to eliminate the error. Fig.10 In the process, for example, the detection device (DET) changes the feed point of the addressing current of the regulated addressing current source (Iqx) for the xth automatically addressing bus node (SLx), for example by means of an analog multiplier (MUX), and exchanges the polarity of the inputs or outputs of the first differential amplifier (D1) by means of a polarity signal (pol).

[0268] Replacement Fig.10 For example, parameters can be reset for some internal devices, such as current sources, in order to eliminate errors if, instead of the addressing current source (Iqx) and multiplier (MUX) of the x-th automatic addressing bus node (SLx), the first addressing current source (Iqx1) of the x-th automatic addressing bus node (SLx) and, for example, the second addressing current source (Iqx2) of the x-th automatic addressing bus node (SLx) are used, wherein the first addressing current source (Iqx1) of the x-th automatic addressing bus node (SLx) feeds its addressing current before the bus shunt resistor (R2) and the second addressing current source (Iqx2) of the x-th automatic addressing bus node (SLx) feeds its addressing current after the bus shunt resistor (R2). In this case, the detection device (DET) sets the addressing current of one of the two current sources (Iqx1, Iqx2) to zero, thereby achieving an equivalent effect compared to the combination of the addressing current source (Iqx) of the xth automatically addressed bus node (SLx) and switching using a multiplier (MUX).

[0269] For example, the detection device (DET) can detect that the adjustment value (rwx) of the x-th automatically addressing bus node (SLx) maximizes the addressing current of the addressing current source (iqx). This can be achieved, for example, in the case of a suitable design by comparing the adjustment value (rwx) with the second threshold value (Ref2). If the derivative of the addressing current of the automatically addressing current source (iqx) with respect to the adjustment value (rwx) is positive, this means that the adjustment value (rwx) is above the second threshold value (Ref2). In addition, the detection device (DET) can simultaneously compare the output (ds1) of the first differential amplifier (D1) with a third reference value. If the output (ds1) of the first differential amplifier (D1) is lower than the third reference value (Ref3), the detection device can infer that there is a negative voltage drop (V R2 ), or infer the voltage drop (V R2 ) is close to zero. This state is illegal because the auto-addressing current source does provide a positive addressing current, which, if properly installed, must flow through the bus shunt resistor (R2), but this obviously does not happen.

[0270] The detection device (DET) can signal such a detected error, for example by means of an error signal, to a bus node, ie an internal computer, or to a suitable control unit.

[0271] Fig.11 The wiring of the hardware for controlling the automatic addressing current source (Iqx) and feeding the automatic addressing current into the data bus is shown if the bus node (SLx) is relative to the Fig.10 The wiring situation is "twisted" into the data bus. By correspondingly controlling the multiplier (MUX), the addressing current is now fed back again with reference to the bus master (ECU) after the bus shunt resistor (R2).

[0272] Fig.12 Corresponding to Figure 5 , and schematically and simplified, shows a bus system of type A with two standard bus nodes (CS1, CS2) without automatic addressing capability and automatically addressable bus nodes (SL1, SL2, SL3), each of which has a bus current splitter jumper switch (S4) and a receiver (Rec). The receiver (Rec) is connected to the other Figure 1 , 5, 6, 7, 8 and 9 are not shown for the sake of clarity. Usually, each automatically addressable bus node (SL1, SL2, SL3) has a control unit, which is connected to the output of the receiver (Rec) and can usually receive commands via the data bus. By means of such commands, the control unit (not shown) can preferably close or open the bus shunt jumper switch (S4). However, it is not absolutely necessary to provide such bus master commands for the control unit, but it is recommended to do so so that the bus master (ECU) can completely monitor the state of the bus shunt jumper switch (S4) of the automatically addressable bus node (SL1, SL2, SL3). Preferably, the bus master command for monitoring the bus shunt jumper switch (S4) can be sent by the bus master (ECU) via a command to all automatically addressable bus nodes (SL1, SL2, SL3) or as a command to a specific automatically addressable bus node (SL1, SL2, SL3). In the latter case, it is necessary that the relevant automatically addressable bus node has a valid bus node address. This can be a previously assigned bus node address or a predetermined default bus node address, which is then usually common to all such automatically addressed bus nodes (SL1, SL2, SL3) which have not yet been assigned a bus node address. It is therefore also conceivable that the bus master (ECU) sends commands for controlling the bus current splitter jumper (S4) only to those automatically addressed bus nodes (SL1, SL2, SL3) which have not yet been assigned a bus node address. For data bus systems, the time after switching on can be divided into two basic time periods:

[0273] An allocation period, during which the automatically addressed bus nodes (SL1, SL2, SL3) are allocated bus node addresses using the aforementioned or previously described automatic addressing method; and

[0274] An operating period during which the data bus operates normally, all bus nodes including the automatically addressed bus nodes (SL1, SL2, SL3) have preferably valid and preferably independent bus node addresses, and during which the automatically addressed bus nodes (SL1, SL2, SL3) behave like standard bus nodes (CS1, CS2).

[0275] Preferably, the corresponding bus shunt jumper switch (S4) of the automatically addressable bus node (SL1, SL2, SL3) is closed during the operating period. This significantly improves the similarity of the electrical characteristics of the automatically addressable bus node (SL1, SL2, SL3) compared to the standard bus node (CS1, CS2), which improves the EMC characteristics. In other words, it is known from the prior art that, if necessary, ferrites must be placed at the bus input and bus output of the bus node in the case of internal KfZ applications. During the operating period, since they are bridged by the bus shunt jumper switch (S4), it is possible to reduce the bus resistance by virtually eliminating the bus shunt resistor (R2), thereby achieving a significant improvement in the bus characteristics and increasing the maximum number of possible bus nodes.

[0276] At the start of the allocation period, preferably all bus shunt jumper switches (S4) are opened. The allocation period preferably starts with the bus master signaling the start of the address allocation to all bus nodes. In this regard, the specific type of the start signal depends on the specific automatic addressing method used based on the bus shunt resistor (R2). Finally, the start signal of the bus master (ECU) thus opens all bus shunt jumper switches (S4) of all automatically addressed bus nodes having such bus shunt jumper switches (S4). If a valid bus node address is assigned to an automatically addressed bus node (SL1, SL2, SL3) by means of a bus shunt resistor (R2) by one of the known methods for automatic addressing, the automatically addressed bus node concerned closes its bus shunt jumper switch (S4) and thereby jumpers the associated bus shunt resistor (R2) for the remainder of the allocation period and the operating period immediately thereafter. This cross-connection should preferably be cancelled by a reset at the time of switching on or can be cancelled by a software command of the bus master (ECU).

[0277] Fig.13 An addressing bus node (SL1) is shown, for which the components belonging to the transceiver are enclosed by a dot-dash line. The signals (RxD) are separated from the bus and, after processing, are supplied to the actual application (e.g. window lifter or seat adjuster), which in turn sends signals to the transceiver, which then serve as control signals (TxD) for controlling the transceiver. The dashed line shows the part of the bus node (SL1) that can be automatically addressed and, according to the invention, feeds the automatic addressing current into the data bus.

[0278] Alternatively, the invention can also be developed by one of the following feature groups, wherein these feature groups can be combined with one another as desired, and individual features of a feature group can also be combined with one or more features of one or more other feature groups and / or one or more of the above-described embodiments.

[0279] 1. A method for assigning bus addresses within a serial data bus consisting of a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU),

[0280] - wherein the bus nodes (SL1, SL2, SL3) can be automatically addressable bus nodes or standard bus nodes; and

[0281] - wherein the data bus has a bus master (ECU); and

[0282] - wherein each bus node (SL2, SL3) has a preceding bus node (SL1, SL2) if it is not the first bus node (SL1); and

[0283] - wherein each bus node (SL2, SL3) is connected to its preceding bus node (SL1, SL2) via a data bus, if it is not the first bus node (SL1); and

[0284] - wherein the first bus node (SL1) is connected to the bus master (ECU) via a data bus; and

[0285] - wherein each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its preceding bus node (SL1, S12) via a bus node output, if it is not the first bus node (SL1); and

[0286] - wherein the first bus node (SL1) sends a bus node output current (i1) to the bus master (ECU) via the bus node output terminal; and

[0287] - wherein each bus node (SL1, SL2) receives a bus node input current (i2, i3) from its subsequent bus node (SL2, S13) via the bus node input, if it is not the last bus node (SL3),

[0288] The steps are as follows:

[0289] Determine the maximum addressing current (I amax );

[0290] For each automatically addressed bus node of the bus nodes (SL1, S12, SL3) which does not yet have a valid bus node address, an initialization sequence having the following steps is carried out until all automatically addressed bus nodes of the bus nodes (S11, S12, S13) have a valid bus node address:

[0291] Signaling the bus address to be assigned to all automatically addressable bus nodes;

[0292] The following steps are performed by all automatically addressable bus nodes (SL1, SL2, SL3), which are referred to below as relevant automatically addressable bus nodes (SLj):

[0293] The bus master (ECU) receives the automatic addressing command via the relevant automatic addressing bus node (SLj);

[0294] The bus master (ECU) receives the bus address to be assigned via the associated automatically addressable bus node (SLj);

[0295] Switching off any existing bus node basic current sources (S1, R3, d1) within the corresponding automatically addressed bus node (SLj);

[0296] receiving, by the bus master (ECU) via the associated automatically-addressed bus node (SLj), a start signal for assigning the bus address to be assigned and starting a timer via the associated automatically-addressed bus node (SLj);

[0297] · The bus input current (i (j+1) ) is fed into the bus node output of the associated automatically addressed bus node (SLj) as the bus output current (i j )

[0298] · Detect the bus node output current (i j ) value;

[0299] The bus node output current (i j ) detects the value and generates the adjustment signal (rw j );

[0300] ·According to the generated adjustment signal (rw j ), with the aid of the regulated automatic addressing current source (Iqj), the bus node output current (i j ) is regulated to a predetermined total current value (I ref ), the addressing current of the automatic addressing current source is the bus output current (i j )

[0301] ·Wherein, the first time constant (τ 1) increasing the addressing current of the regulated automatic addressing current source (Iqj) of the associated automatic addressing bus node (SLj); and

[0302] ·Wherein, the second time constant (τ 2 ) reducing the addressing current of the regulated automatic addressing current source (Iqj) of the associated automatic addressing bus node (SLj);

[0303] Where, the second time constant (τ 2 ) is less than the first time constant (τ 1 );

[0304] comparing the set value (rj) of the associated automatically addressed bus node (SLj) with the threshold value (SWj) of the associated automatically addressed bus node (SLj);

[0305] After starting the timer, at the first time point (t 1 ) freezing the regulation of the addressing current source (Iqj) of the associated automatically addressed bus node (SLj);

[0306] The bus node address to be assigned is accepted by the bus master (ECU) as a valid bus node address of the associated automatically addressed bus node (SLj) if a minimum time has elapsed since the start of the timer and if a comparison of the regulation value (rj) with the threshold value (SWj) shows that the addressing current of the addressing current source (Iqj) of the associated automatically addressed bus node (SLj) is above the current threshold value in magnitude and, at a first point in time (t 1 ) at the second time point (t 2 ) configures the relevant automatically addressed bus node (SLj) as a standard bus node without automatic addressing capability with the bus node address to be assigned as the bus node address of the relevant automatically addressed bus node (SLj), whereby the automatically addressed bus node (SLj) temporarily no longer participates in a subsequent initialization sequence,

[0307] Checking of successful address assignment by the bus master (ECU);

[0308] If necessary, the validity of the last assigned bus node address is cancelled, so that the automatically addressed bus node (SLj) in question behaves again like an automatically addressed bus node (SLj) without a valid bus node address;

[0309] Check whether all automatically addressed bus nodes have obtained valid bus node addresses;

[0310] If not all automatically addressed bus nodes have received a valid bus node address, another initialization sequence is performed.

[0311] 2. The method of item 1, wherein the first time constant (τ 1 ) is the second time constant (τ 2 ) is more than 10 times larger.

[0312] 3. A method as claimed in one or more of the preceding clauses, wherein a second time constant (τ 2 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j ) detected by means of a measuring device (R2, D1, D3).

[0313] 4. A method as claimed in one or more of the preceding clauses, wherein a first time constant (τ 1 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j ) detected by means of a measuring device (R2, D1, D3).

[0314] 5. A method as claimed in one or more of the preceding clauses, wherein a first time constant (τ 1 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j ) is detected by means of a measuring device (R2, D1, D3), so that the first time constant (τ 1 ) has a first value below a threshold and a second value above a threshold.

[0315] 6. Bus nodes for serial data buses (SL1, SL2, SL3),

[0316] - having a bus shunt resistor (R2) connected to the data bus;

[0317] - an addressing current source (Iq1, Iq2, Iq3) for detecting the bus position of a bus node in a data bus, which addressing current source can be adjusted to additionally feed an addressing current into the data bus so that the total current (i1, i2, i3) flowing through the bus shunt resistor (R2) of the bus node (Sl1, SL2, SL3) is equal to a predetermined or calculated or otherwise determined total current (I ref );as well as

[0318] - wherein the addressing current flows through a bus shunt resistor (R2).

[0319] 7. The bus node as described in the preceding paragraph, wherein the bus node has means (R2, D1) for detecting a current flowing through a bus shunt resistor (R2).

[0320] 8. A bus node as claimed in any of the preceding clauses, wherein a probe current flowing through a bus shunt resistor (R2) is used for self-testing.

[0321] 9. The bus node as claimed in one or more of the preceding clauses, wherein the addressing current sources (Iq1, Iq2, Iq3) are switched with a first time constant (τ 1 ) increases the addressing current and increases the addressing current by a time constant less than the first time constant (τ 1 )’s second time constant (τ 2 )Reduce the addressing current.

[0322] 10. A method for assigning bus addresses within a serial data bus consisting of a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU),

[0323] - wherein the bus nodes (SL1, SL2, SL3) can be automatically addressable bus nodes or standard bus nodes; and

[0324] - wherein the data bus has a bus master (ECU); and

[0325] - wherein each bus node (SL2, SL3) has a preceding bus node (SL1, SL2) if it is not the first bus node (SL1); and

[0326] - wherein each bus node (SL2, SL3) is connected to its preceding bus node (SL1, SL2) via a data bus, if it is not the first bus node (SL1); and

[0327] - wherein the first bus node (SL1) is connected to the bus master (ECU) via a data bus; and

[0328] - wherein each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its preceding bus node (SL1, S12) via a bus node output, if it is not the first bus node (SL1); and

[0329] - wherein the first bus node (SL1) sends a bus node output current (i1) to the bus master (ECU) via the bus node output terminal; and

[0330] - wherein each bus node (SL1, SL2) receives a bus node input current (i2, i3) from its subsequent bus node (SL2, S13) via the bus node input, if it is not the last bus node (SL3),

[0331] The steps are as follows:

[0332] Determine the maximum addressing current (I amax );

[0333] For each automatically addressed bus node of the bus nodes (SL1, S12, SL3) which does not yet have a valid bus node address, an initialization sequence with the following steps is carried out until all automatically addressed bus nodes of the bus nodes (S11, S12, S13) have a valid bus node address:

[0334] ·Signaling the bus address assignment to all automatically addressable bus nodes via the automatic addressing command;

[0335] The following steps are performed by all automatically addressable bus nodes (SL1, SL2, SL3), which are referred to below as relevant automatically addressable bus nodes (SLj):

[0336] The automatic addressing command is received, in particular, by the bus master (ECU) via the associated automatic addressing bus node (SLj);

[0337] receiving, by the bus master (ECU) via the associated automatically-addressed bus node (SLj), a start signal for assigning the bus address to be assigned and starting a timer via the associated automatically-addressed bus node (SLj);

[0338] · The bus input current (i (j+1) ) is fed into the bus node output of the associated automatically addressed bus node (SLj) as the bus output current (i j )

[0339] · Detect the bus node output current (i j ) value;

[0340] The bus node output current (i j ) detects the value and generates the adjustment signal (rw j );

[0341] ·According to the generated adjustment signal (rw j ), with the aid of the regulated automatic addressing current source (Iqj), the bus node output current (i j ) is adjusted to a predetermined total current value (I ref ), the addressing current of the automatic addressing current source is the bus output current (i j )

[0342] ·Wherein, the first time constant (τ 1 ) increasing the addressing current of the regulated automatic addressing current source (Iqj) of the associated automatic addressing bus node (SLj); and

[0343] ·Wherein, the second time constant (τ 2 ) reducing the addressing current of the regulated automatic addressing current source (Iqj) of the associated automatic addressing bus node (SLj); and

[0344] Where, the second time constant (τ 2 ) is less than the first time constant (τ 1 );

[0345] comparing the set value (rj) of the associated automatically addressed bus node (SLj) with the threshold value (SWj) of the associated automatically addressed bus node (SLj);

[0346] After starting the timer, at the first time point (t 1 ) freezing the regulation of the addressing current source (Iqj) of the associated automatically addressed bus node (SLj);

[0347] The bus master (ECU) receives the bus address to be assigned via the associated automatically addressable bus node (SLj);

[0348] The bus node address to be assigned is accepted by the bus master (ECU) as a valid bus node address of the associated automatically addressed bus node (SLj) if a minimum time has elapsed since the start of the timer and if a comparison of the regulation value (rj) with the threshold value (SWj) shows that the addressing current of the addressing current source (Iqj) of the associated automatically addressed bus node (SLj) is above the current threshold value in magnitude and, at a first point in time (t 1 ) at the second time point (t 2) configures the relevant automatically-addressable bus node (SLj) as a standard bus node without automatic addressing capability, with the bus node address to be assigned as the bus node address of the relevant automatically-addressable bus node (SLj), whereby the relevant automatically-addressable bus node (SLj) temporarily no longer participates in a subsequent initialization sequence,

[0349] Checking of successful address assignment by the bus master (ECU);

[0350] If necessary, the validity of the last assigned bus node address is cancelled, so that the automatically addressed bus node (SLj) in question behaves again like an automatically addressed bus node (SLj) without a valid bus node address;

[0351] Check whether all automatically addressed bus nodes have obtained valid bus node addresses;

[0352] If not all automatically addressed bus nodes have received a valid bus node address, another initialization sequence is performed.

[0353] 11. The method as described in item 10,

[0354] - performing the following steps by at least some of the automatically addressable bus nodes (SL1, SL2, SL3), hereinafter referred to as the associated automatically addressable bus nodes (SLj):

[0355] Any existing bus node basic current source (S1, R3, d1) is switched off within the relevant automatically addressed bus node (SLj).

[0356] 12. A method as described in one or more of the preceding clauses, wherein the first time constant (τ 1 ) is the second time constant (τ 2 ) is more than 10 times larger.

[0357] 13. A method as claimed in one or more of the preceding clauses, wherein a second time constant (τ 2 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j ) detected by means of a measuring device (R2, D1, D3).

[0358] 14. A method as claimed in one or more of the preceding clauses, wherein a first time constant (τ 1 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j) detected by means of a measuring device (R2, D1, D3).

[0359] 15. A method as claimed in one or more of the preceding clauses, wherein a first time constant (τ 1 ) depends on the associated automatic addressing bus node (SL j ) of the bus node output current (i j ) is detected by means of a measuring device (R2, D1, D3), so that the first time constant (τ 1 ) has a first value below a threshold and a second value above the threshold.

[0360] 16. The method as recited in one or more of the preceding clauses, comprising the following additional steps:

[0361] Check the relevant automatically addressed bus nodes (SL j ) of the bus node output current (i j ) and if the relevant automatically addressed bus node (SL j ) of the bus node output current (i j ) is unreliable, take action.

[0362] 17. The method as described in the preceding clause, comprising the following additional steps:

[0363] If the relevant automatically addressed bus node (SL j ) of the bus node output current (i j ) is unreliable, the feeding point of the addressing current is re-determined;

[0364] 18. The method as recited in one or more of the preceding clauses, comprising the following additional steps:

[0365] If the relevant automatically addressed bus node (SL j ) of the bus node output current (i j ) is unreliable, the bus master controller (ECU) sends a signal to notify the error through the data bus according to the requirements;

[0366] 19. The method as recited in one or more of the preceding clauses, comprising the following additional steps:

[0367] Execute the detection of the associated automatic addressing of the bus nodes (SL j ) of the bus node output current (i j ) value, as follows:

[0368] If the relevant automatically addressed bus node (SLj ) of the bus node output current (i j ) is credible, the first symbol is used to detect the relevant automatic addressing bus node (SL) by means of the measuring device (R2, D1, D3). j ) of the bus node output current (i j ) value; and

[0369] If the relevant automatically addressed bus node (SL j ) of the bus node output current (i j ) is unreliable, the associated automatically addressed bus node (SL) is detected by means of a measuring device (R2, D1, D3) with a second sign opposite to the first sign. j ) of the bus node output current (i j ) value.

[0370] 20. The method according to one or more of the preceding clauses, comprising the following additional steps:

[0371] If the relevant automatically addressed bus node (SL j ) of the bus node output current (i j ) is unreliable, the wrong address is used as the relevant automatic addressing bus node (SL j )'s valid bus node address;

[0372] 21. Bus nodes for serial data buses (SL1, SL2, SL3),

[0373] A bus shunt resistor (R2) connected to the data bus;

[0374] An addressing current source (Iq1, Iq2, Iq3, Iqx) is provided for detecting the bus position of a bus node in a data bus, which addressing current source can be adjusted to additionally feed an addressing current into the data bus so that a total current (i1, i2, i3, ix) flowing through a bus shunt resistor (R2) of a bus node (Sl1, SL2, SL3, SLx) is equal to a predetermined or calculated or otherwise determined total current (I ref );as well as

[0375] The addressing current of the addressing current source (Iq1, Iq2, Iq3, Iqx) is configured to flow through the bus shunt resistor (R2) in normal operation.

[0376] 22. The bus node as defined in the preceding clause, wherein the bus node has means (R2, D1) for detecting a current flowing through a bus shunt resistor (R2).

[0377] 23. A bus node as claimed in any of the preceding clauses, wherein a probe current flowing through a bus shunt resistor (R2) is used for self-testing.

[0378] 24. The bus node as claimed in claim 1, comprising a detection device (DET) which checks the plausibility of internal signals (ds1, ds3) of the bus node (SLx).

[0379] 25. The bus node as claimed in claim 1, wherein the bus node (SLx) or a part (DET) of the bus node (SLx) takes measures if the detection device (DET) does not determine an authentic internal signal within the bus node.

[0380] 26. The bus node as claimed in claim 1, wherein the bus node has a partial device (MUX) which is able to change the feed point of the addressing current of the addressing current source (Iqx).

[0381] 27. A bus node as claimed in any one of the preceding clauses,

[0382] wherein, instead of the addressing current sources (Iq1, Iq2, Iq2, Iqx), the bus node has a first addressing current source (Iqx1) and a second addressing current source (Iqx2); and

[0383] wherein the first addressing current source (Iqx1) feeds its current into a node connected to a first terminal of a bus shunt resistor (R2) when feeding current; and

[0384] wherein the second addressing current source (Iqx2) feeds its current into a node connected to the second terminal of the bus shunt resistor (R2) when feeding the current; and

[0385] Therein, two addressing current sources (Iqx1, Iqx2) feed their currents so that the addressing current flows through the bus shunt resistor (R2).

[0386] 28. A bus node as claimed in any one of the preceding clauses, wherein the addressing current source (Iq1, Iq2, Iq3) is switched with a first time constant (τ 1 ) increases the addressing current and increases the addressing current by a time constant less than the first time constant (τ 1 )’s second time constant (τ 2 )Reduce the addressing current.

[0387] 29. A method for allocating bus addresses within a serial data bus consisting of a chain of bus nodes (SL1, SL2, SL3) and a bus master (ECU),

[0388] Wherein, the bus nodes (SL1, SL2, SL3) may be automatic addressing bus nodes or standard bus nodes; and

[0389] Wherein, the data bus has a bus master (ECU); and

[0390] wherein each bus node (SL2, SL3) has a previous bus node (SL1, SL2) if it is not the first bus node (SL1); and

[0391] wherein each bus node (SL2, SL3) is connected to its preceding bus node (SL1, SL2) via a data bus, if it is not the first bus node (SL1); and

[0392] Wherein, the first bus node (SL1) is connected to the bus master (ECU) via a data bus; and

[0393] wherein each bus node (SL2, SL3) sends a bus node output current (i2, i3) to its preceding bus node (SL1, S12) via a bus node output terminal if it is not the first bus node (SL1); and

[0394] wherein the first bus node (SL1) sends the bus node output current (i1) to the bus master controller (ECU) via the bus node output terminal; and

[0395] Each bus node (SL1, SL2) receives the bus node input current (i2, i3) from its subsequent bus node (SL2, S13) through the bus node input terminal, if it is not the last bus node (SL3).

[0396] The steps are as follows:

[0397] In particular, an assigned bus shunt resistor (R2) of each automatically addressable bus node (SL1, SL2, SL3) is connected to the serial data bus by opening a bus shunt jumper switch (S4) within the corresponding automatically addressable bus node (SL1, SL2, SL3), the bus shunt resistor being part of the corresponding automatically addressable bus node (SL1, SL2, SL3), the bus shunt jumper switch being assigned to the assigned bus shunt resistor (R2);

[0398] Receiving a bus address for at least one automatically addressed bus node (SL1, SL2, SL3) and assigning the bus address to the newly addressed automatically addressed bus nodes (SL1, SL2, SL3) by means of assigned bus shunt resistors (R2) which are not bridged by their assigned bus shunt jumper switches (S4);

[0399] By closing a bus shunt jumper switch (S4) assigned to the assigned bus shunt resistor (R2) of the re-addressed automatically-addressed bus node (SL1, SL2, SL3), the assigned bus shunt resistor (R2) of the re-addressed automatically-addressed bus node (SL1, SL2, SL3) is jumped over, wherein the re-addressed automatically-addressed bus node (SL1, SL2, SL3), after assigning the bus address to the re-addressed automatically-addressed bus node (SL1, SL2, SL3) and closing its assigned bus shunt jumper switch (S4), behaves like a standard bus node until the following event: this action of the re-addressed automatically-addressed bus node (SL1, SL2, SL3) is cancelled;

[0400] If necessary, the bus address for at least one other automatically addressable bus node (SL1, SL2, SL3) is repeatedly acquired and assigned, if necessary, the assigned bus shunt resistor (R2) of the other re-addressed automatically addressable bus nodes (SL1, SL2, SL3) is bridged with the aid of an assigned bus shunt jumper switch (S4) until, if necessary, all automatically addressable bus nodes (SL1, SL2, SL3) have received the bus address.

[0401] 30. A bus node capable of implementing a method for assigning a bus address to a bus node of a serial data bus system,

[0402] wherein a method for assigning bus addresses to bus nodes of a serial data bus system is implemented within an assignment period by means of a bus shunt resistor (R2) in the respective bus node (SL1, SL2, SL3); and

[0403] wherein the implementation of the method for assigning a bus address to a bus node of a serial data bus system in the assignment period is followed by an operation period; and

[0404] Wherein, the bus node has such a bus shunt resistor (R2),

[0405] It is characterized in that

[0406] It has a bus shunt jumper switch (S4);

[0407] The bus shunt jumper switch is opened before assigning the bus address to the bus node within the assignment period; and

[0408] The bus shunt jumper switch is closed after the bus address is assigned to the bus node within the assignment period; and

[0409] The bus shunt jumper switch is closed during the operating period.

[0410] List of Reference Numerals

[0411] CS1 Standard Bus Node

[0412] CS2 Standard Bus Node

[0413] D1 First differential amplifier

[0414] d1 first electrode protection diode

[0415] D2 Second differential amplifier

[0416] d2 Second electrode protection diode

[0417] D3 Third differential amplifier

[0418] DET Detection Device

[0419] ds1 Output of the first differential amplifier (D1)

[0420] ds2 Output of the first differential amplifier (D2)

[0421] ds3 Output of the third differential amplifier (D3)

[0422] ECU Bus Master

[0423] er Error signal on the optional processor within the bus node

[0424] F Non-linear filter for automatic addressing of bus nodes (SL1, SL2, SL3)

[0425] Iq1 Regulated addressing current source of the first automatically addressing bus node (SL1), which provides the addressing current of the first automatically addressing bus node (SL1)

[0426] i1 Bus node output current of the first automatically addressed bus node (SL1)

[0427] Iq2 Regulated addressing current source of the second automatically addressing bus node (SL2), which provides the addressing current of the second automatically addressing bus node (SL2)

[0428] i2 Bus node output current of the second automatically addressed bus node (SL2)

[0429] i2R Bus shunt current flowing through the bus shunt resistor (R2) of the second auto-addressing bus node (SL2)

[0430] Iq3 A regulated addressing current source of the third automatic addressing bus node (SL3), which provides an addressing current of the third automatic addressing bus node (SL3)

[0431] i3 Bus node output current of the third automatically addressed bus node (SL3)

[0432] Iqx Regulated addressing current source of the xth automatically addressable bus node (SLx), which provides the addressing current of the xth automatically addressable bus node (SLx)

[0433] ix Bus node output current of the xth automatically addressed bus node (SLx)

[0434] ixR Bus shunt current flowing through the bus shunt resistor (R2) of the xth auto-addressing bus node (SLx)

[0435] I ref The predefined sum of the output currents of the bus node

[0436] pol signal, when the credibility check fails to obtain a credible internal signal (ds1, ds3), the detection device (DET) uses this signal to switch the polarity of the two input terminals of the first differential amplifier (D1), or to switch the polarity of the output terminal of the first differential amplifier (D1)

[0437] R1 Auxiliary shunt resistor for automatic addressing of bus nodes (SL1, SL2, SL3)

[0438] R2 Bus shunt resistor for automatic addressing of bus nodes (SL1, SL2, SL3)

[0439] R3 Slave pull-up resistor

[0440] Rec Receiver

[0441] Ref Reference value

[0442] rw1 Control value of the first automatically addressed bus node (SL1)

[0443] rw2 Control value of the second automatically addressed bus node (SL2)

[0444] rw3 Control value of the third automatically addressed bus node (SL3)

[0445] rwx Adjustment value of the xth automatically addressed bus node (SLX)

[0446] S1 First switch for automatic addressing of bus nodes (SL1, SL2, SL3)

[0447] S2 Second switch for automatic addressing of bus nodes (SL1, SL2, SL3)

[0448] S3 Third switch for automatic addressing of bus nodes (SL1, SL2, SL3)

[0449] S4 Bus current splitter jumper for automatic addressing of bus nodes (SL1, SL2, SL3)

[0450] SB Switch

[0451] SL1 First automatically addressed bus node

[0452] SL2 Second automatic addressing bus node

[0453] SL3 Third automatic addressing bus node

[0454] SLx xth automatically addressed bus node

[0455] V R2 Voltage drop across the bus shunt resistor (R2) of the associated auto-addressing bus node (SL1, SL2, SL3)

[0456] List of cited literature

[0457] DE –B-10 147 512

[0458] DE-B-10 256 631

[0459] DE-B-10 2010 026 431

[0460] EP-B-1 298 851

[0461] EP-B-1 490 772

[0462] EP-B-1 603 282

[0463] EP-A-2 571 200

[0464] EP-A-2 654 246

[0465] US-B-7 590 140

[0466] US-B-9 331 866

[0467] WO-A-2005 / 050924

Claims

1. A method for controlling a serial data bus system having a bus master connected to a bus line and a plurality of bus nodes connected successively to the bus line, some of the bus nodes being addressed bus nodes and others being designed as standard bus nodes with already defined addresses, wherein the method comprises an addressing phase for assigning addresses to at least some of the bus nodes and an operating phase for operating the data bus system after the end of the addressing phase, wherein at least some of the bus nodes in each case feed a current into the bus line in an addressing phase which flows to the bus master (ECU), and One of the bus nodes is a first bus node connected to the bus line closest to a bus master (ECU), and other bus nodes upstream of the first bus node are connected to the bus line, and one of the bus nodes is a last bus node connected to the bus line farthest from the bus master (ECU), and other bus nodes downstream of the last bus node between the bus node and the bus master (ECU) are connected to the bus line, and At least two of the bus nodes are addressed bus nodes (SL1, SL2, SL3, SLx), each of which has a current measuring device (R2) which can be connected to the bus line and a controllable jumper switch (S4) which is connected in parallel with the current measuring device (R2), and wherein the addressed bus nodes are correspondingly assigned addresses by a bus master (ECU) in an addressing phase, while the other bus nodes are standard bus nodes (CS1, CS2) with addresses which are respectively determined before the execution of the addressing phase, In this method In the addressing phase, each addressed bus node (SL1, SL2, SL3, SLx) is assigned an address when the jumper switch (S4) is open; and In the operating phase, the current measuring device (R2) of each addressed bus node (SL1, SL2, SL3, SLx) is bridged by closing the bridge switch (S4).

2. A method for controlling a serial data bus system having a bus master connected to a bus line and a plurality of bus nodes connected successively to the bus line, some of the bus nodes being addressed bus nodes and others being designed as standard bus nodes with already defined addresses, wherein the method comprises an addressing phase for assigning addresses to at least some of the bus nodes and an operating phase for operating the data bus system after the end of the addressing phase, wherein at least some of the bus nodes in each case feed a current into the bus line in an addressing phase which flows to the bus master (ECU), and One of the bus nodes is a first bus node connected to the bus line closest to a bus master (ECU), and other bus nodes upstream of the first bus node are connected to the bus line, and one of the bus nodes is a last bus node connected to the bus line farthest from the bus master (ECU), and other bus nodes downstream of the last bus node between the bus node and the bus master (ECU) are connected to the bus line, and At least two of the bus nodes are addressed bus nodes (SL1, SL2, SL3, SLx), each of which has a current measuring device (R2) which can be connected to the bus line and a controllable jumper switch (S4) which is connected in parallel with the current measuring device (R2), and wherein the addressed bus nodes are correspondingly assigned addresses by a bus master (ECU) in an addressing phase, In this method In the addressing phase, each addressed bus node (SL1, SL2, SL3, SLx) is assigned an address when the jumper switch (S4) is open; and In the operating phase, the current measuring device (R2) of each addressed bus node (SL1, SL2, SL3, SLx) is bridged by closing the bridge switch (S4).

3. The method according to claim 1 or 2, characterized in that: The addressing phase has a plurality of addressing cycles, wherein each addressing cycle assigns an address to one of the unaddressed or not-yet-addressed addressing bus nodes (SL1, SL2, SL3, SLx), and the addressing bus node (SL1, SL2, SL3, SLx) addressed in the addressing cycle no longer participates in the subsequent address assignment for other not-yet-addressed addressing bus participants, wherein the current measuring device (R2) assigned to the addressed addressing bus node (SL1, SL2, SL3, SLx) in the addressing phase is bridged by closing a bridge switch (S4) connected in parallel with the current measuring device (R2).

4. The method according to claim 1 or 2, characterized in that: During the addressing phase, each unaddressed or not yet addressed addressed bus node (SL1, SL2, SL3, SLx) feeds an addressing current to the bus master (ECU) into the bus line, and the addressing current flows through the current measuring device (R2) of the relevant unaddressed or not yet addressed addressed bus node (SL1, SL2, SL3, SLx).

5. The method according to claim 1 or 2, characterized in that: The current measuring device (R2) is a shunt resistor.

6. A method for controlling an addressable bus node of a serial data bus system according to any one of claims 1 to 5, the serial data bus system having a bus master connected to a bus line and having a plurality of bus nodes connected successively to the bus line, some of the bus nodes being addressable bus nodes and other bus nodes being capable of being designed as standard bus nodes (CS1, CS2) with already determined addresses, wherein: The addressable bus node is configured to be assigned its address by a bus master and has: A current measuring device (R2) which can be connected to the bus line; a jumper switch (S4) connected in parallel with the current measuring device (R2); an addressing current source, for feeding an addressing current to a bus master (ECU) into the bus line; as well as a control unit for controlling the jumper switch (S4), The control unit controls the jumper switch (S4) to be in an open state during an addressing phase of the data bus system for allocating addresses, and controls the jumper switch (S4) to be in a closed state during an operation phase of the data bus system after the addressing phase.

7. The addressable bus node according to claim 6, characterized in that: The current measuring device detects an addressing current which is fed into the bus line by an addressing current source.

8. A method for controlling a serial data bus system, comprising: bus lines; a bus master connected to the bus line; as well as a plurality of bus nodes serially connected to the bus line; The plurality of bus nodes comprises: at least two addressable bus nodes which receive addresses in an addressing phase; as well as zero or at least one standard bus node with a respectively defined address; The method comprises: an addressing phase for assigning an address to at least one of the two addressable bus nodes, and an operating phase for operating the data bus system after the end of the addressing phase; wherein in an addressing phase at least two of the plurality of bus nodes feed respective currents into the bus line, which currents flow to the bus master, and the plurality of bus nodes have: a first bus node which is connected to the bus line at a position upstream of the bus master and in the closest vicinity to the bus master, a last bus node connected to the bus line at a position upstream of the bus master and farthest from the bus master; and zero or at least one intermediate bus node, which is connected to the bus line between the first bus node and the last bus node; Each of the at least two addressable bus nodes receives an address assigned by the bus master during an addressing phase and has a current measuring circuit accessible into the bus line and a controllable jumper switch connected in parallel with the current measuring circuit, and Each of the standard bus nodes—if any—has a respective address, which is determined before the addressing phase is performed. In this method: In the addressing phase, in the open state of the jumper switch, an address is assigned to each addressable bus node; and in the operating phase, the current measuring circuit of each addressed addressable bus node is bypassed by closing the jumper switch.

9. The method according to claim 8, wherein the addressing phase has a plurality of addressing cycles, and, for each addressing cycle: Assigning an address to each of the addressable bus nodes that has not yet been assigned an address; and After the address assignment, this addressable bus node no longer participates in the subsequent address assignment for other addressable bus nodes that have not yet been addressed in the remainder of the addressing phase and, furthermore, after the address assignment, the current measuring circuit is bypassed for this addressable bus node by closing a jumper switch connected in parallel with the current measuring circuit.

10. The method according to claim 8, wherein: During the addressing phase, each addressable bus node which has not yet been assigned an address during this addressing phase feeds a respective addressing current into the bus line to the bus master, wherein the respective addressing current flows through the current measuring circuit of the respective addressable bus node which has not yet been assigned an address.

11. The method according to claim 9, wherein: During the addressing phase, each addressable bus node which has not yet been assigned an address during this addressing phase feeds a respective addressing current into the bus line to the bus master, wherein the respective addressing current flows through the current measuring circuit of the respective addressable bus node which has not yet been assigned an address.

12. The method of claim 8, wherein the current measurement circuit has a shunt resistor.

13. The method of claim 9, wherein the current measurement circuit has a shunt resistor. The method of claim 10 , wherein the current measurement circuit has a shunt resistor.

15. The method of claim 11, wherein the current measurement circuit has a shunt resistor.

16. An addressable bus node for a serial data bus system, wherein the bus system has: bus lines; A bus master connected to the bus line; as well as A plurality of bus nodes connected serially to a bus line, wherein the plurality of bus nodes have: at least two addressable bus nodes which receive addresses assigned by the bus master during an addressing phase; and Zero or at least one standard bus node with a defined address, wherein the addressable bus nodes have: A current measurement circuit that can be connected to the bus line; a jumper switch connected in parallel with the current measuring circuit; an addressing current source for feeding an addressing current flowing into the bus master into the bus line; and a control unit for controlling the jumper switch; The control unit controls the jumper switch to be in an open state during an addressing phase of the data bus system for allocating addresses, and controls the jumper switch to be in a closed state during an operation phase of the data bus system after the addressing phase. wherein the current measurement circuit detects the addressing current fed into the bus line by the addressing current source; and In which, during the addressing phase, each unaddressed or not-yet-addressed addressed bus node (SL1, SL2, SL3, SLx) feeds an addressing current flowing to the bus master controller (ECU) into the bus line, and the addressing current flows through the current measuring circuit of the relevant unaddressed or not-yet-addressed addressed bus node (SL1, SL2, SL3, SLx).

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