Semiconductor device, current detection method and load driving system

Abstract

The present application relates to a semiconductor device, a current detection method and a load driving system. The semiconductor device has a driving transistor coupled to a load and a current detection circuit. The current detection circuit includes: an operational amplifier that amplifies the potential difference between the voltage of a first terminal and the voltage of a second terminal; a sensing transistor that transmits a sensing current between the first terminal and the driving transistor; a voltage supply circuit that has a first current source and supplies a voltage higher than the voltage supplied to a ground voltage terminal to the second terminal; a third terminal that outputs a current based on the sensing current; a second current source that is coupled between the third terminal and the ground voltage terminal; and a current source control circuit that controls the currents of the first current source and the second current source. The detection current detected by the current detection circuit is a current obtained by subtracting the current of the second current source from the current based on the sensing current.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-013305 filed on January 30, 2018 including specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and can be applied to, for example, a semiconductor device that controls a solenoid valve installed in a vehicle such as an automobile. Background Art

[0004] In recent years, in automobiles, solenoid valves are used to control the operation of installed power transmission devices. For example, a method of transmitting driving force by a solenoid valve when changing the speed of a transmission by changing the position of a clutch that transmits driving force from an engine to a transmission is known.

[0005] Generally, the opening / closing of the solenoid valve is controlled by supplying or interrupting current to the solenoid. Therefore, preferably in order to control the solenoid valve, it is required to detect the current supplied to the solenoid with high precision. In order to achieve this, a current detection circuit for detecting the current supplied to the solenoid is proposed (Japanese Unexamined Patent Application Publication No. 2016-201646 (Patent Document 1)). The current detection circuit of Patent Document 1 detects the current supplied to the solenoid by a detection resistor provided between the solenoid driver and the output terminal.

[0006] There is a current detection circuit that uses a sense transistor that detects the current of a drive transistor in a DC-DC converter (Japanese Unexamined Patent Application Publication No. 2017-175746 (Patent Document 2)). An operational amplifier is used in the current detection circuit of Patent Document 2. Even when there is an offset in the operational amplifier, an intentional offset is applied to one end of the input of the operational amplifier to detect the current of the drive transistor on the low side.

[0007] Patent Literature

[0008] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2016-201646

[0009] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2017-175746

[0010] Patent Document 3: U.S. Patent No. 6,377,034 Summary of the invention

[0011] In a current detection circuit in which an intentional offset is applied to one end of an operational amplifier as in Patent Document 2, a nonlinear error occurs when a load current increases.

[0012] Other problems and novel features will become apparent from the description of the present disclosure and the accompanying drawings.

[0013] An overview of representative disclosed contents in the present disclosure will be briefly described below.

[0014] The semiconductor device has a driving transistor and a current detection circuit coupled to a load. The current detection circuit includes: an operational amplifier that amplifies a potential difference between a voltage of a first terminal and a voltage of a second terminal; a sensing transistor that transfers a sensing current between the first terminal and the driving transistor; a voltage supply circuit that has a first current source coupled between a power supply voltage terminal and a second terminal and supplies a voltage higher than a voltage supplied to a ground voltage terminal to the second terminal; a third terminal that outputs a current based on the sensing current; a second current source that is coupled between the third terminal and the ground voltage terminal; and a current source control circuit that controls the currents of the first current source and the second current source. The detection current detected by the current detection circuit is a current obtained by subtracting a current of the second current source from a current based on the sensing current.

[0015] According to this semiconductor device, nonlinear errors can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1D is a diagram showing an operating state of a solenoid driver.

[0017] Figure 2 is a circuit diagram showing a semiconductor device of a first comparative example.

[0018] Figure 3 is the equivalent circuit diagram, which takes into account Figure 2 Device structure of the current detection circuit in FIG.

[0019] FIG. 4A to FIG. 4C is a diagram showing a mechanism causing a nonlinear error.

[0020] Figure 5 is a diagram schematically showing an example of a driving system of an automobile in which an example semiconductor device is incorporated.

[0021] Figure 6 It is shown Figure 5 Block diagram of the configuration of the ECU.

[0022] Figure 7 It is shown Figure 6 A block diagram of the configuration of a semiconductor device in FIG.

[0023] Figure 8It is shown Figure 7 Circuit diagram of the current sensing circuit for the low-side driver.

[0024] Fig. 9 It is shown Figure 8 A diagram of the relationship between the currents of the first current source and the second current source and the solenoid current.

[0025] Fig.10 is a circuit diagram of a current sensing circuit for eliminating intentional offset.

[0026] Fig.11 is a circuit diagram showing a current detection circuit of a low-side driver of a second comparative example.

[0027] Fig.12 It is shown Fig.11 A diagram of the current of the first current source in the current detection circuit.

[0028] Fig.13A and Fig. 13B is a diagram showing the characteristics of the first current source in the case where the negative current source is not used.

[0029] Fig.14 is a circuit diagram showing a current detection circuit of a low-side driver of a first modification.

[0030] Fig.15 is a circuit diagram showing a current detection circuit of a low-side driver of a second modification.

[0031] Fig.16 is a circuit diagram showing a current detection circuit of a low-side driver of a third modification.

[0032] Fig.17 is a circuit diagram showing a current detection circuit of a low-side driver of a fourth modification.

[0033] Fig.18 It is shown Fig.17 A circuit diagram of a first current source and a second current source of a current detection circuit of a low-side driver.

[0034] FIG. 19A to FIG. 19C is a graph showing the solenoid current vs. Fig.17 Diagram of the dependence of the current flowing in the current path in the current sensing circuit of the low-side driver.

[0035] Fig. 20 is a circuit diagram showing a current detection circuit of a low-side driver of a fifth modification.

[0036] Fig.21 It is shown in Fig. 20 A diagram of the current path of the low-side driver current detection circuit in the case where the low-side driver is turned on.

[0037] Fig. 22 It is shown in Fig. 20 Diagram of the current path of the low-side driver's current detection circuit in the case where the high-side driver is turned on.

[0038] Fig.23 is a circuit diagram showing a current detection circuit of a low-side driver of a sixth modification.

[0039] Fig.24 is a circuit diagram showing a current detection circuit of a high-side driver of a seventh modification.

[0040] Fig.25 is a circuit diagram showing a current detection circuit of a low-side driver of an eighth modification.

[0041] Fig.26 It is shown Fig.25 Diagram of the current path of the low-side driver current sensing circuit in the high-side driver state.

[0042] Fig. 27 It is shown Fig.25 Diagram of the current path of the low-side driver state in the current detection circuit of the low-side driver.

[0043] Fig.28 is a circuit diagram showing a current detection circuit of a low-side driver of a ninth modification.

[0044] Fig.29 It is shown Fig.28 Diagram of the current path of the low-side driver current sensing circuit in the high-side driver state.

[0045] Fig.30 It is shown Fig.28 Diagram of the current path of the low-side driver current sensing circuit in the high-side driver state.

[0046] Fig.31 It is shown Fig.28 Diagram of the current path of the low-side driver state in the current detection circuit of the low-side driver.

[0047] Fig.32 It is shown Fig.28 Diagram of the current path of the low-side driver state in the current detection circuit of the low-side driver. DETAILED DESCRIPTION

[0048] Hereinafter, comparative examples, embodiments, and modifications will be described by using the accompanying drawings. In the following description, the same reference numerals refer to the same components, and repeated descriptions may not be given.

[0049] First, refer to Figures 1A to 1D Describes the operating state of the solenoid driver. Figures 1A to 1D is a diagram showing an operating state of a solenoid driver. Figure 1A is a diagram showing a driving operation in high-side driving. Figure 1B is a diagram showing the regenerative operation in the high-side drive. Figure 1C is a diagram showing the regenerative operation in the low-side drive. Figure 1D is a diagram showing a driving operation in low-side driving.

[0050] The solenoid driver has a high-side driver HSD provided between an input voltage terminal Tvin to which an input voltage (Vin) is supplied and an external output terminal Tlo, and a low-side driver LSD provided between a ground voltage terminal Tgnd to which a ground voltage (GND) is supplied and an external output terminal Tlo. The solenoid driving method includes a high-side drive and a low-side drive, which is determined according to whether the solenoid SLN is coupled to the ground voltage (GND) or the input voltage (Vin). In the driving operation in the high-side drive, as Figure 1A As shown, the high-side driver HSD is turned on, and the current (Isln) is transmitted via the external output terminal Tlo and stored in the solenoid SLN. In the driving operation of the low-side driver, as shown in FIG. Figure 1D As shown, the low-side driver LSD is turned on, and the current (Isln) is transferred from the power supply to the solenoid SLN and stored. In the regenerative operation in the high-side drive, as shown Figure 1B As shown, the low-side driver LSD is turned on and current is delivered to the solenoid SLN. In the regenerative operation in the low-side drive, as Figure 1C As shown, the high-side driver HSD is turned on and current is drawn from the solenoid SLN.

[0051] Since the coupling of the solenoid SLN does not change dynamically in the system, the solenoid driver is not always suitable for both high-side drive and low-side drive. On the other hand, a product suitable for both high-side drive and low-side drive as a solenoid driver is needed. Therefore, in some cases, the solenoid driver must be suitable for both high-side drive and low-side drive.

[0052] There can be four types of current detection circuits for solenoid drivers: a current detection circuit for a high-side driver and a current detection circuit for a low-side driver suitable for high-side driving; and a current detection circuit for a high-side driver and a current detection circuit for a low-side driver suitable for low-side driving.

[0053] The current detection circuit is a circuit that detects a current flowing between the drain and source of a MOS transistor as a high-side driver HSD component or detects a current flowing between the drain and source of a MOS transistor as a low-side driver LSD component.

[0054] Will refer to Figure 2An example (first comparative example) of a semiconductor device having a current detection circuit of a low-side driver suitable for high-side driving is described. Figure 2 is a circuit diagram of a semiconductor device of a first comparative example.

[0055] The semiconductor device 10R of the first comparative example has a transistor MN1 of a low-side driver LSD and a current detection circuit 12LR as part of the components provided for the solenoid driver. The current detection circuit 12LR has a transistor MN3 of a sensing transistor STR, transistors MN4, MP1 and MP2, a first operational amplifier A1, and a constant current source CCR. Figure 2 , the solenoid SLN is also shown.

[0056] In the current detection circuit 12LR, the transistor MN3 includes a high withstand voltage N-channel MOS transistor like the transistor MN1. For example, the transistor size of the transistor MN3 is 1 / 1000 of the transistor size of the transistor MN1.

[0057] The transistor MN3 is provided on a current path between a power supply voltage terminal Tvdd to which a power supply voltage (VDD) is supplied and a drain (terminal Td) of the transistor MN1 , and a pulse signal ( VG1 ) is supplied to a gate.

[0058] The first operational amplifier A1 amplifies a potential difference between a voltage supply circuit that supplies a voltage higher than the source voltage of the transistor MN1 (ie, the ground voltage (GND)) and a source voltage of the transistor MN3. The first operational amplifier A1 includes a transistor with a low withstand voltage.

[0059] The gate-source voltage and the drain-source voltage of the transistor MN3 have the same values ​​as the gate-source voltage and the drain-source voltage of the transistor MN1, respectively. Therefore, between the drain and source of the transistor MN3, a current (Isns) proportional to the current (Ilsd) flowing between the drain and source of the transistor MN1 flows. In the comparative example, Isns=(1 / 1000)Ilsd.

[0060] The voltage supply circuit has a transistor MN4 and a constant current source CCR. The transistor MN4 includes, for example, a high withstand voltage N-channel MOS transistor of the same size as the transistor MN3. The transistor MN4 is provided between the non-inverting input terminal Tni of the first operational amplifier A1 and the ground voltage terminal Tgnd, and when the power supply voltage (VDD) is supplied to the gate, the transistor MN4 is always in an on state. That is, the transistor MN4 functions as a resistance element.

[0061] The constant current source CCR is provided between the non-inverting input terminal Tni of the first operational amplifier A1 and the power supply voltage terminal Tvdd, and supplies a current (Ishr) to the non-inverting input terminal Tni of the first operational amplifier A1. Therefore, a voltage higher than the ground voltage (GND) by a predetermined voltage is supplied to the non-inverting input terminal Tni of the first operational amplifier A1, and an intentional offset is applied.

[0062] Next, we will refer to Figure 3 and FIG. 4A to FIG. 4C Describe the mechanism by which the above nonlinear errors occur. Figure 3 is the equivalent circuit diagram, which takes into account Figure 2 Device structure of the current detection circuit in FIG. Figure 4A is a graph showing the relationship between the low-side driver current and the solenoid current. Figure 4B is a graph showing the relationship between the sense transistor current and the solenoid current. Figure 4C is a graph showing the relationship between the current detection error and the solenoid current.

[0063] Each of the low-side driver LSD and the sensing transistor STR includes a high-voltage MOS transistor. The high-voltage MOS transistor is roughly divided into a vertical MOS transistor and a horizontal MOS transistor. In the vertical MOS transistor, the gate electrode and the source electrode are formed in the surface of the semiconductor chip, and the drain electrode is formed in the back. In the horizontal MOS transistor, the gate electrode, the source electrode, and the drain electrode are formed in the surface of the semiconductor chip. In any of the vertical MOS transistor and the horizontal MOS transistor, in the structure of the high-voltage MOS transistor, a body diode as a parasitic diode is formed in parallel with the MOS transistor as the main body. Therefore, as Figure 3 As shown, the low-side driver LSD is configured by coupling the body diode BD in parallel with the transistor MN1. The sensing transistor STR is configured by coupling the body diode BDS in parallel with the transistor MN3.

[0064] The current (Ilsd) flowing in the low-side driver LSD is the sum of the current (Imos) flowing between the source and drain of the transistor MN1 and the current (Idi) flowing in the body diode BD. Figure 4A As shown, the current (Imos) increases in proportion to the solenoid current (Isln) (having linearity), while when the solenoid current (Isln) increases, the current (Idi) increases sharply (having non-linearity).

[0065] The sense current (Isns) flowing in the sense transistor STR is the sum of the current (Ismos) flowing between the source and drain of the transistor MN3 and the current (Idis) flowing in the body diode BDS. Figure 4B As shown, the current (Ismos) increases in proportion to the solenoid current (Isln) (having linearity), and when the solenoid current (Isln) increases, the current (Isdi) increases sharply (having nonlinearity).

[0066] Since the input of the first operational amplifier A1 is different from the ground voltage (GND) when an intentional offset is applied, the Vds of the low-side driver LSD and the Vds of the sensing transistor STR are not equal. Figure 4A and Figure 4B As shown in FIG. 1 , the ratio between the current (Idi) flowing in the body diode BD of the low-side driver LSD and the current (Isdi) flowing in the body diode BDS of the sensing transistor STR does not become a sensing ratio. As a result, as shown in FIG. Figure 4C As shown, when the solenoid current (Isln) is large, the current detection error (CDE) becomes nonlinear, and a nonlinear error occurs in the current detection circuit.

[0067] Since an intentional offset is applied, by shifting left Figure 4A The current (Ilsd) of the low-side driver LSD in the Figure 4B Graph of the current (Isns) of the sense transistor STR in FIG. The scale of the vertical axis is different. Therefore, the solenoid current (Isln) that starts the current flowing in the body diodes BD and BDS in the low-side driver LSD and the sense transistor STR is different.

[0068] As Figure 4C The current detection error (CDE) in the MOS transistor (MOS) is only constant and has an intentional offset that can be subtracted at a later stage. However, a MOS transistor with a body diode BD and BDS (MOS+diode) has a nonlinear curve, and it is difficult to subtract it at a later stage. Since the nonlinear curve fluctuates according to PVT (process conditions, power supply voltage conditions, and temperature conditions), it cannot be simply subtracted. For regenerative operation, the body diode BD is necessary. When the body diode BD as a parasitic diode is not formed in the transistor, a diode is provided externally. In this case as well, a similar nonlinear error occurs.

[0069] Therefore, the current detection circuit of the embodiment has a circuit for applying an intentional offset. Specifically, a first current source for applying, for example, a positive offset is coupled to one of the inputs of a differential amplifier of the current detection circuit, and a second current source for adding, for example, a negative offset is coupled to the output of the current detection circuit. A sense transistor coupled to the other input of the differential amplifier prevents reverse bias and prevents current measurement from being impossible. The offset is adjusted according to the current to be detected. Therefore, the nonlinear error of the current detection circuit using the sense transistor can be reduced.

[0070] Example

[0071] The semiconductor device of the example will be described. First, reference will be made to Figure 5 and Figure 6 An example of a usage mode of a semiconductor device is described. Figure 5 FIG. 1 is a diagram schematically showing an example of a driving system of a car in which the semiconductor device of the embodiment is incorporated. Figure 6 It is shown Figure 5 Block diagram of the configuration of the ECU.

[0072] like Figure 5 As shown, the drive system of the automobile 100 has an engine 101, a clutch 102, a transmission 103, differential gears 104a and 104b, drive wheels 105a and 105b, wheels 105c and 105d, a solenoid valve 106, shafts 107a to 107d, and an electronic control unit (ECU) 1.

[0073] As the engine 101, various engines that generate driving force can be used. The engine 101 transmits the generated driving force to the transmission 103 via the clutch 102. The transmission 103 transmits the driving force to the drive wheel 105a via the differential gear 104a and the shaft 107a, and transmits the driving force to the drive wheel 105b via the differential gear 104a and the shaft 107b. The wheel 105c is coupled to the differential gear 104b via the shaft 107c, and the wheel 105d is coupled to the differential gear 104b via the shaft 107d.

[0074] ECU 1 is a unit that controls the solenoid valve 106. Figure 6 As shown, the ECU 1 has a semiconductor device 10 and a microcontroller (MCU) 20 for controlling the semiconductor device 10. The semiconductor device 10 has a drive circuit 11, a current detection circuit 12, and a control unit 13 for controlling the drive circuit 11. By controlling the solenoid SLN (see Figure 7) to control the opening / closing of the solenoid valve 106. In this example, by opening / closing the solenoid valve 106, the position of the clutch 102 can be changed. That is, by controlling the opening / closing of the solenoid valve 106, the semiconductor device 10 can control the transmission of the driving force from the engine 101 to the transmission 103. The microcontroller 20 is a semiconductor integrated circuit device that has a CPU (not shown) and a memory (not shown) in a single semiconductor chip.

[0075] As will be described later, by precisely controlling the solenoid current, it is possible to reduce vibration when the transmission 103 switches gears. As a result, it is possible to realize a car with less vibration and a comfortable ride.

[0076] Next, we will refer to Figure 7 A semiconductor device 10 is described. Figure 7 It is shown Figure 6 A block diagram of the configuration of a semiconductor device in FIG. Figure 7 Solenoid SLN is also shown.

[0077] The semiconductor device 10 has a drive circuit 11 including transistors MN1 and MN2, a current detection circuit 12, and a control unit 13 including pre-drivers 111 and 112, an analog / digital converter (ADC) 114, a filter 115, and an adding circuit 116 on one semiconductor chip. For example, the semiconductor device 10 is configured as an electronic circuit formed on a silicon substrate or a compound semiconductor substrate. The semiconductor device 10 high-side drives a solenoid SLN.

[0078] The transistor MN1 is a low-side driver (first driver transistor) of the drive circuit 11 and includes a high-withstand voltage N-channel MOS transistor. The transistor MN2 is a high-side driver (second driver transistor) of the drive circuit 11 and includes a high-withstand voltage N-channel MOS transistor.

[0079] More specifically, in the transistor MN1, the drain is coupled to the external output terminal Tlo, the source is coupled to the ground voltage terminal Tgnd, and the pulse signal (VG1) from the control unit 13 is supplied to the gate. In the transistor MN2, the drain is coupled to the input voltage terminal Tvin, the source is coupled to the external output terminal Tlo, and the pulse signal (VG2) from the control unit 13 is supplied to the gate. The ground voltage (GND) is supplied to the ground voltage terminal Tgnd, and the input voltage (Vin) from the outside is supplied to the input voltage terminal Tvin. The external output terminal Tlo is coupled to one end of the solenoid SLN. The other end of the solenoid SLN is coupled to the ground voltage (GND).

[0080] In the drive circuit 11, the on / off of the transistors MN1 and MN2 are complementarily controlled while holding the dead time. For example, first, when the transistor MN2 is turned on and becomes conductive and the transistor MN1 is turned off and becomes non-conductive, the current flows from the input voltage terminal Tvin to the solenoid SLN via the transistor MN2 and the external output terminal Tlo. At this time, the current energy is stored in the solenoid SLN. Thereafter, when the transistor MN2 is turned off and the transistor MN1 is turned on, the current flowing from the input voltage terminal Tvin to the solenoid SLN via the transistor MN2 is interrupted. The solenoid SLN releases the stored current energy to the ground voltage terminal to which the solenoid SLN is coupled so as to maintain the current value of the current that has just flowed. Therefore, the current flows from the ground voltage terminal Tgnd to the solenoid SLN via the transistor MN1.

[0081] The current detection circuit 12 has a current detection circuit (HCDC) 12H for a high-side driver, a current detection circuit (LCDC) 12L for a low-side driver, and a synthesis unit 12S. The synthesis unit 12S includes a switch for switching the detection current of the current detection circuit 12H and the detection current of the current detection circuit 12L. The details of the current detection circuit 12L will be described later.

[0082] The control unit 13 has pre-drivers 111 and 112, a control circuit (CNTR) 113, an analog / digital converter (ADC) 114, a filter 115, and an adding circuit 116. The analog / digital converter 114 converts the detection result (voltage value) based on the current detected by the current detection circuit 12 into a digital detection signal. The digital detection signal averages the current detection result of one cycle (on / off of the transistor MN1) through the filter 115, increases / decreases the instruction value (INVL) from the MCU 20 through the adding circuit 116, and the result is sent to the control circuit 113.

[0083] The control circuit 113 monitors the currents of the transistors MN1 and MN2 of the drive circuit 11 by monitoring the detection result of the current detection circuit 12. The control circuit 113 performs PWM (pulse width modulation) control on the transistors MN1 and MN2 according to the monitoring result, thereby complementarily turning on / off the transistors MN1 and MN2 via the pre-drivers 111 and 112, and controls so that the currents of the transistors MN1 and MN2 (solenoid current (Isln)) converge to a target value.

[0084] As will be described later, by accurately detecting the current of the solenoid driver by the current detection circuit 12L, the solenoid current can be accurately controlled.

[0085] Next, we will refer to Figure 8 and Fig. 9 Describe the current sensing circuit for the low-side driver of the high-side driver. Figure 8 It is shown Figure 7 Circuit diagram of the current sensing circuit for the low-side driver. Fig. 9 It is shown Figure 8 A diagram of the relationship between the currents of the first current source and the second current source and the solenoid current.

[0086] like Figure 8 As shown, the current detection circuit 12L has transistors MN3, MN4, MP1 and MP2, a first operational amplifier A1, a first current source CS1, a second current source CS2 and a current source control circuit (CSCNTR) CSC. Figure 8 Also shown are a transistor MN1 on the low side and a transistor MN2 on the high side as part of the elements provided for the drive circuit 11, and a solenoid SLN of the electromagnetic valve 106. Figure 8 In the embodiment, body diodes as parasitic diodes formed in the transistors MN1, MN2, and MN3 are not shown. They are similarly not shown in the following embodiments and modifications.

[0087] In the current detection circuit 12L, the transistor MN3 is a sense transistor composed of a high-withstand voltage N-channel MOS transistor like the transistor MN1. For example, the transistor size of the transistor MN3 is 1 / N (for example, N=1000) of the transistor size of the transistor MN1.

[0088] The transistor MN3 is provided on a current path between a power supply voltage terminal Tvdd to which a power supply voltage (VDD) is supplied and a drain (terminal Td) of the transistor MN1 , and a pulse signal ( VG1 ) is supplied to a gate.

[0089] The first operational amplifier A1 has an inverting input terminal Tinv as a first terminal and a non-inverting input terminal Tni as a second terminal, and amplifies a potential difference between a voltage supply circuit OVL that supplies a voltage higher than a source voltage of the transistor MN1 (i.e., a ground voltage (GND)) and a source voltage of the transistor MN3. The first operational amplifier A1 includes a transistor with a low withstand voltage.

[0090] The gate-source voltage and the drain-source voltage of the transistor MN3 have the same values ​​as the gate-source voltage and the drain-source voltage of the transistor MN1, respectively. Therefore, between the drain and source of the transistor MN3, a current proportional to the current flowing between the drain and source of the transistor MN1 flows accurately (in the embodiment, a current of 1 / N (for example, N=1000)).

[0091] The output voltage of the first operational amplifier A1 is supplied to the gates of transistors MP1 and MP2. Transistor MP1 is composed of a low withstand voltage P-channel MOS transistor and is arranged in series with transistor MN3. Transistor MP2 includes a low withstand voltage P-channel MOS transistor and is provided on a current path between a power supply voltage terminal Tvdd and an output terminal Tout as a third terminal, which is different from the current path of transistor MP1. Therefore, a current proportional to the current flowing in transistor MP1 flows in transistor MP2. That is, transistors MP1 and MP2 form a current mirror circuit. The current mirror ratio is 1 / M.

[0092] As described above, a voltage supply circuit OVL is further provided, which supplies a voltage higher than the ground voltage (GND) to the non-inverting input terminal Tni coupled to the ground voltage terminal Tgnd as one of the two input terminals of the first operational amplifier A1. The voltage supply circuit OVL has a transistor (first shift transistor) MN4 and a first current source CS1.

[0093] The transistor MN4 includes, for example, a high withstand voltage N-channel MOS transistor of the same size as the transistor MN3. The transistor MN4 is provided between the non-inverting input terminal Tni of the first operational amplifier A1 and the ground voltage terminal Tgnd, and since the power supply voltage (VDD) is supplied to the gate, the transistor MN4 is always in an on state. That is, the transistor MN4 functions as a resistance element.

[0094] The first current source CS1 is provided between the non-inverting input terminal Tni of the first operational amplifier A1 and the power supply voltage terminal Tvdd, and supplies a current (Ish1) to the non-inverting input terminal Tni of the first operational amplifier A1. Therefore, a voltage higher than the ground voltage (GND) is supplied to the non-inverting input terminal Tni of the first operational amplifier A1.

[0095] By the influence of the offset voltage of the first operational amplifier A1, there is a case where the source voltage of the transistor MN3 should become lower than the drain voltage at first. However, if the voltage supply circuit OVL is not provided, the voltage of the inverting input terminal Tinv of the first operational amplifier A1 cannot become a negative voltage lower than the ground voltage (GND) supplied to the non-inverting input terminal Tni, so the source voltage of the transistor MN3 does not become lower than the expected value. As a result, current detection considering the influence of the offset voltage cannot be performed.

[0096] On the other hand, the current detection circuit 12L supplies a voltage higher than the ground voltage (GND) to the non-inverting input terminal Tni of the first operational amplifier A1 by using the voltage supply circuit OVL. Through this operation, the current detection circuit 12L can make the source voltage of the transistor MN3 lower than the drain voltage according to the influence of the offset voltage as expected, thereby performing current detection taking the offset voltage into consideration.

[0097] As described above, the transistor MN3 detects 1 / N (eg, N=1000) of the current flowing in the transistor MN1. The detected sense current (Isns) is sent back by the transistors MP1 and MP2 and output as the detection current (Isig).

[0098] The first current source CS1 and the second current source CS2 have the function of intentionally adding an offset to the detection current. Since the voltage at the virtual ground point of the first operational amplifier A1 rises when the current (Ish1) of the first current source CS1 is transferred to the transistor MN4, the current flowing in the transistor MN3 increases and a positive offset is applied. At this time, the voltage of the external output terminal Tlo is negative.

[0099] When a positive offset is applied by the current (Ish1) of the first current source CS1, the virtual ground of the first operational amplifier A1 becomes a positive voltage even when the solenoid current (Isln) does not flow (Isln=0A), so the current can be detected correctly.

[0100] Since the current (Ish2) of the second current source CS2 is subtracted from the detection current (Isig), a negative offset is applied. When Ish1 becomes 0A according to the increase of the solenoid current (Isln), no offset is applied and an error occurs. However, by applying a negative offset by the current (Ish2) of the second current source CS2, the error can be eliminated.

[0101] like Fig. 9As shown, the current amount (Ish1) of the first current source CS1 and the current amount (Ish2) of the second current source CS2 vary according to the solenoid current (Isln). When the solenoid current (Isln) is less than a predetermined value, the current amount (Ish1) of the first current source CS1 transfers current from the power supply voltage terminal Tvdd to the non-inverting input terminal Tinv. When the solenoid current (Isln) is equal to or greater than a predetermined value, the first current source CS1 does not transfer current. When the solenoid current (Isln) is less than a predetermined value, the second current source CS2 transfers current from the output terminal Tout to the ground voltage terminal Tgnd. When the solenoid current (Isln) is equal to or greater than a predetermined value, no current passes from the second current source CS2. In other words, when the solenoid current (Isln) is less than a predetermined value, the current amount (Ish1) of the first current source CS1 is greater than the current amount (Ish2) of the second current source CS2. When the solenoid current (Isln) is equal to or greater than a predetermined value, the current amount (Ish2) of the second current source CS2 is greater than the current amount (Ish1) of the first current source CS1.

[0102] The current source control circuit CSC is a circuit that detects the solenoid current (Isln) in a simple manner, and controls the current (Ish1) of the first current source CS1 and the current (Ish2) of the second current source CS2 based on the detected current. Specifically, when the solenoid current (Isln) is less than a predetermined value, the current source control circuit CSC controls so that the current amount (Ishl) of the first current source CS1 decreases as the solenoid current (Isln) increases. When the solenoid current (Isln) is equal to or greater than a predetermined value, the current source control circuit CSC controls so that the current is not passed to the first current source CS1; when the solenoid current (Isln) is less than a predetermined value, the current source control circuit CSC controls so that the current is not passed to the second current source CS2; and when the solenoid current (Isln) is equal to or greater than a predetermined value, the current source control circuit CSC controls so that the current of the second current source CS2 increases as the solenoid current (Isln) increases. The current detection accuracy of the current source control circuit CSC is lower than the current detection accuracy of the current detection circuit 12L.

[0103] Since the gain of the first operational amplifier A1 varies with the fluctuation of the intentional offset applied by the first current (Ish1) of the first current source CS1 and the current (Ish2) of the second current source CS2, it is designed so that the desired gain is obtained by adjusting the current mirror ratio of transistors MP1 and MP2.

[0104] Next, an example of a current ( Ish1 ) of the first current source CS1 , a current ( Ish2 ) of the second current source CS2 , and a current mirror ratio of the transistors MP1 and MP2 will be described.

[0105] In order to obtain the desired input / output characteristics in the current detection circuit 12L, it is necessary to appropriately design the current (Ish1) of the first current source CS1, the current (Ish2) of the second current source CS2, and the current mirror ratio of the transistors MP1 and MP2. The above currents satisfy the relationship of equations (1) to (4).

[0106] Isns=(I / N)Isln+Ish1 (1)

[0107] Ish1=K·max(Ish-αIsln,0) (2)

[0108] Ish2=max(αIsln-Ish,0) (3)

[0109] Isig=(Isns / M)–Ish2 (4)

[0110] Isns represents the current flowing in the transistor MN3, α and K represent appropriate constants, M represents the current mirror ratio of the transistors MP1 and MP2, N represents the sensing ratio of the transistor MN2 as the low-side driver and the transistor MN3 as the sensing transistor, Ish is an intentionally offset value and a current value (Isig) output from the current detection circuit when the solenoid current (Isln) is 0 A.

[0111] From the above equations (1) to (4), the following design values ​​are obtained.

[0112] Isig=(1 / MoN)Isln+Ish (5)

[0113] K=Mo (6)

[0114] M=Mo / (1+αMoN) (7)

[0115] α=Ish / Isln0 (8)

[0116] Mo represents the current gain of the sense amplifier, and Isln0 represents the solenoid current such that Ish=αIsln.

[0117] The intentional offset imposed by the current sensing circuit 12L must be removed at a later stage. Fig.10 Describe methods for removing intentional bias. Fig.10 is a circuit diagram of a current sensing circuit for a low-side driver including circuitry to cancel intentional offsets.

[0118] like Fig.10 As shown, the current detection circuit 12L is connected with Fig. 9A circuit obtained by adding a constant current source CC0 in parallel to the second current source CS2 of the current detection circuit 12L in FIG. In other words, the constant current source CC0 is provided between the output terminal Tout and the ground voltage terminal Tgnd. By subtracting the current (Ish0) in an analog manner, the intentional offset can be eliminated from the detection current (Isig). In this case, when Isln=0A, the current (Ish0) is the current (Ish1).

[0119] Next, the reason for using two current sources of the first current source CS1 and the second current source CS2 will be described by using the current detection circuit of the second comparative example. Fig.11 is a circuit diagram showing a current detection circuit of a second comparative example. Fig.12 It is shown Fig.11 A diagram of the current of the first current source in the current detection circuit. Fig.13A and Fig. 13B is a diagram showing the characteristics of the first current source in the case where the negative current source is not used. Fig.13A is a graph showing the current of the first current source, and Fig. 13B is a graph showing current detection error.

[0120] Fig.11 The current detection circuit 12LS of the second comparative example is configured by Figure 8 The current detection circuit 12LS of the example is obtained by removing the second current source CS2 from the current detection circuit 12L. When the current detection circuit 12LS includes only the first current source CS1, as shown in FIG. Fig.12 As shown, the current (Ish1) flowing in the first current source CS1 becomes negative at a certain midpoint. To achieve this, current must be drawn from the ground voltage terminal Tgnd, so a negative power supply is required. In order to achieve both positive and negative currents by using a circuit, two current mirrors must be prepared to handle these two signs. Therefore, two current sources are actually provided.

[0121] In the case where no negative power supply is used, such as Fig.13A As shown in FIG. 1 , the current (Ish1) of the first current source CS1 becomes zero at a certain midpoint. In this case, when the solenoid current (Isln) is large and the detection current value is bent, the intentional offset becomes zero. Therefore, as Fig. 13B As shown, a current detection error (CDE) occurs.

[0122] According to this example, also in the case where there is an offset in the first operational amplifier A1, a current near Isln=0A can be detected. When the current (Ish1) of the first current source CS1 is constant ( Figure 2In the first comparative example), a nonlinear error occurs when the solenoid current (Isln) is large. However, in this embodiment, since Ish1=0A when the solenoid current (Isln) is large, no nonlinear error occurs. In the case of using a detection resistor as in Patent Document 1, a large current must be passed to the detection resistor, and a low resistance value must be achieved with high precision. Therefore, the area of ​​the detection resistor becomes larger. For example, the size of the detection resistor becomes almost the same as the size of the driving transistor. Since the detection resistor is not used in this embodiment, a plurality of semiconductor devices 10 can also be formed in a single semiconductor chip.

[0123] Modification

[0124] Hereinafter, some representative modifications will be described. In the following description of the modification, symbols similar to those in the above-described embodiment may be used for parts having configurations and functions similar to those described in the embodiment. For this part, as long as it is technically consistent, the description in the above-described embodiment may be appropriately used. As long as it is technically consistent, a part of the embodiment and all or part of a plurality of modifications may be appropriately applied in combination.

[0125] First modification

[0126] Although the intentional offset is simulated in this example, the reference Fig.14 Another example (first modification) is described. Fig.14 is a circuit diagram showing a current detection circuit of a low-side driver of a first modification. Fig.14 Also shown is an analog / digital converter (AD converter) 114 as part of the components provided for the control unit 13 .

[0127] Since the detection current is AD converted and the current detection value is used as a digital value, such as Figure 7 As shown, the intentional offset can be eliminated by subtracting the intentional offset from the digital value obtained after AD conversion.

[0128] like Fig.14 As shown, the current detection circuit 12LA Figure 8 The current detection circuit 12L in the embodiment has a resistor Rout between the transistor MP1 (output terminal Tout) and the ground voltage terminal Tgnd. The current detection circuit 12LA converts the output detection current (Isig) into a voltage (Vout) through the resistor Rout. The control unit 13 of the first modification has an adding circuit 117 between the AD converter 114 and the filter 115. The AD converter 114 converts the voltage (Vout) into a digital value, and the adding circuit 117 subtracts a constant (CNST) corresponding to the intentional offset from the digital value to obtain a current detection value.

[0129] Second modification

[0130] Will refer to Fig.15 An example (second modification) in which an object is to be detected by the current source control circuit CSC is described. Fig.15 is a circuit diagram showing a current detection circuit of a low-side driver of a second modification.

[0131] In this example, the current (detection target) detected by the current source control circuit CSC is the solenoid current (Isl1). The detection target of the current source control circuit CSC of the current detection circuit 12LB of the second modification is the current (Ilsd) of the transistor MN1 as the low-side driver.

[0132] Regarding the case of detecting the current (Ilsd) of the transistor MN1, since the current (Ilsd) of the transistor MN1 is almost equal to the solenoid current (Isln), the current (Ish1) of the first current source CS1, the current (Ish2) of the second current source CS2, and the current mirror ratio between the transistors MP1 and MP2 can be obtained from equations (1) to (8) in a manner similar to this example.

[0133] The third modification

[0134] Will refer to Fig.16 An example (third modification) in which an object is to be detected by the current source control circuit CSC is described. Fig.16 is a circuit diagram showing a current detection circuit of a low-side driver of a third modification.

[0135] In this example, the current (detection target) detected by the current source control circuit CSC is the solenoid current (Isln).The detection target of the current source control circuit CSC of the current detection circuit 12LC of the third modification is the current (Isns) of the sense transistor.

[0136] The current (Ish1) of the first current source CS1, the current (Ish2) of the second current source CS2, and the current mirror ratio between the transistors MP1 and MP2 in the current detection circuit 12LC are different from those in the embodiment. The above currents have relations (11) to (14).

[0137] Isns=(I / N)Isln+Ish1 (11)

[0138] Ish1=K·max(Ish-βIsns,0) (12)

[0139] Ish2=max(βIsns-Ish,0) (13)

[0140] Isig=(Isns / M)–Ish2 (14)

[0141] β and K represent appropriate constants, M represents the current mirror ratio of transistors MP1 and MP2, N represents the sense ratio of transistor MN2 and transistor MN3 as a low-side driver, Ish is an intentionally offset value and is the current value (Isig) output from the current detection circuit when the solenoid current (Isln) is 0A.

[0142] From the above equations (11) to (14), the following design values ​​are derived.

[0143] Isig=(1 / MoN)IL+Ish (15)

[0144] K=Mo (16)

[0145] M=(1-β)Mo (17)

[0146] β=NIsh / Isln (18)

[0147] Mo represents the current gain of the sense amplifier, and Isln represents the solenoid current that makes Ish=βIsns.

[0148] The fourth modification

[0149] Will refer to Figures 17 to 19A to Fig.19C An example (fourth modification) of realizing a specific circuit by using MOS transistors as examples of the first current source CS1 and the second current source CS2 is described. Fig.17 is a circuit diagram showing a current detection circuit of a low-side driver of a fourth modification. Fig.18 It is shown Fig.17 A circuit diagram of a first current source and a second current source of a current detection circuit of a low-side driver. FIG. 19A to FIG. 19C is a graph showing the solenoid current vs. Fig.17 Diagram of the dependence of the current flowing in the current path in the current sensing circuit of the low-side driver. Fig.19A is a diagram showing the sensing current and the detection current, Fig.19B is a diagram showing a first replica current, a second replica current, and a current of a constant current source, Fig.19C is a graph showing the current of the first current source and the current of the second current source.

[0150] In the current detection circuit 12LD of the low-side driver of the fourth modification, the current source control circuit CSD does not directly detect the solenoid current (Isln), but detects the sensing current (Isns) as a copy of the solenoid current (Isln) as in the third modification. Specifically, the sensing current (Isns) is copied and the copy is used as the first copy current (Irep1) and the second copy current (Irep2). The current (Ish1) of the first current source CS1 and the current (Irep2) of the second current source CS2 are generated by adding / subtracting the first copy current (Irep1), the second copy current (Irep2) and the current (Icc) of the constant current source CC by the current mirror. Hereinafter, the details will be described.

[0151] Transistors MP1 and MP3 include low withstand voltage P-channel MOS transistors and are provided in series with transistor MN3. Transistors MP2 and MP4 include low withstand voltage P-channel MOS transistors and are provided in series on a current path between a power supply voltage terminal Tvdd and an output terminal Tout as another current path in transistors MP1 and MP3. A first bias voltage (Vbi1) is supplied to the gate of each of transistors MP3 and MP4. In addition, the gate of transistor MP2 is coupled to the gate of transistor MP1 and the output of the first operational amplifier A1. Therefore, in transistors MP2 and MP4, a current (Isig) proportional to the current (Isns) flowing in transistors MP1 and MP3 flows. That is, transistors MP1 to MP4 constitute a current mirror circuit. The current mirror ratio is 1 / M.

[0152] The current source control circuit CSD has transistors MP5 to MP8. Transistors MP5 and MP6 include low withstand voltage P-channel MOS transistors and are arranged in series on a current path between a power supply voltage terminal Tvdd and a first current source CS1, which is different from the current path of transistors MP1 and MP3. A first bias voltage (Vbi1) is supplied to the gate of transistor MP6. In addition, the gate of transistor MP5 is coupled to the gate of transistor MP1 and the output of the first operational amplifier A1. Therefore, in transistors MP5 and MP6, a first replica current (Irep1) proportional to the current (Isns) flowing in transistors MP1 and MP3 flows. That is, transistors MP1, MP3, MP5 and MP6 constitute a current mirror circuit. The current mirror ratio is 1 / ML.

[0153] Transistors MP7 and MP8 include low withstand voltage P-channel MOS transistors and are arranged in series on a current path between a power supply voltage terminal Tvdd and a second current source CS2 as another current path in transistors MP1 and MP3. The first bias voltage (VBI1) is supplied to the gate of transistor MP8. In addition, the gate of transistor MP7 is coupled to the gate of transistor MP1 and the output of the first operational amplifier A1. Therefore, in transistors MP7 and MP8, a second replica current (Irep2) proportional to the current (Isense) flowing in transistors MP1 and MP3 flows. That is, transistors MP1, MP3, MP7 and MP8 constitute a current mirror circuit. The current mirror ratio is 1 / ML.

[0154] like Fig.18 As shown, the first current source CS1 has transistors MP9 to MP12 and MN5 to MN8 and a constant current source CC. Transistors MP9 and MP10 are composed of low-voltage P-channel MOS transistors and are arranged in series with the constant current source CC. One end of the constant current source CC is coupled to the second ground voltage terminal Tgn2. Transistors MP11 and MP12 include low-voltage P-channel MOS transistors and are arranged in series on a current path between the power supply voltage terminal Tvdd and the output of the first current source CS1 (the non-inverting input terminal Tni of the first operational amplifier A1) as another current path in transistors MP9 and MP10. A second bias voltage (Vbi2) is supplied to the gate of each transistor MP10 and MP12. In addition, the gate of transistor MP11 is coupled to the gate of transistor MP9 and the drain of transistor MP10. Therefore, in transistor MP11, a current proportional to the current (Icc) of the constant current source CC flowing in transistors MP9 and MP10 flows. That is, transistors MP9 to MP12 constitute a current mirror circuit. The current mirror ratio is one, and a current (Icc) equivalent to the amount of current of the constant current source CC flows in the transistor MP11.

[0155] Transistors MN5 and MN6 include low withstand voltage N-channel MOS transistors and are arranged in series with transistor MP6. Transistors MN7 and MN8 include low withstand voltage N-channel MOS transistors and are arranged in series on a current path between the second ground voltage terminal Tgn2 and the drain of transistor MP11 as another current path of transistors MN5 and MN6. A third bias voltage (Vbi3) is supplied to the gate of each transistor MN6 and MN8. In addition, the gate of transistor MN5 is coupled to the gate of transistor MN7 and the drain of transistor MN6. Therefore, in transistors MN7 and MN8, a current proportional to the first replica current (Irep1) flowing in transistors MN5 and MN6 flows. That is, transistors MN5 to MN8 constitute a current mirror circuit. The current mirror ratio is 1, and the current (Ish1) of the first current source CS1 becomes a current (Ish1=Icc-Irep1) obtained by subtracting the first replica current (Irep1) from the current (Icc) of the constant current source CC.

[0156] The second current source CS2 has transistors MP13, MP14 and MN9 to MN16. Transistors MP13 and MP14 include low withstand voltage P-channel MOS transistors and are arranged in series with transistor MN10. A second bias voltage (Vbi2) is supplied to the gate of transistor MP14. In addition, the gate of transistor MP13 is coupled to the gate of transistor MP9 and the drain of transistor MP10. Therefore, in transistors MP13 and MP14, a current proportional to the current (Icc) flowing in transistors MP9 and MP10 flows. That is, transistors MP9, MP10, MP13 and MP14 constitute a current mirror circuit. The current mirror ratio is 1, and a current (Icc) equivalent to the current amount of the constant current source CC flows in transistor MP13.

[0157] Transistors MN9 and MN10 include low withstand voltage N-channel MOS transistors and are arranged in series with transistor MP14. Transistors MN 11 and MN12 include low withstand voltage N-channel MOS transistors and are arranged in series on a current path between the second ground voltage terminal Tgn2 and transistor MP8 as another current path for transistors MN9 and MN10. A third bias voltage (Vbi3) is supplied to the gate of each transistor MN10 and MN12. In addition, the gate of transistor MN11 is coupled to the gate of transistor MN9 and the drain of transistor MN10. Therefore, in transistors MN11 and MN12, a current proportional to the current (Icc) flowing in transistors MN9 and MN10 flows. That is, transistors MN 9 to MN12 constitute a current mirror circuit. The current mirror ratio is 1, and a current (Icc) equivalent to the current amount of the constant current source CC flows in transistor MN10.

[0158] Transistors MN13 and MN14 include low withstand voltage N-channel MOS transistors and are arranged in series with transistor MP8. Transistors MN15 and MN16 include low withstand voltage N-channel MOS transistors and are arranged in series on a current path between a second ground voltage terminal Tgn2 and a terminal Tcs2 as a third terminal as another current path for transistors MN13 and MN14. A third bias voltage (Vbi3) is supplied to the gate of each transistor MN14 and MN16. In addition, the gate of transistor MN15 is coupled to the gate of transistor MN13 and the drain of transistor MN14. Therefore, in transistors MN15 and MN16, a current proportional to the current (Irep2-Icc) flowing in transistors MN13 and MN14 flows. That is, transistors MN13 to MN16 constitute a current mirror circuit. The current mirror ratio is 1, and the current of the second current source CS2 is a current obtained by subtracting the current (Icc) of the constant current source CC from the second replica current (Irep2) (Ish2=Irep2-Icc).

[0159] As shown in FIG. 19, in the fourth modification, in the current mirror circuit, a copy of 1 / ML of the sense current (Isns) is generated as a first replica current (Irep1) and a second replica current (Irep2) ( Fig.19B ), and the replica is added to / subtracted from the current (Icc) of the constant current source CC, thereby generating a current (Isln) that fluctuates according to the solenoid current ( Fig.19C ), the current (Ish1) of the first current source CS1 and the current (Ish2) of the second current source CS2. Fig.19A As shown, the detection current (Isig) has linearity. The detection current (Isig) has an offset.

[0160] In order to obtain the desired input / output characteristics in the current detection circuit of the fourth modification, it is necessary to appropriately set the current (Ish1) of the first current source CS1, the current (Ish2) of the second current source CS2, and the current mirror ratio of the transistors MP1 and MP2. The above currents satisfy the relationship of equations (21) to (25).

[0161] Isns=(I / N)Isln+Ish1 (21)

[0162] Ish1=K·max(Ish-αIsln,0) (22)

[0163] Ish2=max(αIsln-Ish,0) (23)

[0164] Isig=(Isns / M)–Ish2 (24)

[0165] Irep=Irep1=Irep2

[0166] =(1 / LM)Isns (25)

[0167] α and K represent appropriate constants, M represents the current mirror ratio of transistors MP1 and MP2, N represents the sense ratio of transistor MN2 and transistor MN3 as a low-side driver, Ish is an intentionally offset value and a current value (Isig) output from the current detection circuit when the solenoid current (Isln) is 0A.

[0168] From the above equations (21) to (25), the following design values ​​are derived.

[0169] Isig=(1 / MoN)Isln+Ish (26)

[0170] K=Mo (27)

[0171] L=Isln0 / (MoN·Ish)+1 (28)

[0172] M=Mo / (1+αMoN) (29)

[0173] Mo represents the current gain of the sense amplifier, and Isln0 represents the solenoid current that makes Ish=Irep.

[0174] In the fourth modification, the main current source control circuit CSD and the current detection circuit commonly use the sense transistor (transistor MN3 ), the first operational amplifier A1 , and the transistors MP1 and MP2 , so that the area and the consumption current can be reduced.

[0175] Fifth modification

[0176] exist Figure 8 In the current detection circuit 12L of the example, when the transistor MN2 as the high-side driver is turned on, the transistor MN3 is turned off. At this time, the load condition of the first operational amplifier A1 is different from the case where the transistor MN1 as the low-side driver is turned on. As a result, there is a possibility that the response of the current detection circuit when the transistor MN1 is turned on may be slow due to transient response. Figure 20 to Figure 22 A current detection circuit of a low-side driver of a fifth modification which improves this is described. Fig. 20 is a circuit diagram showing a current detection circuit of a low-side driver of a fifth modification. Fig.21 It is shown in Fig. 20 A diagram of the current path of the low-side driver current detection circuit in the case where the low-side driver is turned on. Fig. 22 It is shown in Fig. 20Diagram of the current path of the high-side driver's current detection circuit when the low-side driver is turned on.

[0177] like Fig. 20 As shown, the fifth modified current detection circuit 12LE further has a transistor (switching transistor) MN17 for transferring the current to the transistor MN1 during the period when the transistors MN1 and MN3 are turned off. Figure 8 An example of a current detection circuit 12L.

[0178] The transistor MN17 includes, for example, a high withstand voltage N-channel MOS transistor of the same size as the transistor MN3. The transistor MN17 is arranged between the inverting input terminal Tinv of the first operational amplifier A1 and the ground voltage terminal Tgnd. The on / off of the transistor MN17 is controlled by a signal (VDMY), and the phase of the signal (VDMY) is the same as the pulse signal (VG2) which is the inverted signal of the pulse signal (VG1). That is, the on / off of the transistor MN17 is controlled complementarily with respect to the transistors MN2 and MN3. The resistance value of the transistor MN17 when it is turned on represents the same value as the resistance value of the transistor MN3 when it is turned on. Since the other configurations of the current detection circuit 12LE are similar to the configurations of the current detection circuit 12L, they are not described repeatedly.

[0179] When transistor MN1 is turned on, Fig.21 As shown, transistor MN3 is also turned on and current flows in transistor MN3. When transistor MN2 is turned on, as shown in FIG. Fig. 22 As shown, the transistor MN17 is also turned on and current flows in the transistor MN17.

[0180] Therefore, even when the transistor MN3 is turned off, the transistor MN17 is turned on, so the load of the resistance element of the first operational amplifier A1 remains constant. That is, the load condition of the first operational amplifier A1 when the transistor MN1 is turned on and the load condition when the transistor MN2 is turned on can be made the same by the transistor MN17. As a result, the setup time of the first operational amplifier A1 after the on / off switching of the transistor MN3 can be reduced, so that high-speed operation can be achieved.

[0181] Sixth modification

[0182] Although the current is folded back by transistors MP1 and MP2 in the embodiment, the sense current is a current source (PMOS output). The sense current can be configured as a current sink (NMOS output). Fig.23 This configuration example (sixth modification) is described. Fig.23 is a circuit diagram showing a current detection circuit of a low-side driver of a sixth modification.

[0183] In the sixth modified current detection circuit 12LF, the output voltage of the first operational amplifier A1 is supplied to the gate of the transistor MN21 as a current control transistor. The transistor MN21 includes a low withstand voltage N-channel MOS transistor and is arranged in series with the transistor MN3 on the current path between the output terminal Tout and the terminal Td. With this configuration, the detection current (Isig) can be configured as a sink current.

[0184] Seventh modification

[0185] Although the current detection circuit of the low-side driver has been described in the foregoing example and the first to sixth modifications, an example of a current detection circuit of a high-side driver (seventh modification) will be described with reference to FIG. 4 . Fig.24 is a circuit diagram showing a current detection circuit of a high-side driver of a seventh modification.

[0186] The current detection circuit 12HG of the seventh modified high-side driver is obtained by replacing the N-channel MOS transistors in the transistors MN3, MN4 and MN21 of the current detection circuit 12LF of the sixth modified low-side driver with PMOS-channel MOS transistors, and replacing the N-channel MOS transistors constituting the first operational amplifier A1, the first current source CS1 and the second current source CS2 with PMOS-channel MOS transistors.

[0187] like Fig.24 As shown, the current detection circuit 12HG has transistors MP21, MP23 and MP24, a second operational amplifier A2, a third current source CS3, a fourth current source CS4 and a current source control circuit CSC. The high-side driver of the seventh modified drive circuit 11 includes a P-channel MOS transistor MP22.

[0188] In the current detection circuit 12HG, the transistor MP23 is a sensing transistor including a high withstand voltage P-channel MOS transistor, which is the same as in the transistor MP22. For example, the transistor size of the transistor MP23 is 1 / N (for example, N=1000) of the transistor size of the transistor MP22.

[0189] The transistor MP23 is provided on the current path between the inverting input terminal Tinv of the second operational amplifier A2 and the drain (terminal Td) of the transistor MP22, and the pulse signal (VG22) is supplied to the gate. The pulse signal (VG22) is a signal of the same phase as the pulse signal (VG1) except for the dead time.

[0190] The second operational amplifier A2 amplifies a potential difference between a voltage supply circuit OVH that supplies a voltage lower than the source voltage of the transistor MP22 (ie, the input voltage (Vin)) and a source voltage of the transistor MP23. The second operational amplifier A2 includes a transistor with a low withstand voltage.

[0191] The gate-source voltage and the drain-source voltage of the transistor MP23 have the same values ​​as the gate-source voltage and the drain-source voltage of the transistor MP22, respectively. Therefore, between the drain and source of the transistor MP23, a current (in this embodiment, a current of 1 / N (for example, N=1000)) flows which is exactly proportional to the current flowing between the drain and source of the transistor MP22.

[0192] The output voltage of the second operational amplifier A2 is supplied to the gate of a transistor MP21 as a current control transistor. The transistor MP21 includes a low withstand voltage P-channel MOS transistor and is provided in series with the transistor MP23 on a current path between the output terminal Tout and the terminal Td.

[0193] As described above, a voltage supply circuit OVH is further provided, which supplies a voltage lower than the input voltage (Vin) to the non-inverting input terminal Tni coupled to the input voltage terminal Tvin as one of the two input terminals of the second operational amplifier A2. The voltage supply circuit OVH has a transistor MP24 and a first current source CS1.

[0194] The transistor MP24 includes, for example, a high withstand voltage P-channel MOS transistor of the same size as the transistor MP23. The transistor MP24 is provided between the non-inverting input terminal Tni and the input voltage terminal Tvin of the second operational amplifier A2, and when the ground voltage (GND) is supplied to the gate, the transistor MP24 is always in an on state. That is, the transistor MP24 functions as a resistance element.

[0195] The third current source CS3 is provided between the input voltage terminal Tvin and the non-inverting input terminal Tni of the second operational amplifier A2, and draws a current (Ish2) from the non-inverting input terminal Tni of the second operational amplifier A2. Therefore, a voltage lower than the input voltage (Vin) by a predetermined voltage is supplied to the non-inverting input terminal Tni of the second operational amplifier A2.

[0196] By the influence of the offset voltage of the second operational amplifier A2, there is a case where the source voltage of the transistor MP23 should become higher than the drain voltage at first. However, if the voltage supply circuit OVH is not provided, the voltage of the inverting input terminal Tinv of the second operational amplifier A2 cannot become a voltage higher than the input voltage (Vin) supplied to the non-inverting input terminal Tni, so that the source voltage of the transistor MP23 does not become higher than the expected value. As a result, current detection considering the influence of the offset voltage cannot be performed.

[0197] On the other hand, the current detection circuit 12HG supplies a voltage lower than the input voltage (Vin) to the non-inverting input terminal Tni of the first operational amplifier A1 by using the voltage supply circuit OVL. Through this operation, the current detection circuit 12HG can make the source voltage of the transistor MP23 higher than the drain voltage as expected according to the influence of the offset voltage, thereby performing current detection considering the offset voltage.

[0198] As described above, the transistor MP23 detects 1 / N (for example, N=1000) of the current flowing in the transistor MP22. The detected current (Isns) is output as a detection current (Isig) as a sink current through the transistor MP21.

[0199] The third current source CS3 and the fourth current source CS4 have the function of intentionally adding an offset to the detection current. Since the voltage at the virtual reference point of the second operational amplifier A2 drops when the current (Ish3) of the third current source CS3 is delivered to the transistor MP24, the current flowing in the transistor MP23 decreases / increases, and a negative offset is applied.

[0200] When a negative offset is applied by the current (Ish3) of the third current source CS3, even when the solenoid current (Isln) does not flow (Isln=0A), the virtual reference point of the second operational amplifier A2 becomes a voltage lower than the input voltage (Vin), so the current can be detected correctly.

[0201] Since the current (Ish4) of the fourth current source CS4 is added to the detection current (Isig), a positive offset is applied. When Ish1 becomes 0A according to the increase of the solenoid current (Isln), no offset is applied and an error occurs. However, by applying a positive offset of the current (Ish4) of the fourth current source CS4, the error can be eliminated.

[0202] Eighth modification

[0203] Will refer to Figure 25 to Figure 27 An example (eighth modification) of a current detection circuit applicable to both high-side driving and low-side driving is described. Fig.25is a circuit diagram showing a current detection circuit of a low-side driver of an eighth modification. Fig.26 It is shown Fig.25 Diagram of the current path of the current detection circuit in the high-side drive state. Fig. 27 It is shown Fig.25 Diagram of the current path of the low-side current detection circuit in the low-side drive state

[0204] like Fig.25 As shown in Figure 8 The current detection circuit 12L of the embodiment of the eighth modified current detection circuit 12LH is obtained by adding: a transistor (second sensing transistor) MN23 as a sensing transistor for low-side driving, transistors (second shift transistors) MN24 and MN25 constituting a part of the voltage supply circuit for low-side driving, and a transistor MN26. The transistor MN3 operates in high-side driving and can be turned on, and the transistor MN23 operates in low-side driving and can be turned on. The current detection circuit 12L can perform a high-side driving state ( Figure 1B ) current detection and low-side drive state as the second mode ( Figure 1C ) current detection.

[0205] Transistor MN23 includes, for example, a high withstand voltage N-channel MOS transistor of the same size as transistor MN3. Transistor MN23 is arranged between the inverting input terminal Tinv of the first operational amplifier A1 and the ground voltage terminal Tgnd. Transistor MN23 is electrically coupled to transistor MN3 at the contact Ts. The on / off of transistor MN23 is controlled by a signal (VLD) having the same phase as the pulse signal (VG1). The signal (VLD) becomes high only in the low-side drive state. The on / off of transistor MN3 is controlled by a signal (VHD) having the same phase as the pulse signal (VG1). The signal (VHD) becomes high only in the high-side drive state.

[0206] Transistors MN24 and MN25 include, for example, high-voltage N-channel MOS transistors whose gate width is twice the gate width of transistor MN4. Transistors MN24 and MN25 are provided so as to form a current path in series between the non-inverting input terminal Tni of the first operational amplifier A1 and the drain of the transistor MN1, and a signal (LSC) indicating a low-side drive state is supplied to the gate. By coupling transistors MN24 and MN25 in series, current can be prevented from flowing via the body diodes of transistors MN24 and MN25. In the case where transistors MN24 and MN 25 are formed by high-voltage N-channel MOS transistors, the gate width of the high-voltage N-channel MOS transistor is twice the gate width of transistor MN4, and the series resistance of transistors MN24 and 25 can be made equivalent to the resistance of transistor MN4.

[0207] The transistor MN26 includes, for example, a high withstand voltage N-channel MOS transistor of the same size as the transistor MN4. The transistor MN26 is provided between the source of the transistor MN24, the source of the transistor MN25 and the ground voltage terminal Tgnd, and a signal (HSC) indicating a high-side drive state is supplied to the gate.

[0208] In a manner similar to the embodiment, the transistor MN4 is provided between the non-inverting input terminal Tni of the first operational amplifier A1 and the ground voltage terminal Tgnd, and a signal (HSC) indicating a high-side drive state is supplied to a gate.

[0209] like Fig.26 As shown in FIG. 1 , when transistor MN1 is turned on in the high-side driving state, transistors MN3 and MN4 are turned on and transistors MN23 to MN25 are turned off, and the same Figure 8 The coupling relationship of the current detection circuit 12L is similar to that of the transistor MN26, and similar operations are performed. In this state, the transistor MN26 is turned on, and the source of the transistor MN24 and the source of the transistor MN25 become the ground voltage (GND).

[0210] On the other hand, in the high-side driving state, when the transistor MN2 is turned on, the transistor MN4 is turned on, and the transistor MN3 and the transistors MN23 to MN25 are turned off.

[0211] like Fig. 27As shown in , when the transistor MN1 is turned on in the low-side driving state, the transistors MN23 and MN25 are turned on, and the transistors MN3, MN4 and MN26 are turned off. Through the above, the first operational amplifier A1 amplifies the potential difference between the voltage supply circuit OVLL and the drain voltage of the transistor MN23, and the voltage supply circuit OVLL supplies a voltage higher than the drain voltage of the transistor MN1. The voltage supply circuit OVLL includes a first current source CS1 and transistors MN24 and MN25.

[0212] The gate-source voltage and the drain-source voltage of the transistor MP23 have the same values ​​as the gate-source voltage and the drain-source voltage of the transistor MP22, respectively. Therefore, between the drain and source of the transistor MP23, a current (in this embodiment, a current of 1 / N (for example, N=1000)) flows which is exactly proportional to the current flowing between the drain and source of the transistor MP22.

[0213] In the low-side driving state, when the transistor MN2 is turned on, the transistors M3 , MN4 , and MN23 to MN26 are turned off.

[0214] In this modification, by switching on the transistor, current detection in both the high-side drive and the low-side drive can be performed.

[0215] By eliminating transistors MN3, MN4 and MN26 associated with the modified high-side driver, a low-side current sensing circuit for the low-side driver can be obtained.

[0216] Ninth modification

[0217] When transistor MN2, which acts as a high-side driver, is Fig.25 When the high-side drive and low-side drive of the eighth modified current detection circuit 12LH are turned on, the transistors MN3 and MN23 are turned off. At this time, in a similar manner to the current detection circuit 12L of the present embodiment, the load condition of the first operational amplifier A1 is different from the load condition in the state where the transistor MN1 as the low-side driver is turned on. As a result, there is a possibility that the response of the current detection circuit when the transistor MN1 is turned on may become slow due to transient response. Figure 28 to Figure 32 A ninth modified low-side current detection circuit for solving this problem is described. Fig.28 is a circuit diagram showing a low-side current detection circuit of a ninth modification. Fig.29 It is shown Fig.28 Diagram of the current path of the low-side current sensing circuit in the high-side driving state. Fig.30 It is shown Fig.28 Diagram of the current path of the low-side current sensing circuit in the high-side driving state. Fig.31 It is shown Fig.28Diagram of the current path of the low-side current detection circuit in the low-side drive state. Fig.32 It is shown Fig.28 Diagram of the current path of the low-side current detection circuit in the low-side drive state.

[0218] like Fig.28 As shown, by further Fig.25 The current detection circuit 12LH of the eighth modification is added with a transistor (switching transistor) MN17 for passing a current in a period in which the transistors MN1, MN3, and MN23 are turned off, obtaining a current detection circuit 12LI of a ninth modification.

[0219] Transistor MN17 includes, for example, a high-voltage N-channel MOS transistor of the same size as transistor MN3. Transistor MN17 is arranged between the inverting input terminal Tinv of the first operational amplifier A1 and the ground voltage terminal Tgnd. The on / off of transistor MN17 is controlled by a signal (VDMY) having the same phase as the pulse signal (VG2), and the pulse signal (VG2) serves as an inverted signal of the pulse signal (VG1). That is, the on / off of transistor MN17 is controlled complementarily with respect to transistors MN2, MN3 and MN23. The resistance value of transistor MN17 when it is turned on represents the same value as the resistance value of transistor MN3 when it is turned on. Since the other configurations of the current detection circuit 12LI are similar to the configurations of the current detection circuit 12LH, they are not described again.

[0220] like Fig.29 As shown in FIG. 1 , when the transistor MN1 is turned on in the high-side driving state, current flows in the transistor MN3. Fig.30 As shown, when the transistor MN2 is turned on in the high-side driving state, current flows in the transistor MN17. Since the transistor MN17 is turned on even when the transistor MN3 is turned off, the load of the resistance element of the first operational amplifier A1 remains constant. That is, the load condition of the first operational amplifier A1 when the transistor MN1 is turned on and the load condition of the first operational amplifier A1 when the transistor MN2 is turned on can be made the same by the transistor MN17. As a result, the setup time of the first operational amplifier A1 after the on / off switching of the transistor MN3 can be reduced, so that high-speed operation can be achieved.

[0221] like Fig.31 As shown in FIG. 1 , when transistor MN1 is turned on in the low-side state, current flows in transistor MN23. Fig.32As shown, when the transistor MN2 is turned on in the low-side state, current flows in the transistor MN17. Since the transistor MN17 is turned on even when the transistor MN23 is turned off, the load of the resistance element through the first operational amplifier A1 is kept constant. That is, the load condition of the first operational amplifier A1 when the transistor MN1 is turned on and the load condition of the first operational amplifier A1 when the transistor MN2 is turned on can be made the same by the transistor MN17. As a result, the setup time of the first operational amplifier A1 after the on / off switching of the transistor MN23 can be reduced, so that high-speed operation can be achieved.

[0222] By eliminating transistors MN3, MN4 and MN26 associated with the modified high-side driver, a low-side current sensing circuit for the low-side driver can be obtained.

[0223] Although the present invention achieved by the inventors herein is specifically described above based on the embodiments, examples, and modifications, it is apparent that the present invention is not limited to the aforementioned embodiments, examples, and modifications, but may be variously changed without departing from the gist thereof.

[0224] For example, a current detection circuit of a solenoid driver has been described in the examples, but the present invention is not limited to this circuit. A current detection circuit of a DC-DC converter or a driver such as a motor driver may also be employed.

[0225] Although the example in which the drive circuit is constituted by a MOS transistor has been described in the examples, the present invention is not limited to this example. The drive circuit may include an IGBT (Insulated Gate Bipolar Transistor). In this case, the sensing transistor also includes an IGBT.

[0226] Although an example in which a drive circuit is formed by the same semiconductor chip as the current detection circuit and the control unit has been described in the examples, the present invention is not limited to this example. For example, the drive circuit may be formed in a semiconductor chip different from the semiconductor chip of the current detection circuit and the control unit. It is also possible to form the drive circuit and the sensing transistor in the same semiconductor chip, and to form the current detection circuit and the control unit except the sensing transistor on the same semiconductor chip.

[0227] Although the object to be detected by the current source control circuit CSC is one in the example and the second modification and the third modification, the number of the objects to be detected can be multiple. That is, it can be at least one of the solenoid current (Isln), the current of the low-side driver and the current of the sensing transistor.

[0228] Although an example has been described in which each of the first operational amplifier A1 and the second operational amplifier A2 is configured by a low withstand voltage transistor, a high withstand voltage transistor may also be included. Although an example has been described in which the transistors MP1 to MP14 and MP21 are configured by a low withstand voltage P-channel MOS transistor, a high withstand voltage P-channel MOS transistor may also be included. Although an example has been described in which the transistors MN5 to MN16 and MN21 are configured by a low withstand voltage N-channel MOS transistor, they may include a high withstand voltage N-channel MOS transistor.

Claims

1. A semiconductor device, comprising: Driving circuit, driving load; and a current detection circuit for detecting the current flowing in the driving circuit, Wherein, the driving circuit comprises: an external output terminal to which the load is coupled; A first voltage terminal is supplied with an input voltage from the outside; a first drive transistor having a first electrode coupled to the external output terminal and a second electrode coupled to the first voltage terminal; and Wherein, the current detection circuit comprises: a power supply voltage terminal to which a power supply voltage is supplied; a differential amplifier that amplifies a potential difference between a voltage at the first terminal and a voltage at the second terminal; a first sensing transistor that transmits a sensing current between the first electrode and the first terminal of the first driving transistor; a voltage supply circuit for supplying a voltage higher than a ground voltage to the second terminal; The third terminal outputs the detection current; a first current source coupled to the third terminal; and a control circuit for controlling a supply voltage of the voltage supply circuit and a current of the first current source, and wherein the detection current detected by the current detection circuit is a current obtained by subtracting the current of the first current source from the current based on the sense current, The current detection circuit further includes a fourth current source coupled between the third terminal and the first voltage terminal, and a current of the fourth current source is subtracted from the detection current.

2. The semiconductor device according to claim 1, The voltage supply circuit has a second current source coupled between the power supply voltage terminal and the second terminal, and a fourth transistor coupled between the first voltage terminal and the second terminal, in, When the current based on the current flowing in the load is less than a predetermined value, the current of the second current source is greater than the current of the first current source, and when the current based on the current flowing in the load is equal to or greater than the predetermined value, the current of the first current source is greater than the current of the second current source.

3. The semiconductor device according to claim 2, wherein the control circuit detects a current flowing from the external output terminal to the load, the second current source passes current from the power supply voltage terminal to the second terminal when the current based on the current flowing in the load is less than the predetermined value, and does not pass current when the current based on the current flowing from the external output terminal to the load is equal to or greater than the predetermined value, and in, When the current based on the current flowing from the external output terminal to the load is less than the predetermined value, the first current source does not pass the current, And, when a current based on a current flowing from the external output terminal to the load is equal to or greater than the predetermined value, the first current source transfers a current from the third terminal to the first voltage terminal.

4. The semiconductor device according to claim 2, in, when the current based on the current flowing from the external output terminal to the load is less than a predetermined value, the control circuit controls so as to increase the current based on the current flowing from the external output terminal to the load and to decrease the current of the second current source, and when the current based on the current flowing from the external output terminal to the load is equal to or greater than the predetermined value, the control circuit controls so as not to pass the current to the second current source, and Wherein, when the current based on the current flowing from the external output terminal to the load is less than the predetermined value, the current source control circuit controls so as not to pass the current to the first current source, and when the current based on the current flowing from the external output terminal to the load is equal to or greater than the predetermined value, the current source control circuit controls so as to increase the current based on the current flowing from the external output terminal to the load and increase the current of the first current source. 5 . The semiconductor device according to claim 1 , wherein the load is a solenoid having one end coupled to the external output terminal and having the other end supplied with a ground voltage. 6 . The semiconductor device according to claim 1 , wherein a current based on a current flowing from the external output terminal to the load is a current flowing in the first drive transistor. 7 . The semiconductor device according to claim 1 , wherein a current based on a current flowing from the external output terminal to the load is a current flowing in the first sensing transistor.

8. The semiconductor device according to claim 2, further comprising a fourth terminal to which the first voltage is supplied, wherein the control circuit generates a first replica current and a second replica current as copies of the current flowing in the first sensing transistor, The control circuit has a third current source. wherein the second current source is coupled between the power supply voltage terminal and the fourth terminal and generates a current by subtracting the first replica current from the current of the third current source, and The first current source is coupled between the third terminal and the fourth terminal, and generates a current by adding the second replica current to a current of the third current source.

9. The semiconductor device according to claim 1, further comprising: a drive circuit control unit, which controls the drive circuit based on the detection current, The drive circuit control unit includes an analog / digital converter for converting the detection current into a digital value.

10. The semiconductor device according to claim 9, wherein The control unit further includes an adding circuit that subtracts a value corresponding to a voltage value supplied from the voltage supply circuit from the digital value.

11. The semiconductor device according to claim 1, The driving circuit comprises: Input voltage terminal, to which input voltage is supplied, a second driving transistor, setting a conducting state or a non-conducting state between the external output terminal and the input voltage terminal, The current detection circuit further includes a switch transistor, the switch transistor sets a conducting state or a non-conducting state between the first terminal and the first voltage terminal, and Wherein, when the second driving transistor is in an on state, the switch transistor is in an on state.

12. The semiconductor device according to claim 1, in, The current detection circuit also includes: a first transistor coupled to form a current path between the power supply voltage terminal and the first terminal; and a second transistor coupled to form a current path between the power supply voltage terminal and the third terminal, and The output of the differential amplifier is coupled to the gate of the first transistor and the gate of the second transistor, and the first transistor and the second transistor form a current mirror circuit.

13. The semiconductor device according to claim 1, in, The current detection circuit also includes a third transistor coupled to form a current path between the first terminal and the third terminal, and The output of the differential amplifier is coupled to the gate of the third transistor.

14. The semiconductor device according to claim 1, in, The current detection circuit also includes a second sense transistor that passes a sense current between the first terminal and the first voltage terminal. Wherein, the voltage supply circuit comprises: a first shift transistor that sets a conducting state or a non-conducting state between the second terminal and the first voltage terminal; and a second shift transistor that sets a conducting state or a non-conducting state between the second terminal and the first drive transistor, and Wherein, when the semiconductor device operates in a first mode, the first shift transistor enters the on state, and when the semiconductor device operates in a second mode, the second shift transistor enters the on state. 15 . The semiconductor device according to claim 14 , wherein in the first mode, one end of a solenoid is coupled to the external output terminal, and a ground voltage is supplied to the other end of the solenoid. 16 . The semiconductor device according to claim 14 , wherein in the second mode, one end of a solenoid is coupled to the external output terminal, and a power supply voltage is supplied to the other end of the solenoid.

17. The semiconductor device according to claim 14, The driving circuit comprises: Input voltage terminal, to which input voltage is supplied, a second driving transistor, setting a conducting state or a non-conducting state between the external output terminal and the input voltage terminal, The current detection circuit further includes a switching transistor, the switching transistor is used to set a conducting state or a non-conducting state between the first terminal and the first voltage terminal, and Wherein, when the second driving transistor is in the on-state, the switching transistor is set to the on-state.

18. A current detection method, comprising the following steps: delivering current to a first drive transistor having a first electrode and a second electrode, the first electrode being coupled to an external output terminal to which a load is coupled, and the second electrode being coupled to a first voltage terminal to which an input voltage from the outside is supplied; passing a sense current to a first sense transistor coupled between a first terminal of a differential amplifier and the first electrode of the first drive transistor, the differential amplifier amplifying a potential difference between a voltage at the first terminal and a voltage at a second terminal; supplying a voltage higher than a ground voltage to the second terminal; passing current from a first current source to the first voltage terminal, the first current source being coupled to a third terminal outputting a detection current, a fourth current source being coupled between the third terminal and the first voltage terminal; detecting a value of a current flowing in the first drive transistor from which the detection current is obtained by subtracting a current of the first current source from a current based on the sense current; as well as A current of the fourth current source is subtracted from the detection current.

19. A load driving system, comprising: load; A semiconductor device driving the load; and a semiconductor integrated circuit device, controlling said semiconductor device, The semiconductor device comprises: A drive circuit having: an external output terminal to which the load is coupled; a first voltage terminal to which an input voltage from the outside is supplied; an input voltage terminal to which an input voltage is supplied; a first drive transistor having a first electrode coupled to the external output terminal and a second electrode coupled to the first voltage terminal; and a second drive transistor coupled to the external output terminal and the input voltage terminal; and A current detection circuit, comprising: a power supply voltage terminal to which a power supply voltage is supplied; a differential amplifier to amplify a potential difference between a voltage of a first terminal and a voltage of a second terminal; a first sensing transistor to transfer a sensing current between the first terminal and the first electrode of the first driving transistor; a voltage supply circuit to supply a voltage higher than a ground voltage to the second terminal; a third terminal to output a sensing current; a first current source coupled between the third terminal and the first voltage terminal; and a control circuit to control a voltage of the voltage supply circuit and a current of the first current source, and wherein the detection current detected by the current detection circuit is a current obtained by subtracting a current of the first current source from a current based on the sense current, The current detection circuit further includes a fourth current source coupled between the third terminal and the first voltage terminal, and a current of the fourth current source is subtracted from the detection current.

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