Driving device and display device including the driving device

Abstract

The present disclosure relates to a driving device and a display device including the driving device, wherein the driving device includes: an output unit, the output unit being configured to supply a first voltage or a second voltage lower than the first voltage to an output terminal in response to a voltage of a first node and a voltage of a second node; a first driver, the first driver being configured to control the voltage of the second node in response to a signal of a first input terminal and a signal of a second input terminal; a second driver, the second driver being configured to control the voltage of the first node in response to a voltage of a third input terminal and the voltage of the second node; and a first transistor, the first transistor being configured to apply a third voltage lower than the first voltage to the first node or the second node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0065538 filed on June 7, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present invention relates to a driving device and a display device comprising the driving device. Background Art

[0004] Research is being conducted on minimizing battery consumption of various widely used electronic devices such as smart phones, notebook computers, or tablet computers (PCs), etc.

[0005] Most of these electronic devices include a display panel. By minimizing the power consumption of the display panel, the battery consumption of these electronic devices can be minimized. In order to reduce the power consumption of the display panel, the display panel can be driven at a relatively low frequency.

[0006] When driving a display panel by a low-frequency driving method, a strong and reliable driving part should be used. Summary of the invention

[0007] The present invention provides a driving device, which can improve the display quality of a display device, reduce the power consumption of the display device, and stably operate the display device.

[0008] An exemplary embodiment of the present invention provides a driving device, which includes: an output unit, which is configured to supply a first voltage or a second voltage lower than the first voltage to an output terminal in response to a voltage of a first node and a voltage of a second node; a first driver, which is configured to control the voltage of the second node in response to a signal of a first input terminal and a signal of a second input terminal; a second driver, which is configured to control the voltage of the first node in response to a voltage of a third input terminal and the voltage of the second node; and a first transistor, which is configured to apply a third voltage lower than the first voltage to the first node or the second node.

[0009] The first input terminal can receive a signal output from an output terminal of a previous stage or a start signal, the second input terminal can receive a first clock signal, and the third input terminal can receive a second clock signal, the second clock signal having the same time period as the first clock signal and a phase that does not overlap with the phase of the first clock signal.

[0010] The output unit may include: a second transistor, which is located between the first voltage and the output terminal, wherein the gate of the second transistor is connected to the first node; a third transistor, which is located between the output terminal and the second input terminal, wherein the gate of the third transistor is connected to the second node; a first capacitor, which is connected between the second node and the output terminal; and a second capacitor, which is connected between the first node and the first voltage.

[0011] The first transistor may be located between the first node and the third voltage, wherein a gate of the first transistor is connected to a fourth input terminal, and the fourth input terminal may receive a holding control signal having an enable level after a signal is output from an output terminal of a final stage.

[0012] The first driver can control the voltage of the second node in response to the first clock signal, and the first driver can include: a fourth transistor, which is located between the first input terminal and the second node, wherein the gate of the fourth transistor is connected to the second input terminal; and a fifth transistor and a sixth transistor, which are connected in series between the second node and the first voltage, wherein the gate of the fifth transistor can be connected to the third input terminal, and the gate of the sixth transistor is connected to the first node.

[0013] The second driver may include: a seventh transistor, which is located between the first node and the second input terminal, wherein a gate of the seventh transistor is connected to the second node; and an eighth transistor, which is located between the first node and the third voltage, wherein a gate of the eighth transistor is connected to the second input terminal.

[0014] The first driver can control the voltage of the second node in response to the first clock signal, and the first driver can include: a fourth transistor, which is located between the first input terminal and the third node, wherein the gate of the fourth transistor is connected to the second input terminal; and a fifth transistor and a sixth transistor, which are connected in series between the third node and the first voltage, wherein the gate of the fifth transistor can be connected to the third input terminal, and the gate of the sixth transistor is connected to the first node.

[0015] The second driver may include: a seventh transistor, which is located between the first node and the second input terminal, wherein the gate of the seventh transistor is connected to the third node; an eighth transistor, which is located between the first node and the third voltage, wherein the gate of the eighth transistor is connected to the second input terminal; and the first driver includes: a ninth transistor, which is located between the second node and the third node, wherein the gate of the ninth transistor is connected to the third voltage.

[0016] The fourth input terminal receives a scan clock signal having a period different from the periods of the first clock signal and the second clock signal.

[0017] The first input terminal can receive a signal output from an output terminal of a previous stage or a start signal, the second input terminal can receive a first clock signal, and the third input terminal can receive a second clock signal, the second clock signal having the same time period as the first clock signal and a phase that does not overlap with the phase of the first clock signal.

[0018] The output unit may include: a second transistor, which is located between the first voltage and the first node, wherein the gate of the second transistor is connected to the second node; a third transistor, which is located between the first voltage and the output terminal, wherein the gate of the third transistor is connected to the first node; a fourth transistor, which is located between the third voltage and the output terminal, wherein the gate of the fourth transistor is connected to the second node; and a first capacitor, which is connected between the first node and the first voltage.

[0019] The first transistor may be located between the second node and the third voltage, wherein a gate of the first transistor is connected to a fourth input terminal, and the fourth input terminal may receive a holding control signal having an enable level after a signal is output from an output terminal of a final stage.

[0020] The first driver may include: a fifth transistor, which is located between the first input terminal and the second node, wherein the gate of the fifth transistor is connected to the second input terminal; a sixth transistor, which is located between the second input terminal and the third node, wherein the gate of the sixth transistor is connected to the second node; and a seventh transistor, which is located between the third node and the third voltage, wherein the gate of the seventh transistor is connected to the second input terminal.

[0021] The second driver may include: an eighth transistor and a ninth transistor, the eighth transistor and the ninth transistor being connected in series between the first voltage and the second node; a tenth transistor, the tenth transistor being located between the fourth node and the third input terminal, wherein the gate of the tenth transistor is connected to the third node; an eleventh transistor, the eleventh transistor being located between the fourth node and the first node, wherein the gate of the eleventh transistor is connected to the third input terminal; a second capacitor, the second capacitor being connected between the second node and the third input terminal; and a third capacitor, the third capacitor being connected between the third node and the fourth node, wherein the gate of the eighth transistor may be connected to the third input terminal and the gate of the ninth transistor is connected to the third node.

[0022] The first input terminal may receive a scan clock signal having a period different from periods of the first clock signal and the second clock signal.

[0023] The output unit may include: a second transistor, which is located between the fourth input terminal and the first node, wherein the gate of the second transistor is connected to the second node; a third transistor, which is located between the fourth input terminal and the output terminal, wherein the gate of the third transistor is connected to the first node; a fourth transistor, which is located between the third voltage and the output terminal, wherein the gate of the fourth transistor is connected to the second node; and a first capacitor, which is connected between the first node and the fourth input terminal.

[0024] The first transistor may be located between the second node and the third voltage, wherein a gate of the first transistor is connected to a fifth input terminal, and the fifth input terminal may receive a holding control signal having an enable level after a signal is output from the output terminal of a final stage.

[0025] The first driver may include: a fifth transistor and a sixth transistor, which are connected in series between the first input terminal and the second node; a seventh transistor, which is located between the third input terminal and the third node, wherein the gate of the seventh transistor is connected to the second node; and an eighth transistor, which is located between the third node and the third voltage, wherein the gate of the eighth transistor is connected to the third input terminal, wherein the gate of the fifth transistor may be connected to the fourth input terminal, and the gate of the sixth transistor is connected to the first input terminal.

[0026] The second driver may include: a ninth transistor and a tenth transistor, the ninth transistor and the tenth transistor being located in series between the first voltage and the second node; an eleventh transistor, the eleventh transistor being located between the fourth node and the second input terminal, wherein the gate of the eleventh transistor is connected to the third node; a twelfth transistor, the twelfth transistor being located between the fourth node and the first node, wherein the gate of the twelfth transistor is connected to the second input terminal; a second capacitor, the second capacitor being connected between the node to which the ninth transistor and the tenth transistor are connected and the second node; and a third capacitor, the third capacitor being connected between the third node and the fourth node, wherein the gate of the ninth transistor may be connected to the second node and the gate of the tenth transistor is connected to the third node.

[0027] Another exemplary embodiment of the present invention provides a display device, comprising: a display unit, the display unit comprising a plurality of pixels; a scan driver, the scan driver comprising a plurality of stages respectively connected to a plurality of scan lines, the plurality of scan lines being connected to the plurality of pixels, wherein at least one of the plurality of stages is configured to supply a first voltage or a second voltage lower than the first voltage as a scan signal in response to a voltage applied to a first node and a second node; and a holding portion, the holding portion being configured to control the scan driver so that the scan driver does not output a scan signal of an enable level during low-frequency driving, wherein the holding portion can apply a third voltage lower than the first voltage to the first node.

[0028] The display device may further include: a light-emitting driver, the light-emitting driver including a plurality of stages respectively connected to a plurality of light-emitting control lines, the plurality of light-emitting control lines being connected to the plurality of pixels, wherein at least one of the plurality of stages of the light-emitting driver is configured to supply a first voltage or a second voltage as a light-emitting signal in response to a voltage applied to a third node and a fourth node, wherein the holding portion may control the light-emitting driver so that the light-emitting driver maintains the output of the light-emitting control signal at an enable level during low-frequency driving and the light-emitting driver may apply the third voltage to the third node.

[0029] The display unit may include a display area in which the plurality of pixels are disposed and a non-display area surrounding the display area, the scan driver and the holding portion may be located in the non-display area, and the holding portion may be spaced apart from the scan driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic block diagram of a display device according to an exemplary embodiment of the present invention is shown.

[0031] Figure 2 Shown included in Figure 1 A circuit diagram of a pixel in a display device.

[0032] Figure 3 Shown for illustration Figure 1 Schematic diagram of a driving method for a display device.

[0033] Figure 4 Show Figure 1 A timing diagram of a low-frequency driving method for a display device.

[0034] Figure 5 A schematic diagram illustrating a scan driver according to an exemplary embodiment of the present invention.

[0035] Figure 6 A circuit diagram is shown as an example of a stage included in a scan driver according to an exemplary embodiment of the present invention.

[0036] Figure 7 A timing diagram illustrating a driving method of a scan driver according to an exemplary embodiment of the present invention.

[0037] Figure 8 A circuit diagram is shown as another example of a stage included in a scan driver according to an exemplary embodiment of the present invention.

[0038] Fig. 9 A schematic diagram showing a light emitting driver according to an exemplary embodiment of the present invention.

[0039] Fig.10 A circuit diagram is shown as an example of a stage included in a light emitting driver according to an exemplary embodiment of the present invention.

[0040] Fig.11 A timing diagram illustrating a driving method of a light emitting driver according to an exemplary embodiment of the present invention.

[0041] Fig.12 A schematic block diagram of a display device according to another exemplary embodiment of the present invention is shown.

[0042] Fig.13 Shown included in Fig.12 A circuit diagram of a pixel in a display device.

[0043] Fig.14 Show Fig.12 A timing diagram of a low-frequency driving method for a display device.

[0044] Fig.15A schematic diagram illustrating a scan driver according to another exemplary embodiment of the present invention.

[0045] Fig.16 A circuit diagram is shown as an example of a stage included in a scan driver according to another exemplary embodiment of the present invention.

[0046] Fig.17 A timing diagram illustrating a driving method of a scan driver according to another exemplary embodiment of the present invention.

[0047] Fig.18 A schematic diagram showing a display device including a holding portion according to another exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0048] Hereinafter, exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways and therefore, the described embodiments should not be limited to the embodiments set forth herein.

[0049] Like reference numerals may refer to like elements throughout the specification.

[0050] It will be understood that when one component is described as being “connected” or “coupled” to another component, the one component may be directly connected or coupled to the other component, or other components may be located between the one component and the other component.

[0051] Unless the context clearly indicates otherwise, singular forms shall include plural forms.

[0052] Figure 1 A schematic block diagram of a display device according to an exemplary embodiment of the present invention is shown.

[0053] The display device includes a display unit 10, a scan driver 20, a data driver 30, a light emitting driver 40, a power supply 50 and a signal controller 60. Figure 1 The described display device may include constituent elements more than or less than the constituent elements listed above.

[0054] The display unit 10 includes a plurality of pixels PX, each of which is connected to a corresponding scan line among a plurality of scan lines PS1 to PSn, a corresponding data line among a plurality of data lines D1 to Dm, and a corresponding light emission control line among a plurality of light emission control lines EM1 to EMn. Each of the plurality of pixels PX emits light according to a data signal transmitted thereto, and thus the display unit 10 can display an image.

[0055] A plurality of scan lines PS1 to PSn extend in a row direction and are substantially parallel to each other. A plurality of light emission control lines EM1 to EMn extend in a row direction and are substantially parallel to each other. A plurality of data lines D1 to Dm extend in a column direction and are substantially parallel to each other.

[0056] Each of the plurality of pixels PX receives power voltages ELVDD and ELVSS from a power source 50 .

[0057] The scan driver 20 is connected to the display unit 10 through the plurality of scan lines PS1 to PSn. The scan driver 20 generates a plurality of scan signals according to the control signal CONT2 and transmits the plurality of scan signals to corresponding scan lines among the plurality of scan lines PS1 to PSn.

[0058] The control signal CONT2 is an operation control signal of the scan driver 20 generated and transmitted by the signal controller 60. The control signal CONT2 may include a scan start signal, a clock signal switched to a low level at different times, a hold control signal, and the like. The scan start signal is a signal for generating a first scan signal for displaying a frame of an image. The clock signal included in the control signal CONT2 is a synchronization signal for applying a scan signal to a plurality of scan lines PS1 to PSn. The hold control signal is a signal for controlling the scan driver 20 so that the scan driver 20 does not output a scan signal when driven at a low frequency.

[0059] The data driver 30 is connected to each pixel PX of the display unit 10 through a plurality of data lines D1 to Dm. The data driver 30 receives the image data signal DATA and transmits the data signal to a corresponding data line among the plurality of data lines D1 to Dm according to a control signal CONT1.

[0060] The control signal CONT1 is an operation control signal of the data driver 30 generated and transmitted through the signal controller 60 .

[0061] The data driver 30 selects a gray voltage according to the image data signal DATA, and transmits the selected gray voltage as a data signal to the plurality of data lines D1 to Dm. For example, the data driver 30 samples and holds the image data signal DATA input according to the control signal CONT1, and transmits the plurality of data signals to the plurality of data lines D1 to Dm. When a low-level scan signal is applied, the data driver 30 may apply a data signal having a predetermined voltage range to the plurality of data lines D1 to Dm.

[0062] The light emitting driver 40 generates a plurality of light emitting control signals according to the control signal CONT3. The control signal CONT3 may include a light emitting start signal, a light emitting clock signal switched to a low level at different times, a hold control signal, and the like. The light emitting start signal is a signal for generating a first light emitting control signal for displaying a frame of image. The clock signal included in the control signal CONT3 is a synchronization signal for applying the light emitting control signal to a plurality of light emitting control lines EM1 to EMn. The hold control signal is a signal for controlling the light emitting driver 40 so that the light emitting driver 40 continuously outputs the light emitting signal when driven at a low frequency.

[0063] The signal controller 60 receives an input video signal (or image signal) IS input from the outside and an input control signal for controlling display of the input video signal (or image signal) IS. The image signal IS may include brightness information divided into grayscales for each of the pixels PX of the display unit 10.

[0064] The input control signals transmitted to the signal controller 60 include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a main clock signal MCLK.

[0065] The signal controller 60 generates control signals CONT1 to CONT4 and an image data signal DATA according to the image signal IS, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the main clock signal MCLK.

[0066] Signal controller 60 appropriately processes image signal IS according to operating conditions of display unit 10 and data driver 30 based on input image signal IS and input control signal. For example, signal controller 60 may generate image data signal DATA through image processing methods such as gamma correction and brightness compensation for image signal IS.

[0067] For example, the signal controller 60 generates a control signal CONT1 for controlling the operation of the data driver 30, and transmits the generated control signal CONT1 together with the image data signal DATA to the data driver 30. In addition, the signal controller 60 transmits a control signal CONT2 for controlling the operation of the scan driver 20 to the scan driver 20. In addition, the signal controller 60 may transmit a control signal CONT3 to the light emitting driver 40 to operate the light emitting driver 40.

[0068] The signal controller 60 may control driving of the power supply 50. The power supply 50 may supply power supply voltages ELVDD and ELVSS for driving each pixel PX. For example, the signal controller 60 may transmit a control signal CONT4 to the power supply 50 to drive the power supply 50. The power supply 50 may be connected to a power supply line formed in the display unit 10.

[0069] Next, we will refer to Figure 2 A pixel of a display device is described in detail.

[0070] Figure 2 Shown included in Figure 1 A circuit diagram of a pixel in a display device.

[0071] Reference Figure 2 , the pixel PX1 includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst and an organic light emitting diode OLED.

[0072] In the pixel PX1, the gate of the first transistor T1 is connected to one end of the storage capacitor Cst, the source of the first transistor T1 is connected to the first power supply voltage ELVDD, and the drain of the first transistor T1 is electrically connected to the anode of the organic light emitting diode OLED via the third transistor T3. The first transistor T1 receives the data signal D[j] according to the switching operation of the second transistor T2 and supplies the driving current to the organic light emitting diode OLED.

[0073] A gate of the second transistor T2 is connected to the corresponding scan line PSi, a source of the second transistor T2 is connected to the corresponding data line Dj, and a drain of the second transistor T2 is connected to one end of the storage capacitor Cst together with the gate of the first transistor T1.

[0074] The second transistor T2 is turned on according to the scan signal PS[i] to perform a switching operation of transmitting the data signal D[j] to one end of the storage capacitor Cst.

[0075] A gate electrode of the third transistor T3 is connected to the emission control line EMi, a source electrode of the third transistor T3 is connected to the drain electrode of the first transistor T1 , and a drain electrode of the third transistor T3 is connected to the anode electrode of the organic light emitting diode OLED.

[0076] The other end of the storage capacitor Cst is connected to the first power supply voltage ELVDD, and the cathode of the organic light emitting diode OLED is connected to the second power supply voltage ELVSS. Therefore, the organic light emitting diode OLED receives the driving current from the first transistor T1 and emits light, so that the display device displays an image. The storage capacitor Cst charges a voltage corresponding to the data signal D[j] applied to the gate of the first transistor T1, and maintains the voltage even after the second transistor T2 is turned off.

[0077] In the following, reference will be made to Figure 3 Describe the low frequency drive method.

[0078] like Figure 3 As shown in part (a) of FIG. 1 , the display device may1 Therefore, in the predetermined period T 2 (T 2 = k × T 1 ) may include several (k) frames. For example, when the display device displays a dynamic picture, the driving frequency 1 / T is 60 Hz. 1 The display device is driven so that the display device is 2 ) during which 60 frames are displayed.

[0079] Each frame may include a scanning period S for writing a data signal into the pixel PX and a light emitting period E during which the pixel PX emits light according to the data signal written into the pixel PX.

[0080] like Figure 3 As shown in part (b) of FIG. 1 , the display device may 2 For example, when the display device displays a still image, the drive frequency is 1 / T 1 Hz. 2 The display device is driven so that the display device is 2 ) to display a frame during the period.

[0081] One frame may include a scanning period S for writing a data signal into a pixel PX and a light emitting period E during which the pixel PX emits light according to the data signal written into the pixel PX.

[0082] The length of the light-emitting period E may be the period T 2 The length of the display unit 10 other than the scanning period S in the light emitting period E may be greater than the scanning period S, and the scanning signal transmitted to the display unit 10 during the light emitting period E may have a disable level, and the light emitting control signal may have an enable level.

[0083] In the following, reference will be made to Figure 4 A low frequency driving method of a display device is described in detail.

[0084] Figure 4 Show Figure 1 A timing diagram of a low-frequency driving method for a display device.

[0085] In one frame, a low-level scan signal PS[1] is applied to the first scan line PS1 during a period from t1 to t2, and a low-level scan signal PS[2] is applied to the second scan line PS2 during a period from t2 to t3. Similarly, a low-level scan signal is sequentially applied to the third to (n-1)th scan lines during a period from t3 to t4, and a low-level scan signal PS[n] is applied to the nth scan line PSn during a period from t4 to t5.

[0086] After the scan signal PS[1] of low level L is applied to the first scan line PS1 during the period from t1 to t2, the light emission control signal EM[1] of low level L is applied to the corresponding light emission control line EM1 at time t2. For example, the light emission control signal EM[1] of high level H is converted to low level L at time t2.

[0087] After the scan signal PS[2] of the low level L is applied to the second scan line PS2 during the period from t2 to t3, the light emission control signal EM[2] of the low level L is applied to the corresponding light emission control line EM2 at time t3. For example, the light emission control signal EM[2] of the high level H is converted to the low level L at time t3.

[0088] After the scan signal PS[n] of the low level L is applied to the final scan line PSn during the period from t4 to t5, the light emission control signal EM[n] of the low level L is applied to the corresponding light emission control line EMn at time t5. For example, the light emission control signal EM[n] of the high level H is converted to the low level L at time t5.

[0089] After the light emission control signal of low level is applied to all the light emission control lines, at time t6, the holding control signal BPC of low level is applied. Before the light emission period ends, the holding control signal BPC of low level is held until time t7.

[0090] The hold control signal BPC is a signal for controlling the scan driver 20 and the light emitting driver 40. For example, the hold control signal BPC is provided to the scan driver 20 and the light emitting driver 40 so that the scan driver 20 applies a high-level scan signal to the plurality of scan lines PS1 to PSn and the light emitting driver 40 applies a low-level light emitting control signal to the plurality of light emitting control lines EM1 to EMn. This will be described later with reference to Figures 5 to 9 describe.

[0091] At time t8, one frame light emission period ends. Thereafter, the scan signal PS[1] of the low level L is applied to the first scan line PS1 again during the period from t9 to t10, and thus the next frame starts.

[0092] In the following, reference will be made to Figures 5 to 8 describe Figure 1 The scanning driver 20 is provided.

[0093] Figure 5 A schematic diagram illustrating a scan driver according to an exemplary embodiment of the present invention.

[0094] Reference Figure 5, the scan driver 20 includes a plurality of stages PST1 to PSTn. Each of the plurality of stages PST1 to PSTn is connected to a corresponding scan line among the scan lines PS1 to PSn and is synchronously driven by a first clock signal CLK1 and a second clock signal CLK2. The plurality of stages PST1 to PSTn may have the same circuit structure.

[0095] Each of the plurality of stages PST1 to PSTn receives an output signal (eg, a scan signal) of a previous stage or a scan start signal PSSP. For example, the first stage PST1 receives the scan start signal PSSP, and the remaining stages PST2 to PSTn receive an output signal of the corresponding previous stage.

[0096] Each of the plurality of stages PST1 to PSTn receives a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 have the same period, and the phases of the first clock signal CLK1 and the second clock signal CLK2 do not overlap each other. For example, when the period during which the scan signal is supplied to one scan line is one horizontal period (1H), each of the first clock signal CLK1 and the second clock signal CLK2 may have a period of 2H, and may be switched to a low level L in horizontal periods different from each other.

[0097] Figure 6 2 is a circuit diagram showing an example of a stage included in a scan driver according to an exemplary embodiment of the present invention. Figure 6 In the embodiment of the present invention, although the transistor is shown as a P-type transistor, the present invention is not limited thereto. For example, the transistor may be an N-type transistor.

[0098] Reference Figure 6 , one stage PST1 includes a first driver 210 , a second driver 220 , an output unit 230 , and a holding part 240 .

[0099] The output unit 230 controls the level of the scan signal PS[1] supplied to the output terminal 209 in response to the voltages applied to the first and second nodes N1 and N2. To achieve this, the output unit 230 includes a fourth transistor PT4, a fifth transistor PT5, a first capacitor C1, and a second capacitor C2.

[0100] The fourth transistor PT4 is located between the first voltage VGH and the output terminal 209, and the gate of the fourth transistor PT4 is connected to the first node N1. The fourth transistor PT4 controls the connection between the first voltage VGH and the output terminal 209 in response to the voltage applied to the first node N1. In this case, the first voltage VGH is set to a high level, such as a high-level voltage.

[0101] The fifth transistor PT5 is located between the output terminal 209 and the second input terminal 203, and a gate of the fifth transistor PT5 is connected to the second node N2. The fifth transistor PT5 controls the connection between the output terminal 209 and the second input terminal 203 in response to a voltage applied to the second node N2.

[0102] The first capacitor C1 is connected between the second node N2 and the output terminal 209. The first capacitor C1 charges a voltage corresponding to turning on and off of the fifth transistor PT5.

[0103] The second capacitor C2 is connected between the first node N1 and the first voltage VGH. The second capacitor C2 charges the voltage applied to the first node N1.

[0104] The first driver 210 controls the voltage of the second node N2 and the voltage of the third node N3 in response to the signal supplied to the first to third input terminals 201 to 205. To achieve this, the first driver 210 includes first, second and third transistors PT1, PT2 and PT3 and an eighth transistor PT8.

[0105] The first transistor PT1 is located between the third input terminal 205 and the third node N3, and a gate of the first transistor PT1 is connected to the first input terminal 201. The first transistor PT1 controls connection between the third input terminal 205 and the third node N3 in response to a voltage supplied to the first input terminal 201.

[0106] The second transistor PT2 and the third transistor PT3 are connected in series between the third node N3 and the first voltage VGH. For example, the second transistor PT2 is located between the third transistor PT3 and the third node N3, and the gate of the second transistor PT2 is connected to the second input terminal 203. The second transistor PT2 controls the connection between the third transistor PT3 and the third node N3 in response to the voltage applied to the second input terminal 203.

[0107] The third transistor PT3 is located between the second transistor PT2 and the first voltage VGH, and a gate of the third transistor PT3 is connected to the first node N1. The third transistor PT3 controls the connection between the second transistor PT2 and the first voltage VGH in response to the voltage level of the first node N1.

[0108] The eighth transistor PT8 is located between the second node N2 and the third node N3, and the gate of the eighth transistor PT8 is connected to the second voltage VGL. The eighth transistor PT8 is turned on by the second voltage VGL to connect the second node N2 and the third node N3 to each other. In this case, the second voltage VGL is set to a low level, such as a low-level voltage.

[0109] The second driver 220 controls the voltage of the first node N1 in response to the voltage level of the first input terminal 201 and the voltage level of the third node N3. To achieve this, the second driver 220 includes a sixth transistor PT6 and a seventh transistor PT7.

[0110] The sixth transistor PT6 is located between the first node N1 and the first input terminal 201, and a gate of the sixth transistor PT6 is connected to the third node N3. The sixth transistor PT6 controls the connection between the first node N1 and the first input terminal 201 in response to a voltage level of the third node N3.

[0111] The seventh transistor PT7 is located between the first node N1 and the second voltage VGL, and a gate of the seventh transistor PT7 is connected to the first input terminal 201. The seventh transistor PT7 controls the connection between the first node N1 and the second voltage VGL in response to the voltage level of the first input terminal 201.

[0112] The holding section 240 controls the voltage of the first node N1 in response to the signal supplied to the fourth input terminal 207. To achieve this, the holding section 240 includes a ninth transistor PT9.

[0113] The ninth transistor PT9 is located between the first node N1 and the second voltage VGL, and a gate of the ninth transistor PT9 is connected to the fourth input terminal 207. The ninth transistor PT9 controls the connection between the first node N1 and the second voltage VGL in response to the level of the hold control signal BPC supplied to the fourth input terminal 207.

[0114] Figure 7 A timing diagram illustrating a driving method of a scan driver according to an exemplary embodiment of the present invention.

[0115] Reference Figure 7 , the first clock signal CLK1 and the second clock signal CLK2 are switched to the low level L at different times (e.g., CLK1: ta1, ta5, and ta9, etc., CLK2: ta3, ta7, and ta11, etc.) at intervals of 1H. The scan start signal PSSP of the low level is supplied synchronously with the first clock signal CLK1 supplied to the first input terminal 201.

[0116] For example, at time ta5 , when the first clock signal CLK1 switches to the low level L, the scanning start signal PSSP switches to the low level L.

[0117] When the first clock signal CLK1 of low level L is supplied, the first transistor PT1 and the seventh transistor PT7 are turned on. When the first transistor PT1 is turned on, the third input terminal 205 and the third node N3 are electrically connected to each other. The third node N3 is set to a low level voltage by the low level scan start signal PSSP supplied to the third input terminal 205. When the third node N3 is set to a low level voltage, the sixth transistor PT6 is turned on.

[0118] In addition, the second node N2 is also set to a low level voltage through the turned-on eighth transistor PT8. When the second node N2 is set to a low level voltage, the fifth transistor PT5 is turned on.

[0119] When the fifth transistor PT5 is turned on, the second input terminal 203 and the output terminal 209 are electrically connected. In this case, since the second clock signal CLK2 applied to the second input terminal 203 is a high level, a high level voltage is output to the output terminal 209.

[0120] When the sixth transistor PT6 is turned on, the first input terminal 201 and the first node N1 are electrically connected. Then, the voltage of the first clock signal CLK1 supplied to the first input terminal 201 (in other words, the low level voltage) is supplied to the first node N1. In addition, the seventh transistor PT7 is turned on in response to the first clock signal CLK1, so that the voltage of the second voltage VGL is supplied to the first node N1. In this case, the voltage of the second voltage VGL is set to the same voltage (similar voltage) as the low level of the first clock signal CLK1, so that the first node N1 stably maintains the low level voltage.

[0121] When the low level voltage is supplied to the first node N1, the fourth transistor PT4 and the third transistor PT3 are turned on. When the third transistor PT3 is turned on, the first voltage VGH is electrically connected to the second transistor PT2. In this case, since the second transistor PT2 is set to the cut-off state, even if the third transistor PT3 is turned on, the third node N3 stably maintains the low level voltage. When the fourth transistor PT4 is turned on, the first voltage VGH is supplied to the output terminal 209. In this case, the first voltage VGH is set to the same voltage as the high level voltage supplied to the second input terminal 203, so that the output terminal 209 stably maintains a high level.

[0122] At time ta6, the scanning start signal PSSP and the first clock signal CLK1 are switched to a high level. Then, the first transistor PT1 and the seventh transistor PT7 are turned off. In this case, the fifth transistor PT5 and the sixth transistor PT6 maintain a turned-on state corresponding to the voltage stored in the first capacitor C1.

[0123] When the fifth transistor PT5 maintains the on state, the output terminal 209 and the second input terminal 203 maintain an electrically connected state. Therefore, the output terminal 209 receives the high level voltage from the second input terminal 203.

[0124] In addition, since the sixth transistor PT6 is kept in the on state, the first node N1 is electrically connected to the first input terminal 201. In this case, the voltage of the first input terminal 201 is set to a high-level voltage corresponding to the high-level first clock signal CLK1, so that the first node N1 is also set to a high-level voltage. When the high-level voltage is supplied to the first node N1, the fourth transistor PT4 is turned off.

[0125] At time ta7, the second clock signal CLK2 switches to a low level. The low-level second clock signal CLK2 is supplied to the second input terminal 203. In this case, since the fifth transistor PT5 is set to an on state, the second clock signal CLK2 supplied to the second input terminal 203 is supplied to the output terminal 209. In this case, the output terminal 209 outputs the second clock signal CLK2 as the scan signal PS[1] to the scan line PS1. In addition, in the low-level period (ta7 to ta8) of the second clock signal CLK2, the voltage of the first node N1 is a level L0 lower than the low level L.

[0126] After the scan signal PS[1] is output to the scan line PS1, at time ta9, the first clock signal CLK1 is switched to a low level. When the low-level first clock signal CLK1 is supplied, the first transistor PT1 and the seventh transistor PT7 are turned on. When the first transistor PT1 is turned on, the third input terminal 205 and the third node N3 are electrically connected. In this case, the supplied scan start signal PSSP is a high level, so that the third input terminal 205 is set to a high-level voltage. Therefore, when the first transistor PT1 is turned on, a high-level voltage is supplied to the third node N3, so that the fifth transistor PT5 and the sixth transistor PT6 are turned off.

[0127] When the seventh transistor PT7 is turned on, the second voltage VGL is supplied to the first node N1, so that the third transistor PT3 and the fourth transistor PT4 are turned on. When the fourth transistor PT4 is turned on, the first voltage VGH is supplied to the output terminal 209. Then, the fourth transistor PT4 and the third transistor PT3 remain in a turned-on state corresponding to the voltage charged in the second capacitor C2, so that the output terminal 209 stably receives the first voltage VGH.

[0128] In addition, at time ta11, when the second clock signal CLK2 switches to a low level, the second transistor PT2 is turned on. In this case, the third transistor PT3 is set to an on state and the first voltage VGH is supplied to the third node N3. In this case, the fifth transistor PT5 and the sixth transistor PT6 are stably kept in an off state.

[0129] At time ta14, the output of the low-level scan signals PS[1] to PS[n] to the scan lines PS1 to PSn is completed. Then, at time ta15, the hold control signal BPC is switched to a low level. In this case, the first clock signal CLK1 and the second clock signal CLK2 can stop timing. In other words, the first clock signal CLK1 and the second clock signal CLK2 can maintain a high level.

[0130] When the hold control signal BPC is switched to a low level, the fourth transistor PT4 is turned on because the second voltage VGL is supplied to the first node N1. Then, the first voltage VGH is supplied to the output terminal 209 through the turned-on fourth transistor PT4. In other words, none of the stages PST1 to PSTn of the scan driver 20 outputs the scan signals PS[1] to PS[n] of a low level. For example, the scan signals PS[1] to PS[n] maintain a high level.

[0131] Therefore, for low-frequency driving of the display device, the scan driver 20 according to the present exemplary embodiment can stably maintain the scan signals PS[ 1 ] to PS[n] at a high level for a predetermined period.

[0132] If known, in Figure 7 In the embodiment, the signal cycle of ta1 to ta15 starts repeatedly at ta16 and lasts at least until ta27.

[0133] Figure 8 A circuit diagram is shown as another example of a stage included in a scan driver according to an exemplary embodiment of the present invention.

[0134] like Figure 8 As shown in Figure 6 Compared with the stage PST1 shown in FIG, the stage PST1′ includes the first transistor PT1 to the seventh transistor PT7, the ninth transistor PT9, the first capacitor C1 and the second capacitor C2, but does not include the eighth transistor PT8. Figure 7 The driving method is roughly the same, so its description will be omitted.

[0135] exist Figure 8In the stage PST1', the control signal BPC is switched to a low level. Therefore, the second voltage VGL is supplied to the first node N1 through the turned-on ninth transistor PT9, so that the fourth transistor PT4 is turned on. Then, the first voltage VGH is supplied to the output terminal 209 through the turned-on fourth transistor PT4. In other words, the stages PST1' to PSTn' of the scan driver 20 do not output the low-level scan signals PS[1] to PS[n].

[0136] Therefore, for low-frequency driving of the display device, the scan driver 20 according to the present exemplary embodiment may maintain the scan signals PS[ 1 ] to PS[n] at a high level for a predetermined period.

[0137] In the following, reference will be made to Figures 9 to 11 describe Figure 1 The light emitting driver 40.

[0138] Fig. 9 A schematic diagram showing a light emitting driver according to an exemplary embodiment of the present invention.

[0139] The light emitting driver 40 includes a plurality of stages EST1 to ESTn. Each of the plurality of stages EST1 to ESTn is connected to a corresponding light emitting control line among the light emitting control lines EM1 to EMn and is synchronously driven by the first clock signal ECLK1 and the second clock signal ECLK2. The plurality of stages EST1 to ESTn may have the same circuit structure.

[0140] The plurality of stages EST1 to ESTn sequentially output light emitting control signals. When the light emitting control signals are output, the light emitting control signals overlap with each other within a predetermined period.

[0141] Each of the plurality of stages EST1 to ESTn receives an output signal (eg, a light emitting control signal) of a previous stage or a light emitting start signal ESP. For example, the first stage EST1 receives the light emitting start signal ESP, and the remaining stages EST2 to ESTn receive an output signal of the corresponding previous stage.

[0142] Each of the plurality of stages EST1 to ESTn receives a first clock signal ECLK1 and a second clock signal ECLK2. The first clock signal ECLK1 and the second clock signal ECLK2 have the same period, and phases of the first clock signal ECLK1 and the second clock signal ECLK2 do not overlap each other.

[0143] Fig.10 1 is a circuit diagram showing an example of a stage included in a light emitting driver according to an exemplary embodiment of the present invention. Fig.10 In the embodiment of the present invention, although the transistor is shown as a P-type transistor, the present invention is not limited thereto. For example, the transistor may be an N-type transistor.

[0144] Reference Fig.10 , one stage EST1 includes a first driver 310 , a second driver 320 , an output unit 330 , and a holding part 340 .

[0145] The output unit 330 controls the level of the light emission control signal EM[1] supplied to the output terminal 309 in response to the voltage applied to the first node N11 and the second node N12. To achieve this, the output unit 330 includes an eighth transistor ET8, a ninth transistor ET9, a tenth transistor ET10, and a third capacitor EC3.

[0146] The eighth transistor ET8 is located between the first voltage VGH and the first node N11, and the gate of the eighth transistor ET8 is connected to the second node N12. The eighth transistor ET8 controls the connection between the first voltage VGH and the first node N11 in response to the voltage applied to the second node N12. In this case, the first voltage VGH is set to a high level, such as a high-level voltage.

[0147] The ninth transistor ET9 is located between the first voltage VGH and the output terminal 309, and a gate of the ninth transistor ET9 is connected to the first node N11. The ninth transistor ET9 controls the connection between the first voltage VGH and the output terminal 309 in response to a voltage applied to the first node N11.

[0148] The tenth transistor ET10 is located between the output terminal 309 and the second voltage VGL, and the gate of the tenth transistor ET10 is connected to the second node N12. The tenth transistor ET10 controls the connection between the output terminal 309 and the second voltage VGL in response to the voltage applied to the second node N12. In this case, the second voltage VGL is set to a low level, such as a low-level voltage.

[0149] The third capacitor EC3 is connected between the first node N11 and the first voltage VGH. The third capacitor EC3 charges the voltage applied to the first node N11.

[0150] The first driver 310 controls the voltage of the second node N12 and the voltage of the third node N13 in response to signals supplied to the first input terminal 301 and the third input terminal 305. To achieve this, the first driver 310 includes first to third transistors ET1 to ET3.

[0151] The first transistor ET1 is located between the third input terminal 305 and the second node N12, and a gate of the first transistor ET1 is connected to the first input terminal 301. The first transistor ET1 controls connection between the third input terminal 305 and the second node N12 in response to a voltage supplied to the first input terminal 301.

[0152] The second transistor ET2 is located between the third node N13 and the first input terminal 301, and a gate of the second transistor ET2 is connected to the second node N12. The second transistor ET2 controls connection between the first input terminal 301 and the third node N13 in response to a voltage level of the second node N12.

[0153] The third transistor ET3 is located between the third node N13 and the second voltage VGL, and a gate of the third transistor ET3 is connected to the first input terminal 301. The third transistor ET3 controls the connection between the third node N13 and the second voltage VGL in response to a voltage supplied to the first input terminal 301.

[0154] The second driver 320 controls the voltage of the first node N11, the voltage of the second node N12, and the voltage of the fourth node N14 in response to the voltage level of the second input terminal 303 and the voltage level of the third node N13. To achieve this, the second driver 320 includes a fourth transistor ET4, a fifth transistor ET5, a sixth transistor ET6, a seventh transistor ET7, a first capacitor EC1, and a second capacitor EC2.

[0155] The fourth transistor ET4 and the fifth transistor ET5 are connected in series between the second node N12 and the first voltage VGH. For example, the fourth transistor ET4 is located between the fifth transistor ET5 and the second node N12, and the gate of the fourth transistor ET4 is connected to the second input terminal 303. The fourth transistor ET4 controls the connection between the fifth transistor ET5 and the second node N12 in response to the voltage supplied to the second input terminal 303.

[0156] The fifth transistor ET5 is located between the fourth transistor ET4 and the first voltage VGH, and a gate of the fifth transistor ET5 is connected to the third node N13. The fifth transistor ET5 controls the connection between the fourth transistor ET4 and the first voltage VGH in response to the voltage level of the third node N13.

[0157] The sixth transistor ET6 is located between the fourth node N14 and the second input terminal 303, and a gate of the sixth transistor ET6 is connected to the third node N13. The sixth transistor ET6 controls connection between the fourth node N14 and the second input terminal 303 in response to a voltage level of the third node N13.

[0158] The seventh transistor ET7 is located between the fourth node N14 and the first node N11, and a gate of the seventh transistor ET7 is connected to the second input terminal 303. The seventh transistor ET7 controls connection between the fourth node N14 and the first node N11 in response to a voltage level of the second input terminal 303.

[0159] The first capacitor EC1 is connected between the second node N12 and the second input terminal 303 , and the second capacitor EC2 is connected between the third node N13 and the fourth node N14 .

[0160] The holding section 340 controls the voltage of the second node N12 in response to the signal supplied to the fourth input terminal 307. To achieve this, the holding section 340 includes an eleventh transistor ET11.

[0161] The eleventh transistor ET11 is located between the second node N12 and the second voltage VGL, and a gate of the eleventh transistor ET11 is connected to the fourth input terminal 307. The eleventh transistor ET11 controls connection between the second node N12 and the second voltage VGL in response to a level of a hold control signal BPC supplied to the fourth input terminal 307.

[0162] Fig.11 A timing diagram illustrating a driving method of a light emitting driver according to an exemplary embodiment of the present invention.

[0163] Reference Fig.11 The first clock signal ECLK1 and the second clock signal ECLK2 are switched to the low level L at different times (e.g., ECLK1: tb1, tb5, and tb9, etc., ECLK2: tb3, tb7, and tb11, etc.). The light emission start signal ESP of the high level is supplied synchronously with the first clock signal ECLK1 supplied to the first input terminal 301.

[0164] For example, at time tb1, when the first clock signal ECLK1 switches to the low level L, the light emission start signal ESP switches to the high level H. The light emission start signal ESP is provided only to the first stage EST1, and may maintain a high level during a period from time tb1 to time tb9.

[0165] When the first clock signal ECLK1 of a low level L is supplied, the first transistor ET1 and the third transistor ET3 are turned on.

[0166] When the first transistor ET1 is turned on, the third input terminal 305 and the second node N12 are electrically connected. The second node N12 is set to a high level voltage by the high level light emission start signal ESP supplied to the third input terminal 305. When the second node N12 is set to a high level voltage, the second transistor ET2, the eighth transistor ET8, and the tenth transistor ET10 are turned off.

[0167] When the third transistor ET3 is turned on, the third node N13 and the second voltage VGL are electrically connected, and thus the second voltage VGL is supplied to the third node N13. In this case, the voltage of the second voltage VGL is set to the same voltage as (or a similar voltage to) the low level of the first clock signal ECLK1.

[0168] When the third node N13 is set to a low level voltage, the fifth transistor ET5 and the sixth transistor ET6 are turned on.

[0169] When the fifth transistor ET5 is turned on, the first voltage VGH and the fourth transistor ET4 are electrically connected. In this case, since the fourth transistor ET4 is set to a cut-off state, the second node N12 maintains a high level even if the fifth transistor ET5 is turned on.

[0170] When the sixth transistor ET6 is turned on, the second input terminal 303 and the fourth node N14 are electrically connected. In this case, since the second clock signal ECLK2 applied to the second input terminal 303 has a high level, a high level voltage is also output to the fourth node N14.

[0171] The seventh transistor ET7 is in a turned-off state by the second clock signal ECLK2 having a high level. The voltage of the first node N11 is kept at a high level by the third capacitor EC3. Since the voltage of the first node N11 is kept at a high level, the ninth transistor ET9 is in a turned-off state. Therefore, the light emitting control signal EM[1] maintains a low level voltage.

[0172] At time tb3, the second clock signal ECLK2 switches to a low level. The light emission start signal ESP and the first clock signal ECLK1 maintain a high level.

[0173] The first transistor ET1 and the third transistor ET3 are in a turned-off state by the first clock signal ECLK1 having a high level. Since the voltage of the second node N12 maintains a high level, the second transistor ET2, the eighth transistor ET8, and the tenth transistor ET10 are in a turned-off state.

[0174] The second clock signal ECLK2 of a low level is supplied to the second input terminal 303. In this case, the fourth transistor ET4 and the seventh transistor ET7 are turned on. In addition, since the voltage of the third node N13 is at a low level, the fifth transistor ET5 and the sixth transistor ET6 are in a turned-on state.

[0175] The voltage of the third node N13 is bootstrapped by the potential change amount of the second clock signal ECLK2 through the coupling of the second capacitor EC2. In other words, in the low level period (tb3 to tb4) of the second clock signal ECLK2, the voltage of the third node N13 is a level L2 lower than the low level L. In the low level period (tb11 to tb12) of the second clock signal ECLK2, the voltage of the second node N12 is a level L1 lower than the low level L.

[0176] The second clock signal ECLK2 having a low level is provided to the first node N11 through the turned-on sixth transistor ET6 and seventh transistor ET7. Therefore, at time tb3, the voltage of the first node N11 is a low level. Since the voltage of the first node N11 is a low level, the ninth transistor ET9 is turned on.

[0177] Since the ninth transistor ET9 is turned on and the tenth transistor ET10 is in a turned-off state, the light emission control signal EM[1] switches to a high level.

[0178] At time tb9, the first clock signal ECLK1 switches to a low level, and the light emission start signal ESP switches to a low level. The second clock signal ECLK2 maintains a high level.

[0179] The first clock signal ECLK1 having a low level is supplied to the gate of the first transistor ET1 and the gate of the third transistor ET3. Therefore, the first transistor ET1 and the third transistor ET3 are turned on.

[0180] The light emission start signal ESP having a low level is supplied to the gate of the second transistor ET2 and the second node N12 through the turned-on first transistor ET1. Therefore, the voltage of the second node N12 is a low level, and the second transistor ET2 is turned on.

[0181] The first clock signal ECLK1 having a low level is supplied to the third node N13 through the turned-on second transistor ET2, and the second voltage VGL is supplied to the third node N13 through the turned-on third transistor ET3. Therefore, the voltage of the third node N13 is a low level.

[0182] The second clock signal ECLK2 having a high level is supplied to the fourth transistor ET4 and the seventh transistor ET7. Therefore, the fourth transistor ET4 and the seventh transistor ET7 are in a turned-off state.

[0183] Since the voltage of the second node N12 is low level, the eighth transistor ET8 is turned on. The first voltage VGH is provided to the first node N11 through the turned-on eighth transistor ET8. Therefore, the voltage of the first node N11 is high level. Since the voltage of the first node N11 is high level, the ninth transistor ET9 is turned off.

[0184] Since the voltage of the second node N12 is a low level, the tenth transistor ET10 is turned on. The second voltage VGL is provided to the output terminal 309 through the turned-on tenth transistor ET10. Therefore, the first light emitting control signal EM[1] has a low level.

[0185] At time tb19, the output of the low-level scan signal EM[n] from the final stage ESTn to the light emitting control line EMn is started. Then, at time tb21, the hold control signal BPC is switched to a low level. In this case, the first clock signal ECLK1 and the second clock signal ECLK2 may stop clocking. For example, the first clock signal ECLK1 may be kept at a high level and the second clock signal ECLK2 may be kept at a high level. Fig.11 The time tb21 may correspond to Figure 7 The time is ta15.

[0186] When the hold control signal BPC is switched to a low level, the second voltage VGL is supplied to the second node N12, so that the tenth transistor ET10 is turned on. Then, the second voltage VGL is supplied to the output terminal 309 through the turned-on tenth transistor ET10. In other words, all stages EST1 to ESTn of the light emitting driver 40 maintain the output of the light emitting control signals EM[1] to EM[n] of a low level.

[0187] Therefore, for low-frequency driving of the display device, the light emitting driver 40 according to the present exemplary embodiment can stably maintain the light emitting control signals EM[1] to EM[n] at a low level for a predetermined period.

[0188] If known, in Fig.11 In the embodiment, the signal cycle from tb1 to tb21 starts again at tb22 and lasts at least until tb27.

[0189] In the following, reference will be made to Figures 12 to 17 A display device according to another exemplary embodiment of the present invention is described.

[0190] Fig.12 A schematic block diagram of a display device according to another exemplary embodiment of the present invention is shown.

[0191] The display device includes a display unit 11, a first scan driver 21, a second scan driver 22, a data driver 31, a light emitting driver 41, a power supply 51 and a signal controller 61. Fig.12 The described display device may include more elements than the elements listed above or fewer elements than the elements listed above.

[0192] Can be omitted Fig.12 Among the elements of the display device shown in Figure 1 The elements of the display device are the same or similar to the description of the elements.

[0193] The display unit 11 includes a plurality of pixels PX, each of which is connected to a corresponding first scan line among a plurality of first scan lines PS0 to PSn, a corresponding second scan line among a plurality of second scan lines NS0 to NSn, a corresponding data line among a plurality of data lines D1 to Dm, and a corresponding light emission control line among a plurality of light emission control lines EM1 to EMn. Each of the plurality of pixels PX emits light according to a data signal transmitted thereto, and thus the display unit 11 can display an image.

[0194] A plurality of first scan lines PS0 to PSn extend in a row direction and are substantially parallel to each other. A plurality of second scan lines NS0 to NSn extend in a row direction and are substantially parallel to each other. A plurality of light emission control lines EM1 to EMn extend in a row direction and are substantially parallel to each other. A plurality of data lines D1 to Dm extend in a column direction and are substantially parallel to each other.

[0195] Each of the plurality of pixels PX receives an initialization voltage Vint and power supply voltages ELVDD and ELVSS from a power source 51 .

[0196] The second scan driver 22 is connected to the display unit 11 through the plurality of second scan lines NS0 to NSn. The second scan driver 22 generates a plurality of scan signals according to the control signal CONT13 and transmits the plurality of scan signals to corresponding scan lines among the plurality of second scan lines NS0 to NSn.

[0197] The signal controller 61 receives an input video signal (or image signal) IS input from the outside and an input control signal for controlling the display of the input video signal (or image signal) IS. The input control signal transmitted to the signal controller 61 includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a main clock signal MCLK. The signal controller 61 generates control signals CONT11 to CONT15 and an image data signal DATA according to the image signal IS, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the main clock signal MCLK.

[0198] The signal controller 61 may control the driving of the power supply 51. The power supply 51 may supply an initialization voltage Vint for initializing the gate of the first transistor and the anode of the organic light emitting diode included in each pixel PX of the display unit 11 to a predetermined voltage. In addition, the power supply 51 may provide power supply voltages ELVDD and ELVSS for driving each pixel PX. For example, the signal controller 61 may transmit a control signal CONT15 to the power supply 51 to drive the power supply 51. The power supply 51 may be connected to a power supply line formed in the display unit 11.

[0199] In the following, reference will be made to Fig.13 A pixel of a display device is described in detail.

[0200] Fig.13 Shown included in Fig.12 A circuit diagram of a pixel in a display device.

[0201] Reference Fig.13 , a pixel PX2 of a display device according to another exemplary embodiment of the present invention includes first to seventh transistors T11 to T17 , a storage capacitor Cst, and an organic light emitting diode OLED.

[0202] In the pixel PX2, the gate of the first transistor T11 is connected to one end of the storage capacitor Cst, the source of the first transistor T11 is connected to the first power supply voltage ELVDD via the fifth transistor T15, and the drain of the first transistor T11 is electrically connected to the anode of the organic light emitting diode OLED via the sixth transistor T16. The first transistor T11 receives the data signal D[j] according to the switching operation of the second transistor T12 to supply the driving current to the organic light emitting diode OLED.

[0203] The gate of the second transistor T12 is connected to the corresponding first scan line PSi, the source of the second transistor T12 is connected to the corresponding data line Dj, and the drain of the second transistor T12 is connected to the source of the first transistor T11 and to the first power supply voltage ELVDD via the fifth transistor T15.

[0204] The second transistor T12 performs a switching operation in which the second transistor T12 is turned on according to the scan signal PS[i] to transmit the data signal D[j] to the source electrode of the first transistor T11.

[0205] A gate of the third transistor T13 is connected to the corresponding second scan line NSi, a source of the third transistor T13 is connected to the drain of the first transistor T11 and to the anode of the organic light emitting diode OLED via the sixth transistor T16, and a drain of the third transistor T13 is connected to one end of the storage capacitor Cst, the source of the fourth transistor T14, and the gate of the first transistor T11.

[0206] The third transistor T13 is turned on according to the second scan signal NS[i] received through the corresponding second scan line NSi to connect the gate and the drain of the first transistor T11 to each other, thereby diode-connecting the first transistor T11.

[0207] A gate electrode of the fourth transistor T14 is connected to the previous second scan line NSi-1, a drain electrode of the fourth transistor T14 is connected to the initialization voltage Vint, and a source electrode of the fourth transistor T14 is connected to the drain electrode of the third transistor T13.

[0208] The fourth transistor T14 is turned on according to the scan signal NS[i-1] received through the previous second scan line NSi-1 to transfer the initialization voltage Vint to the gate of the first transistor T11, thus performing an operation for initializing the voltage of the gate of the first transistor T11.

[0209] A gate of the fifth transistor T15 is connected to the corresponding emission control line EMi, a source of the fifth transistor T15 is connected to the first power supply voltage ELVDD, and a drain of the fifth transistor T15 is connected to the source of the first transistor T11 and the drain of the second transistor T12.

[0210] The gate of the sixth transistor T16 is connected to the corresponding emission control line EMi, the source of the sixth transistor T16 is connected to the drain of the first transistor T11 and the source of the third transistor T13, and the drain of the sixth transistor T16 is connected to the anode of the organic light emitting diode OLED and the source of the seventh transistor T17.

[0211] The fifth transistor T15 and the sixth transistor T16 are simultaneously turned on according to the emission control signal EM[i] received through the emission control line EMi. In this case, a driving current flows through the organic light emitting diode OLED by the first power voltage ELVDD and the voltage stored in the storage capacitor Cst.

[0212] A gate electrode of the seventh transistor T17 is connected to the previous first scan line PSi-1, a drain electrode of the seventh transistor T17 is connected to the initialization voltage Vint, and a source electrode of the seventh transistor T17 is connected to the anode electrode of the organic light emitting diode OLED and the drain electrode of the sixth transistor T16.

[0213] The seventh transistor T17 is turned on according to the scan signal PS[i-1] received through the previous first scan line PSi-1. In this case, the seventh transistor T17 performs an operation for initializing the voltage of the anode of the organic light emitting diode OLED with the initialization voltage Vint.

[0214] The other end of the storage capacitor Cst is connected to the first power voltage ELVDD, and the cathode of the organic light emitting diode OLED is connected to the second power voltage ELVSS. Therefore, the organic light emitting diode OLED receives the driving current from the first transistor T11 to emit light, so that the display device displays an image.

[0215] The pixel PX2 includes an oxide semiconductor thin film transistor and a low temperature polysilicon (LTPS) thin film transistor.

[0216] The oxide semiconductor thin film transistor includes a gate, a source and a drain. The oxide semiconductor thin film transistor includes an active layer made of an oxide semiconductor. Herein, the oxide semiconductor may include an amorphous oxide semiconductor or a crystalline oxide semiconductor. The oxide semiconductor thin film transistor may be an N-type transistor.

[0217] The LTPS thin film transistor includes a gate, a source and a drain. The LTPS thin film transistor includes an active layer made of polysilicon. The LTPS thin film transistor may be a P-type thin film transistor or an N-type thin film transistor. In the present exemplary embodiment, the LTPS thin film transistor is a P-type transistor.

[0218] LTPS thin film transistors have high electron mobility and thus have fast driving characteristics.

[0219] The oxide semiconductor thin film transistor can be manufactured by a low temperature process, and has a lower charge mobility than the LTPS thin film transistor. The oxide semiconductor thin film transistor has excellent off-current characteristics.

[0220] The first transistor T11 , the second transistor T12 , the fifth transistor T15 , the sixth transistor T16 , and the seventh transistor T17 may be P-type LTPS thin film transistors, and the third transistor T13 and the fourth transistor T14 may be N-type oxide semiconductor thin film transistors.

[0221] In the present exemplary embodiment, when the third transistor T13 and the fourth transistor T14 connected to the second node NA2 are oxide semiconductor thin film transistors, leakage current from the second node NA2 is minimized, and thus an image having desired brightness can be displayed.

[0222] In addition, in the present exemplary embodiment, the first transistor T11, the sixth transistor T16, and the seventh transistor T17 located at the current supply path for supplying current to the organic light emitting diode OLED are LTPS thin film transistors. When the first transistor T11, the sixth transistor T16, and the seventh transistor T17 located at the current supply path are LTPS thin film transistors, current can be stably supplied to the organic light emitting diode OLED through the fast driving characteristics of the LTPS thin film transistors.

[0223] In the following, reference will be made to Fig.14 Detailed Description Fig.12 A low-frequency driving method for a display device.

[0224] Fig.14 Show Fig.12 A timing diagram of a low-frequency driving method for a display device.

[0225] In one frame, during the period from t0 to t1, a low-level first scan signal PS[0] is applied to a dummy first scan line PS0, and a high-level second scan signal NS[0] is applied to a dummy second scan line NS0. During the period from t1 to t2, a low-level first scan signal PS[1] is applied to the first first scan line PS1, and a high-level second scan signal NS[1] is applied to the first second scan line NS1. Similarly, a low-level first scan signal is sequentially applied to the second to (n-1)th first scan lines PS2 to PSn-1, and a low-level second scan signal is sequentially applied to the second to (n-1)th second scan lines NS2 to NSn-1. During the period from t4 to t5, a low-level first scan signal PS[n] is applied to the nth first scan line PSn, and a high-level second scan signal NS[n] is applied to the nth second scan line NSn.

[0226] After the first scan signal PS[1] of low level L and the second scan signal NS[1] of high level H are respectively applied to the first first scan line PS1 and the first second scan line NS1 during the period from t1 to t2, at time t2, the light emitting control signal EM[1] of low level L is applied to the corresponding light emitting control line EM1.

[0227] After the first scan signal PS[2] of low level L and the second scan signal NS[2] of high level H are respectively applied to the second first scan line PS2 and the second second scan line NS2 during the period from t2 to t3, at time t3, the light emitting control signal EM[2] of low level L is applied to the corresponding light emitting control line EM2.

[0228] After the first scan signal PS[n] of a low level L and the second scan signal NS[n] of a high level H are respectively applied to the last first scan line PSn and the last second scan line NSn during the period from t4 to t5, at time t5, the light emitting control signal EM[n] of a low level L is applied to the corresponding light emitting control line EMn.

[0229] After applying the low-level emission control signals EM[1] to EM[n] to all emission control lines EM1 to EMn, the low-level holding control signal BPC is applied at time t6. The low-level holding control signal BPC is held until time t7 before the emission period ends.

[0230] The hold control signal BPC is a signal for controlling the first scan driver 21, the second scan driver 22 and the light emitting driver 41, and is provided to the first scan driver 21, the second scan driver 22 and the light emitting driver 41, so that the first scan driver 21 applies a high-level first scan signal to the plurality of first scan lines PS1 to PSn, the second scan driver 22 applies a low-level second scan signal to the plurality of second scan lines NS1 to NSn, and the light emitting driver 41 applies a low-level light emitting control signal to the plurality of light emitting control lines EM1 to EMn.

[0231] Next, at time t8, the light-emitting period of one frame ends. During the next period from t9 to t10, the low-level first scan signal PS[0] and the high-level second scan signal NS[0] are applied again to the dummy first scan line PS0 and the dummy second scan line NS0, respectively, so that the next frame starts and lasts at least until t13.

[0232] In the following, reference will be made to Figures 15 to 18 describe Fig.12 The second scanning driver 22 is configured to:

[0233] Fig.15 A schematic diagram of a scan driver according to another exemplary embodiment of the present invention is shown, and Fig.16 A circuit diagram of a stage included in a scan driver according to another exemplary embodiment of the present invention is shown.

[0234] Reference Fig.15 , the second scan driver 22 includes a plurality of stages NST0 to NSTn. Each of the plurality of stages NST0 to NSTn is connected to a corresponding scan line among the second scan lines NS0 to NSn, and is synchronously driven by the first clock signal ECLK1, the second clock signal ECLK2, and the scan clock signal NCLK. The plurality of stages NST0 to NSTn may have the same circuit structure.

[0235] Each of the plurality of stages NST0 to NSTn receives an output signal (eg, a second scan signal) of a previous stage or a second scan start signal NSSP. For example, the first stage NST0 receives the second scan start signal NSSP, and the remaining stages NST1 to NSTn receive an output signal of a corresponding previous stage.

[0236] Each of the plurality of stages NST0 to NSTn receives a first clock signal ECLK1 and a second clock signal ECLK2. The first clock signal ECLK1 and the second clock signal ECLK2 have the same period, and phases of the first clock signal ECLK1 and the second clock signal ECLK2 do not overlap each other.

[0237] The plurality of stages NST0 to NSTn receive a scan clock signal NCLK. The scan clock signal NCLK has a period different from the first clock signal ECLK1 and the second clock signal ECLK2. When the period during which the scan signal is supplied to one second scan line NS0 is one horizontal period (1H), the scan clock signal NCLK may have a period of 1H and may be switched to a high level H.

[0238] Reference Fig.16 , one stage NST0 includes a first driver 410, a second driver 420, an output unit 430, and a holding section 440. Fig.16 In the embodiment, although the transistor is shown as a P-type transistor, the present invention is not limited thereto. For example, the transistor may be an N-type transistor.

[0239] The output unit 430 controls the level of the scan signal NS[0] supplied to the output terminal 409 in response to the voltage applied to the first node N21 and the second node N22. To achieve this, the output unit 430 includes an eighth transistor NT8, a ninth transistor NT9, a tenth transistor NT10, and a third capacitor NC3.

[0240] The eighth transistor NT8 is located between the fourth input terminal 407 supplied with the scan clock signal NCLK and the first node N21, and the gate of the eighth transistor NT8 is connected to the second node N22. The eighth transistor NT8 controls the connection between the fourth input terminal 407 and the first node N21 in response to the voltage applied to the second node N22.

[0241] The ninth transistor NT9 is located between the fourth input terminal 407 and the output terminal 409, and a gate of the ninth transistor NT9 is connected to the first node N21. The ninth transistor NT9 controls the connection between the fourth input terminal 407 and the output terminal 409 in response to a voltage applied to the first node N21.

[0242] The tenth transistor NT10 is located between the output terminal 409 and the second voltage VGL, and the gate of the tenth transistor NT10 is connected to the second node N22. The tenth transistor NT10 controls the connection between the output terminal 409 and the second voltage VGL in response to the voltage applied to the second node N22. In this case, the second voltage VGL is set to a low level such as a low-level voltage.

[0243] The third capacitor NC3 is connected between the first node N21 and the fourth input terminal 407. The third capacitor NC3 is charged with a voltage applied to the first node N21.

[0244] The first driver 410 controls voltages of the second node N22 and the third node N23 in response to signals supplied to the second, third and fourth input terminals 403, 405 and 407. To achieve this, the first driver 410 includes an eleventh transistor NT11 and first to third transistors NT1 to NT3.

[0245] The eleventh transistor NT11 is located between the third input terminal 405 and the first transistor NT1, and a gate of the eleventh transistor NT11 is connected to the fourth input terminal 407. The eleventh transistor NT11 controls connection between the third input terminal 405 and the first transistor NT1 in response to a voltage supplied to the fourth input terminal 407.

[0246] The first transistor NT1 is located between the eleventh transistor NT11 and the second node N22, and the gate of the first transistor NT1 is connected to the second input terminal 403. The first transistor NT1 controls the connection between the eleventh transistor NT11 and the second node N22 in response to the voltage supplied to the second input terminal 403.

[0247] In other words, the eleventh transistor NT11 and the first transistor NT1 may transfer the second scan start signal NSSP to the second node N22 according to the level of the scan clock signal NCLK and the level of the second clock signal ECLK2.

[0248] The second transistor NT2 is located between the third node N23 and the second input terminal 403, and a gate of the second transistor NT2 is connected to the second node N22. The second transistor NT2 controls the connection between the second input terminal 403 and the third node N23 in response to the voltage level of the second node N22.

[0249] The third transistor NT3 is located between the third node N23 and the second voltage VGL, and a gate of the third transistor NT3 is connected to the second input terminal 403. The third transistor NT3 controls the connection between the third node N23 and the second voltage VGL in response to a voltage supplied to the second input terminal 403.

[0250] The second driver 420 controls the voltage of the first node N21, the voltage of the second node N22, and the voltage of the fourth node N24 in response to the voltage level of the first input terminal 401 and the voltage level of the second node N22. To achieve this, the second driver 420 includes a fourth transistor NT4, a fifth transistor NT5, a sixth transistor NT6, a seventh transistor NT7, a first capacitor NC1, and a second capacitor NC2.

[0251] The fourth transistor NT4 is located between the first input terminal 401 and the fifth transistor NT5, and a gate of the fourth transistor NT4 is connected to the second node N22. The fourth transistor NT4 controls the connection between the fifth transistor NT5 and the first input terminal 401 in response to the voltage level of the second node N22.

[0252] The fifth transistor NT5 is located between the fourth transistor NT4 and the first voltage VGH, and a gate of the fifth transistor NT5 is connected to the third node N23. The fifth transistor NT5 controls the connection between the fourth transistor NT4 and the first voltage VGH in response to the voltage level of the third node N23.

[0253] The sixth transistor NT6 is located between the fourth node N24 and the first input terminal 401, and a gate of the sixth transistor NT6 is connected to the third node N23. The sixth transistor NT6 controls the connection between the fourth node N24 and the first input terminal 401 in response to the voltage level of the third node N23.

[0254] The seventh transistor NT7 is located before the fourth node N24 and the first node N21, and a gate of the seventh transistor NT7 is connected to the first input terminal 401. The seventh transistor NT7 controls connection between the fourth node N24 and the first node N21 in response to a voltage level of the first input terminal 401.

[0255] The first capacitor NC1 is connected to a node between the fourth transistor NT4 and the fifth transistor NT5 and to the second node N22 , and the second capacitor NC2 is connected to a node between the fifth transistor NT5 and the sixth transistor NT6 and to the fourth node N24 .

[0256] The holding section 440 controls the voltage of the second node N22 in response to the signal supplied to the fifth input terminal 411. To achieve this, the holding section 440 includes a twelfth transistor NT12.

[0257] The twelfth transistor NT12 is located between the second node N22 and the second voltage VGL, and a gate of the twelfth transistor NT12 is connected to the fifth input terminal 411. The twelfth transistor NT12 controls the connection between the second node N22 and the second voltage VGL in response to the level of the hold control signal BPC supplied to the fifth input terminal 411.

[0258] Fig.17 A timing diagram illustrating a driving method of a scan driver according to another exemplary embodiment of the present invention.

[0259] Reference Fig.17 , the first clock signal ECLK1 and the second clock signal ECLK2 are switched to the low level L at different times (e.g., ECLK1: tc1, tc5, and tc9, etc., ECLK2: tc3, tc7, and tc11, etc.). The second scan start signal NSSP of a high level is supplied synchronously with the first clock signal ECLK1 supplied to the first input terminal 401.

[0260] For example, at time tc1, the first clock signal ECLK1 is switched to a low level, the second scan start signal NSSP and the scan clock signal NCLK maintain a low level, and the second clock signal ECLK2 maintains a high level. In addition, the voltages of the first node N21 and the second node N22 have a low level.

[0261] Since the voltage of the second node N22 is at a low level, the second transistor NT2 , the fourth transistor NT4 , the eighth transistor NT8 , and the tenth transistor NT10 are in a turned-on state.

[0262] The second clock signal ECLK2 of a high level is supplied to the third node N23 through the second transistor NT2 of the on state. In other words, the voltage of the third node N23 is a high level H.

[0263] The second voltage VGL is supplied to the output terminal 409 through the tenth transistor NT10 in the on state. The stage NST0 of the scan driver 22 outputs the second scan signal NS[0] of a low level.

[0264] The scan clock signal NCLK of a low level is supplied to the first node N21 through the eighth transistor NT8 in the turned-on state. The voltage of the first node N21 is stably maintained at a low level.

[0265] Since the voltage of the first node N21 is low, the ninth transistor NT9 is turned on and the low-level scan clock signal NCLK is supplied to the output terminal 409. The stage NST0 of the scan driver 22 stably outputs the low-level second scan signal NS[0].

[0266] During the period from tc1 to tc2, the low-level first clock signal ECLK1 is supplied to the first input terminal 401. The voltage at one end of the first capacitor NC1 is changed by the potential change amount of the first clock signal ECLK1 through the fourth transistor NT4 in the on state. The voltage of the second node N22 is bootstrapped by the potential change amount of the first clock signal ECLK1 through the coupling of the first capacitor NC1. In other words, in the low-level period (tc1 to tc2) of the first clock signal ECLK1, the voltage of the second node N22 is a level L4 lower than the low level L.

[0267] The seventh transistor NT7 is turned on by the low-level first clock signal ECLK1. The turned-on seventh transistor NT7 electrically connects the first node N21 and the fourth node N24. Since the voltage of the first node N21 is low-level, the voltage of the fourth node N24 is low-level.

[0268] Then, the second capacitor NC2 charges a voltage difference between the third node N23 of the high level H and the fourth node N24 of the low level.

[0269] At time tc3 , the second clock signal ECLK2 switches to the low level L. The scanning clock signal NCLK maintains the low level, and the first clock signal ECLK1 maintains the high level.

[0270] Before the second clock signal ECLK2 is switched to the low level L, the second scan start signal NSSP is switched to the high level H. The second scan start signal NSSP is provided only to the first stage NST0, and the second scan start signal NSSP may maintain a high level during a period from tc3 to about tc7. The first clock signal ECLK1 maintains a high level until tc5.

[0271] The eleventh transistor NT11 is turned on by the scan clock signal NCLK of low level L. When the second clock signal ECLK2 of low level L is supplied, the first transistor NT1 and the third transistor NT3 are turned on. Then, the second scan start signal NSSP of high level H is supplied to the second node N22 through the turned-on first transistor NT1, and the second voltage VGL is supplied to the third node N23 through the turned-on third transistor NT3. Therefore, the voltage of the second node N22 is high level, and the voltage of the third node N23 is low level.

[0272] Since the voltage of the third node N23 is low level, the fifth transistor NT5 and the sixth transistor NT6 are turned on. Since the first voltage VGH is provided to one end of the first capacitor NC1 connected to the fourth transistor NT4 by the turned-on fifth transistor NT5, a high level voltage is applied to the opposite end of the first capacitor NC1 to be discharged.

[0273] The first clock signal ECLK1 of the high level H is supplied to the fourth node N24 through the turned-on sixth transistor NT6. Then, the second capacitor NC2 charges a voltage difference between the first clock signal ECLK1 of the high level H and the third node N23 of the low level.

[0274] At time tc5 , the first clock signal ECLK1 switches to the low level L. The second clock signal ECLK2 and the second scan start signal NSSP maintain a high level.

[0275] Before the first clock signal ECLK1 is switched to the low level L, the scan clock signal NCLK is switched to the high level H. The scan clock signal NCLK may maintain a high level during a period from tc5 to about tc9.

[0276] The eleventh transistor NT11 is turned off by the scanning clock signal NCLK having a high level.

[0277] Furthermore, before the first clock signal ECLK1 is switched to the low level L, the voltage of the second node N22 is a high level, and the voltage of the third node N23 is a low level.

[0278] Since the voltage of the second node N22 is at a high level, the second transistor NT2 , the fourth transistor NT4 , the eighth transistor NT8 , and the tenth transistor NT10 are in a turned-off state.

[0279] Since the voltage of the third node N23 is at a low level, the fifth transistor NT5 and the sixth transistor NT6 are in a turned-on state.

[0280] The first voltage VGH is supplied to one end of the first capacitor NC1 connected to the fourth transistor NT4 through the fifth transistor NT5 in the on state.

[0281] The voltage at one end of the second capacitor NC2 is changed by the potential change amount of the first clock signal ECLK1 through the sixth transistor NT6 in the on state. The voltage of the third node N23 is bootstrapped by the potential change amount of the first clock signal ECLK1 through the coupling of the second capacitor NC2. In other words, during the low level period (tc5 to tc6) of the first clock signal ECLK1, the voltage of the third node N23 is a level L5 lower than the low level L.

[0282] In addition, the first clock signal ECLK1 of a low level is supplied to the fourth node N24 through the sixth transistor NT6 of the turned-on state.

[0283] The seventh transistor NT7 is turned on by the low-level first clock signal ECLK1, and the fourth node N24 and the first node N21 are electrically connected by the turned-on seventh transistor NT7.

[0284] Since the voltage of the fourth node N24 is at a low level, the voltage of the first node N21 maintains a low level.

[0285] Since the voltage of the first node N21 is low, the ninth transistor NT9 is turned on and the high-level scan clock signal NCLK is provided to the output terminal 409. Then, the stage NST0 of the scan driver 22 outputs the high-level second scan signal NS[0].

[0286] At time tc7 , the second clock signal ECLK2 switches to the low level L. The scanning clock signal NCLK maintains the high level, and the first clock signal ECLK1 maintains the high level.

[0287] Before the second clock signal ECLK2 is switched to the low level L, the second scan start signal NSSP is switched to the low level L.

[0288] The seventh transistor NT7 is turned off by the first clock signal ECLK1 of a high level, and the eleventh transistor NT11 is turned off by the scan clock signal NCLK of a high level.

[0289] When the second clock signal ECLK2 of the low level L is supplied, the first transistor NT1 and the third transistor NT3 are turned on. Then, the turned-on first transistor NT1 electrically connects the eleventh transistor NT11 and the second node N22, and supplies the second voltage VGL to the third node N23 through the turned-on third transistor NT3. Therefore, the voltage of the second node N22 maintains a high level H, and the voltage of the third node N23 maintains a low level.

[0290] Since the voltage of the third node N23 is low level, the fifth transistor NT5 and the sixth transistor NT6 are turned on. Since the first voltage VGH is provided to one end of the first capacitor NC1 connected to the fourth transistor NT4 by the turned-on fifth transistor NT5, a high level voltage is applied to the opposite end of the first capacitor NC1 to be discharged.

[0291] The first clock signal ECLK1 of the high level H is supplied to the fourth node N24 through the turned-on sixth transistor NT6. Then, the second capacitor NC2 charges a voltage difference between the first clock signal ECLK1 of the high level H and the third node N23 of the low level.

[0292] After time tc8, the scan clock signal NCLK switches to a low level. Then, the low-level scan clock signal NCLK is provided to the output terminal 409 through the ninth transistor NT9 in the on state. In other words, the stage NST0 of the scan driver 22 outputs a low-level second scan signal NS[0].

[0293] Furthermore, at time tc9 , the voltage of the first node N21 is a level L3 lower than the low level L.

[0294] After time tc18, when the scan clock signal NCLK switches to a low level, the output of the high-level scan signal NS[n] from the final stage NSTn to the second scan line NSn is terminated. Then, at time tc23, the hold control signal BPC switches to a low level. In this case, the first clock signal ECLK1, the second clock signal ECLK2, and the scan clock signal NCLK can stop timing.

[0295] When the hold control signal BPC is switched to a low level, the second voltage VGL is supplied to the second node N22, so the tenth transistor NT10 is turned on. Then, the second voltage VGL is supplied to the output terminal 409 through the turned-on tenth transistor NT10. In other words, all stages NST0 to NSTn of the second scan driver 22 maintain the output of the second scan signals NS[0] to NS[n] of the low level.

[0296] Therefore, for low-frequency driving of the display device, the second scan driver 22 according to the present exemplary embodiment may maintain the second scan signals NS[0] to NS[n] at a high level for a predetermined period.

[0297] If known, in Fig.17 In the embodiment, the signal cycle of tc1 to tc23 starts again at tc24 and lasts at least until tc29.

[0298] In the following, reference will be made to Fig.18 An exemplary embodiment of the present invention is described in which the holding portion 240 , 340 , and 440 of each of the scanning drivers 20 , 21 , and 22 and the light emitting drivers 40 and 41 is provided as one constituent element.

[0299] Fig.18 A schematic diagram showing a display device including a holding portion according to another exemplary embodiment of the present invention.

[0300] like Fig.18 As shown in , the display unit 10 of the display device includes a display area DA for displaying an image and a non-display area NDA surrounding the display area DA.

[0301] The scan driver 20 and the light emitting driver 40 may be located in the non-display area NDA. The scan driver 20 includes a plurality of stages (PST1, PST2, PST3, ...), and the light emitting driver 40 includes a plurality of stages (EST1, EST2, EST3, ...).

[0302] In addition, the holding portion 70 may be located in the non-display area NDA. The holding portion 70 may be spaced apart from the scan driver 20 and the light emitting driver 40.

[0303] The holding section 70 includes at least one transistor and is connected to a first holding line HL1 and a second holding line HL2. The first holding line HL1 is connected to all stages (EST1, EST2, EST3, ...) of the light emitting driver 40, and the second holding line HL2 is connected to all stages (PST1, PST2, PST3, ...) of the scanning driver 20.

[0304] For example, the first holding line HL1 is connected to Fig.10 The second holding line HL2 is connected to the second node N12 of the stage EST1 shown in FIG. Figure 6 In addition, the second holding line HL2 is connected to the first node N1 of the stage PST1 shown in FIG. Fig.16 The second node N22 of the stage NST0 shown in FIG.

[0305] Then, the holding section 70 supplies the second voltage VGL to the first and second holding lines HL1 and HL2 according to the level of the holding control signal BPC.

[0306] Exemplary embodiments of the present invention provide a driving device that can apply a signal having the same level for a relatively long period during low-frequency driving, and a display device including the same.

[0307] Exemplary embodiments of the present invention provide a driving device which can apply signals having the same level without applying a clock signal during low-frequency driving, and a display device including the same.

[0308] According to exemplary embodiments of the present invention, the display quality of a display device can be improved.

[0309] According to exemplary embodiments of the present invention, power consumption of a display device can be reduced.

[0310] According to the exemplary embodiments of the present invention, a display device can be stably operated.

[0311] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various modifications may be made to the exemplary embodiments without departing from the spirit and scope of the invention.

Claims

1. A driving device, wherein: The driving device comprises: a plurality of stages configured to output a first voltage or a second voltage lower than the first voltage as an output signal, Wherein, each of the plurality of stages comprises: an output unit configured to supply the first voltage or the second voltage to an output terminal in response to a voltage of the first node and a voltage of the second node; a first driver configured to control the voltage of the second node and the voltage of a third node in response to at least one of a signal of a first input terminal, a signal of a second input terminal, and a signal of a third input terminal; a second driver configured to control the voltage of the first node in response to the signal of the second input terminal and the voltage of the third node; and a first transistor configured to apply the second voltage to the first node or the second node, the first transistor being located between the first node and the second voltage, and a gate of the first transistor being connected to a fourth input terminal, wherein, after a signal is output from an output terminal of a final stage of the plurality of stages, the fourth input terminals of all the stages of the plurality of stages simultaneously receive a holding control signal having an enable level, wherein the enable level of the hold control signal is held until the light emitting period in the low frequency driving mode ends, and The light emitting period in the low-frequency driving mode is longer than the light emitting period in the normal driving mode.

2. The driving device according to claim 1, wherein: The first input terminal receives a signal output from an output terminal of a previous stage or a start signal, the second input terminal receives a first clock signal, and the third input terminal receives a second clock signal, the second clock signal having the same time period as the first clock signal and a phase that does not overlap with the phase of the first clock signal.

3. The driving device according to claim 2, wherein: The output unit comprises: a second transistor located between the first voltage and the output terminal, wherein a gate of the second transistor is connected to the first node; a third transistor, the third transistor being located between the output terminal and the third input terminal, wherein a gate of the third transistor is connected to the second node; a first capacitor connected between the second node and the output terminal; and A second capacitor is connected between the first node and the first voltage.

4. The driving device according to claim 3, wherein: The second node and the third node are the same node, The first driver controls the voltage of the second node in response to the first clock signal and the second clock signal, and The first driver comprises: a fourth transistor located between the first input terminal and the second node, wherein a gate of the fourth transistor is connected to the second input terminal; and a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor being connected in series between the second node and the first voltage, The gate of the fifth transistor is connected to the third input terminal, and the gate of the sixth transistor is connected to the first node.

5. The driving device according to claim 4, wherein: The second driver comprises: a seventh transistor located between the first node and the second input terminal, wherein a gate of the seventh transistor is connected to the second node; and an eighth transistor, the eighth transistor being located between the first node and the second voltage, wherein a gate of the eighth transistor is connected to the second input terminal.

6. The driving device according to claim 3, wherein: The second node and the third node are different nodes, The first driver controls the voltage of the second node and the voltage of the third node in response to the first clock signal, the second clock signal, and the signal output from the output terminal of the previous stage or the start signal, and The first driver comprises: a fourth transistor located between the first input terminal and the third node, wherein a gate of the fourth transistor is connected to the second input terminal; and a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor being connected in series between the third node and the first voltage, The gate of the fifth transistor is connected to the third input terminal, and the gate of the sixth transistor is connected to the first node.

7. The driving device according to claim 6, wherein: The second driver comprises: a seventh transistor, the seventh transistor being located between the first node and the second input terminal, wherein a gate of the seventh transistor is connected to the third node; an eighth transistor located between the first node and the second voltage, wherein a gate of the eighth transistor is connected to the second input terminal; and The first driver further includes: A ninth transistor, the ninth transistor is located between the second node and the third node, wherein a gate of the ninth transistor is connected to the second voltage.

Images