Display Panel

Abstract

A display panel is provided, comprising: a substrate having a non-display area surrounding an opening area and a display area outside the non-display area; a plurality of display elements arranged in the display area; a plurality of first lines extending in a first direction and bypassing the opening area along an edge of the opening area; a plurality of second lines extending in a second direction intersecting the first direction, the plurality of second lines bypassing the opening area along an edge of the opening area; and a plurality of third lines extending in the second direction and bypassing the opening area along an edge of the opening area, at least one of the plurality of third lines including a meandering portion located between adjacent first lines of the plurality of first lines in the non-display area.

Description

[0001] Korean Patent Application No. 10-2018-0090453, filed on August 2, 2018 in the Korean Intellectual Property Office and entitled “DISPLAY PANEL,” is hereby incorporated by reference in its entirety. Technical Field

[0002] One or more embodiments relate to a display panel and a display device including the same. Background Art

[0003] In recent years, the purpose of display devices has become more diverse. In addition, since display devices are thin and lightweight, the scope of their use has gradually expanded. As display devices are variously utilized, various methods can be used in designing the shape of the display devices, and further, functions that can be combined or cooperated with the display devices are increased. Summary of the invention

[0004] According to one or more embodiments, the display panel may include: a substrate having a non-display area surrounding an opening area and a display area outside the non-display area; a plurality of display elements arranged in the display area; a plurality of first lines extending in a first direction and bypassing the opening area along an edge of the opening area; a plurality of second lines extending in a second direction intersecting the first direction, the plurality of second lines bypassing the opening area along an edge of the opening area; and a plurality of third lines extending in the second direction and bypassing the opening area along an edge of the opening area, at least one of the plurality of third lines including a meandering portion in the non-display area located between adjacent first lines of the plurality of first lines.

[0005] The meandering portion of at least one of the plurality of third lines may be arranged between the meandering portions of adjacent first lines.

[0006] At least one of the plurality of second lines may include a meandering portion between adjacent first lines in the non-display area.

[0007] The meandering portion of at least one of the plurality of third lines may be spaced apart from the meandering portion of at least one of the plurality of second lines.

[0008] The plurality of third lines may have a constant voltage.

[0009] At least one of the plurality of third lines may further include an auxiliary line extending opposite to the meandering portion.

[0010] The auxiliary line may be connected to at least one third line among the plurality of third lines.

[0011] A pitch between adjacent first lines in the non-display area may be smaller than a pitch between adjacent first lines in the display area.

[0012] The display panel may further include: an encapsulation substrate covering the display element and facing the substrate; and a sealing material surrounding the opening region between the substrate and the encapsulation substrate.

[0013] The display panel may further include an electrode layer disposed in the non-display area, the electrode layer including a hole corresponding to the opening area.

[0014] The electrode layer may have a constant voltage.

[0015] The electrode layer may cover at least a portion of the plurality of first lines, the plurality of second lines, and the plurality of third lines.

[0016] According to one or more embodiments, a display panel may include: a substrate including a non-display area surrounding an opening area and a display area surrounding the non-display area; a plurality of display elements arranged in the display area; a plurality of voltage lines arranged above the substrate and bypassing the opening area along edges of the opening area in the non-display area; a plurality of signal lines arranged above the substrate and bypassing the opening area along edges of the opening area in the non-display area; and a packaging member covering the display elements, wherein at least one of the plurality of voltage lines includes a tortuous portion located between adjacent signal lines in the non-display area.

[0017] The signal line may include a data line extending to cross the plurality of voltage lines.

[0018] At least one of the plurality of voltage lines may further include an auxiliary line extending opposite to the meandering portion.

[0019] The signal line may include a scan line extending in the same direction as a direction in which the plurality of voltage lines extend.

[0020] A meandering portion of at least one of the voltage lines may not overlap a meandering portion of an adjacent signal line.

[0021] The display panel may further include an insulating layer disposed between the plurality of signal lines and the plurality of voltage lines.

[0022] The display panel may further include an electrode layer having a ring shape disposed in the non-display area, the electrode layer including a hole corresponding to the opening area.

[0023] The voltage line may have a constant voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0025] Figure 1 shows a perspective view of a display device according to an embodiment;

[0026] FIG. 2A to FIG. 2C shows a cross-sectional view of a display device according to an embodiment;

[0027] FIG. 3A to FIG. 3C shows a cross-sectional view of a display device according to another embodiment;

[0028] Figure 4 shows a plan view of a display panel according to an embodiment;

[0029] Figure 5 An equivalent circuit diagram of a pixel in a display panel according to an embodiment is shown;

[0030] Fig. 6A A plan view showing a pixel circuit of one pixel in a display panel according to an embodiment;

[0031] Figure 6B Shown throughout Fig. 6A a cross-sectional view of a display element of a pixel circuit;

[0032] Figure 7 A plan view showing wiring around an opening area according to an embodiment;

[0033] Figure 8 Shows Figure 7 an enlarged plan view of section VIII;

[0034] Fig. 9A and Fig. 9B Shown along Figure 8 A cross-sectional view of the wiring taken along line IX-IX';

[0035] Fig. 10A and Fig. 10B Shown along Figure 7 A cross-sectional view of a display panel according to an embodiment taken along line XX';

[0036] Fig.11 shows a plan view of a display panel according to another embodiment;

[0037] Fig.12 shows a plan view of a display panel according to another embodiment;

[0038] Fig.13 Shows Fig.12 an enlarged plan view of part XIII;

[0039] Fig.14 shows a plan view of a display panel according to another embodiment;

[0040] Fig.15A and Fig. 15B Shown along Fig.14a cross-sectional view of the display panel according to the embodiment taken along line XV-XV′; and

[0041] Fig.16 A plan view of a display panel according to another embodiment is shown. DETAILED DESCRIPTION

[0042] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations to those skilled in the art.

[0043] In the drawings, the sizes of layers and regions may be exaggerated for clarity. It will also be understood that when a layer or element is referred to as being "on" another layer or element, the layer or element can be directly on the other layer or element, or there may be intervening layers or intervening elements. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more intervening layers. Like reference numerals refer to like elements throughout.

[0044] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When a statement such as "at least one of..." is placed after a list of elements (elements), it modifies the entire list of elements (elements), rather than modifying the individual elements (elements) in the list.

[0045] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component.

[0046] As used herein, the singular forms "a (kind / one)" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises / includes" and variations thereof used herein specify the presence of stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0047] When a certain embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0048] The embodiment can prevent wiring and the like arranged outside the display area from being viewed due to external light. However, it should be understood that the effects described herein should be considered only in a descriptive sense and not for limiting the disclosure.

[0049] It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, the layer, region, or component may be “directly connected” to the other layer, region, or component, or may be “indirectly connected” to the other layer, region, or component and have other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “connected or electrically connected” to another layer, region, or component, the layer, region, or component may be “directly connected or electrically connected” to the other layer, region, or component, or may be “indirectly connected or electrically connected” to the other layer, region, or component and have other layers, regions, or components interposed therebetween.

[0050] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0051] Reference Figure 1 , the display device 1 may include a display area DA that emits light and a non-display area NDA that does not emit light. The display device 1 may provide a predetermined image by using light emitted from a plurality of pixels arranged in the display area DA.

[0052] The display device 1 may include an opening area OA. The opening area OA may be at least partially surrounded by the display area DA. In an embodiment, Figure 1 It is shown that the opening area OA is completely surrounded by the display area DA. The non-display area NDA may include a first non-display area NDA1 surrounding the opening area OA and a second non-display area NDA2 surrounding the periphery of the display area DA. For example, the first non-display area NDA1 may completely surround the perimeter of, for example, the opening area OA, the display area DA may completely surround the perimeter of, for example, the first non-display area NDA1, and the second non-display area NDA2 may completely surround the perimeter of, for example, the display area DA.

[0053] The opening area OA may be an area where an electronic component is disposed. The opening area OA may be understood as a transmission area through which light and / or sound output from the electronic component to the outside or propagated from the outside toward the electronic component may pass. In an embodiment, when light passes through the opening area OA, the transmittance may be about 50% or more, for example, about 70% or more, about 75% or more, about 80% or more, about 85% or more, or about 90% or more.

[0054] Although an organic light emitting display device is exemplarily described below as the display device 1 according to an embodiment, the display device is not limited thereto. In another embodiment, various types of display devices such as an inorganic light emitting display and a quantum dot light emitting display may be used.

[0055] although Figure 1 The opening area OA is shown to be arranged at one side (upper right side) of the quadrilateral display area DA, but the embodiment is not limited thereto. The shape of the display area DA can be, for example, a circle, an ellipse, or a polygon such as a triangle or a pentagon, and the position of the opening area OA can be changed in various ways.

[0056] FIG. 2A to FIG. 2C is a cross-sectional view of a display device 1 according to the embodiment. FIG. 2A to FIG. 2C Along with Figure 1 Corresponding to the cross-section taken by line II-II'.

[0057] Reference Figure 2A , the display device 1 may include a display panel 10 including a display element and a component 20 corresponding to the opening area OA.

[0058] The display panel 10 may include a substrate 100, an encapsulation substrate 300 as an encapsulation member facing the substrate 100, and a display element layer 200 disposed between the substrate 100 and the encapsulation substrate 300. A sealing material (sealant) 350 surrounding a side surface of the display element layer 200 may be disposed between the substrate 100 and the encapsulation substrate 300. Figure 2A It is shown that the sealing material 350 is arranged at two opposite sides of the opening area OA, but it is understood that the opening area OA is completely surrounded by the sealing material 350 when viewed in a direction perpendicular to the main surface of the substrate 100 .

[0059] The substrate 100 may include, for example, glass or a polymer resin. The polymer resin may include, for example, polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP). The substrate 100 including the polymer resin may have a flexible, rollable or bendable property. The substrate 100 may have a multilayer structure including a layer and an inorganic layer including the above-mentioned polymer resin. For example, the substrate 100 may include a first resin layer, a first inorganic layer, a second resin layer and a second inorganic layer stacked in sequence. The encapsulation substrate 300 may include, for example, glass or the above-mentioned polymer resin.

[0060] The display element layer 200 may include a circuit layer including a thin film transistor TFT, an organic light emitting diode OLED as a display element connected to the thin film transistor TFT, and at least one insulating layer IL between the circuit layer and the OLED. The thin film transistor TFT and the OLED connected thereto may be arranged in the display area DA, and some wirings WL of the display element layer 200 may be located in the first non-display area NDA1 (for example, the first non-display area NDA1 is located in the first non-display area NDA1). Figure 4 The wiring WL may provide a predetermined signal or voltage to pixels spaced apart from each other with the opening area OA therebetween. Figure 2A It is shown that the wiring WL does not overlap the sealing material 350 in the first non-display area NDA1 , but a portion of the sealing material 350 may also be disposed over the wiring WL.

[0061] The display panel 10 may include a through hole 10H corresponding to (eg, overlapping) the opening area OA. For example, the substrate 100 and the encapsulation substrate 300 may include through holes 100H and 300H corresponding to (eg, overlapping) the opening area OA, respectively. In addition, the display element layer 200 may include a through hole corresponding to the opening area OA.

[0062] Additional elements such as an input detector configured to detect a touch input, an anti-reflection member including a polarizer, a retarder, a color filter and / or a black matrix, and a transparent window may be further arranged above the display panel 10. For example, the additional element may be located on the encapsulation substrate 300, for example, so that the encapsulation substrate 300 is located between the display element layer 200 and the additional element.

[0063] The component 20 may be located in the opening area OA. The opening area OA may be a component area (e.g., a camera area, a sensor area, a speaker area, etc.). The component 20 may be an electronic component that uses light or sound. For example, the electronic component may be a sensor such as an infrared sensor that receives and uses light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small lamp that outputs light, or a speaker that outputs sound. Electronic components that use light may use light in various bands such as visible light, infrared light, and ultraviolet light. In the case where the display panel 10 includes a through hole 10H corresponding to the opening area OA, the light or sound output or received by the electronic component may be more effectively utilized.

[0064] The display panel 10 includes a through hole 10H corresponding to the opening area OA. Figure 2A Differently, some components of the display panel 10 may not include through holes. Figure 2BAs shown in FIG. 1 , although the package substrate 300 includes a through hole 300H corresponding to the opening area OA, the substrate 100 may not include a through hole. Figure 2C As shown in , both the substrate 100 and the package substrate 300 may not include a through hole corresponding to the opening area OA. Figure 2B and Figure 2C As shown in FIG. 1 , even if the substrate 100 does not include the through hole 100H, the portion of the display element layer 200 corresponding to the opening area OA is removed, so the light transmittance of the electronic element can be ensured. Figure 2B and Figure 2C In the case of the display panel 10 shown in FIG. 1 , it may be appropriate to use an electronic component utilizing light as the electronic component.

[0065] FIG. 2A to FIG. 2C The component 20 is described as being located below the display panel 10. In another embodiment, the component 20 may be located inside the through hole 10H to overlap with the side surface of the display panel 10 defining the through hole 10H in the x-direction.

[0066] The component 20 may be another member other than the above-mentioned electronic components. For example, in the case where the display panel 10 is used as a smart watch or a dashboard for a car, the component 20 may be a member including a pointer of a clock or a pointer indicating predetermined information (such as the speed of the vehicle, etc.). Alternatively, the component 20 may include an element such as a decoration that increases the aesthetics of the display panel 10.

[0067] FIG. 3A to FIG. 3C is a cross-sectional view of a display device 1 ′ according to another embodiment. FIG. 3A to FIG. 3C Along with Figure 1 Corresponding to the cross-section taken by line II-II'.

[0068] Reference Figure 3A , the display device 1' may include a display panel 10' and a component 20. In addition, the display device 1' may further include an input detector configured to detect a touch input, an anti-reflection member, and a window disposed above the display panel 10'.

[0069] The display panel 10' according to the present embodiment may include a thin film encapsulation layer 300' as an encapsulation member. For example, the thin film encapsulation layer 300' of the display panel 10' may be thinner than FIG. 2A to FIG. 2C The encapsulation substrate 300 of the display panel 10 in the embodiment is thin and flexible. In this case, the flexibility of the display panel 10' is further improved. For the convenience of description, the following mainly describes the differences.

[0070] The thin film encapsulation layer 300' may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, Figure 3AA first inorganic encapsulating layer 310 and a second inorganic encapsulating layer 330 and an organic encapsulating layer 320 located between the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 are shown.

[0071] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer material such as acrylic resin, epoxy resin, PI, and polyethylene.

[0072] The display panel 10' may include a through hole 10H corresponding to the opening area OA. For example, the substrate 100 and the thin film encapsulation layer 300' may include through holes 100H and 300H, respectively. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 and the organic encapsulation layer 320 may include holes corresponding to (e.g., overlapping) the opening area OA, respectively. The size of the hole of the organic encapsulation layer 320 may be larger than the size of the hole of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. Therefore, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contact each other around the opening area OA. For example, as Figure 3A As shown in , the organic encapsulation layer 320 may be, for example, completely enclosed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, so that the edge of the first inorganic encapsulation layer 310 and the edge of the second inorganic encapsulation layer 330 may contact each other and extend toward the opening area OA, for example, in parallel with the substrate 100. Figure 3A As shown in FIG. 1 , side surfaces of the first and second inorganic encapsulating layers 310 and 330 in the display element layer 200 and the substrate 100 and the insulating layer IL may be flush with each other to define side walls of the through holes 10H.

[0073] The display panel 10' includes a through hole 10H corresponding to the opening area OA. Figure 3A Differently, the display panel 10' may not include the through hole 10H. Figure 3B As shown in , although the thin film encapsulation layer 300' includes a through hole 300H corresponding to the opening area OA, the substrate 100 may not include the through hole 100H. Figure 3C As shown in , both the substrate 100 and the thin film encapsulation layer 300' may not include a through hole corresponding to the opening area OA. Figure 3B and Figure 3C As shown in FIG. 1 , even if the substrate 100 does not include the through hole 100H, a portion of the display element layer 200 corresponding to the opening area OA is removed, and thus the light transmittance of the electronic element can be ensured as described above.

[0074] In the case where the thin film encapsulation layer 300' does not include a through hole, such as Figure 3C As shown in FIG. 1 , each of at least one inorganic encapsulation layer and at least one organic encapsulation layer may cover the substrate 100 in the opening area OA. In this case, a portion of the display element layer 200 corresponding to the opening area OA between the substrate 100 and the thin film encapsulation layer 300 ′ may be removed. Figure 3A It is shown that a portion of the insulating layer IL corresponding to the opening area OA is completely removed, but only some sub-layers of the multi-layered insulating layer IL may be removed.

[0075] FIG. 3A to FIG. 3C The component 20 is shown as being located below the display panel 10'. In another embodiment, for example, the component 20 may be located inside the through hole 10H (e.g., inside the through hole 100H extending to the substrate 100, the through hole 200H of the display element layer 200, and the through hole 300H of the thin film encapsulation layer 300'). In another example, the component 20 may be located above the substrate 100 and located Figure 3B The inside of the through hole 200H of the display element layer 200 .

[0076] Figure 4 is a plan view of a display panel 10 according to an embodiment.

[0077] Reference Figure 4 , the display panel 10 includes a plurality of pixels P arranged in a display area DA. Each pixel P may include a display element such as an organic light emitting diode. Each pixel P may emit, for example, red, green, blue, or white light through an organic light emitting diode. In this specification, a pixel P may be understood as a pixel that emits light of one color among red, green, blue, and white as described above. By referring to Figures 2A to 3C The described encapsulation member covers the display area DA and can protect the display area DA from external air or moisture.

[0078] The opening area OA may be arranged in the display area DA (eg, in Figure 4 , the display area DA is represented as a dotted quadrilateral), and a plurality of pixels P may be arranged around the opening area OA. The plurality of pixels P may surround the opening area OA, and a first non-display area NDA1 where no pixels P are arranged may be located between the opening area OA and the display area DA. For example, the first non-display area NDA1 may be located between the opening area OA and the plurality of pixels P in the display area DA. Wiring configured to apply a predetermined signal or power to the plurality of pixels P spaced around the opening area OA may bypass the opening area OA (for example, be located completely outside the opening area OA). The following will refer to Figure 7 To describe the structure that allows bypass wiring.

[0079] Each pixel P is arranged in the non-display area NDA (for example, in the second non-display area NDA2 (for example, in Figure 4 In the figure, the second non-display area NDA2 is represented as the area between the dotted quadrilateral and the outer solid line)) and is electrically connected to the external circuit. The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the first power line 160 and the second power line 170 may be arranged in the second non-display area NDA2.

[0080] The first scan driving circuit 110 may provide a scan signal to each pixel P through a scan line SL. The first scan driving circuit 110 may provide an emission control signal to each pixel P through an emission control line EL. The second scan driving circuit 120 may be arranged side by side with the first scan driving circuit 110, and the display area DA is located between the second scan driving circuit 120 and the first scan driving circuit 110. Some pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 110, and other pixels P may be electrically connected to the second scan driving circuit 120. In another embodiment, the second scan driving circuit 120 may be omitted.

[0081] The terminal 140 may be arranged on one side of the substrate 100. The terminal 140 may not be covered by the insulating layer, but may be exposed and electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits a signal or power of the controller to the display panel 10. The control signal generated by the controller may be transmitted to the first scan driving circuit 110 and the second scan driving circuit 120 respectively through the printed circuit board PCB. The controller may transmit the driving voltage ELVDD and the common voltage ELVSS (see below) respectively through the first connection wiring 161 and the second connection wiring 171. Figure 5 ) is supplied to the first power line 160 and the second power line 170. The driving voltage ELVDD may be supplied to each pixel P through the driving voltage line PL connected to the first power line 160, and the common voltage ELVSS may be supplied to the counter electrode of the pixel P connected to the second power line 170.

[0082] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each pixel P through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151. Figure 4 The data driving circuit 150 is shown to be arranged in the printed circuit board PCB, but in another embodiment, the data driving circuit 150 may be arranged over the substrate 100. For example, the data driving circuit 150 may be arranged between the terminal 140 and the first power line 160.

[0083] The first power line 160 may include a first sub-line 162 and a second sub-line 163 extending side by side in the x-direction, and the display area DA is located between the first sub-line 162 and the second sub-line 163 in the y-direction. The first power line 160 may be electrically connected to the terminal 140 via a first connection wiring 161 extending from the first sub-line 162. The second power line 170 has a ring shape with one side open and may partially surround the display area DA. The second power line 170 may be electrically connected to the terminal 140 via a second connection wiring 171.

[0084] Figure 5 is an equivalent circuit diagram of one pixel P in the display panel 10 according to the embodiment.

[0085] Reference Figure 5 , the pixel P includes a pixel circuit PC and an OLED connected to the pixel circuit PC. The pixel circuit PC may include a storage capacitor Cst and a plurality of thin film transistors. The thin film transistors and the storage capacitor Cst may be connected to the signal lines SL, SL-1, EL and DL, the initialization voltage line VL and the driving voltage line PL.

[0086] although Figure 5 It is shown that each pixel P is connected to the signal lines SL, SL-1, EL and DL, the initialization voltage line VL and the driving voltage line PL, but the embodiment is not limited thereto. In another embodiment, at least one of the signal lines SL, SL-1, EL and DL, the initialization voltage line VL and the driving voltage line PL can be shared by adjacent pixels.

[0087] The plurality of thin film transistors may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 , and a second initialization thin film transistor T7 .

[0088] The signal line may include a scan line SL configured to transmit a scan signal Sn, a previous scan line SL-1 configured to transmit a previous scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL configured to transmit an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SL and configured to transmit a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transmits an initialization voltage Vint for initializing the driving thin film transistor T1 and the pixel electrode.

[0089] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the OLED through the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin film transistor T2 and drives the driving current I OLED Supply to OLED.

[0090] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scanning line SL, the switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, the switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1, and is connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scanning signal Sn transmitted through the scanning line SL, and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0091] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1, and is connected to the pixel electrode of the OLED through the emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and the driving thin film transistor T1 is diode-connected by electrically connecting the driving gate electrode G1 of the driving thin film transistor T1 to the driving drain electrode D1 of the driving thin film transistor T1.

[0092] The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1, the first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and the first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and performs an operation of initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0093] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0094] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the OLED.

[0095] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL, so that the driving voltage ELVDD is transmitted to the OLED and the driving current I OLED Flow through the OLED.

[0096] The second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SL-1, the second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to initialize the pixel electrode of the OLED.

[0097] although Figure 5 The first initialization thin film transistor T4 and the second initialization thin film transistor T7 are shown to be connected to the previous scan line SL-1, but the embodiment is not limited thereto. In another embodiment, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 and driven in response to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the next scan line) and driven in response to a signal transmitted through the signal line.

[0098] The second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the OLED receives the common voltage ELVSS. Therefore, the OLED can receive the driving current I from the driving thin film transistor T1. OLED and emits light to display images.

[0099] although Figure 5 It is illustrated that each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 includes a double gate electrode, but each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may include one gate electrode.

[0100] Fig. 6A is a plan view of a pixel circuit of a pixel p in the display panel 10 according to the embodiment.

[0101] Reference Fig. 6A , a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7 are arranged along the semiconductor layer 1130. The semiconductor layer 1130 is arranged above a substrate having a buffer layer including an inorganic insulating material arranged thereon.

[0102] Some areas of the semiconductor layer 1130 correspond to the semiconductor layer of the driving thin film transistor T1, the semiconductor layer of the switching thin film transistor T2, the semiconductor layer of the compensation thin film transistor T3, the semiconductor layer of the first initialization thin film transistor T4, the semiconductor layer of the operation control thin film transistor T5, the semiconductor layer of the emission control thin film transistor T6, and the semiconductor layer of the second initialization thin film transistor T7. In other words, it can be understood that the semiconductor layer of the driving thin film transistor T1, the semiconductor layer of the switching thin film transistor T2, the semiconductor layer of the compensation thin film transistor T3, the semiconductor layer of the first initialization thin film transistor T4, the semiconductor layer of the operation control thin film transistor T5, the semiconductor layer of the emission control thin film transistor T6, and the semiconductor layer of the second initialization thin film transistor T7 are connected to each other and bent into various shapes.

[0103] The semiconductor layer 1130 includes a channel region and a source region and a drain region located at two opposite sides of the channel region. The source region and the drain region can be understood as the source electrode and the drain electrode of the relevant thin film transistor. In the following, for the convenience of description, the source region and the drain region are respectively referred to as the source electrode and the drain electrode.

[0104] The driving thin film transistor T1 includes a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 located in two opposite sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 can form a long channel length inside a narrow space by having a curved shape such as an inverted Ω shape. In the case where the length of the driving channel region is long, since the driving range of the gate voltage is widened, the grayscale of the light emitted from the OLED can be more finely controlled, and the display quality can be improved.

[0105] The switching thin film transistor T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 located in two opposite sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0106] The compensation thin film transistor T3 is a double thin film transistor and may include a compensation gate electrode G3 respectively overlapping two compensation channel regions, and includes a compensation source electrode S3 and a compensation drain electrode D3 arranged in two opposite sides of the compensation channel region. The compensation thin film transistor T3 may be connected to the driving gate electrode G1 of the driving thin film transistor T1 through a node connection line 1174 described below.

[0107] The first initialization thin film transistor T4 is a double thin film transistor and may include a first initialization gate electrode G4 respectively overlapping two first initialization channel regions, and a first initialization source electrode S4 and a first initialization drain electrode D4 arranged in two opposite sides of the first initialization channel region.

[0108] The operation control thin film transistor T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 arranged in two opposite sides of the operation control channel region. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0109] The emission control thin film transistor T6 may include an emission control gate electrode G6 overlapping the emission control channel region and an emission control source electrode S6 and an emission control drain electrode D6 arranged in two opposite sides of the emission control channel region. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0110] The second initialization thin film transistor T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 arranged in two opposite sides of the second initialization channel region.

[0111] The above-mentioned thin film transistors may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0112] The scan line SL, the previous scan line SL- 1 , the emission control line EL, and the driving gate electrode G1 may be disposed over the semiconductor layer 1130 with an insulating layer therebetween.

[0113] The scan line SL may extend in the x direction. Some regions of the scan line SL may correspond to the switch gate electrode G2 and the compensation gate electrode G3. For example, regions of the scan line SL that overlap the channel region of the switch thin film transistor T2 and the channel region of the compensation thin film transistor T3 may be the switch gate electrode G2 and the compensation gate electrode G3.

[0114] The previous scan line SL-1 may extend in the x-direction, and some regions of the previous scan line SL-1 may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7. For example, regions of the previous scan line SL-1 overlapping the channel regions of the first initialization thin film transistor T4 and the second initialization thin film transistor T7 may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0115] The emission control line EL may extend in the x direction. Some regions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6. For example, regions of the emission control line EL overlapping the channel region of the operation control thin film transistor T6 and the channel region of the emission control thin film transistor 7 may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0116] The driving gate electrode G1 is a floating electrode and may be electrically connected to the compensation thin film transistor T3 through the node connection line 1174 .

[0117] The electrode voltage line HL may be disposed over the scan line SL, the previous scan line SL- 1 , the emission control line EL, and the driving gate electrode G1 with an insulating layer therebetween.

[0118] The electrode voltage line HL may extend in the x direction to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1 and form a storage capacitor Cst with the driving gate electrode G1. For example, the driving gate electrode G1 may serve as a first storage capacitor plate Cst1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may serve as a second storage capacitor plate Cst2 of the storage capacitor Cst.

[0119] The second storage capacitor plate Cst2 of the storage capacitor Cst is electrically connected to the driving voltage line PL. In this regard, the electrode voltage line HL can be connected to the driving voltage line PL arranged above the electrode voltage line HL through the contact hole 1158. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the voltage level of the driving voltage line PL. For example, the electrode voltage line HL can have a constant voltage of +5V. The electrode voltage line HL can be understood as a lateral driving voltage line.

[0120] Since the driving voltage line PL extends in the y direction and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the x direction crossing the y direction, the plurality of driving voltage lines PL and the electrode voltage lines HL may form a mesh structure in the display area DA.

[0121] The data line DL, the driving voltage line PL, the initialization link line 1173, and the node connection line 1174 may be disposed above the electrode voltage line HL with an insulating layer therebetween.

[0122] The data line DL may extend in the y direction, and may be connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode S2.

[0123] As described above, the driving voltage line PL extends in the y direction and is connected to the electrode voltage line HL through the contact hole 1158. In addition, the driving voltage line PL may be connected to the operation control thin film transistor T5 through the contact hole 1155. The driving voltage line PL may be connected to the operation control source electrode S5 through the contact hole 1155.

[0124] One end of the initialization connection line 1173 may be connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to the initialization voltage line VL (which will be described below) through the contact hole 1151 .

[0125] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157 .

[0126] The initialization voltage line VL may be disposed over the data line DL, the driving voltage line PL, the initialization link line 1173, and the node connection line 1174 with an insulating layer therebetween.

[0127] The initialization voltage line VL extends in the x direction. The initialization voltage line VL may be connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through the initialization connection line 1173. The initialization voltage line VL may have a constant voltage (eg, -2V).

[0128] The initialization voltage line VL may be disposed at a position adjacent to the pixel electrode 210 (see FIG. Fig. 6A ) and may include the same material as that of the pixel electrode 210. The pixel electrode 210 may be connected to the emission control thin film transistor T6. The pixel electrode 210 may be connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 may be connected to the emission control drain electrode D6 through the contact hole 1153.

[0129] although Fig. 6A It is shown that the initialization voltage line VL is arranged in the same layer as the pixel electrode 210 , but the initialization voltage line VL may be arranged in the same layer as the electrode voltage line HL.

[0130] Reference Figure 6B The pixel electrode 210 is disposed on the planarization insulating layer PIL covering the pixel circuit PC. One end of the pixel electrode 210 is covered by the pixel definition layer PDL.

[0131] The intermediate layer 220 is disposed on a portion of the pixel electrode 210 exposed by the opening of the pixel defining layer PDL, and includes an emission layer 222. The emission layer 222 may include a polymer or a low-molecular organic material that emits light of a predetermined color. Figure 6B As shown in , the intermediate layer 220 may include a first functional layer 221 disposed below the emission layer 222 and / or a second functional layer 223 disposed on the emission layer 222 .

[0132] The first functional layer 221 may be a single layer or a multilayer. For example, when the first functional layer 221 includes a polymer material, the first functional layer 221 is a hole transport layer (HTL) of a single structure and may include poly (3,4) -ethylene - dioxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 221 includes a low molecular weight material, the first functional layer 221 may include a hole injection layer (HIL) and the HTL.

[0133] The second functional layer 223 is not necessarily provided. For example, in the case where the first functional layer 221 and the emission layer 222 include a polymer material, the second functional layer 223 is preferably formed to make the characteristics of the OLED excellent. The second functional layer 223 may be a single layer or a multilayer. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0134] The counter electrode 230 faces the pixel electrode 210, and the intermediate layer 220 is located between the counter electrode 230 and the pixel electrode 210. The counter electrode 230 may include a conductive material with a low work function. For example, the counter electrode 230 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca and one of their alloys. Alternatively, the counter electrode 230 may also include a (semi) transparent layer including a conductive material such as ITO, IZO, ZnO or In over the (semi) transparent layer including the above materials. 2 O 3 Layers of material.

[0135] although Figure 5 and Fig. 6A It is shown that the pixel circuit PC includes seven thin film transistors and one storage capacitor, but the embodiment is not limited thereto. The number of thin film transistors and the storage capacitor may be variously changed according to the design of the pixel circuit PC.

[0136] Figure 7 is a plan view of wiring around an opening area according to an embodiment, Figure 8 yes Figure 7 An enlarged plan view of section VIII, Fig. 9A and Fig. 9B Shown along Figure 8 A cross-sectional view of the wiring taken along line IX-IX'.

[0137] Reference Figure 7 , the data lines DL0 to DL7 may extend in the y direction, and the driving voltage lines PL0 to PL7 may extend in the y direction. The driving voltage lines PL0 and PL7 of the driving voltage lines PL0 to PL7 may extend continuously to cross the display area DA, but the driving voltage lines PL1 to PL6 around the opening area OA may be cut around the opening area OA. The cut portions of the driving voltage lines PL1 to PL6 corresponding to the upper portion of the opening area OA may be connected to the reference Figure 4 As described above, the second sub-line 163 , portions of the cut driving voltage lines PL1 to PL6 corresponding to the lower portion of the opening area OA may be connected to the first sub-line 162 .

[0138] The data lines DL1 to DL6 may bypass the opening area OA. For example, each of the data lines DL1 to DL6 may include a first portion extending along the y direction and a second portion bypassing (eg, bending) along an edge of the opening area OA. Figure 7 As shown in , the first portion may be linear and include two portions on opposite sides of the opening area OA, and the second portion may be a tortuous (e.g., curved) portion connecting the two portions of the linear portion. The tortuous (e.g., curved) portion of each of the data lines DL1 to DL6 may be located in the first non-display area NDA1 (e.g., completely outside the opening area OA). For example, as Figure 7 As shown in , the meandering portion of each of the data lines DL1 to DL6 located in the first non-display area NDA1 may be bent around the opening area OA (e.g., trace the shape of the opening area OA) to connect two corresponding linear portions of a corresponding data line among the data lines DL1 to DL6. Figure 7 In the embodiment, each meandering portion has an arc shape (eg, a smoothly curved arc shape), but the present disclosure is not limited thereto. For example, each meandering portion generally has an arc shape, but partially has a Z-shape, etc.

[0139] The pixels P located above and below the opening area OA may be electrically connected to the data lines DL1 to DL6 bypassing the opening area OA, and may receive signals from the relevant data lines DL1 to DL6. Figure 7 As shown in FIG, the first, second, and third data lines DL1 to DL6 may be bent along the left edge of the opening area OA, and the fourth, fifth, and sixth data lines DL4, DL5, and DL6 may be bent along the right edge of the opening area OA.

[0140] The scan lines SL0 to SL5 may extend in the x direction crossing the data lines DL0 to DL7. The first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 may bypass (eg, detour) the opening area OA. Figure 7As shown in , the first scan line SL1 and the second scan line SL2 may be bent along the upper edge of the opening area OA, and the third scan line SL3 and the fourth scan line SL4 may be bent along the lower edge of the opening area OA. Each of the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 may include a portion extending along the x direction in the display area DA and a portion meandering (e.g., bending) along the edge of the opening area OA in the first non-display area NDA1. The pixels P located at the left and right sides of the opening area OA may be electrically connected to the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 bypassing the opening area OA.

[0141] The electrode voltage lines HL0 to HL4 may extend in the x-direction intersecting the data lines DL0 to DL7. The first electrode voltage line HL1, the second electrode voltage line HL2, and the third electrode voltage line HL3 may bypass the opening area OA. For example, the first electrode voltage line HL1 may include a portion extending in the x-direction and a portion bypassing the upper side of the opening area OA (e.g., bending around the upper side of the opening area OA). The third electrode voltage line HL3 may include a portion extending in the x-direction and a portion bypassing the lower side of the opening area OA (e.g., bending around the lower side of the opening area OA). The second electrode voltage line HL2 may include a portion extending in the x-direction and portions bypassing the upper and lower sides of the opening area OA, respectively. The tortuous portions of the second electrode voltage line HL2 may be connected to each other to form a ring shape.

[0142] In an embodiment, the number of data lines DL1 to DL6 bypassing the opening area OA may be greater than the number of scan lines SL1 to SL4 bypassing the opening area OA and / or the number of electrode voltage lines HL1 to HL3 bypassing the opening area OA. In another embodiment, the number of data lines bypassing the opening area OA, the number of scan lines bypassing the opening area OA, and / or the number of electrode voltage lines bypassing the opening area OA may be the same. In yet another embodiment, the number of data lines bypassing the opening area OA may be smaller than the number of scan lines bypassing the opening area OA and / or the number of electrode voltage lines bypassing the opening area OA.

[0143] A meandering portion (or curved portion) of at least one of the electrode voltage lines HL1 to HL3 in the first non-display area NDA1 may be located between meandering portions (or curved portions) of adjacent (neighboring) data lines in the first non-display area NDA1.

[0144] For example, the meander portion HL1-CP of the first electrode voltage line HL1 may be located between the meander portion DL1-CP of the first data line DL1 and the meander portion DL2-CP of the second data line DL2 adjacent to each other (see FIG. 2 ). Figure 7 and Figure 8 In addition, the meandering portion HL1-CP of the first electrode voltage line HL1 may be located between the meandering portion of the fifth data line DL5 and the meandering portion of the sixth data line DL6 adjacent to each other (see FIG. 2 ). Figure 7 The meandering portions HL2-CP1 and HL2-CP2 of the second electrode voltage line HL2 may be located between the meandering portion DL2-CP of the second data line DL2 and the meandering portion DL3-CP of the third data line DL3 adjacent to each other, and may be connected to each other to form a ring shape (see Figure 7 and Figure 8 In addition, the meandering portions HL2-CP1 and HL2-CP2 of the second electrode voltage line HL2 may be located between the meandering portion of the fourth data line DL4 and the meandering portion of the fifth data line DL5 adjacent to each other (see Figure 7 Similarly, the meandering portion of the third electrode voltage line HL3 may be located between the meandering portion DL1-CP of the first data line DL1 and the meandering portion DL2-CP of the second data line DL2, which are adjacent to each other, and between the meandering portion of the fifth data line DL5 and the meandering portion of the sixth data line DL6, which are adjacent to each other (see Figure 7 ).

[0145] like Figure 7 As shown in FIG. 1 , the pitch between the data lines adjacent to each other in the first non-display area NDA1 (e.g., the first pitch d between the bent portions of the data lines) is smaller than the second pitch D between the data lines adjacent to each other in the display area DA. In this case, the display quality of some pixels located in the display area DA may be degraded due to the parasitic capacitance between the data lines adjacent to each other and arranged to have the first pitch d. However, in an embodiment, the occurrence of the parasitic capacitance may be reduced by the electrode voltage line HL of a constant voltage between the data lines adjacent to each other.

[0146] Reference Fig. 9A , the coupling between the meandering portion DL2-CP of the second data line DL2 and the meandering portion DL3-CP of the third data line DL3 can be reduced by the meandering portion HL2-CP of the second electrode voltage line HL2. Since the electrode voltage line has a constant voltage, the coupling between the data lines adjacent to each other can be more effectively reduced. Fig. 9A The relationship between the second and third data lines and the second electrode voltage line has been described, but the relationship also applies to the data lines adjacent to each other in the first non-display area NDA1 and the electrode voltage line disposed therebetween.

[0147] The effect of reducing coupling by the electrode voltage line is applicable to the adjacent scan lines in the first non-display area NDA1. Figure 7, a meandering portion of at least one of the electrode voltage lines HL1 to HL3 located in the first non-display area NDA1 may be located between meandering portions (bend portions) of the scan lines SL1 to SL4 adjacent to each other located in the first non-display area NDA1. Each of the electrode voltage lines HL1 to HL3 having a constant voltage may reduce coupling between the scan lines SL1 to SL4 adjacent to each other in the first non-display area NDA1.

[0148] The meandering portions of the scan lines SL1 to SL4 may be arranged between the data lines DL1 to DL6 adjacent to (neighboring) each other in the first non-display area NDA1.

[0149] For example, the meandering portion of the first scan line SL1 may be located between the meandering portion of the first data line DL1 and the meandering portion of the second data line DL2, and between the meandering portion of the fifth data line DL5 and the meandering portion of the sixth data line DL6 (see FIG. Figure 7 The meander portion SL2-CP of the second scan line SL2 may be located between the meander portion DL2-CP of the second data line DL2 and the meander portion DL3-CP of the third data line DL3 that are adjacent to each other (see Figure 7 and Figure 8 In addition, the meandering portion SL2-CP of the second scan line SL2 may be located between the meandering portion of the fourth data line DL4 and the meandering portion of the fifth data line DL5 adjacent to each other (see Figure 7 The meandering portion of the third scan line SL3 may be located between the meandering portion of the second data line DL2 and the meandering portion of the third data line DL3 that are adjacent to each other, and between the meandering portion of the fourth data line DL4 and the meandering portion of the fifth data line DL5 (see Figure 7 Similarly, the meandering portion of the fourth scan line SL4 may be located between the meandering portion of the first data line DL1 and the meandering portion of the second data line DL2, and between the meandering portion of the fifth data line DL5 and the meandering portion of the sixth data line DL6 (see Figure 7 ).

[0150] As described above, the meandering portions of each of the electrode voltage lines HL1 to HL3 and each of the scan lines SL1 to SL4 may be located between the data lines adjacent to each other in the first non-display area NDA1 and spaced apart from each other.

[0151] For example, the meandering portion SL2-CP of the second scan line SL2 may be located between the meandering portion DL2-CP of the second data line DL2 and the meandering portion DL3-CP of the third data line DL3 and spaced apart from the meandering portion HL2-CP1 of the second electrode voltage line HL2. Figure 8As shown in , the meandering portion SL2-CP of the second scan line SL2 may be spaced apart from the meandering portion DL2-CP of the second data line DL2 by a first distance d1, and the meandering portion HL2-CP1 of the second electrode voltage line HL2 may be spaced apart from the meandering portion SL2-CP of the second scan line SL2 by a second distance d2, and spaced apart from the meandering portion DL3-CP of the third data line DL3 by a third distance d3. Figure 8 The relationship between the second scan line SL2 and the second electrode voltage line HL2 has been described, but the relationship is also applicable to other lines.

[0152] exist Figure 7 On a plane of the invention, the data lines DL1 to DL6, the scan lines SL1 to SL4, and the electrode voltage lines HL1 to HL3 may be symmetrical with respect to a virtual line passing through the center of the opening area OA.

[0153] Since the data lines DL1 to DL6 and the scan lines SL1 to SL4 crossing each other on the plane overlap each other in some parts but are arranged in different layers, no electrical short circuit occurs. Similarly, since the data lines DL1 to DL6 and the electrode voltage lines HL1 to HL3 crossing each other on the plane overlap each other in some parts but are arranged in different insulating layers, no electrical short circuit occurs.

[0154] like Fig. 9A As shown in , the first insulating layer IL1 and the second insulating layer IL2 are arranged on the substrate 100, and the scan line (for example, the meandering portion SL2-CP of the second scan line SL2) can be arranged on the first insulating layer IL1 and the second insulating layer IL2. The second scan line SL2 may be covered by the third insulating layer IL3, and the electrode voltage line (for example, the meandering portion HL2-CP of the second electrode voltage line HL2) may be arranged on the third insulating layer IL3. The second electrode voltage line HL2 may be covered by the fourth insulating layer IL4, and the data line (for example, the meandering portion DL2-CP of the second data line DL2 and the meandering portion DL3-CP of the third data line DL3) may be arranged on the fourth insulating layer IL4. The data line may be covered by the fifth insulating layer IL5. The first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4 and the fifth insulating layer IL5 may include an inorganic insulating material such as silicon oxynitride or silicon nitride. In another embodiment, as Fig. 9B As shown in , the data line may be covered by an organic insulating layer OL including an organic insulating material. The organic insulating layer OL may be a reference Figure 6B In another embodiment, although not shown, the data line may be formed by a fifth insulating layer IL5 (see Fig. 9A ) and the organic insulating layer OL on the fifth insulating layer IL5 (see Fig. 9B )cover.

[0155] Fig. 10A and Fig. 10B is along Figure 7 A cross-sectional view of a display panel according to an embodiment taken along line XX'.

[0156] Reference Fig. 10A , a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, and a fifth insulating layer IL5 stacked in sequence may be arranged on the substrate 100. Side surfaces of the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 may form side surfaces of a through hole 10H provided in the display panel 10. As a comparative example, in the case where an organic insulating material is exposed through the through hole 10H, impurities (e.g., moisture) may penetrate into the organic insulating material. Therefore, the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 include an inorganic insulating layer having low moisture permeability.

[0157] The scan lines, electrode voltage lines and data lines are arranged in different layers in the first non-display area NDA1. In this regard, the first scan line SL1 and the second scan line SL2 are arranged above the second insulating layer IL2, the first electrode voltage line HL1 and the second electrode voltage line HL2 are arranged above the third insulating layer IL3, and the fourth data line DL4, the fifth data line DL5 and the sixth data line DL6 are arranged above the fourth insulating layer IL4.

[0158] The sealing material 350 is disposed above the above wirings (eg, scan lines, electrode voltage lines, and data lines) in the first non-display area NDA1. The sealing material 350 may overlap some of the above wirings, thus reducing the area of ​​the first non-display area NDA1.

[0159] although Fig. 10A It is illustrated that the wiring is covered by the fifth insulating layer IL5 which is an inorganic insulating layer, but the embodiment is not limited thereto.

[0160] Reference Fig. 10B , the wiring may be covered by the organic insulating layer OL. Fig. 10B The organic insulating layer OL may be as shown above. Figure 6B The planarization insulating layer PIL and / or the pixel definition layer PDL described above. In order to prevent moisture penetration in the lateral direction, the end OLE of the organic insulating layer OL can be positioned more inward than the ends of the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. For example, the end OLE of the organic insulating layer OL can be positioned more inward (toward the display area DA) than the inner sidewall 350IS of the sealing material 350.

[0161] Fig.11 is a plan view of a display panel according to another embodiment.

[0162] Although reference has been described Figure 7 and Figure 8 The embodiment described above, in which the electrode voltage lines HL1, HL2 and HL3 reduce the coupling between the data lines DL1, DL2, DL3, DL4, DL5 and DL6 adjacent to each other in the first non-display area NDA1 and the coupling between the scan lines SL1, SL2, SL3 and SL4 adjacent to each other in the first non-display area NDA1, but as another embodiment, Fig.11 It is described that the initialization voltage lines VL1, VL2 and VL3 can reduce the coupling between the data lines DL1, DL2, DL3, DL4, DL5 and DL6 adjacent to each other in the first non-display area NDA1 and the coupling between the scan lines SL1, SL2, SL3 and SL4 adjacent to each other in the first non-display area NDA1.

[0163] The meandering portions (or curved portions) of the initialization voltage lines VL1, VL2, and VL3 may be located between the adjacent data lines DL1, DL2, DL3, DL4, DL5, and DL6 in the first non-display area NDA1, for example, between the meandering portions of the adjacent data lines DL1, DL2, DL3, DL4, DL5, and DL6. Similarly, the meandering portions (or curved portions) of the initialization voltage lines VL1, VL2, and VL3 may be located between the adjacent scan lines SL1, SL2, SL3, and SL4 in the first non-display area NDA1, for example, between the meandering portions of the scan lines SL1, SL2, SL3, and SL4.

[0164] Since the initialization voltage lines VL1, VL2, and VL3 have a constant voltage (eg, -2V), coupling between data lines adjacent to each other and scan lines adjacent to each other in the first non-display area NDA1 can be effectively reduced.

[0165] Fig.12 is a plan view of a display panel according to another embodiment, Fig.13 yes Fig.12 An enlarged plan view of portion XIII.

[0166] Fig.12 The display panel shown in FIG. 1 includes a Figure 7 The structure of the display panel described is the same as that of the display panel described above. For ease of description, Fig.12 The scanning lines, electrode voltage lines and data lines around the opening area OA are shown. Fig.12The display panel shown in the reference Figure 7 The display panel described is different in that the electrode voltage lines also include auxiliary lines, so for ease of description, the difference is mainly described below.

[0167] Reference Fig.12 , each electrode voltage line bypassing the edge of the opening area OA may also include an auxiliary line. In this regard, Fig.12 It is shown that the first electrode voltage line HL1 , the second electrode voltage line HL2 , and the third electrode voltage line HL3 include auxiliary lines HL1 -A, ( HL2 -A1 , HL2 -A2 ), and HL3 -A, respectively.

[0168] like Fig.12 and Fig.13 As shown in the figure, in the case where the meandering portion HL1-CP of the first electrode voltage line HL1 extends to the upper side of the opening area OA, there is a region between the meandering portion DL1-CP of the first data line DL1 and the meandering portion DL2-CP of the second data line DL2 where the meandering portion HL1-CP is not arranged. The auxiliary line HL1-A of the first electrode voltage line HL1 may be located in the region where the meandering portion HL1-CP is not arranged to reduce or suppress the occurrence of parasitic capacitance in the relevant region. The auxiliary line HL1-A of the first electrode voltage line HL1 may be located between the first data line DL1 and the second data line DL2 and between the fifth data line DL5 and the sixth data line DL6.

[0169] The auxiliary line HL1-A of the first electrode voltage line HL1 may extend between the first electrode voltage line HL1 and the second electrode voltage line HL2 adjacent thereto toward a downward direction opposite to the meandering portion HL1-CP, and may be bent and aligned with the extending portion HL1-SP (see Fig.13 ) are connected to form a closed curve. In the case where the auxiliary line HL1-A does not form a closed loop with another part, the auxiliary line HL1-A itself will serve as a lightning rod and become a forward path of static electricity (ESD) around the opening area OA. However, in this embodiment, since the auxiliary line HL1-A forms a closed curve with the extension part HL1-SP, the penetration of static electricity can be prevented.

[0170] Similarly, the second electrode voltage line HL2 may include an auxiliary line HL2-A1 extending in a direction opposite to the meandering portion HL2-CP1 and an auxiliary line HL2-A2 extending in a direction opposite to the meandering portion HL2-CP2. The auxiliary lines HL2-A1 and HL2-A2 of the second electrode voltage line HL2 may be spaced apart from the meandering portions HL2-CP1 and HL2-CP2 by a predetermined interval, and the occurrence of parasitic capacitance between the first data line DL1 and the second data line DL2 may be reduced. In addition, the auxiliary lines HL2-A1 and HL2-A2 of the second electrode voltage line HL2 may be in an area between the second electrode voltage line HL2 and an electrode voltage line adjacent thereto (see Fig.13 ) is located between the fifth data line DL5 and the sixth data line DL6.

[0171] Similarly, the auxiliary line HL3 -A of the third electrode voltage line HL3 may be located between the first data line DL1 and the second data line DL2 , and between the fifth data line DL5 and the sixth data line DL6 .

[0172] although Fig.12 and Fig.13 It has been described that each of the electrode voltage lines HL1, HL2, and HL3 includes the auxiliary line, but the above reference Fig.11 The initialization voltage lines VL1, VL2 and VL3 described above may also include Fig.12 and Fig.13 Auxiliary lines in .

[0173] Fig.14 is a plan view of a display panel according to another embodiment, Fig.15A and Fig. 15B is along Fig.14 2 is a cross-sectional view of a display panel according to an embodiment taken along line XV-XV′.

[0174] Reference Fig.14 , a ring-shaped electrode layer VL-R in which an area corresponding to the opening area OA is opened may be arranged in the first non-display area NDA1. The electrode layer VL-R may be connected to the initialization voltage lines VL1, VL2, and VL3 as a whole, and may have the same voltage level (e.g., a constant voltage) as that of the initialization voltage lines VL1, VL2, and VL3. The electrode layer VL-R may cover all wirings in the first non-display area NDA1.

[0175] The electrode layer VL-R may cover the meandering portion of the scan line, the meandering portion of the electrode voltage line, and the meandering portion of the data line arranged below the electrode layer VL-R. Fig.15AIt is shown that the meander portion SL2-CP of the second scan line SL2, the meander portion HL2-CP of the second electrode voltage line HL2, the meander portion DL2-CP of the second data line DL2, and the meander portion DL3-CP of the third data line DL3 are covered by the electrode layer VL-R.

[0176] The coupling between the data lines adjacent to each other in the first non-display area NDA1 can be offset by the electrode layer VL-R and the wiring thereunder (eg, the meandering portion HL2-CP of the second electrode voltage line HL2). Fig.15A As shown in FIG. 1 , the coupling between the meandering portion DL2-CP of the second data line DL2 and the meandering portion DL3-CP of the third data line DL3 can be offset by the electrode layer VL-R and the meandering portion HL2-CP of the second electrode voltage line HL2 thereunder.

[0177] although Fig.15A The fifth insulating layer IL5 as an inorganic insulating layer is shown to be arranged between the electrode layer VL-R and the data line, but according to another embodiment (such as Fig. 15B As shown in FIG. 1 , the organic insulating layer OL may be disposed between the electrode layer VL-R and the data line. Alternatively, both the inorganic insulating layer and the organic insulating layer may be disposed between the electrode layer VL-R and the data line.

[0178] Fig.16 is a plan view of a display panel according to another embodiment.

[0179] Although in reference Fig.14 The electrode layers VL-R and the initialization voltage lines VL1, VL2 and VL3 in the display panel described are arranged on the same insulating layer and include the same material, but as another embodiment, Fig.16 It is shown that the electrode layers VL-R and the initialization voltage lines VL1, VL2 and VL3 are arranged on different layers. The differences are mainly described below.

[0180] In an embodiment, the electrode layer VL-R may be connected to the pixel electrode 210 (see Fig. 6A ) are arranged on the same layer, and the initialization voltage lines VL1, VL2 and VL3 may be arranged between the substrate and the pixel electrode 210, for example, with the electrode voltage line HL (see Fig. 6A ) are arranged above the same layer. In this case, the initialization voltage lines VL1, VL2, and VL3 and the electrode layers VL-R may be electrically connected to each other through contact holes CNT passing through the insulating layer arranged therebetween.

[0181] By way of summary and review, one or more embodiments include a display panel and a device including the display panel as a method of adding functions that can be combined or cooperated with a display device, wherein the display panel includes an opening area for electronic components (e.g., a camera, a sensor, etc.) located inside a display area. In addition, according to an embodiment of the present disclosure, the display quality can be improved by reducing or offsetting parasitic capacitance generated in wiring around an opening area corresponding to an electronic component such as a sensor or a camera.

[0182] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be construed only in a general and descriptive sense, and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art as of the time of filing this application that, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display panel, comprising: a substrate including a non-display area surrounding the opening area and a display area outside the non-display area; a plurality of display elements arranged in the display area; A plurality of first lines extending in a first direction and bypassing the opening area along an edge of the opening area; a plurality of second lines extending in a second direction intersecting the first direction, and the plurality of second lines bypassing the opening area along the edge of the opening area; a plurality of third lines extending in the second direction and bypassing the opening area along the edge of the opening area, wherein one of the plurality of third lines includes a meandering portion located between adjacent first lines of the plurality of first lines in the non-display area; as well as a plurality of pixel circuits in the display area and electrically connected to the plurality of display elements, the plurality of pixel circuits including a first pixel circuit including a plurality of transistors and a storage capacitor, One of the plurality of second lines is electrically connected to one of the plurality of transistors, and one of the plurality of third lines is electrically connected to another of the plurality of transistors.

2. The display panel according to claim 1, wherein: The meandering portion of the one of the plurality of third lines is arranged between the meandering portions of the adjacent first lines.

3. The display panel according to claim 2, wherein: The one of the plurality of second lines includes a meandering portion between the adjacent first lines in the non-display area.

4. The display panel according to claim 3, wherein: The meandering portion of the one of the plurality of third lines is spaced apart from the meandering portion of the one of the plurality of second lines.

5. The display panel according to claim 1, wherein: The plurality of third lines have a constant voltage.

6. The display panel according to claim 1, wherein: The one of the plurality of third lines further includes an auxiliary line extending opposite to the meandering portion.

7. The display panel according to claim 6, wherein: The auxiliary line is connected to the one third line among the plurality of third lines.

8. The display panel according to claim 1, wherein: A pitch between the adjacent first lines in the non-display area is smaller than a pitch between the adjacent first lines in the display area.

9. The display panel according to claim 1, further comprising: A packaging substrate, covering the display element and facing the substrate; as well as A sealing material is provided between the substrate and the packaging substrate and surrounds the opening area. 10 . The display panel according to claim 1 , further comprising an electrode layer located in the non-display area, the electrode layer comprising a hole corresponding to the opening area.

11. The display panel according to claim 10, wherein: The electrode layer has a constant voltage.

12. The display panel according to claim 10, wherein: The electrode layer covers at least a portion of the plurality of first lines, the plurality of second lines, and the plurality of third lines.

13. A display panel, comprising: A substrate, comprising a non-display area surrounding the opening area and a display area surrounding the non-display area; a plurality of display elements arranged in the display area; a plurality of voltage lines arranged above the substrate, extending in a first direction, bypassing the opening area along an edge of the opening area in the non-display area, and having a constant voltage level; A plurality of signal lines are arranged above the substrate and bypass the opening area along the edge of the opening area in the non-display area; as well as a packaging member covering the display element, wherein the plurality of signal lines include a plurality of data lines extending in a second direction intersecting the first direction, and Wherein, at least one voltage line among the plurality of voltage lines comprises a meandering portion located between adjacent data lines among the plurality of data lines in the non-display area.

14. The display panel according to claim 13, wherein: The at least one voltage line among the plurality of voltage lines further includes an auxiliary line extending opposite to the meandering portion.

15. The display panel according to claim 13, wherein: The plurality of signal lines include a scan line extending in the same direction as a direction in which the plurality of voltage lines extend.

16. The display panel according to claim 13, wherein: The meandering portion of the at least one voltage line among the plurality of voltage lines does not overlap with the meandering portion of the adjacent signal line. 17 . The display panel according to claim 13 , further comprising an insulating layer between the plurality of signal lines and the plurality of voltage lines. 18 . The display panel according to claim 13 , further comprising an electrode layer having a ring shape in the non-display area, the electrode layer including a hole corresponding to the opening area.

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