Modify the processor frequency based on the interrupt rate

Abstract

A processor includes a processing engine, at least one performance counter, and a power control circuit. The at least one performance counter is configured to determine at least one interrupt rate metric of the first processing engine. The power control circuit is configured to: use the at least one performance counter to determine whether the at least one interrupt rate metric has reached a first threshold when the first processing engine is operating at a first frequency level; and in response to a determination that the at least one interrupt rate metric has reached the first threshold when the first processing engine is operating at the first frequency level, increase the operating frequency of the first processing engine from the first frequency level to a second frequency level.

Description

Technical Field

[0001] The embodiments relate to computer processors, and more particularly, to modifying the operating frequency in a computer processor. Background Art

[0002] Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic that can be present on an integrated circuit device. As a result, computer system configurations have evolved from single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and / or complete systems on individual integrated circuits. Further, as the density of integrated circuits has increased, the power requirements for computing systems have also increased. As a result, there is an urgent need for energy efficiency and energy conservation associated with integrated circuits. Brief Description of the Drawings

[0003] Figure 1 is a block diagram of a portion of a system in accordance with an embodiment of the present invention.

[0004] Figure 2 is a block diagram of a processor in accordance with an embodiment of the present invention.

[0005] Figure 3 is a block diagram of a multi-domain processor in accordance with another embodiment of the present invention.

[0006] Figure 4 is an embodiment of a processor that includes multiple cores.

[0007] Figure 5 is a block diagram of the microarchitecture of a processor core in accordance with one embodiment of the present invention.

[0008] Figure 6 is a block diagram of the microarchitecture of a processor core in accordance with another embodiment.

[0009] Figure 7 is a block diagram of the microarchitecture of a processor core in accordance with yet another embodiment.

[0010] Figure 8 is a block diagram of the microarchitecture of a processor core in accordance with a further embodiment.

[0011] Figure 9 is a block diagram of a processor in accordance with another embodiment of the present invention.

[0012] Figure 10 is a block diagram of a representative SoC in accordance with an embodiment of the present invention.

[0013] Figure 11 is a block diagram of another example SoC in accordance with an embodiment of the present invention.

[0014] Figure 12 is a block diagram of an example system that can be used with the embodiments.

[0015] Figure 13 is a block diagram of another example system that can be used with the embodiments.

[0016] Figure 14 is a block diagram of a representative computer system.

[0017] Figure 15 is a block diagram of a system according to an embodiment of the present invention.

[0018] Figure 16 is a block diagram illustrating an IP core development system for manufacturing an integrated circuit to perform operations according to an embodiment.

[0019] Figure 17 is a diagram of an example system according to one or more embodiments.

[0020] Figure 18 is a diagram of an example control logic according to one or more embodiments.

[0021] Figure 19 is a flowchart of an example method according to one or more embodiments.

[0022] Figure 20 is a flowchart of an example method according to one or more embodiments.

[0023] Figures 21A - 21B is a block diagram illustrating a general vector-friendly instruction format and its instruction templates according to an embodiment of the present invention;

[0024] Figures 22A - 22D is a block diagram illustrating an exemplary special vector-friendly instruction format according to an embodiment of the present invention;

[0025] Figure 23 is a block diagram of a register architecture according to an embodiment of the present invention;

[0026] Figure 24A is a block diagram showing an exemplary in-order pipeline and an exemplary out-of-order issue / execution pipeline with register renaming illustrating an embodiment of the present invention.

[0027] Figure 24B is a block diagram illustrating an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary out-of-order issue / execution architecture core with register renaming according to an embodiment of the present invention;

[0028] Figures 25A - 25B A block diagram illustrating a more specific exemplary in-order core architecture, which will be one of several logic blocks (including other cores of the same type and / or different types) in a chip;

[0029] Figure 26is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have an integrated graphics device according to an embodiment of the present invention;

[0030] Figures 27 - 28 is a block diagram of an exemplary computer architecture; and

[0031] Figure 29 is a block diagram of converting binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention by using a software instruction converter. Detailed Description

[0032] In computer technology, an interrupt is a signal sent to a processor (e.g., a central processing unit) indicating an event that requires the processor's attention. For example, an input device (e.g., a keyboard) may send an interrupt to indicate that the processor should read the key pressed by the user. In another example, a device driver may send an interrupt to indicate that the processor should read data stored in a buffer. In yet another example, a software thread may use an inter-processor interrupt (IPI) to synchronize with another software thread. Interrupts may be referred to herein as masked or unmasked. As used herein, "unmasked" means an interrupt that can be temporarily ignored by the processor, while "masked" means an interrupt that cannot be ignored by the processor.

[0033] In some processors, the operating parameters of the processor may be dynamically adjusted to reduce power consumption. For example, the operating frequency may be reduced when the processor utilization of program instructions is relatively low, thereby improving power efficiency. However, when handling an interrupt, the processor may appear to have relatively low utilization and may thus cause a reduction in the processor frequency. As a result, the performance of handling interrupts may be reduced.

[0034] According to one or more embodiments, performance counters may be adjusted to determine an interrupt rate metric of a processing engine (e.g., the number or proportion of cycles used by the processing engine to handle masked interrupts, the number or proportion of cycles used by the processing engine to handle masked and unmasked interrupts, etc.). The power control circuit of the processor may use the performance counters to determine whether the interrupt rate metric has reached a corresponding threshold. If so, the power control circuit may increase the operating frequency of the processing engine. Further, if the processing engine is already at the maximum frequency, the power control circuit may maintain that maximum frequency and may prevent a reduction to a lower frequency associated with other parameters (e.g., frequency reduction due to low processor utilization). Accordingly, one or more embodiments may improve the interrupt performance of the processing engine. Details of various embodiments are further described below with reference to Figures 17 - 20 Various details of some embodiments are further described.

[0035] Now refer toFigure 1 , which is a block diagram of a portion of a system according to an embodiment of the present invention. Figure 1 As shown in , system 100 may include various components including processor 110, which is shown as a multi-core processor. Processor 110 may be coupled to power supply 150 via external voltage regulator 160, which may perform a first voltage conversion to provide a regulated main voltage Vreg to processor 110.

[0036] As can be seen, the processor 110 can be a single-die processor including multiple cores 120a-120n. In addition, each core can be associated with an integrated voltage regulator (IVR) 125a-125n, which receives a regulated main voltage and generates an operating voltage that is provided to one or more agents of the processor associated with the IVR. Accordingly, an IVR implementation can be provided to allow fine-grained control of the voltage of each individual core and thus power and performance. Thus, each core can operate at an independent voltage and frequency, thereby allowing great flexibility and providing a wide range of opportunities to balance power consumption and performance. In some embodiments, the use of multiple IVRs allows components to be grouped into different power layers, so that power is regulated by the IVR and is provided only to those components in the group. During power management, when the processor is placed in a low-power state, a given power layer of an IVR can be powered down or powered off, while another power layer of another IVR remains active or fully powered. Similarly, cores 120 may include or be associated with independent clock generation circuitry, such as one or more phase-locked loops (PLLs), to independently control the operating frequency of each core 120 .

[0037] Still refer to Figure 1 , additional components may be present within the processor, including an input / output interface (IF) 132, another interface 134, and an integrated memory controller (IMC) 136. It can be seen that each of these components can be provided by another integrated voltage regulator 125 X In one embodiment, the interface 132 can be The interface 134 may be implemented via a Peripheral Component Interconnect Express (PCIe) interconnect that provides a point-to-point (PtP) link in a cache coherence protocol that includes multiple layers, including a physical layer, a link layer, and a protocol layer. TM ) protocol to communicate.

[0038] Also shown is a Power Control Unit (PCU) 138, which may include circuitry comprising hardware, software, and / or firmware for performing power management operations for processor 110. It can be seen that PCU 138 provides control information to an external voltage regulator 160 via a digital interface 162 to cause the voltage regulator to generate a suitable regulated voltage. PCU 138 also provides control information to a plurality of IVRs 125 via another digital interface 163 to control the generated operating voltage (or to disable the corresponding IVR in a low power mode). In various embodiments, PCU 138 may include various power management logic units for performing hardware-based power management. Such power management may be fully controlled by the processor (e.g., via various processor hardware and may be triggered by workload and / or power, thermal, or other processor constraints), and / or power management may be performed in response to an external source such as a platform or a managed power source or system software.

[0039] In Figure 1 PCU 138 is illustrated as presenting as separate logic from the processor. In other cases, PCU 138 may execute on one or more of the given cores in core 120. In some cases, PCU 138 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other embodiments, the power management operations to be performed by PCU 138 may be implemented externally to the processor, such as by a separate Power Management Integrated Circuit (PMIC) or another component external to the processor. In still other embodiments, the power management operations to be performed by PCU 138 may be implemented within the BIOS or other system software.

[0040] Although not shown in Figure 1 in some embodiments, processor 110 and / or core 120 may include all or part of the components and / or processes described below with reference to Figures 17 - 20

[0041] ​Embodiments may be particularly suitable for multi-core processors, where each of the multiple cores may operate at independent voltage and frequency points. As used herein, the term "domain" is used to mean a collection of hardware and / or logic that operates at the same voltage and frequency point. Additionally, a multi-core processor may further include other non-core processing engines, such as fixed function units, graphics engines, and the like. Such processors may include independent domains other than the cores, such as one or more domains associated with the graphics engine (referred to herein as the graphics domain) and one or more domains associated with the non-core circuitry (referred to herein as the system agent). While many implementations of multi-domain processors may be formed on a single semiconductor die, other implementations may be realized by a multi-chip package, where different domains may be present on different semiconductor dies of a single package.

[0042] Although not shown for ease of illustration, it should be understood that additional components, such as non-core logic and other components (such as internal memory (e.g., one or more levels of cache memory hierarchies, etc.)), may be present within the processor 110. Additionally, although shown as having an integrated voltage regulator in Figure 1 the implementation of, however, multiple embodiments are not limited thereto. For example, other regulated voltages may be provided to on-chip resources from an external voltage regulator 160 or one or more additional external sources of regulated voltage.

[0043] Note that the power management techniques described herein can be independent of and complementary to an operating system (OS)-based power management (OSPM) mechanism. According to one example OSPM technique, a processor can operate at various performance states or levels (so-called P-states, from P0 to PN). Generally, the P1 performance state can correspond to the highest guaranteed performance state that can be requested by the OS. In addition to this P1 state, the OS can further request a higher performance state, i.e., the P0 state. This P0 state can thus be an opportunistic state, an overclocking or turbo mode state, in which when power and / or thermal budget is available, the processor hardware can configure the processor or at least some of its parts to operate at a frequency higher than the guaranteed frequency. In many implementations, the processor can include a plurality of so-called bin frequencies that are fused or otherwise written into the processor during manufacturing, which are higher than the maximum frequency guaranteed by P1 and exceed the maximum peak frequency of a particular processor. Additionally, according to one OSPM mechanism, the processor can operate at various power states or levels. For power states, the OSPM mechanism can specify different power consumption states, generally referred to as C-states (C0, C1 to Cn states). When a core is active, it runs in the C0 state, and when the core is idle, it can be placed in a core low power state, also referred to as a non-zero C-state for the core (e.g., C1 - C6 states), with each C-state being at a lower power consumption level (such that C6 is a deeper low power state than C1, etc.).

[0044] It should be understood that many different types of power management techniques can be used alone or in combination in different embodiments. As a representative example, a power controller can control the processor to manage power by some form of dynamic voltage and frequency scaling (DVFS), in which the operating voltage and / or operating frequency of one or more cores or other processor logic can be dynamically controlled to reduce power consumption in certain situations. In an example, the Enhanced Intel SpeedStep TM technology provided by Intel Corporation of Santa Clara, California can be used to perform DVFS to provide optimal performance at the lowest power consumption level. In another example, Intel TurboBoost TM technology can be used to perform DVFS so that one or more cores or other computing engines can operate at a frequency higher than the guaranteed operating frequency based on conditions (e.g., workload and availability).

[0045] Another power management technique that can be used in some examples is to dynamically exchange workloads between different computing engines. For example, a processor may include asymmetric cores or other processing engines that operate at different power consumption levels, such that in a power-constrained situation, one or more workloads can be dynamically switched to execute on a lower-power core or other computing engine. Another exemplary power management technique is Hardware Duty Cycling (HDC), which can cause a core and / or other computing engine to be periodically enabled and disabled according to a duty cycle, such that one or more cores become inactive during the inactive period of the duty cycle and active during the active period of the duty cycle.

[0046] Power management techniques can also be used when there are constraints in the operating environment. For example, when power and / or thermal constraints are encountered, power can be reduced by lowering the operating frequency and / or voltage. Other power management techniques include throttling the instruction execution rate or limiting the scheduling of instructions. Additionally, instructions of a given instruction set architecture can include explicit or implicit directions regarding power management operations. Although described in these specific examples, it should be understood that many other power management techniques can be used in a particular embodiment.

[0047] Multiple embodiments can be implemented in processors for various markets, including server processors, desktop processors, mobile processors, etc. Now refer to Figure 2 , which shows a block diagram of a processor according to an embodiment of the present invention. As shown in Figure 2 , the processor 200 can be a multi-core processor including multiple cores 210a–210n. In one embodiment, each such core can be an independent power domain and can be configured to enter and exit an active state and / or a maximum performance state based on the workload. One or more of the cores 210 can be heterogeneous relative to the other cores, e.g., having different microarchitectures, instruction set architectures, pipeline depths, power, and performance capabilities. The various cores can be coupled via an interconnect 215 to a system agent 220 that includes various components. It can be seen that the system agent 220 can include a shared cache 230, which can be a last-level cache. Additionally, the system agent can include an integrated memory controller 240 for communicating with system memory ( Figure 2 , not shown in the figure) via a memory bus, for example. The system agent 220 also includes various interfaces 250 and a power control unit 255, and the power control unit 255 can include logic for performing the power management techniques described herein.

[0048] Furthermore, connections to various off-chip components such as peripheral devices, mass storage devices, etc. can be made through the interfaces 250a-250n. Although shown in Figure 2is shown in this particular implementation in the embodiments, but the scope of the present invention is not limited to this aspect.

[0049] Although not shown in Figure 2 In some embodiments, the processor 200 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 as described.

[0050] Now referring to Figure 3 , shown is a block diagram of a multi-domain processor according to another embodiment of the present invention. As Figure 3 shown in the embodiments of

[0051] the processor 300 includes multiple domains. Specifically, the core domain 310 may include multiple cores 310a–310n, the graphics domain 320 may include one or more graphics engines, and there may also be a system agent domain 350. In some embodiments, the system agent domain 350 can execute at an independent frequency independent of the core domain and can be powered at all times to handle power control events and power management, such that the domains 310 and 320 can be controlled to dynamically enter and exit high-power states and low-power states. Each of the domains 310 and 320 can operate at different voltages and / or powers. Note that although only three domains are shown, it should be understood that the scope of the present invention is not limited to this aspect and additional domains may exist in other embodiments. For example, there may be multiple core domains, each core domain including at least one core.

[0052] Generally, in addition to various execution units and additional processing elements, each of the cores 310a-310n may further include multiple low-level caches. Further, the various cores may be coupled to each other and to a shared cache memory, which is formed by multiple units of last-level caches (LLCs) 340a–340n. In embodiments, the LLC 340 may be shared among multiple cores, the graphics engine, and various media processing circuits. As shown, the ring interconnect 330 thus couples the multiple cores together and provides an interconnect among the multiple cores, the graphics domain 320, and the system agent domain 350. In one embodiment, the interconnect 330 may be part of the core domain. However, in other embodiments, the ring interconnect may be in its own domain.

[0052] As further shown, the system agent domain 350 may include a display controller 352, which may provide control of and an interface to an associated display. As further shown, the system agent domain 350 may include a power control unit 355, which may include logic for performing the power management techniques described herein.

[0053] As Figure 3As further shown, the processor 300 may also include an integrated memory controller (IMC) 370, which may provide an interface to system memory such as dynamic random access memory (DRAM). There may be multiple interfaces 380a–380n to enable interconnection between the processor and other circuits. For example, in one embodiment, at least one direct media interface (DMI) interface and one or more PCIe TM interfaces may be provided. Additionally, one or more QPI interfaces may be provided to enable communication between other agents such as additional processors or other circuits. Although shown at this high level in the Figure 3 embodiment, it will be understood that the scope of the present invention is not limited to this aspect.

[0054] Although not shown in the Figure 3 figure, in some embodiments, the processor 300 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0055] Referring to Figure 4 , an embodiment of a processor including multiple cores is illustrated. The processor 400 includes any processor or processor device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system-on-a-chip (SoC), or other device for executing code. In one embodiment, the processor 400 includes at least two cores - cores 401 and 402, which may include asymmetric or symmetric cores (the illustrated embodiment). However, the processor 400 may include any number of processing elements, which may be symmetric or asymmetric.

[0056] In one embodiment, a processing element refers to the hardware or logic for supporting software threads. Examples of hardware processing elements include: thread units, thread slots, threads, process units, contexts, context units, logical processors, hardware threads, cores, and / or any other element capable of holding the state of the processor, such as an execution state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware capable of being independently associated with code such as software threads, operating systems, applications, or other code. A physical processor generally refers to an integrated circuit that potentially includes any number of other processing elements such as cores or hardware threads.

[0057] A core generally refers to the logic on an integrated circuit that can maintain an independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast, a hardware thread generally refers to any logic on an integrated circuit that can maintain an independent architectural state, where the independently maintained architectural states share access to execution resources. As can be seen, when some resources are shared while other resources are dedicated to the architectural state, the boundary between the terms hardware thread and core overlaps. However, cores and hardware threads are often treated by an operating system as a single logical processor, where the operating system can schedule operations on each logical processor separately.

[0058] As Figure 4 As illustrated, physical processor 400 includes two cores - core 401 and core 402. Here, cores 401 and 402 are considered symmetric cores, i.e., these cores have the same configuration, functional units, and / or logic. In another embodiment, core 401 includes an out-of-order processor core, while core 402 includes an in-order processor core. However, cores 401 and 402 can be individually selected from any type of core, such as a native core, a software-managed core, a core suitable for executing a native instruction set architecture (ISA), a core suitable for executing a translated ISA, a co-designed core, or other known cores. However, for further discussion, the multiple functional units illustrated in core 401 will be described in more detail below, since the multiple units in core 402 operate in a similar manner.

[0059] As depicted, core 401 includes two hardware threads, which may also be referred to as hardware thread slots. Thus, in one embodiment, a software entity such as an operating system potentially views processor 400 as four separate processors, i.e., four logical processors or processing elements capable of concurrently executing four software threads. As described above, the first thread is associated with architectural state register 401a, the second thread is associated with architectural state register 401b, the third thread may be associated with architectural state register 402a, and the fourth thread may be associated with architectural state register 402b. Here, each of the architectural state registers (401a, 401b, 402a, and 402b) may be referred to as a processing element, thread slot, or thread unit as described above. As illustrated, the architectural state of register 401a is replicated in architectural state register 401b, thus enabling storage of individual architectural states / contexts for the logical processors. In core 401, other smaller resources for architectural state registers 401a and 401b may also be replicated, such as the instruction pointer and the rename logic in allocator and renamer block 430. Some resources such as the reorder buffer in reorder / retirement unit 435, branch target buffer, and instruction translation lookaside buffer (BTB and I-TLB) 420, load / store buffers, and queues may be shared through partitioning. Other resources such as general-purpose internal registers, (multiple) page table base registers, lower-level data cache, and data TLB 450, multiple portions of (multiple) execution units 440, and reorder / retirement unit 435 may potentially be fully shared.

[0060] Processor 400 generally includes other resources that may be fully shared, shared through partitioning, or dedicated / specific to the processing elements. In Figure 4 FIG. 5, an embodiment of an illustrative logical unit / resource of a processor is illustrated. Note that the processor may include or omit any of these functional units and include any other known functional units, logic, or firmware not depicted. As illustrated, core 401 includes a simplified, representative out-of-order (OOO) processor core. However, in different embodiments, an in-order processor may be utilized.

[0061] The core 401 also includes a decoding module 425 coupled to the fetch unit for decoding the fetched elements. In one embodiment, the fetch logic includes respective sequence generators associated with the architectural state registers 401a, 401b. Generally, the core 401 is associated with a first ISA that defines / specifies the instructions executable on the processor 400. Machine code instructions that are part of the first ISA often include a portion of the instruction (referred to as the opcode) that references / specifies the instruction or operation to be performed. The decoding module 425 includes circuitry for operating to identify these instructions from the opcodes of these instructions and passing the decoded instructions in a pipeline for processing as defined by the first ISA. For example, in one embodiment, the decoding module 425 includes logic designed to or adapted to identify specific instructions such as transactional instructions. As a result of being identified by the decoding module 425, the architecture or core 401 takes specific, predefined actions to perform the tasks associated with the appropriate instructions. It is important to note that any of the tasks, blocks, operations, and methods described herein can be performed in response to single or multiple instructions; some of them can be new instructions or old instructions.

[0062] In one example, the allocator and renamer block 430 includes an allocator for reserving resources, such as a register file for storing instruction processing results. However, the architectural state registers 401a and 401b are potentially capable of out-of-order execution, where the allocator and renamer block 430 also reserves other resources (such as a reorder buffer for tracking instruction results). The renamer block 430 may also include a register renamer for renaming program / instruction reference registers to other registers internal to the processor 400. The reorder / retirement unit 435 includes components such as the reorder buffer, load buffer, and store buffer described above for supporting out-of-order execution of out-of-order executed instructions and later in-order retirement.

[0063] In one embodiment, the scheduler and (multiple) execution units 440 include a scheduler unit for scheduling instructions / operations on multiple execution units. For example, scheduling floating-point instructions on ports of execution units having available floating-point execution units. Also included is a register file associated with the execution units for storing information instruction processing results. Exemplary execution units include floating-point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

[0064] Lower-level data caches and data translation lookaside buffers (D-TLBs) 450 are coupled to the execution units 440. The data caches are used to store recently used / operated-upon elements (such as data operands), potentially maintaining these elements in a memory coherent state. The D-TLBs are used to store recent virtual / linear to physical address translations. As a specific example, the processor may include a page table structure for breaking physical memory into multiple virtual pages.

[0065] Here, cores 401 and 402 share access to a higher-level or further-away cache 410, which caches for recently fetched elements. Note that higher-level or further-away refers to an increasing cache level or further away from the execution units. In one embodiment, the higher-level cache 410 is a last-level data cache (the last-level cache in the memory hierarchy on processor 400), such as a second or third-level data cache. However, the higher-level cache 410 is not limited thereto, as it may be associated with or include an instruction cache. Alternatively, a trace cache (a type of instruction cache) may be coupled after the decode module 425 for storing recently decoded traces.

[0066] In the depicted configuration, processor 400 also includes a bus interface 405 and a power control unit 460 that can perform power management in accordance with embodiments of the present invention. In this case, the bus interface 405 is used to communicate with devices external to processor 400 (such as system memory and other components).

[0067] The memory controller 470 may interface with other devices such as one or more memories. In an example, the bus interface 405 includes a ring interconnect that interconnects with a memory controller for interfacing with memories and a graphics controller for interfacing with a graphics processor. In a SoC environment, even more devices such as network interfaces, coprocessors, memories, graphics processors, and any other known computer devices / interfaces may be integrated onto a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0068] Although not shown in Figure 4 In some embodiments, processor 400 may include all or part of the components and / or processes described below with reference to Figures 17 - 20

[0069] Now refer to Figure 5 , which shows a block diagram of the microarchitecture of a processor core according to an embodiment of the present invention. As Figure 5As shown, the processor core 500 can be an out-of-order processor of the multi-stage pipeline type. The core 500 can operate at various voltages based on the received operating voltage, which can be received from an integrated voltage regulator or an external voltage regulator.

[0070] As Figure 5 shown, the core 500 includes a front-end unit 510, which can be used to fetch the instructions to be executed and prepare these instructions for later use in the processor pipeline. For example, the front-end unit 510 can include a fetch unit 501, an instruction cache 503, and an instruction decoder 505. In some implementations, the front-end unit 510 can further include a trace cache, microcode storage, and micro-operation storage. The fetch unit 501 can fetch macro instructions (e.g., from memory or the instruction cache 503) and feed them to the instruction decoder 505 to decode them into primitives, i.e., micro-operations for execution by the processor.

[0071] The out-of-order (OOO) engine 515 is coupled between the front-end unit 510 and the execution unit 520, and the OOO engine 515 can be used to receive microinstructions and prepare them for execution. More specifically, the OOO engine 515 can include a plurality of buffers for reordering the microinstruction stream and allocating the multiple resources required for execution, and for providing renaming of the logical registers at the storage locations in the multiple register files (e.g., register file 530 and extended register file 535). The register file 530 can include separate register files for integer and floating-point operations. For configuration, control, and additional operations, there can also be a set of machine-specific registers (MSR) 538 and can be accessed by various logics within (and external to) the core 500.

[0072] There can be a variety of resources in the execution unit 520, including, for example, a variety of integer, floating-point, and single instruction multiple data (SIMD) logic units and other specialized hardware. For example, in addition to these execution units, such execution units can include one or more arithmetic logic units (ALU) 522 and one or more vector execution units 524.

[0073] The results from the execution unit can be provided to the retirement logic, i.e., the reorder buffer (ROB) 540. More specifically, the ROB 540 can include a variety of arrays and logics to receive information associated with the executed instructions. Then, this information is checked by the ROB 540 to determine whether the instruction can be retired effectively and whether the result data is committed to the architectural state of the processor, or whether one or more exceptions that prevent the normal retirement of the instruction occur. Of course, the ROB 540 can handle other operations associated with retirement.

[0074] As Figure 5As shown, the ROB 540 is coupled to the cache 550. In one embodiment, the cache 550 may be a lower-level cache (e.g., an L1 cache), although the scope of the present invention is not limited thereto. Moreover, the execution unit 520 may be directly coupled to the cache 550. From the cache 550, data communication with higher-level caches, system memory, and so on may occur. Although shown at this high level in the Figure 5 embodiment, it should be understood that the scope of the present invention is not limited in this regard. For example, although the Figure 5 implementation involves an out-of-order machine such as one having the x86 instruction set architecture (ISA), the scope of the present invention is not limited in this regard. That is, other embodiments may be implemented in: an in-order processor; a reduced instruction set computing (RISC) processor such as an ARM-based processor; or a processor having another type of ISA, where the other type of ISA may emulate the instructions and operations of different ISAs via an emulation engine and associated logic circuitry.

[0075] Although not shown in the Figure 5 , in some embodiments, the core 500 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0076] Now referring to Figure 6 , shown is a block diagram of the microarchitecture of a processor core according to another embodiment. In the Figure 6 embodiment, the core 600 may be a low-power core having a different microarchitecture, such as an Atom - TM (Atom TM ) processor designed to reduce power consumption and having a relatively limited pipeline depth. As shown, the core 600 includes an instruction cache 610 coupled to provide instructions to an instruction decoder 615. A branch predictor 605 may be coupled to the instruction cache 610. Note that the instruction cache 610 may be further coupled to another level of cache memory, such as an L2 cache (not shown in Figure 6 for ease of illustration). Further, the instruction decoder 615 provides the decoded instructions to an issue queue (IQ) 620 for storage and delivery to a given execution pipeline. A microcode ROM 618 is coupled to the instruction decoder 615.

[0077] The floating-point pipeline 630 includes a floating-point (FP) register file 632, which may include multiple architectural registers having a given bit width (such as 128, 256, or 512 bits). The pipeline 630 includes a floating-point scheduler 634 for scheduling instructions to be executed on one of the multiple execution units of the pipeline. In the illustrated embodiment, such execution units include an ALU 635, a shuffle unit 636, and a floating-point adder 638. Further, the results generated in these execution units can be fed back to the registers of the buffer and / or register file 632. Of course, it should be understood that although these several example execution units are shown, additional or different floating-point execution units may exist in another embodiment.

[0078] An integer pipeline 640 may also be provided. In the illustrated embodiment, the pipeline 640 includes an integer (INT) register file 642, which may include multiple architectural registers having a given bit width (such as 128 or 256 bits). The pipeline 640 includes an integer execution (IE) scheduler 644 for scheduling instructions to be executed on one of the multiple execution units of the pipeline. In the illustrated embodiment, such execution units include an ALU 645, a shifter unit 646, and a jump execution unit (JEU) 648. Further, the results generated in these execution units can be fed back to the registers of the buffer and / or register file 642. Of course, it should be understood that although these several example execution units are shown, additional or different integer execution units may exist in another embodiment.

[0079] A memory execution (ME) scheduler 650 may schedule memory operations to be executed in an address generation unit (AGU) 652, which is also coupled to a TLB 654. As shown, these structures may be coupled to a data cache 660, which may be an L0 and / or L1 data cache, which in turn is coupled to additional levels of the cache memory hierarchy, including an L2 cache memory.

[0080] To provide support for out-of-order execution, an allocator / renamer 670 may also be provided in addition to a reorder buffer 680, which is configured to reorder instructions that are executed out of order for orderly retirement. Although shown in Figure 6 this particular pipeline architecture in the illustration, it should be understood that many variations and alternatives are possible.

[0081] Although not shown in Figure 6 some embodiments, the core 600 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0082] Note that in a processor with an asymmetric core, such as according toFigure 5 and 6 The microarchitecture of 6 can dynamically exchange workloads between cores for power management reasons because these cores, although having different pipeline designs and depths, can have the same or related ISAs. Such dynamic core exchange can be performed in a manner transparent to user applications (and also possibly to the kernel).

[0083] Refer to Figure 7 , which shows a block diagram of the microarchitecture of a processor core according to another embodiment. As Figure 7 illustrated, core 700 can include a multi-stage in-order pipeline to execute at very low power levels. As one such example, core 700 can have a microarchitecture based on the ARM Cortex A53 design available from ARM Holdings plc, Sunnyvale, California. In an implementation, an 8-stage pipeline configured to execute 32-bit and 64-bit code can be provided. Core 700 includes a fetch unit 710 configured to fetch instructions and provide these instructions to a decode unit 715, which can decode instructions, such as macro instructions having a given ISA (such as the ARMv8 ISA). Additionally, a notice queue 730 can be coupled to the decode unit 715 to store the decoded instructions. The decoded instructions are provided to an issue logic 725, where the decoded instructions can be issued to a given one of a plurality of execution units.

[0084] Further refer to Figure 7 , the issue logic 725 can issue an instruction to one of a plurality of execution units. In the illustrated embodiment, these execution units include an integer unit 735, a multiplication unit 740, a floating-point / vector unit 750, a dual-issue unit 760, and a load / store unit 770. The results of these different execution units can be provided to a write-back (WB) unit 780. It should be understood that although a single write-back unit is shown for ease of illustration, in some implementations, separate multiple write-back units can be associated with each of the execution units. Additionally, it should be understood that although Figure 7 each of the units and logic shown in Figure 7 is represented at a high level, a particular implementation can include multiple or different structures. Processors designed using one or more cores having a pipeline such as that in Figure 7 can be implemented in many different end products, ranging from mobile devices to server systems. Figure 7 Figure 7

[0085] Although not shown in Figure 7 , in some embodiments, core 700 can include all or part of the components and / or processes described below with reference to Figures 17 - 20 Figures 17 - 20

[0086] Refer to Figure 8, shown is a block diagram of a microarchitecture of a processor core according to a further embodiment. As Figure 8 illustrated, the core 800 may include a multi-level out-of-order pipeline with multiple issue to execute at a very high performance level (which may occur at a power consumption level higher than Figure 7 that of the core 700). As one such example, the core 800 may have a microarchitecture designed according to ARM Cortex A57. In an implementation, a 15 (or greater) stage pipeline configured to execute 32-bit and 64-bit code may be provided. Additionally, the pipeline may provide 3-way (or greater) width and 3-way (or greater) issue operations. The core 800 includes a fetch unit 810 configured to fetch instructions and provide the instructions to a decoder / renamer / dispatcher unit 815 coupled to a cache 820. The unit 815 may decode the instructions, such as macro instructions having an ARMv8 instruction set architecture, rename register references within the instructions, and dispatch the instructions (eventually) to selected execution units. The decoded instructions may be stored in a queue 825. Note that although a single queue structure is shown in Figure 8 for ease of illustration, it should be understood that separate multiple queues may be provided for each of multiple different types of execution units.

[0087] In Figure 8 is also shown issue logic 830 to which the decoded instructions stored in the queue 825 may be issued to selected execution units. In a particular embodiment, the issue logic 830 may also be implemented with separate issue logic for each of multiple different types of execution units coupled to the issue logic 830.

[0088] The decoded instructions may be issued to a given one of the multiple execution units. In the illustrated embodiment, these execution units include one or more integer units 835, a multiplication unit 840, a floating point / vector unit 850, a branch unit 860, and a load / store unit 870. In an embodiment, the floating point / vector unit 850 may be configured to process 128 or 256-bit SIMD or vector data. Additionally, the floating point / vector unit 850 may perform IEEE-754 double precision floating point operations. The results of these different execution units may be provided to a write-back unit 880. Note that in some implementations, each execution unit may be associated with a separate write-back unit. Additionally, it should be understood that although Figure 8 each of the units and logic shown in is represented at a high level, a particular implementation may include multiple or different structures.

[0089] Although not shown in Figure 8 , in some embodiments, the core 800 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0090] Note that in a processor with asymmetric cores, such as the microarchitecture according to Figure 7 and 8 , due to power management reasons, the workloads can be dynamically swapped because these cores, although having different pipeline designs and depths, can have the same or related ISAs. Such dynamic core swapping can be performed in a manner that is transparent to the user application (and also potentially to the kernel).

[0091] Processors designed to use one or more cores with pipelines in any one or more of Figures 5 - 8 can be implemented in many different end products, ranging from mobile devices to server systems. Now referring to Figure 9 , shown is a block diagram of a processor according to another embodiment of the present invention. In the embodiment of Figure 9 , the processor 900 can be a SoC including multiple domains, and each of the domains can be controlled to operate at an independent operating voltage and operating frequency. As a specific illustrative example, the processor 900 can be a processor based on the architecture Core TM (Core), such as an i3, i5, i7, or another such processor available from Intel Corporation. However, other low-power processors, such as those based on ARM designs from Advanced Micro Devices, Inc. of Sunnyvale, California (AMD), from ARM Holdings plc or its licensees, or those based on MIPS designs from MIPS Technologies, Inc. of Sunnyvale, California or their licensees or adopters, can alternatively be present in other embodiments, such as the Apple A7 processor, the Qualcomm Snapdragon processor, or the Texas Instruments OMAP processor. Such a SoC can be used in low-power systems such as smart phones, tablet computers, phablet computers, ultrabooks TM computers, or other portable computing devices, which can include a heterogeneous system architecture with a processor design based on a heterogeneous system architecture.

[0092] In Figure 9In the high-level view shown, the processor 900 includes a plurality of core units 910a - 910n. Each core unit may include one or more processor cores, one or more cache memories, and other circuitry. Each core unit 910 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions such as NEON)) or other instruction sets or combinations thereof. Note that some of the core units may be heterogeneous resources (e.g., having different designs). Additionally, each such core may be coupled to a cache memory (not shown), which in an embodiment may be a shared level 2 (L2) cache memory. A non-volatile memory 930 may be used to store various programs and other data. For example, this storage device may be used to store at least portions of microcode, boot information such as BIOS, other system software, etc.

[0093] Each core unit 910 may also include an interface such as a bus interface unit for enabling interconnection to additional circuitry of the processor. In an embodiment, each core unit 910 is coupled to a coherence fabric, which may act as a primary cache coherence on-die interconnect that is further coupled to a memory controller 935. The memory controller 935 in turn controls communication with a memory such as DRAM (not shown in Figure 9 for ease of illustration).

[0094] In addition to these core units, additional processing engines are present within the processor, including at least one graphics unit 920, which may include one or more graphics processing units (GPUs) for performing graphics processing and possibly general-purpose operations (so-called GPGPU operations) on the graphics processor. Additionally, there may be at least one image signal processor 925. The signal processor 925 may be configured to process incoming image data received from one or more capture devices, whether internal or external to the SoC.

[0095] There may also be other accelerators. In the Figure 9 illustration, a video decoder 950 may perform decoding operations, including encoding and decoding of video information, e.g., providing hardware acceleration support for high-definition video content. A display controller 955 may further be provided to accelerate display operations, including providing support for internal and external displays of the system. Additionally, there may be a security processor 945 for performing security operations such as secure boot operations, various encryption operations, etc.

[0096] Each of the multiple units may control its power consumption via a power manager 940, which may include control logic for performing the various power management techniques described herein.

[0097] In some embodiments, the processor 900 may further include a non-uniformity structure coupled to a coherence structure to which various peripheral devices may be coupled. One or more interfaces 960a - 960d implement communication with one or more off-chip devices. Such communication may be via various communication protocols, such as PCIe TM , GPIO, USB, I 2 C, UART, MIPI, SDIO, DDR, SPI, HDMI, and other types of communication protocols. Although shown at this high level in the Figure 9 embodiment, it will be understood that the scope of the present invention is not limited to this aspect.

[0098] Although not shown in the Figure 9 , in some embodiments, the processor 900 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0099] Now referring to Figure 10 , shown is a block diagram of a representative SoC. In the illustrated embodiment, the SoC 1000 may be a multi-core SoC configured for low-power operation, which is to be optimized for incorporation into a smart phone or other low-power devices such as a tablet computer or other portable computing device. As an example, the SoC 1000 may be implemented using an asymmetric core or different types of cores such as a combination of higher-power cores and / or low-power cores (e.g., out-of-order cores and in-order cores). In different embodiments, these cores may be based on architecture TM core design or ARM architecture design. In other embodiments, a mix of Intel cores and ARM cores may be implemented in a given SoC.

[0100] As Figure 10 shown, the SoC 1000 includes a first core domain 1010 having a plurality of first cores 1012a–1012d. In the example, these cores may be low-power cores such as in-order cores. In one embodiment, these first cores may be implemented as ARM Cortex A53 cores. These cores are in turn coupled to the cache memory 1015 of the core domain 1010. Additionally, the SoC 1000 includes a second core domain 1020. In Figure 10In the illustrated example, the second core domain 1020 has a plurality of second cores 1022a–1022d. In the example, these cores may be cores that consume higher power than the first core 1012. In an embodiment, these second cores may be out-of-order cores that can be implemented as ARM Cortex A57 cores. These cores are in turn coupled to the cache memory 1025 of the core domain 1020. Note that although Figure 10 the example shown in

[0101] includes 4 cores in each domain, it will be understood that in other examples, more or fewer cores may be present in a given domain. Figure 10 Further referring to

[0102] , a graphics domain 1030 is also provided, which may include one or more graphics processing units (GPUs) configured to independently execute, for example, graphics workloads provided by one or more of the cores in the core domains 1010 and 1020. As an example, in addition to providing graphics and display rendering operations, the GPU domain 1030 can be used to provide display support for various screen sizes. Figure 10 As shown, the various domains are coupled to a coherence interconnect 1040, which in an embodiment may be a cache coherence interconnect structure that is in turn coupled to an integrated memory controller 1050. In some examples, the coherence interconnect 1040 may include a shared cache memory, such as an L3 cache. In an embodiment, the memory controller 1050 may be a direct memory controller for providing communication with off-chip memory via a plurality of channels (such as a plurality of channels for DRAM (not shown in

[0103] for ease of illustration)). Figure 10 In different examples, the number of core domains may vary. For example, for a low-power SoC suitable for incorporation into a mobile computing device, there may be a limited number of core domains such as

[0104] In other embodiments, there may be a larger number of core domains and additional optional IP logic, such that the SoC can be scaled proportionally to higher performance (and power) levels for incorporation into other computing devices such as desktops, servers, high performance computing systems, base stations, etc. As one such example, 4 core domains each having a given number of out-of-order cores may be provided. Further, in addition to optional GPU support (which may take the form of a GPGPU as an example), one or more accelerators may be provided for providing hardware support optimized for specific functions (such as web services, network processing, switching, etc.). Additionally, there may be input / output interfaces for coupling such accelerators to a plurality of off-chip components.

[0105] Although not shown in Figure 10 In some embodiments, SoC 1000 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0106] Now referring to Figure 11 , a block diagram of another example SoC is shown. In an embodiment of Figure 11 , SoC 1100 may include various circuits for high performance to allow for multimedia applications, communication, and other functions. Thus, SoC 1100 is suitable for incorporation into a variety of portable and other devices such as smart phones, tablet computers, smart TVs, etc. In the example shown, SoC 1100 includes a central processing unit (CPU) domain 1110. In an embodiment, a plurality of individual processor cores may be present in CPU domain 1110. As an example, CPU domain 1110 may be a quad-core processor with 4 multi-threaded cores. Such a processor may be a homogeneous or heterogeneous processor, e.g., a mix of low-power and high-power processor cores.

[0107] Furthermore, a GPU domain 1120 is provided to perform advanced graphics processing in one or more GPUs for handling graphics and computing APIs. A DSP unit 1130 may provide one or more low-power DSPs that, in addition to handling advanced computations that may occur during the execution of multimedia instructions, also handle low-power multimedia applications such as music playback, audio / video, etc. Furthermore, a communication unit 1140 may include various components for providing connectivity via various wireless protocols such as cellular communication (including 3G / 4G LTE), wireless local area protocols such as Bluetooth TM and IEEE 802.11, etc.

[0108] Further, the multimedia processor 1150 can be used to perform the capture and playback of high-definition video and audio content, including the processing of user gestures. The sensor unit 1160 can include multiple sensors and / or a sensor controller for docking to various off-chip sensors present in a given platform. One or more separate ISPs can be provided to the image signal processor 1170, which is used to perform image processing with reference to content captured from one or more cameras (including still cameras and video cameras) of the platform.

[0109] The display processor 1180 can provide support for the connection to a high-definition display at a given pixel density, including the ability to wirelessly transmit content for playback on such a display. Further, the location unit 1190 can include a GPS receiver with support for multiple GPS constellations in order to provide the application with high-precision positioning information obtained using such a GPS receiver. It will be understood that although shown in this example with this particular set of components, many variations and alternatives are possible. Figure 11 the example of

[0110] Although not shown in Figure 11 In some embodiments, the SoC 1100 can include all or part of the components and / or processes described below with reference to Figures 17 - 20

[0111] Now referring to Figure 12 , shown is a block diagram of an example system that can be used with multiple embodiments. As can be seen, the system 1200 can be a smart phone or other wireless communicator. The baseband processor 1205 is configured to perform various signal processing on communication signals that would be transmitted from or received by the system. Further, the baseband processor 1205 is coupled to an application processor 1210, which can be the main CPU of the system, to execute the OS and other system software in addition to user applications such as many well-known social media and multimedia applications. The application processor 1210 can further be configured to perform various other computing operations for the device.

[0112] Further, the application processor 1210 can be coupled to a user interface / display 1220, e.g., a touch screen display. In addition, the application processor 1210 can be coupled to a memory system including non-volatile memory (i.e., flash memory 1230) and system memory (i.e., dynamic random access memory (DRAM) 1235). As further shown, the application processor 1210 is further coupled to a capture device 1240 such as one or more image capture devices that can record video and / or still images.

[0113] Still referring to Figure 12 ​, a Universal Integrated Circuit Card (UICC) 1246, including a subscriber identity module and possibly a secure storage device and an encryption processor, is also coupled to the application processor 1210. The system 1200 may further include a security processor 1250 that may be coupled to the application processor 1210. A plurality of sensors 1225 may be coupled to the application processor 1210 to enable input of various sensed information, such as an accelerometer and other environmental information. An audio output device 1295 may provide an interface to output sound, for example, in the form of voice communication, played or streamed audio data, etc.

[0114] As further illustrated, a Near Field Communication (NFC) non-contact interface 1260 is provided, which communicates in the NFC near field via an NFC antenna 1265. Although Figure 12 a separate antenna is shown in, it is understood that in some implementations, one antenna or different sets of antennas may be provided to implement various wireless functions.

[0115] A Power Management Integrated Circuit (PMIC) 1215 is coupled to the application processor 1210 to perform platform-level power management. To this end, the PMIC 1215 may issue power management requests to the application processor 1210 as needed to enter certain low-power states. In addition, based on platform constraints, the PMIC 1215 may also control the power levels of other components of the system 1200.

[0116] To enable communication transmission and reception, various circuits may be coupled between the baseband processor 1205 and the antenna 1290. Specifically, there may be a Radio Frequency (RF) transceiver 1270 and a Wireless Local Area Network (WLAN) transceiver 1275. Generally, wireless data and calls may be received and transmitted using the RF transceiver 1270 according to a given wireless communication protocol, such as a 3G or 4G wireless communication protocol (such as according to Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Long Term Evolution (LTE), or other protocols). In addition, there may be a GPS sensor 1280. Other wireless communications, such as the reception and transmission of radio signals (e.g., AM / FM and other signals), may also be provided. In addition, local wireless communication may also be achieved via the WLAN transceiver 1275.

[0117] Although not shown in Figure 12 , in some embodiments, the system 1200 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0118] Now refer to Figure 13 , which shows a block diagram of another example system that may be used with multiple embodiments. In Figure 13In the illustrated example, system 1300 can be a mobile low-power system such as a tablet computer, 2:1 tablet, phablet, or other convertible or stand-alone tablet system. As illustrated, there is a SoC 1310, and the SoC 1310 can be configured to operate as an application processor of the device.

[0119] Various devices can be coupled to the SoC 1310. In the illustrated example, the memory subsystem includes a flash memory 1340 and a DRAM 1345 that are coupled to the SoC 1310. Additionally, a touch panel 1320 is coupled to the SoC 1310 to provide display capabilities and user input via touch, including providing a virtual keyboard on the display of the touch panel 1320. To provide wired network connectivity, the SoC 1310 is coupled to an Ethernet interface 1330. A peripheral hub 1325 is coupled to the SoC 1310 to enable docking with various peripheral devices, such as can be coupled to the system 1300 through any one of a variety of ports or other connectors.

[0120] In addition to the internal power management circuits and functions in the SoC 1310, a PMIC 1380 is also coupled to the SoC 1310 to provide platform-based power management, e.g., based on whether the system is powered by a battery 1390 or by alternating current via an AC adapter 1395. In addition to this power management based on the power source, the PMIC 1380 can also perform platform power management activities based on environmental and usage conditions. Further, the PMIC 1380 can transfer control and status information to the SoC 1310 to cause various power management actions in the SoC 1310.

[0121] Still referring Figure 13 to, to provide wireless capabilities, a WLAN unit 1350 is coupled to the SoC 1310 and in turn coupled to an antenna 1355. In various implementations, the WLAN unit 1350 can provide communication according to one or more wireless protocols.

[0122] As further illustrated, a plurality of sensors 1360 can be coupled to the SoC 1310. These sensors can include various accelerometers, environmental and other sensors, including user pose sensors. Finally, an audio codec 1365 is coupled to the SoC 1310 to provide an interface to an audio output device 1370. It will of course be understood that while shown in this particular implementation in Figure 13 , many variations and alternatives are possible.

[0123] Although not shown in Figure 13 , in some embodiments, the system 1300 can include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0124] Referring now to Figure 14 , shown is a block diagram of an exemplary computer system 1400 such as a notebook, ultrabook TM or other small form factor systems. In one embodiment, the processor 1410 includes a microprocessor, multi-core processor, multi-threaded processor, ultra-low voltage processor, embedded processor, or other known processing elements. In the illustrated implementation, the processor 1410 serves as the main processing unit and a central hub for communicating with many of the various components of the system 1400, and may include power management circuitry as described herein. As an example, the processor 1410 is implemented as a SoC.

[0125] In one embodiment, the processor 1410 communicates with the system memory 1415. As an exemplary example, the system memory 1415 is implemented to provide a given amount of system memory via multiple memory devices or modules.

[0126] To provide persistent storage of information such as data, applications, one or more operating systems, etc., a mass storage device 1420 may also be coupled to the processor 1410. In various embodiments, to achieve a thinner and lighter system design and to improve system response, the mass storage device may be implemented via an SSD, or the mass storage device may be implemented primarily using a hard disk drive (HDD) with a smaller amount of SSD storage devices acting as SSD caches to enable non-volatile storage of context states and other such information during a power-down event, such that upon restart of system activity, a fast power-on can occur. Figure 14 Also shown is that a flash device 1422 may be coupled to the processor 1410, for example, via a Serial Peripheral Interface (SPI). The flash device may provide non-volatile storage of system software including basic input / output software (BIOS) and other firmware of the system.

[0127] Various input / output (I / O) devices may be present within the system 1400. Figure 14 In an embodiment specifically shown, a display 1424 may be a high-definition LCD or LED panel that further provides a touch screen 1425. In one embodiment, the display 1424 may be coupled to the processor 1410 via a display interconnect that may be implemented as a high-performance graphics interconnect. The touch screen 1425 may be coupled to the processor 1410 via another interconnect that, in an embodiment, may be an I 2 C interconnect. As Figure 14As further shown, in addition to the touch screen 1425, user input via touch can also be performed via the touchpad 1430, which can be configured within the chassis and can also be coupled to the same I 2 C interconnect as the touch screen 1425.

[0128] For purposes of perceptual computing and others, various sensors can be present within the system and can be coupled to the processor 1410 in different ways. Certain inertial sensors and environmental sensors can be coupled to the processor 1410 through the sensor hub 1440 (e.g., via I 2 C interconnect). In Figure 14 the illustrated embodiment, these sensors can include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443, and a gyroscope 1444. Other environmental sensors can include one or more thermal sensors 1446, which in some embodiments are coupled to the processor 1410 via a system management bus (SMBus) bus.

[0129] As Figure 14 is also visible, various peripheral devices can be coupled to the processor 1410 via a low pin count (LPC) interconnect. In the illustrated embodiment, various components can be coupled through the embedded controller 1435. Such components can include a keyboard 1436 (e.g., coupled via a PS2 interface), a fan 1437, and a thermal sensor 1439. In some embodiments, the touchpad 1430 can also be coupled to the EC 1435 via a PS2 interface. Additionally, a security processor such as a trusted platform module (TPM) 1438 can also be coupled to the processor 1410 via this LPC interconnect.

[0130] The system 1400 can communicate with external devices in various ways, including wirelessly. In Figure 14 the illustrated embodiment, there are various wireless modules, each of which can correspond to a radio configured for a specific wireless communication protocol. One way to perform wireless communication within a short distance (such as in the near field) can be via the NFC unit 1445, which in one embodiment can communicate with the processor 1410 via the SMBus. Note that via this NFC unit 1445, devices in close proximity to each other can communicate.

[0131] As Figure 14 is further shown, additional wireless units can include other short - range wireless engines, including the WLAN unit 1450 and the Bluetooth TM unit 1452. By using the WLAN unit 1450, Wi - Fi TM communication can be achieved, while by Bluetooth TMUnit 1452 can perform short - range Bluetooth TM communications. These units can communicate with the processor 1410 via a given link.

[0132] In addition, wireless wide - area communication (e.g., according to cellular or other wireless wide - area protocols) can be performed via the WWAN unit 1456, which can in turn be coupled to a subscriber identity module (SIM) 1457. Additionally, to allow reception and use of location information, there can also be a GPS module 1455. Note that in the Figure 14 embodiment shown, the WWAN unit 1456 and an integrated capture device such as the camera module 1454 can communicate via a given link.

[0133] To provide audio input and output, an audio processor can be implemented via a digital signal processor (DSP) 1460, which can be coupled to the processor 1410 via a high - definition audio (HDA) link. Similarly, the DSP 1460 can communicate with an integrated encoder / decoder (codec) and amplifier 1462, which can in turn be coupled to an output speaker 1463 that can be implemented within a rack. Similarly, the amplifier and codec 1462 can be coupled to a microphone 1465 to receive audio input from the microphone 1465, and in an embodiment, the microphone 1465 can be implemented via a dual - array microphone (such as a digital microphone array) to provide high - quality audio input for voice - activated control of various operations within the system. Additionally note that audio output can be provided from the amplifier / codec 1462 to a headphone jack 1464. Although shown with these specific components in the Figure 14 embodiment, it should be understood that the scope of the present invention is not limited in this regard.

[0134] Although not shown in Figure 14 some embodiments, the system 1400 can include all or part of the components and / or processes described below with reference to Figures 17 - 20 The embodiments can be implemented in many different system types. Now refer to

[0135] which shows a block diagram of a system according to an embodiment of the present invention. As Figure 15 shown, the multi - processor system 1500 is a point - to - point interconnect system and includes a first processor 1570 and a second processor 1580 coupled via a point - to - point interconnect 1550. As Figure 15 shown, Figure 15As shown, each of processors 1570 and 1580 can be a multi-core processor including first and second processor cores (i.e., processor cores 1574a and 1574b and processor cores 1584a and 1584b), although there may be more cores in these processors. Each of the processors may include a PCU or other power management logic to perform processor-based power management as described herein.

[0136] Still referring to Figure 15 , the first processor 1570 also includes a Memory Controller Hub (MCH) 1572 and Point-to-Point (P-P) interfaces 1576 and 1578. Similarly, the second processor 1580 includes an MCH 1582 and P-P interfaces 1586 and 1588. As Figure 15 shown, the MCHs 1572 and 1582 couple the multiple processors to respective memories (i.e., memories 1532 and 1534), which can be multiple portions of system memory (e.g., DRAM) locally attached to the respective processors. The first processor 1570 and the second processor 1580 can be coupled to the chipset 1590 via P-P interconnections 1562 and 1564, respectively. As Figure 15 shown in

[0137] , the chipset 1590 includes P-P interfaces 1594 and 1598. Figure 15 In addition, the chipset 1590 includes an interface 1592 that couples the chipset 1590 to the high-performance graphics engine 1538 via a P-P interconnection 1539. Further, the chipset 1590 can be coupled to the first bus 1516 via an interface 1596. As Figure 15 shown, various input / output (I / O) devices 1514 and a bus bridge 1518 can be coupled to the first bus 1516, and the bus bridge 1518 couples the first bus 1516 to a second bus 1520. In one embodiment, various devices can be coupled to the second bus 1520, including, for example, a keyboard / mouse 1522, a communication device 1526, and a data storage unit 1528 such as a disk drive or other mass storage device that may include code 1530. In addition, an audio I / O 1524 can be coupled to the second bus 1520. Multiple embodiments can be incorporated into other types of systems, including mobile devices such as smart cellular phones, tablet computers, netbooks, ultrabooks TM and the like.

[0138] Although not shown in Figure 15 , in some embodiments, the system 1500 may include all or part of the components and / or processes described below with reference to Figures 17 - 20 .

[0139] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions representing various logics within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. These representations, known as “IP cores,” are reusable units of the logic of an integrated circuit, and these reusable units may be stored on a tangible machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be provided to multiple customers or fabrication agencies, which load the hardware model onto a fabrication machine for manufacturing the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

[0140] Figure 16 FIG. is a block diagram of an IP core development system 1600 that can be used to fabricate an integrated circuit to perform operations according to an embodiment. The IP core development system 1600 can be used to generate modular, reusable designs that can be included in a larger design or used to build an entire integrated circuit (e.g., a SoC integrated circuit). A design agency 1630 can generate a software simulation 1610 of an IP core design in a high-level programming language (e.g., C / C++). The software simulation 1610 can be used to design, test, or verify the behavior of the IP core. A register transfer level (RTL) design can then be created or synthesized from the simulation model. The RTL design 1615 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including performing associated logic using the modeled digital signals. In addition to the RTL design 1615, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0141] The RTL design 1615 or an equivalent can be further synthesized by the design agency into a hardware model 1620, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored using a non-volatile memory 1640 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for transfer to a third-party fabrication agency 1665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) over a wired connection 1650 or a wireless connection 1660. The fabrication agency 1665 can then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations according to the components and / or processes described below with reference to Figures 17 - 20 the described components and / or processes.

[0142] Now refer to Figure 17, shown is a block diagram of a system 1700 according to one or more embodiments. In some embodiments, system 1700 may be all or part of an electronic device or component. For example, system 1700 may be a cellular phone, a computer, a server, a network device, a system-on-chip (SoC), a controller, a wireless transceiver, a power supply unit, etc. Further, in some embodiments, system 1700 may be part of a group of related or interconnected devices such as a data center, a computing cluster, etc.

[0143] As Figure 17 shown, system 1700 may include a processor 1710 operatively coupled to a system memory 1705. Further, although not shown in Figure 17 it, system 1700 may include other components. In one or more embodiments, system memory 1705 may be implemented using any type(s) of computer memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile memory (NVM), a combination of DRAM and NVM, etc.).

[0144] Processor 1710 may be a general-purpose hardware processing device (e.g., a central processing unit (CPU), a system-on-chip (SoC), etc.). As shown, processor 1710 may include any number of processing engines 1715A - 1715N (collectively also referred to as processing engines 1715), a power control circuit 1720, and one or more performance counters 1730. For example, each processing engine 1715 may be a general-purpose processing core.

[0145] In one or more embodiments, power control circuit 1720 and / or the performance counters 1730 may be implemented in hardware components. Power control circuit 1720 may control power-related parameters of processing engines 1715. For example, power control circuit 1720 may be a power control unit (PCU) for controlling the operating frequency (also referred to as the clock frequency) of processing engines 1715. In some examples, power control circuit 1720 and / or the performance counters 1730 may be implemented in the microarchitecture of processor 1710 and / or processing engines 1715. In some embodiments, the performance counters 1730 may be implemented in software.

[0146] In one or more embodiments, the performance counter(s) 1730 may be adjusted to determine one or more interrupt rate metrics of the processing engine 1715. For example, the performance counter 1730 may count the number of clock cycles during which the processing engine 1715 disposes of masked interrupts over a given time period or a given number of clock cycles, and may thus determine the proportion of the processing load associated with disposing of masked interrupts. In another example, the performance counter 1730 may count the number of clock cycles during which the processing engine 1715 disposes of all interrupts (including masked and unmasked interrupts) over a given time period or a given number of clock cycles, and may determine the proportion of the processing load associated with disposing of all interrupts. In yet another example, the performance counter 1730 may indicate the average amount of time consumed by the processing engine 1715 to dispose of masked and / or unmasked interrupts. In still another example, the performance counter 1730 may indicate the average number of masked and / or unmasked interrupts disposed of by the processing engine 1715 over a given time period or a given number of clock cycles. In some embodiments, the performance counter 1730 may reflect a sliding window corresponding to a fixed time period or a fixed number of clock cycles. Note that these examples are not limiting, and it is contemplated that the performance counter(s) 1730 may be used to count or determine other interrupt rate metrics.

[0147] In one or more embodiments, the power control circuit 1720 may read or interact with the performance counter 1730 to determine the interrupt rate metric of the processing engine 1715, and may compare the interrupt rate metric with a defined threshold. If it is determined that the interrupt rate metric has reached the threshold (e.g., is equal to or has exceeded the threshold), then the power control circuit 1720 may increase or maintain the operating frequency of the processing engine 1715.

[0148] For example, if the processing engine 1715 has not reached its maximum operating frequency (e.g., the highest operating frequency allowed or specified for the processing engine 1715), then the power control circuit 1720 may increase the operating frequency to a higher frequency level. In this way, the power control circuit 1720 may improve the performance of the processing engine 1715 in disposing of interrupts.

[0149] In another example, if the processing engine 1715 is already at its maximum operating frequency, the power control circuit 1720 may maintain the maximum operating frequency. Further, the power control circuit 1720 may prevent the operating frequency from being reduced due to other parameter(s) when the interrupt rate metric meets a threshold. For example, during a period of low processor utilization, the operating system (OS) may send a hint signal to the power control circuit 1720 to indicate that the power control circuit 1720 should reduce the operating frequency. In this example, when the interrupt rate metric meets the threshold, the power control circuit 1720 may ignore the OS hint. Thus, the power control circuit 1720 may improve interrupt handling performance by maintaining the operating frequency.

[0150] In one or more embodiments, the power control circuit 1720 may modify or affect other operating parameters of the processor 1710 and / or the processing engine 1715 based on a determination that the interrupt rate metric meets a threshold. For example, the power control circuit 1720 may cause adjustments to voltage levels, current levels, thermal settings or parameters (such as fan speed, coolant flow), power states, and the like.

[0151] Now refer to Figure 18 , shown is an example control logic 1800 according to one or more embodiments. The control logic 1800 may generally correspond to Figure 17 the example embodiments of some or all of the processor 1710 shown in Figure 18 As shown in

[0152] In some examples, the power control unit 1850 may correspond to some or all of the power control circuit 1720 shown in Figure 17 . Further, the total interrupt counter 1810 and the masked interrupt counter 1815 may be included in the Figure 17 performance counter(s) 1730 shown in

[0153] In some embodiments, the total interrupt threshold 1820 and / or the masked interrupt threshold 1825 may be user-configurable and / or stored in a memory or register of the power control unit 1850 (e.g., in a non-volatile memory). Further, in some embodiments, the total interrupt threshold 1820 and / or the masked interrupt threshold 1825 may be set or adjusted based on a hint signal from the operating system.

[0154] In some embodiments, the masked interrupt counter 1815 may provide or indicate an interrupt metric based on a proportion of the processing load associated with handling masked interrupts. For example, the masked interrupt counter 1815 may be adjusted to count the number of clock cycles during which the associated processing engine handles only masked interrupts during a given time period or a given number of clock cycles. In another example, the masked interrupt counter 1815 may be adjusted to reflect the average amount of time used by the associated processing engine to handle masked interrupts. In yet another example, the masked interrupt counter 1815 may be adjusted to reflect the average number of masked interrupts handled by the associated processing engine during a given time period or a given number of clock cycles.

[0155] In some embodiments, the total interrupt counter 1810 may provide or indicate an interrupt metric based on a proportion of the processing load associated with handling all types of interrupts. For example, the total interrupt counter 1810 may be adjusted to count the number of clock cycles during which the associated processing engine handles all types of interrupts (including masked and unmasked interrupts) during a given time period or a given number of clock cycles. In another example, the total interrupt counter 1810 may be adjusted to reflect the average amount of time used by the associated processing engine to handle both masked and unmasked interrupts. In yet another example, the total interrupt counter 1810 may be adjusted to reflect the average number of masked interrupts handled by the associated processing engine during a given time period or a given number of clock cycles, including both masked and unmasked interrupts.

[0156] In one or more embodiments, the first comparison logic 1830 may compare the count value of the total interrupt counter 1810 with the total interrupt threshold 1820. Further, when the total interrupt counter 1810 has reached the total interrupt threshold 1820, the first comparison logic 1830 may notify (e.g., via a signal, notification flag, or register, etc.) the frequency controller 1840. In response to this notification, the frequency controller 1840 may increase the operating frequency of the associated processing engine or may maintain the associated processing engine at the maximum operating frequency.

[0157] In one or more embodiments, the second comparison logic 1835 may compare the count value of the masked interrupt counter 1815 with the masked interrupt threshold 1825. Further, when the masked interrupt counter 1815 has reached the masked interrupt threshold 1825, the second comparison logic 1835 may notify the frequency controller 1840. In response to this notification, the frequency controller 1840 may increase the operating frequency of the associated processing engine or may maintain the associated processing engine at the maximum operating frequency.

[0158] In some embodiments, the frequency controller 1840 may increase or maintain the operating frequency in response to a signal from the first comparison logic 1830 or the second comparison logic 1835. In other embodiments, the frequency controller 1840 may increase or maintain the operating frequency only when signals from both the first comparison logic 1830 and the second comparison logic 1835 are received within a given time period.

[0159] In one or more embodiments, the power control unit 1850 may modify or affect other operating parameters based on signals from the first comparison logic 1830 and / or the second comparison logic 1835. For example, the power control unit 1850 may cause adjustments to voltage levels, current levels, thermal settings, power states, and the like.

[0160] Now referring to Figure 19 , shown is a flowchart of a method 1900 for frequency control according to one or more embodiments. In various embodiments, the method 1900 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processing device), or a combination thereof. In some implementations, one or more components shown in Figures 17 - 18 (e.g., the power control circuit 1720 and / or the performance counter(s) 1730) may be used to perform the method 1900. In a firmware or software embodiment, the method 1900 may be implemented by computer-executed instructions stored in a non-transitory machine-readable medium such as an optical, semiconductor, or magnetic storage device. The machine-readable medium may store data that, if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform the method. For illustrative purposes, the actions involved in the method 1900 may be described below with reference to Figures 17 - 18 for illustration, Figures 17 - 18 shows an example according to one or more embodiments. However, the scope of the embodiments discussed herein is not limited in this regard.

[0161] Block 1910 may include adjusting one or more performance counters to determine at least one interrupt rate metric of a first processing engine. For example, referring toFigures 17 - 18 The total interrupt counter 1810 can be incremented to count the number of masked and unmasked interrupts handled by the processing engine 1715A during a given time period or a given number of clock cycles. In some embodiments, the count of the total interrupt counter 1810 can indicate the proportion of clock cycles used by the processing engine 1715A to handle masked and unmasked interrupts.

[0162] Block 1920 can include determining whether at least one interrupt rate metric has reached a first threshold when the first processing engine is operating at a first frequency level using one or more performance counters. For example, referring to Figures 17 - 18 , the first comparison logic 1830 can determine that the count value of the total interrupt counter 1810 has reached the total interrupt threshold 1820.

[0163] Block 1930 can include: in response to determining that at least one interrupt rate metric has reached a first threshold when the first processing engine is operating at a first frequency level, increasing the operating frequency of the first processing engine from the first frequency level to a second frequency level. For example, referring to Figures 17 - 18 , in response to the determination that the total interrupt counter 1810 has reached the total interrupt threshold 1820, the first comparison logic 1830 can cause the frequency controller 1840 to increase the operating frequency of the processing engine 1715A. In some embodiments, if the processing engine 1715A has not used the maximum operating frequency, the frequency controller 1840 can increase the operating frequency. After block 1930, method 1900 is complete.

[0164] Now referring to Figure 20 , shown is a flowchart of a method 2000 for frequency control according to one or more embodiments. In various embodiments, method 2000 can be performed by processing logic that can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processing device), or a combination thereof. In some implementations, one or more components shown in Figures 17 - 18 (e.g., the power control circuit 1720 and / or the (multiple) performance counters 1730) can be used to perform method 2000. In a firmware or software embodiment, method 2000 can be implemented by computer-executed instructions stored in a non-transitory machine-readable medium such as an optical, semiconductor, or magnetic storage device. The machine-readable medium can store data that, if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform the method. For illustrative purposes, the actions involved in method 2000 will be described below with reference to Figures 17 - 18 , Figures 17 - 18 showing an example according to one or more embodiments. However, the scope of the various embodiments discussed herein is not limited in this regard.

[0165] Block 2010 may include detecting an interruption in the processing engine. Block 2020 may include incrementing a counter to count the cycles in which the processing engine disposes of the interruption. For example, referring to Figures 17 - 18 , the counter 1815 for masked interruptions may be incremented based on the detection of masked interruptions disposed of by the processing engine 1715A. In some embodiments, the counter 1815 for masked interruptions may count the masked interruptions during a given time period or a given number of clock cycles. Thus, in some embodiments, the count of the counter 1815 for masked interruptions may indicate the proportion of clock cycles that the processing engine 1715A uses to dispose of masked interruptions.

[0166] Diamond box 2030 may include determining whether the counter has reached an associated threshold. For example, referring to Figures 17 - 18 , the second comparison logic 1835 may determine whether the count of the counter 1815 for masked interruptions is equal to or greater than the masked interruption threshold 1825.

[0167] If it is determined at diamond box 2030 that the counter has not reached the associated threshold, method 2000 does not include increasing the operating frequency, but instead returns to block 2010 to continue detecting interruptions in the processing engine. However, if it is determined at diamond box 2030 that the counter has reached the associated threshold, method 2000 continues at diamond box 2040.

[0168] Diamond box 2040 includes determining whether the processing engine is already at the maximum operating frequency. If it is determined at diamond box 2040 that the processing engine is not already at the maximum operating frequency, then at block 2050, the operating frequency may be increased. For example, referring to Figure 17 , the power control circuit 1720 may determine that the processing engine 1720A is not currently operating at the highest allowed frequency level, and in response may increase the operating frequency to the next defined level. After block 2050, method 2000 returns to block 2010 to continue detecting interruptions in the processing engine.

[0169] However, if it is determined at diamond box 2040 that the processing engine is already at the maximum operating frequency, then at block 2060, a decrease in the operating frequency may be blocked. For example, referring to Figure 17, the power control circuit 1720 may determine that the processing engine 1720A is currently operating at the highest allowable frequency level. Assume that the power control circuit 1720 receives a command or indication to reduce the operating frequency (e.g., from an operating system, driver, main power controller, etc.). Alternatively, the power control circuit 1720 may include internal logic indicating a requirement to reduce the operating frequency (e.g., due to low processor utilization). In such a case, the power control circuit 1720 may prevent the operating frequency from being reduced in response to a determination that the masked interrupt counter 1815 is equal to or greater than the masked interrupt threshold 1825. In some examples, the power control circuit 1720 may continue to prevent such frequency reduction for a given period of time, and / or while the masked interrupt counter 1815 continues to meet the masked interrupt threshold 1825. After block 2060, method 2000 returns to block 2010 to continue detecting interrupts in the processing engine.

[0170] In some embodiments, method 2000 may be performed using multiple threshold levels and multiple increases in the operating frequency. For example, assume that block 2050 reduces the operating frequency to a first frequency level after the counter reaches a first threshold level (at diamond box 2030). Further, as described above, the output of block 2050 may loop back to block 2010 to continue detecting interrupts. Further assume that at block 2020, the counter may continue to count cycles until it reaches a second threshold level higher than the first threshold level. In response to a determination at diamond box 2030 that the second threshold level has been reached, the operating frequency may be further increased to a second frequency level higher than the first frequency level at block 2050. In this way, method 2000 may be repeated using multiple threshold levels as required.

[0171] Note that although Figures 17 - 20 the figures illustrate example implementations, other variations are possible. For example, it is contemplated that one or more embodiments may be implemented in the example devices and systems described with reference to Figures 1 - 16 the figures.

[0172] Note that the examples shown in Figures 1 - 20 are provided for illustrative purposes and Figures 1 - 20 the examples shown in Figures 1 - 20 are not intended to limit any embodiment. Specifically, although embodiments may be shown in a simplified form for clarity, embodiments may include any number and / or arrangement of processors, cores, and / or additional components (e.g., buses, storage media, connectors, power components, buffers, interfaces, etc.). For example, it is contemplated that some embodiments may include any number of components in addition to those shown, and different arrangements of the shown components may occur in certain implementations. Additionally, it is contemplated that Figures 1 - 20 the details of the examples shown may be used anywhere in one or more embodiments.

[0173] described below Figures 21A - 29 The following describes in detail exemplary architectures and systems for implementing the embodiments above. In some embodiments, one or more of the hardware components and / or instructions described above are emulated as detailed below or implemented as software modules.

[0174] Embodiments of the instructions described in detail above may be implemented in a "general vector friendly instruction format" which is described in detail below. In other embodiments, such a format is not utilized and another instruction format is used; however, the descriptions below of write mask registers, various data transforms (mixing, broadcasting, etc.), addressing, etc. generally apply to the descriptions of the embodiments of the instructions above. Additionally, exemplary systems, architectures, and pipelines are described in detail below. Embodiments of the instructions above may be executed on such systems, architectures, and pipelines, but are not limited to those systems, architectures, and pipelines described in detail.

[0175] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, position of bits) to specify the operation to be performed (e.g., opcode) and the operand(s) and / or other data fields (e.g., mask) on which the operation is to be performed, etc. Some instruction formats are further broken down by the definition of instruction templates (or sub-formats). For example, an instruction template of a given instruction format may be defined as different subsets of the fields of that instruction format (the fields included typically in the same order, but at least some fields having different bit positions since fewer fields are included), and / or defined as having a given field interpreted in a different manner. Thus, each instruction of the ISA is expressed using a given instruction format (and if defined, according to a given one of the instruction templates in that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD (addition) instruction has a specific opcode and instruction format, the specific instruction format including an opcode field for specifying the opcode and operand fields for selecting the operands (source 1 / destination and source 2); and the appearance of the ADD instruction in the instruction stream will result in specific contents in the operand fields for selecting specific operands. Advanced Vector Extensions (AVX) (AVX1 and AVX2) and SIMD extension sets using the Vector Extension (VEX) encoding scheme have been introduced and / or published (see, for example, the September 2014 64 and IA-32 Architectures Software Developer's Manual; and see the October 2014 Advanced Vector Extensions Programming Reference).

[0176] Exemplary instruction formats

[0177] Embodiments of the (multiple) instructions described herein can be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the (multiple) instructions can be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

[0178] General Vector Friendly Instruction Format

[0179] A vector friendly instruction format is an instruction format suitable for vector instructions (e.g., there are specific fields dedicated to vector operations). Although embodiments are described in which both vector and scalar operations are supported via the vector friendly instruction format, alternative embodiments use only vector operations via the vector friendly instruction format.

[0180] Figures 21A - 21B is a block diagram illustrating a general vector friendly instruction format and its instruction templates according to an embodiment of the present invention. Figure 21A is a block diagram illustrating a general vector friendly instruction format and its Class A instruction templates according to an embodiment of the present invention; and Figure 21B is a block diagram illustrating a general vector friendly instruction format and its Class B instruction templates according to an embodiment of the present invention. Specifically, Class A and Class B instruction templates are defined for the general vector friendly instruction format 2100, both of which include instruction templates for no memory access 2105 and memory access 2120. The term "general" in the context of the vector friendly instruction format refers to an instruction format not tied to any particular instruction set.

[0181] Although embodiments of the present invention will be described in which the vector friendly instruction format supports the following: a 64 - byte vector operand length (or size) with a 32 - bit (4 - byte) or 64 - bit (8 - byte) data element width (or size) (and thus, a 64 - byte vector is composed of 16 double - word - sized elements, or alternatively of 8 quad - word - sized elements); a 64 - byte vector operand length (or size) with a 16 - bit (2 - byte) or 8 - bit (1 - byte) data element width (or size); a 32 - byte vector operand length (or size) with a 32 - bit (4 - byte), 64 - bit (8 - byte), 16 - bit (2 - byte), or 8 - bit (1 - byte) data element width (or size); and a 16 - byte vector operand length (or size) with a 32 - bit (4 - byte), 64 - bit (8 - byte), 16 - bit (2 - byte), or 8 - bit (1 - byte) data element width (or size); alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., a 256 - byte vector operand) with larger, smaller, or different data element widths (e.g., a 128 - bit (16 - byte) data element width).

[0182] Figure 21AThe Class A instruction templates in [ ] include: 1) within the instruction templates without memory access 2105, an instruction template showing a fully rounded control type operation 2110 without memory access and an instruction template of a data transformation type operation 2115 without memory access; and 2) within the instruction templates of memory access 2120, an instruction template showing the timeliness 2125 of memory access and an instruction template of non - timeliness 2130 of memory access. Figure 21B The Class B instruction templates in [ ] include: 1) within the instruction templates without memory access 2105, an instruction template showing a write - mask - controlled partial rounded control type operation 2112 without memory access and an instruction template of a write - mask - controlled vsize type operation 2117 without memory access; and 2) within the instruction templates of memory access 2120, an instruction template showing the write - mask control 2127 of memory access.

[0183] The general vector - friendly instruction format 2100 includes the following fields in the order illustrated in [ ]. Figures 21A - 21B as follows.

[0184] Format field 2140 - - The specific value (instruction format identifier value) in this field uniquely identifies the vector - friendly instruction format and thereby identifies that the instruction appears in the instruction stream in the vector - friendly instruction format. Thus, this field is optional in the sense that it is not required for an instruction set that only has the general vector - friendly instruction format.

[0185] Base operation field 2142 - - Its content differentiates different base operations.

[0186] Register index field 2144 - - Its content directly or through address generation specifies the position of source or destination operands in registers or in memory. These fields include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although in one embodiment N can be up to three source registers and one destination register, alternative embodiments can support more or fewer source and destination registers (e.g., can support up to two sources, where one of these sources also serves as a destination; can support up to three sources, where one of these sources also serves as a destination; can support up to two sources and one destination).

[0187] Modifier field 2146 - The content thereof will specify the instructions in the general vector instruction format that specify memory accesses from those that do not in the general vector instruction format; i.e., it differentiates between the instruction templates with no memory access 2105 and the instruction templates with memory access 2120. A memory access operation reads and / or writes to the memory hierarchy (in some cases, using values in registers to specify source and / or destination addresses), while a non-memory access operation does not (e.g., the source and / or destination are registers). Although in one embodiment, this field also selects between three different ways to perform memory address calculation, alternative embodiments may support more, fewer, or different ways to perform memory address calculation.

[0188] Extended operation field 2150 - The content thereof differentiates which one of various different operations, in addition to the base operation, is to be performed. This field is context-dependent. In one embodiment of the present invention, this field is divided into a class field 2168, an alpha field 2152, and a beta field 2154. The extended operation field 2150 allows multiple sets of common operations to be performed in a single instruction rather than in 2, 3, or 4 instructions.

[0189] Scale field 2160 - The content thereof allows the content of the index field used for memory address generation (e.g., for address generation using (2 比例 * index + base)) to be scaled.

[0190] Displacement field 2162A - The content thereof is used as part of memory address generation (e.g., for address generation using (2 比例 * index + base + displacement)).

[0191] Displacement factor field 2162B (note that the juxtaposition of displacement field 2162A directly above displacement factor field 2162B indicates the use of one or the other) - The content thereof is used as part of address generation; it specifies the displacement factor that will scale the size (N) of the memory access - where N is the number of bytes in the memory access (e.g., for use with (2 比例*(Address generation with index + base + scaled displacement). The redundant low-order bits are ignored, and thus the displacement is multiplied by the content of the displacement factor field by the total size (N) of the memory operand to generate the final displacement that will be used in calculating the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 2174 (described later in this document) and the data manipulation field 2154C. The displacement field 2162A and the displacement factor field 2162B are not used in instruction templates without memory access 2105, and / or different embodiments may implement only one of the two or neither of the two, in the sense that the displacement field 2162A and the displacement factor field 2162B are optional.

[0192] Data element width field 2164 - whose content differentiates which of the multiple data element widths will be used (in some embodiments for all instructions; in other embodiments only for some of the instructions). If only one data element width is supported and / or some aspect of the opcode is used to support the data element width, then this field is not needed, in the sense that this field is optional.

[0193] Write mask field 2170 - whose content controls, on a per-data element position basis, whether the data element positions in the destination vector operand reflect the results of the base operation and the augmentation operation. Class A instruction templates support merge-write masks, while Class B instruction templates support both merge-write masks and zero-write masks. When merged, the vector mask allows any set of elements in the destination to be protected from update during the execution of any operation (specified by the base operation and the augmentation operation); in another embodiment, the old value of each element of the destination where the corresponding mask bit has 0 is retained. In contrast, when zeroing, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, the elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified), however, the elements being modified do not necessarily have to be contiguous. Thus, the write mask field 2170 allows partial vector operations, which include loads, stores, arithmetic, logic, etc. Although embodiments of the present invention have been described in which the content of the write mask field 2170 selects one write mask register among multiple write mask registers that contains the write mask to be used (and thus, the content of the write mask field 2170 indirectly identifies the mask to be executed), alternative embodiments alternatively or additionally allow the content of the mask write field 2170 to directly specify the mask to be executed.

[0194] Immediate digit field 2172 - the content of which permits the specification of an immediate number. This field is optional in the sense that it does not exist in a general vector-friendly format where immediate numbers are not supported and does not exist in instructions that do not use immediate numbers.

[0195] Class field 2168 - the content of which differentiates between different classes of instructions. Refer to Figures 21A - 21B , the content of this field selects between class A and class B instructions. In Figures 21A - 21B , rounded rectangles are used to indicate that a particular value exists in the field (e.g., for class A 2168A and class B 2168B of class field 2168 in Figures 21A - 21B respectively).

[0196] Class A instruction template

[0197] In the case of the instruction template of a class A non-memory access 2105, the α field 2152 is interpreted as the RS field 2152A whose content differentiates which of different augmentation operation types is to be performed (e.g., for instruction templates of a fully rounded control type operation 2110 without memory access and a data transformation type operation 2115 without memory access, rounding 2152A.1 and data transformation 2152A.2 are specified respectively), and the β field 2154 differentiates which of the specified type of operations is to be performed. In the instruction template of a non-memory access 2105, the scale field 2160, the displacement field 2162A, and the displacement factor field 2162B do not exist.

[0198] Instruction template for non-memory access - fully rounded control type operation

[0199] In the instruction template of a non-memory access fully rounded control type operation 2110, the β field 2154 is interpreted as the rounding control field 2154A whose (multiple) content provides static rounding. Although in the described embodiments of the present invention, the rounding control field 2154A includes a suppress all floating-point exceptions (SAE) field 2156 and a rounding operation control field 2158, alternative embodiments may support both concepts, may encode both concepts into the same field, or have only one or the other of these concepts / fields (e.g., may have only the rounding operation control field 2158).

[0200] SAE field 2156 - the content of which differentiates whether to disable the reporting of exception events; when the content of the SAE field 2156 indicates enabling suppression, a given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler.

[0201] Rounding operation control field 2158 - the content thereof differentiates which one of a set of rounding operations is to be performed (e.g., rounding up, rounding down, rounding towards zero, and rounding to the nearest). Thus, the rounding operation control field 2158 allows the rounding mode to be changed instruction by instruction. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 2158 overrides the register value.

[0202] Instruction template for instructions without memory access - data transformation type operations

[0203] In the instruction template for data transformation type operations 2115 without memory access, the β field 2154 is interpreted as a data transformation field 2154B, the content of which differentiates which one of multiple data transformations is to be performed (e.g., no data transformation, mixing, broadcasting).

[0204] In the case of the instruction template for class A memory access 2120, the α field 2152 is interpreted as an eviction hint field 2152B, the content of which differentiates which eviction hint is to be used (in Figure 21A for the instruction template for memory access timeliness 2125 and the instruction template for memory access non - timeliness 2130, timeliness 2152B.1 and non - timeliness 2152B.2 are respectively specified), and the β field 2154 is interpreted as a data manipulation field 2154C, the content of which differentiates which one of multiple data manipulation operations (also called primitives) is to be performed (e.g., no manipulation, broadcasting, up - conversion of the source, and down - conversion of the destination). The instruction template for memory access 2120 includes a scale field 2160 and optionally includes a displacement field 2162A or a displacement factor field 2162B.

[0205] Vector memory instructions use conversion support to perform loading vectors from memory and storing vectors to memory. Like ordinary vector instructions, vector memory instructions transfer data from / to memory in a data - element - by - data - element manner, where the elements actually transferred are specified by the content of the vector mask selected as the write mask.

[0206] Instruction template for memory access - timeliness

[0207] Timely data is data that may benefit from cache operations and be reused quickly enough. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0208] Instruction template for memory access - non - timeliness

[0209] Non-temporal data is data that is unlikely to benefit from cache operations in the first-level cache being reused quickly enough and that should be given eviction priority. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0210] Class B instruction template

[0211] In the case of the Class B instruction template, the α field 2152 is interpreted as a write mask control (Z) field 2152C, the content of which differentiates whether the write mask controlled by the write mask field 2170 should be merged or zeroed.

[0212] In the case of the instruction template for a Class B non-memory access 2105, a part of the β field 2154 is interpreted as an RL field 2157A, the content of which differentiates which of different expansion operation types is to be performed (e.g., for instruction templates for non-memory access, write mask control, partial rounding control type operations 2112, and non-memory access, write mask control, VSIZE type operations 2117, rounding 2157A.1 and vector length (VSIZE) 2157A.2 are specified respectively), while the remaining part of the β field 2154 differentiates which of the operations of the specified type is to be performed. In the instruction template for a non-memory access 2105, the scale field 2160, displacement field 2162A, and displacement factor field 2162B do not exist.

[0213] In the instruction template for a non-memory access, write mask control, partial rounding control type operation 2112, the remaining part of the β field 2154 is interpreted as a rounding operation control field 2159A, and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flag and does not invoke any floating-point exception handler).

[0214] The rounding operation control field 2159A - like the rounding operation control field 2158, the content of which differentiates which of a set of rounding operations is to be performed (e.g., round up, round down, round towards zero, and round to nearest). Thus, the rounding operation control field 2159A allows the rounding mode to be changed instruction by instruction. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 2159A overrides the register value.

[0215] In the instruction template for a non-memory access, write mask control, VSIZE type operation 2117, the remaining part of the β field 2154 is interpreted as a vector length field 2159B, the content of which differentiates which of multiple data vector lengths is to be performed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0216] In the case of the instruction template for a class B memory access 2120, a portion of the β field 2154 is interpreted as a broadcast field 2157B, the content of which differentiates whether to perform a broadcast type data manipulation operation, and the remainder of the β field 2154 is interpreted as a vector length field 2159B. The instruction template for the memory access 2120 includes a scale field 2160 and optionally includes a displacement field 2162A or a displacement factor field 2162B.

[0217] For the general vector friendly instruction format 2100, it is shown that the full opcode field 2174 includes a format field 2140, a base operation field 2142, and a data element width field 2164. Although one embodiment is shown in which the full opcode field 2174 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 2174 includes less than all of these fields. The full opcode field 2174 provides the operation code (opcode).

[0218] The extended operation field 2150, the data element width field 2164, and the write mask field 2170 allow these features to be specified per instruction in the general vector friendly instruction format.

[0219] The combination of the write mask field and the data element width field creates various types of instructions because these instructions allow the mask to be applied based on different data element widths.

[0220] The various instruction templates that occur within classes A and B are beneficial in different scenarios. In some embodiments of the present invention, different processors or different cores within a processor may support only class A, only class B, or may support both classes. For example, a high-performance general-purpose out-of-order core intended for general computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both general computing and graphics and / or scientific (throughput) computing may support both class A and class B (of course, cores having some mix of templates and instructions from both classes, but not all templates and instructions from both classes are within the scope of the present invention). Similarly, a single processor may include multiple cores, all of which support the same class, or where different cores support different classes. For example, in a processor having separate graphics and general-purpose cores, a core within the graphics core intended primarily for graphics and / or scientific computing may support only class A, while one or more within the general-purpose core may be high-performance general-purpose cores with out-of-order execution and register renaming that support only class B for general computing. Another processor without a separate graphics core may include one or more general-purpose in-order or out-of-order cores that support both class A and class B. Of course, in different embodiments of the present invention, features from one class may also be implemented in other classes. Programs written in a high-level language will be made (e.g., just-in-time compiled or statically compiled) into various different executable forms, which include: 1) a form having only instructions of the (multiple) classes supported by the target processor for execution; or 2) a form having alternative routines and control flow code, where the alternative routines are written using different combinations of instructions from all classes, and the control flow code selects these routines for execution based on the instructions supported by the processor currently executing the code.

[0221] Exemplary dedicated vector-friendly instruction format

[0222] FIG. 22 is a block diagram illustrating an exemplary dedicated vector-friendly instruction format in accordance with an embodiment of the present invention. FIG. 22 shows a dedicated vector-friendly instruction format 2200, which is dedicated in the sense that it specifies the positions, sizes, interpretations, and orders of the various fields, as well as the values of some of those fields. The dedicated vector-friendly instruction format 2200 can be used to extend the x86 instruction set, and thus some of the fields therein are similar or identical to those used in the existing x86 instruction set and its extensions (e.g., AVX). The format remains consistent with the prefix encoding field, real opcode byte field, MOD R / M field, SIB field, displacement field, and immediate number field of the existing x86 instruction set with extensions. The fields from FIG. 21 are illustrated, and the fields from FIG. 22 are mapped to the fields from FIG. 21.

[0223] It should be understood that, although embodiments of the present invention are described in the context of the general vector friendly instruction format 2100 with reference to the special vector friendly instruction format 2200 for illustrative purposes, the present invention is not limited to the special vector friendly instruction format 2200 unless otherwise stated. For example, the general vector friendly instruction format 2100 contemplates various possible sizes for the various fields, while the special vector friendly instruction format 2200 is shown with fields of specific sizes. As a specific example, although the data element width field 2164 is illustrated as a one-bit field in the special vector friendly instruction format 2200, the present invention is not limited thereto (i.e., the general vector friendly instruction format 2100 contemplates other sizes for the data element width field 2164).

[0224] The general vector friendly instruction format 2100 includes the following fields in the order listed below Figure 22A as illustrated in

[0225] EVEX prefix (bytes 0 - 3) 2202 - Encoded in a four-byte form.

[0226] Format field 2140 (EVEX byte 0, bits [7:0]) - The first byte (EVEX byte 0) is the format field 2140, and it contains 0x62 (in one embodiment of the present invention, the only value for distinguishing the vector friendly instruction format).

[0227] The second - fourth bytes (EVEX bytes 1 - 3) include multiple bit fields that provide specialized capabilities.

[0228] REX field 2205 (EVEX byte 1, bits [7 - 5]) - Composed of the EVEX.R bit field (EVEX byte 1, bit [7] – R), the EVEX.X bit field (EVEX byte 1, bit [6] – X), and (2157BEX byte 1, bit [5] – B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields and are encoded in one's complement form, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. Other fields of these instructions encode the lower three bits (rrr, xxx, and bbb) of the register index as known in the art, whereby Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0229] REX’ Field 2210 - This is the first part of REX’ Field 2210 and is the EVEX.R’ bit field (EVEX byte 1, bit [4] – R’) that encodes the upper 16 or lower 16 registers of the extended 32 - register set. In one embodiment of the present invention, this bit is stored in bit - reversed format along with the other bits indicated below to (in the well - known x86 32 - bit mode) distinguish from the BOUND instruction, whose real opcode byte is 62 but does not accept the value 11 in the MOD field in the MODR / M field (described below); alternative embodiments of the present invention do not store this indicated bit and the other indicated bits below in reversed format. The value 1 is used to encode the lower 16 registers. In other words, R’Rrrr is formed by combining EVEX.R’, EVEX.R, and other RRRs from other fields.

[0230] Opcode Map Field 2215 (EVEX byte 1, bits [3:0] – mmmm) - Its content encodes the implicit leading opcode byte (0F, 0F 38, or 0F 3).

[0231] Data Element Width Field 2164 (EVEX byte 2, bit [7] – W) - Represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the data type (32 - bit data element or 64 - bit data element).

[0232] EVEX.vvvv 2220 (EVEX byte 2, bits [6:3] - vvvv) - The functions of EVEX.vvvv can include the following: 1) EVEX.vvvv encodes the first source register operand specified in reversed (1's complement) form and is valid for instructions with two or more source operands; 2) EVEX.vvvv encodes the destination register operand specified in 1's complement form for a specific vector displacement; or 3) EVEX.vvvv does not encode any operand, this field is reserved and should contain 1111b. Thus, the EVEX.vvvv field 2220 encodes the 4 low - order bits of the first source register specifier stored in reversed (1's complement) form. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to 32 registers.

[0233] EVEX.U 2168 Class Field (EVEX byte 2, bit [2] - U) - If EVEX.U = 0, it indicates class A or EVEX.U0; if EVEX.U = 1, it indicates class B or EVEX.U1.

[0234] Prefix Encoding Field 2225 (EVEX byte 2, bits [1:0] - pp) - provides additional bits for the base operation field. In addition to providing support for traditional SSE instructions in EVEX prefix format, this also has the benefit of compressing the SIMD prefix (the EVEX prefix only requires 2 bits instead of a byte to express the SIMD prefix). In one embodiment, to support traditional SSE instructions using SIMD prefixes (66H, F2H, F3H) in both traditional format and EVEX prefix format, these traditional SIMD prefixes are encoded into the SIMD prefix encoding field; and at runtime they are expanded into traditional SIMD prefixes before being provided to the PLA (thus, without modification, the PLA can execute these traditional instructions in both traditional format and EVEX format). Although newer instructions can directly use the content of the EVEX prefix encoding field as an opcode extension, for consistency, a particular embodiment expands it in a similar way but allows different meanings specified by these traditional SIMD prefixes. Alternative embodiments can redesign the PLA to support 2-bit SIMD prefix encoding and thus do not require expansion.

[0235] Alpha Field 2152 (EVEX byte 3, bit [7] – EH, also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.Write Mask Control, and EVEX.N; also illustrated as alpha) - as previously described, this field is context-specific.

[0236] Beta Field 2154 (EVEX byte 3, bits [6:4] - SSS, also known as EVEX.s 2-0 , EVEX.r 2-0 , EVEX.rr1, EVEX.LL0, EVEX.LLB, also illustrated as beta beta beta) - as previously described, this field is context-specific.

[0237] REX’ Field 2210 - this is the remainder of the REX’ field and is a EVEX.V’ bit field (EVEX byte 3, bit [3] – V’) that can be used to encode the upper 16 or lower 16 registers of the extended 32-register set. This bit is stored in bit-reversed format. The value 1 is used to encode the lower 16 registers. In other words, V’VVVV is formed by combining EVEX.V’ and EVEX.vvvv.

[0238] Write mask field 2170 (EVEX byte 3, bits [2:0] - kkk) - the content thereof specifies the index of the register in the write mask register, as previously described. In one embodiment of the present invention, the specific value EVEX.kkk = 000 has a special behavior that implies no write mask is used for a particular instruction (this can be implemented in various ways, including using a write mask hardwired to all objects or hardware that bypasses the mask hardware).

[0239] The real opcode field 2230 (byte 4) is also referred to as the opcode byte. A part of the opcode is specified in this field.

[0240] The MOD R / M field 2240 (byte 5) includes the MOD field 2242, the Reg field 2244, and the R / M field 2246. As previously described, the content of the MOD field 2242 differentiates between memory access operations and non-memory access operations. The role of the Reg field 2244 can be boiled down to two cases: encoding a destination register operand or a source register operand; or being regarded as an opcode extension and not being used to encode any instruction operand. The role of the R / M field 2246 can include the following: encoding an instruction operand that references a memory address; or encoding a destination register operand or a source register operand.

[0241] Scale, Index, Base (SIB) byte (byte 6) - as previously described, the content of the scale field 2160 is used for memory address generation. SIB.xxx 2254 and SIB.bbb 2256 - the content of these fields has been previously mentioned for register indices Xxxx and Bbbb.

[0242] Displacement field 2162A (bytes 7 - 10) - when the MOD field 2242 contains 10, bytes 7 - 10 are the displacement field 2162A, and it works the same as the traditional 32-bit displacement (disp32) and works at the byte granularity.

[0243] Displacement factor field 2162B (byte 7) - When the MOD field 2242 contains 01, byte 7 is the displacement factor field 2162B. The position of this field is the same as that of the traditional x86 instruction set 8-bit displacement (disp8) which works at byte granularity. Since disp8 is sign-extended, it can only address between -128 and 127 byte offsets; in terms of a 64-byte cache line, disp8 uses 8 bits that can be set to only four really useful values -128, -64, 0, and 64; since a larger range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 2162B is a reinterpretation of disp8; when using the displacement factor field 2162B, the actual displacement is determined by multiplying the content of the displacement factor field by the size (N) of the memory operand access. This type of displacement is called disp8*N. This reduces the average instruction length (one byte for the displacement but with a much larger range). Such compressed displacements are based on the assumption that the effective displacement is a multiple of the granularity of the memory access, and thus the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 2162B replaces the traditional x86 instruction set 8-bit displacement. Thus, the displacement factor field 2162B is encoded in the same way as the x86 instruction set 8-bit displacement (therefore, there is no change in the ModRM / SIB encoding rules), the only difference being that disp8 is overloaded to disp8*N. In other words, there is no change in the encoding rules or encoding length, but only a change in the hardware's interpretation of the displacement value (which requires scaling the displacement by the size of the memory operand to obtain a byte-wise address offset). The immediate field 2172 operates as previously described.

[0244] Full opcode field

[0245] Figure 22B is a block diagram showing the fields that make up the full opcode field 2174 with a dedicated vector-friendly instruction format 2200 according to an embodiment of the present invention. Specifically, the full opcode field 2174 includes a format field 2140, a base operation field 2142, and a data element width (W) field 2164. The base operation field 2142 includes a prefix encoding field 2225, an opcode mapping field 2215, and a real opcode field 2230.

[0246] Register index field

[0247] Figure 22CFIG. is a block diagram of fields that make up register index field 2144 having a special vector-friendly instruction format 2200 in accordance with one embodiment of the present invention. Specifically, register index field 2144 includes a REX field 2205, a REX' field 2210, a MODR / M.reg field 2244, a MODR / M.r / m field 2246, a VVVV field 2220, an xxx field 2254, and a bbb field 2256.

[0248] Expansion operation field

[0249] Figure 22D FIG. is a block diagram of fields that make up expansion operation field 2150 having a special vector-friendly instruction format 2200 in accordance with one embodiment of the present invention. When the class (U) field 2168 contains 0, it indicates EVEX.U0 (class A 2168A); when it contains 1, it indicates EVEX.U1 (class B 2168B). When U = 0 and the MOD field 2242 contains 11 (indicating no memory access operation), the α field 2152 (EVEX byte 3, bit [7] – EH) is interpreted as the rs field 2152A. When the rs field 2152A contains 1 (rounding 2152A.1), the β field 2154 (EVEX byte 3, bit [6:4] – SSS) is interpreted as the rounding control field 2154A. The rounding control field 2154A includes a one-bit SAE field 2156 and a two-bit rounding operation control field 2158. When the rs field 2152A contains 0 (data transformation 2152A.2), the β field 2154 (EVEX byte 3, bit [6:4] – SSS) is interpreted as a three-bit data transformation field 2154B. When U = 0 and the MOD field 2242 contains 00, 01, or 10 (indicating a memory access operation), the α field 2152 (EVEX byte 3, bit [7] – EH) is interpreted as the eviction hint (EH) field 2152B, and the β field 2154 (EVEX byte 3, bit [6:4] – SSS) is interpreted as a three-bit data manipulation field 2154C.

[0250] When U = 1, the α field 2152 (EVEX byte 3, bit [7] – EH) is interpreted as the write mask control (Z) field 2152C. When U = 1 and the MOD field 2242 contains 11 (indicating no memory access operation), a part of the β field 2154 (EVEX byte 3, bit [4] – S 0 ) is interpreted as the RL field 2157A; when it contains 1 (rounding 2157A.1), the rest of the β field 2154 (EVEX byte 3, bit [6-5] – S 2-1) is interpreted as a rounding operation control field 2159A, and when the RL field 2157A contains 0 (VSIZE 2157.A2), the remainder of the β field 2154 (EVEX byte 3, bits [6-5] - S 2-1 ) is interpreted as a vector length field 2159B (EVEX byte 3, bits [6-5] – L 1-0 ). When U = 1 and the MOD field 2242 contains 00, 01, or 10 (indicating a memory access operation), the β field 2154 (EVEX byte 3, bits [6:4] – SSS) is interpreted as a vector length field 2159B (EVEX byte 3, bits [6-5] – L 1-0 ) and a broadcast field 2157B (EVEX byte 3, bit [4] – B).

[0251] Exemplary Register Architecture

[0252] Figure 23 is a block diagram of a register architecture 2300 according to an embodiment of the present invention. In the illustrated embodiment, there are 32 vector registers 2310 that are 512 bits wide; these registers are referred to as zmm0 through zmm31. The lower 256 bits of the lower 16 zmm registers overlay the registers ymm0 - 16. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) overlay the registers xmm0 - 15. The specialized vector-friendly instruction format 2200 operates on these overlaid register banks, as illustrated in the following table.

[0253]

[0254] In other words, the vector length field 2159B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half of the previous length, and instruction templates that do not have a vector length field 2159B operate on the maximum vector length. Additionally, in one embodiment, the class B instruction templates of the specialized vector-friendly instruction format 2200 operate on packed or scalar single / double precision floating-point data and packed or scalar integer data. A scalar operation is an operation performed on the lowest-order data element position in a zmm / ymm / xmm register; depending on the embodiment, the higher-order data element positions either remain the same as before the instruction or are zeroed.

[0255] Write Mask Register 2315 - In the illustrated embodiment, there are eight write mask registers (k0 to k7), each write mask register being 64 bits in size. In an alternative embodiment, the write mask register 2315 is 16 bits in size. As previously described, in one embodiment of the present invention, the vector mask register k0 cannot be used as a write mask; when the encoding that normally indicates k0 is used as a write mask, it selects the hard-wired write mask 0xFFFF, effectively disabling the write mask for that instruction.

[0256] General Purpose Registers 2325 - In the illustrated embodiment, there are sixteen 64-bit general purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0257] Scalar Floating-Point Stack Register File (x87 Stack) 2345, overlaid with the MMX Packed Integer Flat Register File 2350 - In the illustrated embodiment, the x87 stack is an eight-element stack for performing scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extensions; while using the MMX registers to perform operations on 64-bit packed integer data and to save operands for some operations performed between the MMX and XMM registers.

[0258] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0259] Exemplary Core Architecture, Processor, and Computer Architecture

[0260] Processor nuclear energy is implemented in different ways, for different purposes, and in different processors. For example, the implementation of such cores can include: 1) general-purpose in-order cores designed for general computing; 2) high-performance general-purpose out-of-order cores designed for general computing; 3) dedicated cores designed primarily for graphics and / or scientific (throughput) computing. The implementation of different processors can include: 1) a CPU that includes one or more general-purpose in-order cores designed for general computing and / or one or more general-purpose out-of-order cores designed for general computing; and 2) a coprocessor that includes one or more dedicated cores designed primarily for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which can include: 1) a coprocessor on a chip separate from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case, such a coprocessor is sometimes referred to as dedicated logic or as a dedicated core, such dedicated logic such as, integrated graphics and / or scientific (throughput) logic); and 4) a system-on-chip that can include the described CPU (sometimes referred to as (multiple) application cores or (multiple) application processors), the coprocessor described above, and additional functions on the same die. Exemplary core architectures are then described, followed by exemplary processor and computer architectures.

[0261] Exemplary Core Architectures

[0262] In-Order and Out-of-Order Core Block Diagrams

[0263] Figure 24A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register-renamed out-of-order issue / execution pipeline in accordance with embodiments of the present invention. Figure 24B is a block diagram showing an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary register-renamed out-of-order issue / execution architecture core in accordance with embodiments of the present invention. Figures 24A - 24B The solid block diagrams in show an in-order pipeline and an in-order core, while the optional addition of the dashed block diagrams shows a register-renamed, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0264] In Figure 24A the processor pipeline 2400 includes a fetch stage 2402, a length decoding stage 2404, a decoding stage 2406, an allocation stage 2408, a renaming stage 2410, a scheduling (also referred to as dispatch or issue) stage 2412, a register read / memory read stage 2414, an execution stage 2416, a write-back / memory write stage 2418, an exception handling stage 2422, and a commit stage 2424.

[0265] Figure 24BA processor core 2490 is shown, which includes a front-end unit 2430 that is coupled to an execution engine unit 2450, and both the front-end unit 2430 and the execution engine unit 2450 are coupled to a memory unit 2470. The core 2490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 2490 can be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and so on.

[0266] The front-end unit 2430 includes a branch prediction unit 2432 that is coupled to an instruction cache unit 2434, the instruction cache unit 2434 is coupled to an instruction translation lookaside buffer (TLB) 2436, the instruction translation lookaside buffer 2436 is coupled to an instruction fetch unit 2438, and the instruction fetch unit 2438 is coupled to a decode unit 2440. The decode unit 2440 (or decoder) can decode the instructions and generate, as output, one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, or otherwise reflect, or are derived from the original instructions. The decode unit 2440 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), and so on. In one embodiment, the core 2490 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in the decode unit 2440, or otherwise within the front-end unit 2430). The decode unit 2440 is coupled to a rename / allocator unit 2452 in the execution engine unit 2450.

[0267] The execution engine unit 2450 includes a rename / allocator unit 2452 that is coupled to a retirement unit 2454 and a collection 2456 of one or more scheduler units. The (multiple) scheduler units 2456 represent any number of different schedulers, including reservation stations, a central instruction window, and the like. The (multiple) scheduler units 2456 are coupled to the (multiple) physical register file units 2458. Each of the (multiple) physical register file units 2458 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, a status (e.g., an instruction pointer that is the address of the next instruction to be executed), and so on. In one embodiment, the (multiple) physical register file units 2458 include a vector register unit, a write mask register unit, and a scalar register unit. These register units can provide architectural vector registers, vector mask registers, and general-purpose registers. The (multiple) physical register file units 2458 are overlapped by the retirement unit 2454 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using the (multiple) reorder buffers and the (multiple) retirement register files; using the (multiple) future files, the (multiple) history buffers, the (multiple) retirement register files; using register maps and register pools, and so on). The retirement unit 2454 and the (multiple) physical register file units 2458 are coupled to the (multiple) execution clusters 2460. The (multiple) execution clusters 2460 include a collection 2462 of one or more execution units and a collection 2464 of one or more memory access units. The execution units 2462 can perform various operations (e.g., shift, add, subtract, multiply) and can operate on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). Although some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The (multiple) scheduler units 2456, the (multiple) physical register file units 2458, and the (multiple) execution clusters 2460 are shown as potentially having multiple because certain embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline that each has its own scheduler unit, (multiple) physical register file units, and / or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented where only the execution cluster of that pipeline has the (multiple) memory access units 2464). It should also be understood that in the case of using separate pipelines, one or more of these pipelines can be out-of-order issue / execution, and the remaining pipelines can be in-order.

[0268] A set of memory access units 2464 is coupled to a memory unit 2470 that includes a data TLB unit 2472, which is coupled to a data cache unit 2474 that is coupled to a second-level (L2) cache unit 2476. In one exemplary embodiment, the memory access units 2464 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 2472 in the memory unit 2470. An instruction cache unit 2434 is also coupled to the second-level (L2) cache unit 2476 in the memory unit 2470. The L2 cache unit 2476 is coupled to one or more other levels of cache and ultimately to main memory.

[0269] As an example, an exemplary register-renamed out-of-order issue / execution core architecture may implement a pipeline 2400 as follows: 1) Instruction fetch 2438 performs a fetch stage 2402 and a length decoding stage 2404; 2) A decode unit 2440 performs a decode stage 2406; 3) A rename / allocator unit 2452 performs an allocation stage 2408 and a rename stage 2410; 4) A (plurality of) scheduler units 2456 perform a schedule stage 2412; 5) A (plurality of) physical register file units 2458 and a memory unit 2470 perform a register read / memory read stage 2414; An execution cluster 2460 performs an execution stage 2416; 6) The memory unit 2470 and the (plurality of) physical register file units 2458 perform a write-back / memory write stage 2418; 7) Each unit may be involved in an exception handling stage 2422; and 8) A retirement unit 2454 and the (plurality of) physical register file units 2458 perform a commit stage 2424.

[0270] The core 2490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added with more recent versions); the MIPS instruction set of MIPS Technologies, Inc. of Sunnyvale, California; the ARM instruction set of ARM Holdings plc of Sunnyvale, California (with optional additional extensions such as NEON)), including the (plurality of) instructions described herein. In one embodiment, the core 2490 includes logic for supporting SIMD (Single Instruction, Multiple Data) instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using SIMD data.

[0271] It should be understood that the core supports multithreading (a collection of two or more parallel operations or threads), and this multithreading can be accomplished in various ways, including time-division multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads for which the physical core is simultaneously multithreading), or a combination thereof (e.g., time-division fetching and decoding and subsequent simultaneous multithreading as in simultaneous multithreading in hyperthreading technology).

[0272] Although register renaming has been described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor also include separate instruction and data cache units 2434 / 2474 and a shared L2 cache unit 2476, alternative embodiments can have a single internal cache for both instructions and data, such as, for example, a first-level (L1) internal cache or multiple levels of internal caches. In some embodiments, the system can include a combination of an internal cache and an external cache outside the core and / or the processor. Alternatively, all caches can be outside the core and / or the processor.

[0273] Specific exemplary in-order core architecture

[0274] Figures 25A - 25B A block diagram illustrating a more specific exemplary in-order core architecture, which would be one of several logic blocks in a chip (including other cores of the same type and / or different types). Depending on the application, the logic block communicates with some fixed-function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0275] Figure 25A A block diagram of a single processor core according to an embodiment of the present invention and its connection to the on-die interconnect network 2502 and a local subset 2504 of its second-level (L2) cache. In one embodiment, the instruction decoder 2500 supports the x86 instruction set with a compact data instruction set extension. The L1 cache 2506 allows low-latency access to the cache memory for data entering the scalar and vector units. Although in one embodiment (for simplicity of design), the scalar unit 2508 and the vector unit 2510 use separate register sets (scalar registers 2512 and vector registers 2514 respectively), and the data transferred between these registers is written to memory and then read back from the first-level (L1) cache 2506, alternative embodiments of the present invention can use different methods (e.g., using a single register set or including a communication path that allows data to be transferred between the two register banks without being written and read back).

[0276] The local subset 2504 of the L2 cache is part of a global L2 cache that is partitioned into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 2504 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 2504 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 2504 and flushed from other subsets as necessary. A ring network ensures data sharing consistency. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0277] Figure 25B is part of a processor core according to an embodiment of the present invention Figure 25A exploded view. Figure 25B includes part of the L1 data cache 2506A with the L1 cache 2504, and more details regarding the vector unit 2510 and vector registers 2514. Specifically, the vector unit 2510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 2528) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports mixing of register inputs through the mixing unit 2520, numerical conversion through the numerical conversion units 2522A-B, and replication of memory inputs through the replication unit 2524. The write mask register 2526 allows masking of resulting vector writes.

[0278] Figure 26 is a block diagram of a processor 2600 that may have more than one core, may have an integrated memory controller, and may have an integrated graphics device according to an embodiment of the present invention. Figure 26 The solid box in shows a processor 2600 having a single core 2602A, a system agent unit 2610, and a set of one or more bus controller units 2616, while the optional addition of the dashed box shows an alternative processor 2600 having multiple cores 2602A-N, a set of one or more integrated memory controller units 2614 in the system agent unit 2610, and dedicated logic 2608.

[0279] Accordingly, different implementations of the processor 2600 can include: 1) a CPU, where the dedicated logic 2608 is integrated graphics and / or scientific (throughput) logic (which can include one or more cores), and the cores 2602A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of both); 2) a coprocessor, where the cores 2602A-N are a large number of dedicated cores designed primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where the cores 2602A-N are a large number of general-purpose in-order cores. Thus, the processor 2600 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, and so on. The processor can be implemented on one or more chips. The processor 2600 can be part of one or more substrates, and / or can be implemented on one or more substrates using any of a variety of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0280] The memory hierarchy includes one or more levels of cache within the cores, a collection 2606 of one or more shared cache units, and external memory (not shown) coupled to a collection 2614 of integrated memory controller units. The collection 2606 of shared cache units can include one or more intermediate levels of cache, such as, a second level (L2), a third level (L3), a fourth level (L4), or other levels of cache, a last-level cache (LLC), and / or a combination of the above. Although in one embodiment, a ring-based interconnect unit 2612 interconnects the integrated graphics logic 2608, the collection 2606 of shared cache units, and the system agent unit 2610 / (multiple) integrated memory controller units 2614, alternative embodiments can use any number of well-known techniques to interconnect such units. In one embodiment, coherence is maintained between one or more cache units 2606 and the cores 2602A-N.

[0281] In some embodiments, one or more of the cores 2602A-N are capable of implementing multithreading. The system agent unit 2610 includes those components that coordinate and operate the cores 2602A-N. The system agent unit 2610 can include, for example, a power control unit (PCU) and a display unit. The PCU can be the logic and components required to regulate the power states of the cores 2602A-N and the integrated graphics logic 2608, or can include such logic and components. The display unit is used to drive one or more externally connected displays.

[0282] The cores 2602A-N may be homogeneous or heterogeneous in terms of the architectural instruction set; that is, two or more of the cores 2602A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of that instruction set or a different instruction set.

[0283] Exemplary computer architecture

[0284] Figures 27 - 28 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop devices, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can incorporate a processor and / or other execution logic as disclosed herein are generally suitable.

[0285] Now referring to Figure 27 , shown is a block diagram of a system 2700 in accordance with an embodiment of the present invention. The system 2700 may include one or more processors 2710, 2715, which are coupled to a controller hub 2720. In one embodiment, the controller hub 2720 includes a Graphics Memory Controller Hub (GMCH) 2790 and an Input / Output Hub (IOH) 2750 (which may be on separate chips); the GMCH 2790 includes a memory and graphics controller to which a memory 2740 and a coprocessor 2745 are coupled; the IOH 2750 couples input / output (I / O) devices 2760 to the GMCH 2790. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory 2740 and the coprocessor 2745 are directly coupled to the processor 2710, and the controller hub 2720 and the IOH 2750 are in a single chip.

[0286] The optionality of the additional processor 2715 is indicated by the dashed line in Figure 27 . Each processor 2710, 2715 may include one or more of the processing cores described herein and may be a certain version of the processor 2600.

[0287] The memory 2740 can be, for example, a dynamic random access memory (DRAM), a phase change memory (PCM), or a combination of both. For at least one embodiment, the controller hub 2720 communicates with the processors 2710, 2715 via a multi-branch bus such as a front side bus (FSB), a point-to-point interface such as a QuickPath Interconnect (QPI), or a similar connection 2795.

[0288] In one embodiment, the coprocessor 2745 is a specialized processor, such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like. In one embodiment, the controller hub 2720 can include an integrated graphics accelerator.

[0289] There can be various differences between the processors 2710, 2715 in terms of a series of quality metrics including architecture, microarchitecture, thermal, power consumption characteristics, and the like.

[0290] In one embodiment, the processor 2710 executes instructions that control general types of data processing operations. Coprocessor instructions can be embedded within these instructions. The processor 2710 identifies these coprocessor instructions as being of a type that should be executed by the attached coprocessor 2745. Accordingly, the processor 2710 issues these coprocessor instructions (or control signals representing coprocessor instructions) to the coprocessor 2745 on a coprocessor bus or other interconnect. The coprocessor(s) 2745 receive and execute the received coprocessor instructions.

[0291] Now referring to Figure 28 , shown is a block diagram of an SoC 2800 in accordance with an embodiment of the present invention. Figure 26 Similar elements in [the figure] use similar reference numerals. Additionally, the dashed boxes are optional features on more advanced SoCs. In Figure 28 , the interconnect unit(s) 2802 are coupled to: an application processor 2810, which includes a set of one or more cores 202A-N and a shared cache unit(s) 2606; a system agent unit 2610; bus controller unit(s) 2616; integrated memory controller unit(s) 2614; a set of one or more coprocessors 2820, which can include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 2830; a direct memory access (DMA) unit 2832; and a display unit 2840 for coupling to one or more external displays. In one embodiment, the coprocessor(s) 2820 include specialized processors such as, for example, a network or communication processor, a compression engine, a GPGPU, a high throughput MIC processor, or an embedded processor, and the like.

[0292] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the invention may be implemented as a computer program or program code executing on a programmable system that includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0293] The program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0294] The program code may be implemented in a high-level procedural programming language or an object-oriented programming language in order to communicate with the processing system. If desired, the program code may also be implemented in assembly language or machine language. In fact, the mechanisms described herein are not limited to any specific programming language scope. In any case, the language may be a compiled language or an interpreted language.

[0295] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represent various logic in a processor, which instructions, when read by the machine, cause the machine to fabricate logic for performing the techniques described herein. Such representations, referred to as “IP cores,” may be stored on a tangible machine-readable medium and supplied to various customers or manufacturing facilities to be loaded into the manufacturing machines that actually fabricate the logic or processor.

[0296] Such machine-readable storage media may include, but are not limited to, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, which include storage media such as a hard disk; any other type of disk, including floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disk (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); phase change memory (PCM); magnetic or optical cards; or any other type of medium suitable for storing electronic instructions.

[0297] Accordingly, embodiments of the present invention also include non-transitory, tangible machine-readable media that contain instructions or contain design data, such as a hardware description language (HDL), that define the structures, circuits, devices, processors, and / or system features described herein. These embodiments are also referred to as program products.

[0298] Emulation (including binary translation, code morphing, etc.)

[0299] In some cases, an instruction converter can be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter can transform (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction or instructions into one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on the processor, off the processor, or partly on the processor and partly off the processor.

[0300] Figure 29 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Figure 29 shows that a program in the form of a high-level language 2902 can be compiled using an x86 compiler 2904 to generate x86 binary code 2906 that can be natively executed by a processor 2916 having at least one x86 instruction set core. A processor 2916 having at least one x86 instruction set core represents any processor that performs substantially the same functions as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise processing: 1) a substantial portion of the instruction set of the Intel x86 instruction set core, or 2) a target code version of an application or other software targeted to run on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. An x86 compiler 2904 represents a compiler operable to generate x86 binary code 2906 (e.g., target code) that can be executed on a processor 2916 having at least one x86 instruction set core with or without additional linking. Similarly, Figure 29It is shown that an alternative instruction set compiler 2908 can be used to compile a program in the form of a high-level language 2902 to generate alternative instruction set binary code 2910 that can be natively executed by a processor 2914 that does not have at least one x86 instruction set core (e.g., a processor having a core that executes the MIPS instruction set of MIPS Technologies, Inc. of Sunnyvale, California, and / or the ARM instruction set of ARM Holdings plc of Sunnyvale, California). An instruction converter 2912 is used to convert x86 binary code 2906 into code that can be natively executed by a processor 2914 that does not have an x86 instruction set core. This converted code is not likely to be the same as the alternative instruction set binary code 2910 because it is difficult to manufacture an instruction converter that can do so; however, the converted code will perform general operations and consists of instructions from an alternative instruction set. Thus, the instruction converter 2912 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute x86 binary code 2906 through emulation, simulation, or any other process.

[0301] The following sentences and / or examples relate to further embodiments.

[0302] In Example 1, a processor for modifying an operating frequency, the processor comprising: a plurality of processing engines; at least one performance counter for determining at least one interrupt rate metric of a first processing engine; and a power control circuit. The power control circuit is configured to: use the at least one performance counter to determine whether the at least one interrupt rate metric has reached a first threshold when the first processing engine is operating at a first frequency level; and in response to a determination that the at least one interrupt rate metric has reached the first threshold when the first processing engine is operating at the first frequency level, increase the operating frequency of the first processing engine from the first frequency level to a second frequency level.

[0303] In Example 2, the subject matter of Example 1 may optionally include: the power control circuit is configured to: detect an indication of a decrease in the operating frequency of the first processing engine; use the at least one performance counter to determine whether the at least one interrupt rate metric has reached the first threshold when the first processing engine is operating at the maximum frequency level of the first processing engine; and in response to a determination that the at least one interrupt rate metric has reached the first threshold when the first processing engine is operating at the maximum frequency level, prevent a decrease in the operating frequency of the first processing engine from the maximum frequency level.

[0304] In Example 3, the subject matter of Examples 1-2 may optionally include: the power control circuit is configured to: in response to a determination that the at least one interrupt rate metric has not reached the first threshold when the first processing engine is operating at the first frequency level, cause the first processing engine to continue to operate at the first frequency level.

[0305] In Example 4, the subject matter as described in Examples 1 - 3 may optionally include: at least one performance counter including at least one hardware counter of a processor.

[0306] In Example 5, the subject matter as described in Examples 1 - 4 may optionally include: at least one interrupt rate metric including a first interrupt metric based on a proportion of processing load for handling masked interrupts, wherein the first interrupt metric is associated with a first threshold.

[0307] In Example 6, the subject matter as described in Examples 1 - 5 may optionally include: at least one interrupt rate metric further including a second interrupt metric based on a proportion of processing load for handling masked and unmasked interrupts, wherein the second interrupt metric is associated with a second threshold.

[0308] In Example 7, the subject matter as described in Examples 1 - 6 may optionally include at least one register for storing values of the first threshold and the second threshold.

[0309] In Example 8, the subject matter as described in Examples 1 - 7 may optionally include: a power control circuit is a power control unit of a processor, wherein the power control unit and a first processing engine are separate components of the processor.

[0310] In Example 9, a method for modifying an operating frequency includes: adjusting a hardware counter to determine an interrupt rate metric of a processor, wherein the interrupt rate metric is at least one selected from a proportion of processing cycles for handling masked interrupts and a proportion of processing cycles for handling both masked and unmasked interrupts; determining, based on the hardware counter, whether the interrupt rate metric has reached a threshold when the processor is operating at a first frequency level; and in response to a determination that the interrupt rate metric has reached the threshold when the processing engine is operating at the first frequency level, increasing the operating frequency of the processor from the first frequency level to a second frequency level.

[0311] In Example 10, the subject matter as described in Example 9 may optionally include: detecting an indication of a decrease in the operating frequency of the processor; determining, based on the hardware counter, whether the interrupt rate metric has reached a threshold when the processor is operating at a maximum frequency level of the processor; and in response to a determination that at least one interrupt rate metric has reached the threshold when the processor is operating at the maximum frequency level, preventing a decrease in the operating frequency of the processor from the maximum frequency level.

[0312] In Example 11, the subject matter as described in Examples 9 - 10 may optionally include: in response to a determination that the interrupt rate metric has not reached the threshold when the processor is operating at a first frequency level, maintaining the processor at the first frequency level.

[0313] In Example 12, the subject matter as described in Examples 9-11 may optionally include: a hardware counter for counting masked interrupts that occur during a sliding time window, and an interrupt rate metric based on a proportion of processing load for handling the masked interrupts.

[0314] In Example 13, the subject matter as described in Examples 9-12 may optionally include: a hardware counter for counting masked and unmasked interrupts that occur during a sliding time window, and an interrupt rate metric based on a proportion of processing load for handling the masked and unmasked interrupts.

[0315] In Example 14, the subject matter as described in Examples 9-13 may optionally include: the hardware counter is at least one selected from a total interrupt counter and a masked interrupt counter of a processor.

[0316] In Example 15, a computing device for modifying an operating frequency includes: one or more processors; and a memory having multiple instructions stored therein, which when executed by the one or more processors cause the computing device to perform the method as described in any one of claims 9 to 14.

[0317] In Example 16, at least one machine-readable medium has data stored thereon, which if used by at least one machine causes the at least one machine to perform the method as described in any one of claims 9 to 14.

[0318] In Example 17, an electronic device for modifying an operating frequency includes means for performing the method as described in any one of claims 9 to 14.

[0319] In Example 18, a system for modifying an operating frequency includes an external memory coupled to a processor. The processor includes a plurality of processing engines, at least one performance counter, and a power control unit. The power control unit is configured to: use the at least one performance counter to determine whether at least one interrupt rate metric has reached a first threshold when a first processing engine is operating at a first frequency level; determine whether the first frequency level is a maximum frequency level of the first processing engine; and in response to a determination that the at least one interrupt rate metric has reached the first threshold when the first processing engine is not operating at the maximum frequency level, increase the operating frequency of the first processing engine to a second frequency level.

[0320] In Example 19, the subject matter as described in Example 18 may optionally include: the power control unit is configured to: in response to a determination that at least one interrupt rate metric has reached the first threshold when the first processing engine is operating at the maximum frequency level, maintain the processor at the maximum frequency level.

[0321] In Example 20, the subject matter as described in Examples 18 - 19 may optionally include: a power control unit for: detecting an indication of a reduction in the operating frequency of a first processing engine from a maximum frequency level; and preventing a reduction in the operating frequency of the first processing engine from that maximum frequency level when at least one interrupt rate metric is equal to or greater than a first threshold.

[0322] In Example 21, the subject matter as described in Examples 18 - 20 may optionally include: at least one performance counter including a hardware counter for counting only masked interrupts handled by a first processing engine.

[0323] In Example 22, the subject matter as described in Examples 18 - 21 may optionally include: at least one performance counter including a hardware counter for counting both masked and unmasked interrupts handled by a first processing engine.

[0324] In Example 23, the subject matter as described in Examples 18 - 22 may optionally include: at least one performance counter including: a first hardware counter for determining a first interrupt metric based on a proportion of a processing load for handling only masked interrupts, wherein the first interrupt metric is associated with a first threshold; and a second hardware counter for determining a second interrupt metric based on a proportion of a processing load for handling both masked and unmasked interrupts, wherein the second interrupt metric is associated with a second threshold.

[0325] In Example 24, an apparatus for modifying an operating frequency includes: means for adjusting a hardware counter to determine an interrupt rate metric of a processor, wherein the interrupt rate metric is at least one selected from a proportion of processing cycles for handling masked interrupts and a proportion of processing cycles for handling both masked and unmasked interrupts; means for determining, based on the hardware counter, whether the interrupt rate metric has reached a threshold when the processor is operating at a first frequency level; and means for increasing the operating frequency of the processor from the first frequency level to a second frequency level in response to a determination that the interrupt rate metric has reached the threshold when the processing engine is operating at the first frequency level.

[0326] In Example 25, the subject matter as described in Example 24 may optionally include: means for detecting an indication of a reduction in the operating frequency of the processor; means for determining, based on the hardware counter, whether the interrupt rate metric has reached a threshold when the processor is operating at a maximum frequency level of the processor; and means for preventing a reduction in the operating frequency of the processor from that maximum frequency level in response to a determination that at least one interrupt rate metric has reached the threshold when the processor is operating at the maximum frequency level.

[0327] In Example 26, the subject matter as described in Examples 24 - 25 may optionally include: means for maintaining the processor at a first frequency level in response to a determination that an interrupt rate metric has not reached a threshold while the processor is operating at a first frequency level.

[0328] In Example 27, the subject matter as described in Examples 24 - 26 may optionally include: a hardware counter for counting masked interrupts that occur during a sliding time window, and an interrupt rate metric based on a proportion of a processing load for handling the masked interrupts.

[0329] In Example 28, the subject matter as described in Examples 24 - 27 may optionally include: a hardware counter for counting masked and unmasked interrupts that occur during a sliding time window, and an interrupt rate metric based on a proportion of a processing load for handling the masked and unmasked interrupts.

[0330] In Example 29, the subject matter as described in Examples 24 - 28 may optionally include: the hardware counter is at least one selected from a total interrupt counter and a masked interrupt counter of the processor.

[0331] While some embodiments are described with reference to specific integrated circuits, such as those in a computing platform or a processor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein can be applied to other types of circuits or semiconductor devices. For example, the disclosed embodiments are not limited to any particular type of computer system. That is, the disclosed embodiments can be used in many different system types, including server computers (e.g., tower, rack, blade, microserver, etc.), communication systems, storage systems, desktop computers of any configuration, laptop computers, notebooks, and tablet computers (including 2:1 tablets, phablets, etc.), and the disclosed embodiments can also be used in other devices, such as handheld devices, system-on-chips (SoC), and embedded applications. Some examples of handheld devices include: cellular phones such as smart phones, Internet Protocol devices, digital cameras, personal digital assistants (PDA), and handheld PCs. Embedded applications typically can include: microcontrollers, digital signal processors (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system capable of performing the functions and operations taught herein. Additionally, embodiments can be implemented in mobile terminals with standard voice capabilities, such as mobile phones, smart phones, and tablet phones, and / or in non-mobile terminals without standard wireless voice communication capabilities, such as many wearable devices, tablets, notebooks, desktops, microservers, servers, etc. Further, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but can also relate to software implementations.

[0332] Embodiments can be implemented in code and can be stored on a non-transitory storage medium having instructions stored thereon that can be used to program a system to perform the instructions. Embodiments can also be implemented in data and can be stored on a non-transitory storage medium that, if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. The storage medium can include, but is not limited to: any type of disk, including floppy disks, optical disks, solid state drives (SSD), compact disk read only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks; semiconductor devices, such as read only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM), erasable programmable read only memory (EPROM), flash memory, electrically erasable programmable read only memory (EEPROM); magnetic or optical cards; or any other type of medium suitable for storing electronic instructions.

[0333] It is contemplated that various combinations of the above examples are possible. The embodiments can be used in many different types of systems. For example, in one embodiment, a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices, and conversely, other embodiments can relate to other types of devices for processing instructions, or one or more machine-readable media that include instructions that, in response to execution of these instructions on a computing device, cause the device to implement one or more of the methods and techniques described herein.

[0334] References in the specification to "one embodiment", "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation covered by the present invention. Thus, the appearances of the phrase "one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Additionally, the particular features, structures, or characteristics may be established in other suitable forms different from the particular embodiments illustrated, and all such forms may be covered within the claims of this application. As used herein, "in response to" refers to a direct causal relationship.

[0335] Although the present invention has been described with reference to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. The appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the present invention.

Claims

1. A processor for modifying an operating frequency, comprising: a plurality of processing engines; at least one performance counter for determining a plurality of interrupt rate metrics for a first processing engine, wherein a first interrupt metric of the plurality of interrupt rate metrics is based on a proportion of processing load for handling masked interrupts, and wherein a second interrupt metric of the plurality of interrupt rate metrics is based on a proportion of processing load for handling masked and unmasked interrupts; and a power control circuit configured to: use the at least one performance counter to determine whether at least one of the plurality of interrupt rate metrics has reached a first threshold while the first processing engine is operating at a first frequency level; and in response to a determination that at least one of the plurality of interrupt rate metrics has reached the first threshold while the first processing engine is operating at the first frequency level, increase the operating frequency of the first processing engine from the first frequency level to a second frequency level.

2. The processor according to claim 1, wherein the power control circuit is configured to: detect an indication of a decrease in the operating frequency of the first processing engine; use the at least one performance counter to determine whether at least one of the plurality of interrupt rate metrics has reached the first threshold while the first processing engine is operating at a maximum frequency level of the first processing engine; and in response to a determination that at least one of the plurality of interrupt rate metrics has reached the first threshold while the first processing engine is operating at the maximum frequency level, prevent a decrease in the operating frequency of the first processing engine from the maximum frequency level.

3. The processor according to claim 1, wherein the power control circuit is configured to: in response to a determination that at least one of the plurality of interrupt rate metrics has not reached the first threshold while the first processing engine is operating at the first frequency level, keep the first processing engine at the first frequency level.

4. The processor according to claim 1, wherein, the at least one performance counter includes at least one hardware counter of the processor.

5. The processor according to claim 1, wherein, the at least one interrupt rate metric is the first interrupt metric, and wherein the first interrupt metric is associated with the first threshold.

6. The processor according to claim 5, wherein, the second interrupt metric is associated with a second threshold.

7. The processor according to claim 6, further comprising at least one register for storing values of the first threshold and the second threshold.

8. The processor according to claim 1, wherein, the power control circuit is a power control unit of the processor, and wherein the power control unit and the first processing engine are separate components of the processor.

9. A method for modifying an operating frequency, comprising: Adjust at least one hardware counter to determine multiple interrupt rate metrics of a processor, wherein the at least one hardware counter is included in the processor, wherein a first interrupt metric among the multiple interrupt rate metrics is based on a proportion of processing cycles for handling masked interrupts, and wherein a second interrupt metric among the multiple interrupt rate metrics is based on a proportion of processing cycles for handling both masked interrupts and unmasked interrupts; Based on the at least one hardware counter, determine whether at least one of the multiple interrupt rate metrics has reached a first threshold when the processor is operating at a first frequency level; and In response to a determination that at least one of the interrupt rate metrics has reached the first threshold when the processor is operating at the first frequency level, increase the operating frequency of the processor from the first frequency level to a second frequency level.

10. The method according to claim 9, further comprising: Detect an indication of a decrease in the operating frequency of the processor; Based on the at least one hardware counter, determine whether at least one of the interrupt rate metrics has reached the first threshold when the processor is operating at the maximum frequency level of the processor; and In response to a determination that at least one of the interrupt rate metrics has reached the first threshold when the processor is operating at the maximum frequency level, prevent a decrease in the operating frequency of the processor from the maximum frequency level.

11. The method according to claim 9, further comprising: In response to a determination that at least one of the interrupt rate metrics has not reached the first threshold when the processor is operating at the first frequency level, maintain the processor at the first frequency level.

12. The method according to claim 9, wherein, The at least one hardware counter includes a first counter for counting masked interrupts that occur during a sliding time window.

13. The method according to claim 12, wherein, The at least one hardware counter includes a second counter for counting masked interrupts and unmasked interrupts that occur during the sliding time window.

14. The method according to claim 9, wherein, The at least one hardware counter includes the total interrupt counter and the masked interrupt counter of the processor.

15. A computing device for modifying an operating frequency, comprising: One or more processors; and A memory having multiple instructions stored therein, which when executed by the one or more processors, cause the computing device to perform the method according to any one of claims 9 to 14.

16. At least one machine-readable medium having data stored thereon, which if used by at least one machine causes the at least one machine to perform the method according to any one of claims 9 to 14.

17. An electronic device for modifying an operating frequency, comprising means for performing the method according to any one of claims 9 to 14.

18. A system for modifying an operating frequency, comprising: A processor, comprising a plurality of processing engines, at least one performance counter, and a power control unit, wherein the at least one performance counter is configured to determine a plurality of interrupt rate metrics for a first processing engine, wherein a first interrupt metric among the plurality of interrupt rate metrics is based on a proportion of processing load for handling masked interrupts, and wherein a second interrupt metric among the plurality of interrupt rate metrics is based on a proportion of processing load for handling masked and unmasked interrupts, and the power control unit is configured to: Use the at least one performance counter to determine whether at least one of the plurality of interrupt rate metrics has reached a first threshold when the first processing engine is operating at a first frequency level; Determine whether the first frequency level is the maximum frequency level of the first processing engine; and In response to a determination that at least one of the plurality of interrupt rate metrics has reached the first threshold when the first processing engine is not operating at the maximum frequency level, increase the operating frequency of the first processing engine to a second frequency level; and An external memory coupled to the processor.

19. The system according to claim 18, wherein the power control unit is configured to: In response to a determination that at least one of the plurality of interrupt rate metrics has reached the first threshold when the first processing engine is operating at the maximum frequency level, maintain the processor at the maximum frequency level.

20. The system according to claim 18, wherein the power control unit is configured to: Detect an indication of a decrease in the operating frequency of the first processing engine from the maximum frequency level; and Prevent a decrease in the operating frequency of the first processing engine from the maximum frequency level when the at least one interrupt rate metric is equal to or greater than the first threshold.

21. The system according to claim 18, wherein, The at least one performance counter includes a hardware counter for counting only masked interrupts handled by the first processing engine.

22. The system according to claim 18, wherein, The at least one performance counter includes a hardware counter for counting both masked and unmasked interrupts handled by the first processing engine.

23. The system according to claim 18, wherein, The at least one performance counter includes: A first hardware counter for determining the first interrupt metric, wherein the first interrupt metric is associated with the first threshold; and A second hardware counter for determining the second interrupt metric, wherein the second interrupt metric is associated with a second threshold.

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