Pixel circuit

Abstract

A pixel circuit is provided, which includes: an organic light emitting diode (OLED); a first transistor having a first electrode, a second electrode and a first gate electrode; a second transistor connected between a data line and the first electrode and controlled by a first scan line; a third transistor connected between the second electrode of the first transistor and the first gate electrode and controlled by the first scan line; a fourth transistor connected between the first gate electrode and a first initialization voltage line and controlled by a second scan line; a fifth transistor connected between a power line and the first electrode and controlled by a first emission line; a sixth transistor connected between the second electrode and the OLED and controlled by a second emission line; and a storage capacitor connected between the first gate electrode and the power line, wherein the first emission line and the second emission line are located at different nodes.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0098582, filed on August 23, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention generally relate to a pixel circuit. Background Art

[0003] As information technology develops, the importance of display devices as a connection medium between users and information has increased. Therefore, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly being used.

[0004] The organic light emitting display device displays an image using an organic light emitting diode that generates light through recombination of electrons and holes. The organic light emitting display device has a high response speed and is driven with low power consumption.

[0005] Recently, research has been conducted to solve the hysteresis problem and the step efficiency problem by allowing a driving transistor of a pixel circuit for driving an organic light emitting diode to be pre-biased.

[0006] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0007] A device constructed according to an exemplary embodiment of the invention provides a pixel circuit capable of preventing or reducing the occurrence of undesired emission and overcurrent and reducing power consumption by causing a driving transistor to be on-biased.

[0008] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0009] According to one or more exemplary embodiments of the invention, a pixel circuit includes: an organic light emitting diode; a first transistor including a source electrode, a drain electrode and a gate electrode; a second transistor having a source electrode connected to a data line, a drain electrode connected to the source electrode of the first transistor and a gate electrode connected to a first scan line; a third transistor having a source electrode connected to the drain electrode of the first transistor, a drain electrode connected to the gate electrode of the first transistor and a gate electrode connected to the first scan line; a fourth transistor having a source electrode connected to the gate electrode of the first transistor, a drain electrode connected to the first initialization voltage line and a gate electrode connected to the second scan line; a fifth transistor having a source electrode connected to the first power voltage line, a drain electrode connected to the source electrode of the first transistor and a gate electrode connected to the first emission line; a sixth transistor having a source electrode connected to the drain electrode of the first transistor, a drain electrode connected to the anode electrode of the organic light emitting diode and a gate electrode connected to the second emission line; and a storage capacitor having a first electrode connected to the gate electrode of the first transistor and a second electrode connected to the first power voltage line, wherein the first emission line and the second emission line are located at different nodes.

[0010] The first transmission line and the second transmission line may be configured to transmit a first transmission signal and a second transmission signal, respectively, and the first transmission signal may have a phase delayed compared to a phase of the second transmission signal.

[0011] The first scan line and the second scan line may be located at different nodes.

[0012] The first scan line and the second scan line may be configured to transmit a first scan signal and a second scan signal, respectively, and the first scan signal may have a phase delayed compared to a phase of the second scan signal.

[0013] The on-level pulse of the first scan signal may partially overlap the off-level pulse of the first emission signal.

[0014] The on-level pulse of the second scan signal may partially overlap the off-level pulse of the second emission signal.

[0015] Generation of an on-level pulse of the second scan signal may overlap with the first emission signal having an on-level.

[0016] The on-level pulse of the second scan signal may overlap a transition time portion of the off-level pulse of the first emission signal.

[0017] The pixel circuit may further include a seventh transistor having a source electrode connected to the anode electrode of the organic light emitting diode, a drain electrode connected to the second initialization voltage line, and a gate electrode connected to the third scan line.

[0018] The on-level pulse of the third scan signal applied to the third scan line may partially overlap with a transition time of the off-level pulse of the second emission signal applied to the second emission line.

[0019] The pixel circuit may further include: a first gate insulating layer covering source electrodes, drain electrodes, and channels of the first to seventh transistors. Gate electrodes of the first to seventh transistors, the first to third scan lines, the first and second emission lines, the first and second initialization voltage lines, and one electrode of the storage capacitor may be located on the first gate insulating layer.

[0020] The pixel circuit may further include: a second gate insulating layer covering the first gate insulating layer, gate electrodes of the first to seventh transistors, the first to third scan lines, the first emission line and the second emission line, the first initialization voltage line and the second initialization voltage line, and one electrode of the storage capacitor. The other electrode of the storage capacitor may be located on the second gate insulating layer.

[0021] The pixel circuit may further include: an interlayer insulating layer covering the second gate insulating layer and another electrode of the storage capacitor; and a first contact electrode located on the interlayer insulating layer, the first contact electrode being connected to the source electrode of the seventh transistor. The data line and the first power voltage line may be located on the interlayer insulating layer.

[0022] The pixel circuit may further include: a through hole layer covering the interlayer insulating layer, the first contact electrode, the data line and the first power voltage line. The anode electrode of the organic light emitting diode may be located on the through hole layer and connected to the source electrode of the seventh transistor through the first contact electrode.

[0023] The third scan line, the second emission line, the second initialization voltage line, the first scan line, the second scan line, the first emission line, and the first initialization voltage line may be sequentially located on the same layer in the first direction.

[0024] The second initialization voltage line may vertically overlap a point at which the source electrode of the sixth transistor and the drain electrode of the first transistor contact each other.

[0025] The second initialization voltage line may vertically overlap a point at which the source electrode of the sixth transistor and the drain electrode of the third transistor contact each other.

[0026] The second initialization voltage line may be connected to a drain electrode of a fourth transistor of a previous stage pixel circuit.

[0027] The third scan line may be connected to a gate electrode of a fourth transistor of a previous stage pixel circuit.

[0028] The first initialization voltage line may be connected to a drain electrode of a seventh transistor of a next stage pixel circuit.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept, wherein the accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0031] Figure 1 is a diagram illustrating a display device according to an exemplary embodiment.

[0032] Figure 2 , Figure 3 and Figure 4 is a diagram showing a pixel circuit and a driving method thereof according to the prior art.

[0033] Figure 5 is a diagram illustrating a pixel circuit according to an exemplary embodiment.

[0034] Figure 6 is a diagram illustrating a driving method of a pixel circuit according to an exemplary embodiment.

[0035] Figure 7 is a diagram illustrating a driving method of a pixel circuit according to another exemplary embodiment.

[0036] Figure 8 , Fig. 9 and Fig.10 is a diagram showing an exemplary layout of a pixel circuit according to an exemplary embodiment.

[0037] Fig.11 is a diagram illustrating a pixel circuit according to another exemplary embodiment. DETAILED DESCRIPTION

[0038] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words for non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, in order to avoid unnecessarily obscuring various exemplary embodiments, known structures and devices are shown in block diagram form. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, construction, and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0039] Unless otherwise specified, the exemplary embodiments shown will be understood as exemplary features that provide details of variations of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0040] Cross-hatching and / or shading are generally provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not express or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the element. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two continuously described processes can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0041] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bonded to" another element or layer, the element or layer may be directly on, directly connected to or directly bonded to the other element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or layer. For this reason, the term "connected" may represent a physical connection, an electrical connection, and / or a fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system such as an x-axis, a y-axis, and a z-axis, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be named as the second element.

[0043] Spatially relative terms such as "under," "beneath," "below," "below," "above," "upper," "on," "higher," "side" (e.g., as in "sidewall"), and the like may be used herein for descriptive purposes to describe the relationship of one element to another element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements or features described as being "under" or "beneath" other elements or features would subsequently be located "above" the other elements or features. Thus, the exemplary term "under" may include both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0044] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "a kind of" and "the (said)" are also intended to include plural forms. In addition, when the terms "include" and / or "comprise" are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than degree terms, and as such, are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0045] As is customary in the art, some exemplary embodiments are described and shown in the accompanying drawings according to functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., such as logic circuits, which can be formed using semiconductor-type manufacturing technology or other manufacturing technology. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by hardware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. In addition, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0047] Figure 1 is a diagram illustrating a display device 10 according to an exemplary embodiment.

[0048] Reference Figure 1 The display device 10 may include a timing controller 11 , a data driver 12 , a scan driver 13 , an emission driver 14 and a pixel unit 15 .

[0049] The timing controller 11 may provide the grayscale value and the control signal to the data driver 12 to be suitable for the specifications of the data driver 12. In addition, the timing controller 11 may provide the clock signal, the scan start signal, etc. to the scan driver 13 to be suitable for the specifications of the scan driver 13. In addition, the timing controller 11 may provide the clock signal, the emission stop signal, etc. to the emission driver 14 to be suitable for the specifications of the emission driver 14.

[0050] The data driver 12 may generate data voltages using the grayscale values ​​and control signals received from the timing controller 11 to provide to the data lines D1, D2, D3, ..., and Dn. For example, the data driver 12 may sample grayscale values ​​using a clock signal, and may apply data voltages corresponding to the grayscale values ​​to the data lines D1 to Dn in units of pixel rows. Here, n may be a natural number.

[0051] The scan driver 13 can generate a scan signal by receiving a clock signal, a scan start signal, etc. from the timing controller 11 to provide the scan lines S1, S2, S3, ..., and Sm. For example, the scan driver 13 can sequentially provide a scan signal having a conduction level pulse to the scan lines S1 to Sm. For example, the scan driver 13 can be constructed in the form of a shift register, and can generate a scan signal in the following manner: the scan start signal provided in the form of a conduction level pulse is sequentially transmitted to the next level circuit under the control of the clock signal. Here, m can be a natural number.

[0052] The emission driver 14 may generate an emission signal by receiving a clock signal, an emission stop signal, etc. from the timing controller 11 to provide the emission lines E1, E2, E3, ..., and Eo. For example, the emission driver 14 may sequentially provide an emission signal having a cut-off level pulse to the emission lines E1, E2, E3, ..., and Eo. For example, the emission driver 14 may be constructed in the form of a shift register, and may generate an emission signal in the following manner: the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal. Here, o may be a natural number.

[0053] The pixel unit 15 includes a plurality of pixel circuits. Each pixel circuit PXij can be connected to a corresponding data line, a corresponding scan line, and a corresponding emission line. Figure 5 The construction and driving method of the pixel circuit PXij are described in detail. Here, i and j may be natural numbers. The pixel circuit PXij may refer to a pixel circuit in which a scanning transistor is connected to an i-th scanning line and to a j-th data line.

[0054] In an exemplary embodiment, the timing controller 11, the data driver 12, the scan driver 13, the emission driver 14 and / or one or more components thereof may be implemented by one or more general components and / or dedicated components such as one or more discrete circuits, digital signal processing chips, integrated circuits, application-specific integrated circuits, microprocessors, processors, programmable arrays, field programmable arrays, instruction set processors, etc.

[0055] According to one or more exemplary embodiments, the features, functions, processes, etc. described herein may be implemented by software, hardware (e.g., a general purpose processor, a digital signal processing (DSP) chip, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc.), firmware, or a combination thereof. In this manner, the timing controller 11, the data driver 12, the scan driver 13, the emission driver 14, and / or one or more of their components may include one or more memories (not shown) or be otherwise associated with one or more memories (not shown), the one or more memories including codes (e.g., instructions) configured to cause the timing controller 11, the data driver 12, the scan driver 13, the emission driver 14, and / or one or more of their components to perform one or more of the features, functions, processes, etc. described herein.

[0056] The memory may be any medium that participates in providing code to one or more software, hardware, and / or firmware components for execution. Such memory may be implemented in any suitable form including, but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks. Volatile media include dynamic memory. Transmission media include coaxial cables, copper wires, and optical fibers. Transmission media may also take the form of acoustic, optical, or electromagnetic waves. Common forms of computer readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, any other magnetic media, compact disk-read only memory (CD-ROM), compact disk-rewritable (CD-RW), digital video disk (DVD), DVD-rewritable (DVD-RW), any other optical media, punch cards, paper tape, optical mark sheets, any other physical medium with patterns of holes or other optically identifiable markings, random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), FLASH-EPROM, any other memory chip or cartridge, carrier wave, or any other medium from which information can be read by, for example, a controller / processor.

[0057] Figure 2 , Figure 3 and Figure 4 is a diagram showing a pixel circuit PXij_r and a driving method thereof according to the prior art.

[0058] Reference Figure 2 , the pixel circuit PXij_r includes first to seventh transistors M1_r, M2_r, M3_r, M4_r, M5_r, M6_r, and M7_r, a storage capacitor Cst_r, and an organic light emitting diode OLED_r.

[0059] The first transistor M1_r may include a source electrode, a drain electrode, and a gate electrode. The first transistor M1_r may be referred to as a driving transistor.

[0060] A source electrode of the second transistor M2_r may be connected to the data line Dj, a drain electrode of the second transistor M2_r may be connected to the source electrode of the first transistor M1_r, and a gate electrode of the second transistor M2_r may be connected to the scan line Si. The second transistor M2_r may be referred to as a scan transistor or a switch transistor.

[0061] A source electrode of the third transistor M3_r may be connected to the drain electrode of the first transistor M1_r, a drain electrode of the third transistor M3_r may be connected to the gate electrode of the first transistor M1_r, and a gate electrode of the third transistor M3_r may be connected to the scan line Si.

[0062] A source electrode of the fourth transistor M4_r may be connected to the gate electrode of the first transistor M1_r, a drain electrode of the fourth transistor M4_r may be connected to the initialization voltage line VINT, and a gate electrode of the fourth transistor M4_r may be connected to the previous stage scan line S(i-1).

[0063] A source electrode of the fifth transistor M5_r may be connected to the first power voltage line ELVDD, a drain electrode of the fifth transistor M5_r may be connected to the source electrode of the first transistor M1_r, and a gate electrode of the fifth transistor M5_r may be connected to the emission line Ei.

[0064] A source electrode of the sixth transistor M6_r may be connected to the drain electrode of the first transistor M1_r, a drain electrode of the sixth transistor M6_r may be connected to the anode electrode of the organic light emitting diode OLED_r, and a gate electrode of the sixth transistor M6_r may be connected to the emission line Ei.

[0065] A source electrode of the seventh transistor M7_r may be connected to the anode electrode of the organic light emitting diode OLED_r, a drain electrode of the seventh transistor M7_r may be connected to the initialization voltage line VINT, and a gate electrode of the seventh transistor M7_r may be connected to the previous stage scan line S(i-1).

[0066] One electrode of the storage capacitor Cst_r may be connected to the gate electrode of the first transistor M1_r, and the other electrode of the storage capacitor Cst_r may be connected to the first power voltage line ELVDD.

[0067] An anode electrode of the organic light emitting diode OLED_r may be connected to the source electrode of the seventh transistor M7_r, and a cathode electrode of the organic light emitting diode OLED_r may be connected to the second power voltage line ELVSS.

[0068] First, we will describe the use Figure 3 The driving method drives the pixel circuit PXij_r.

[0069] Reference Figure 3 , the emission signal Eir is applied to the emission line Ei, the previous stage scanning signal S(i-1)r is applied to the previous stage scanning line S(i-1), and the scanning signal Sir is applied to the scanning line Si.

[0070] During the period t1r to t2r, the emission signal Eir is at the on level, and the previous stage scanning signal S(i-1)r becomes the on level. Because the first to seventh transistors M1_r, M2_r, M3_r, M4_r, M5_r, M6_r and M7_r of the pixel circuit PXij_r are P-type transistors, the on level can be a low level voltage, and the off level can be a high level voltage.

[0071] Therefore, transistors M4_r, M5_r, M6_r and M7_r are in a conducting state. In addition, the gate electrode of the first transistor M1_r is connected to the initialization voltage line VINT through the fourth transistor M4_r, so the first transistor M1_r is also in a conducting state. For example, the voltage level of the initialization voltage applied to the initialization voltage line VINT may be equal to or less than the voltage level of the second power voltage applied to the second power voltage line ELVSS. The voltage level of the first power voltage applied to the first power voltage line ELVDD may be higher than the voltage level of the second power voltage.

[0072] Therefore, the source electrode of the first transistor M1_r is connected to the first power voltage line ELVDD through the fifth transistor M5_r, and the gate electrode of the first transistor M1_r is connected to the initialization voltage line VINT through the fourth transistor M4_r. Therefore, during the period t1r to t2r, the first transistor M1_r to which the high gate-source voltage is applied is in a conductive bias state.

[0073] When the first transistor M1_r is in the on bias state, the data voltage of the current frame subsequently input is always less than the on bias voltage. Therefore, the data voltage of the current frame has nothing to do with the data voltage of the previous frame. Therefore, the hysteresis problem and the step efficiency problem can be solved.

[0074] The hysteresis problem refers to a problem in which a curve of a gate-source voltage and a source-drain current of a transistor when a data voltage of a current frame is higher than a data voltage of a previous frame is different from a curve of a gate-source voltage and a source-drain current of a transistor when a data voltage of a current frame is lower than a data voltage of a previous frame. The step efficiency problem refers to a problem in which, when a grayscale is rapidly changed in units of frames (for example, when a black grayscale of a previous frame is changed to a white grayscale in a current frame), a brightness corresponding to an intermediate grayscale is displayed instead of a brightness corresponding to a target grayscale due to the difference between such curves.

[0075] During the period t2r to t3r, the transistors M5_r and M6_r are turned off. Since the transistors M4_r and M7_r maintain a turned-on state, the charges stored in the storage capacitor Cst_r and the charges stored in the organic light emitting diode OLED_r are initialized according to the initialization voltage.

[0076] Next, the transistors M2_r and M3_r are turned on by the on-level pulse of the scan signal Sir, and the data voltage is written to the storage capacitor Cst_r through the data line Dj and the transistors M2_r, M1_r, and M3_r.

[0077] Next, the level of the emission signal Eir changes to a turn-on level, so that the transistors M5_r and M6_r are turned on. Therefore, when the drive current flows through the drive current path connecting the first power voltage line ELVDD, the transistor M5_r, the transistor M1_r and the transistor M6_r, the organic light emitting diode OLED_r and the second power voltage line ELVSS, the organic light emitting diode OLED_r emits light. Based on the voltage written to the storage capacitor Cst_r, the amount of the drive current is determined by the first transistor M1_r.

[0078] However, Figure 3 There are several problems with the drive method.

[0079] First, a problem is that the pulse of the previous scanning signal S(i-1)r generated in the period t1r to t3r overlaps with the transition time of the emission signal Eir. The term "transition" refers to the change of the logic level of the signal. For example, the case where the logic level of the signal changes from a low level to a high level can be represented as a rising transition, and the case where the logic level of the signal changes from a high level to a low level can be represented as a falling transition. In actual products, the required overlapping time is about 1μs, so it may be difficult to accurately overlap the pulse of the previous scanning signal S(i-1)r with the transition time of the emission signal Eir.

[0080] In addition, because the period t1r to t2r is the period in which the organic light emitting diode OLED_r emits light, the organic light emitting diode OLED_r may emit light with an unexpected brightness level. In order to maximally suppress this situation, the path through which the driving current flows can be changed by turning on the seventh transistor M7_r. However, because the initialization voltage is applied to the gate electrode of the first transistor M1_r, an overcurrent flows from the first power voltage line ELVDD to the initialization voltage line VINT, so the line may be burned out. Therefore, the problem of overpower consumption may occur.

[0081] Furthermore, when the initialization voltage is applied to the gate electrode of the first transistor M1_r while the black grayscale is being expressed, current instantaneously flows through the organic light emitting diode OLED_r, and thus, there may be a problem in that the black grayscale cannot be maintained.

[0082] Next, we will describe the use of Figure 4 The driving method drives the pixel circuit PXij_r.

[0083] Reference Figure 4 , the emission signal Eir' is applied to the emission line Ei, the previous stage scanning signal S(i-1)r' is applied to the previous stage scanning line S(i-1), and the scanning signal Sir' is applied to the scanning line Si.

[0084] exist Figure 4 In the driving method, the data voltage of the previous level pixel row and the pixel row before the previous level pixel row is applied to the gate electrode of the first transistor M1_r through the first pulse P1r' and the second pulse P2r' of the scanning signal Sir', so that the first transistor M1_r is turned on and biased. The data voltage of the current level pixel row is written by the third pulse P3r' of the scanning signal Sir'. Subsequently, when the level of the emission signal Eir' becomes the on level, the organic light emitting diode OLED_r can emit light using the data voltage of the current level pixel row.

[0085] and Figure 3 The driving method is similar to that of Figure 4 The driving method also has the advantage that the first transistor M1_r is biased to be turned on. Figure 4 The driving method also has several disadvantages.

[0086] First, a plurality of pulses will be applied to each of the scan lines S1, S2, S3, ..., and Sm, and therefore, the off-level pulse of the emission signal Eir' will be maintained for a long time. Therefore, there is a problem that the emission time of the organic light emitting diode OLED_r is reduced, and because the number of rising / falling operations in the built-in circuit of the emission driver 14 increases, power consumption increases.

[0087] In addition, since the data voltages of the previous level pixel rows and the pixel rows before the previous level pixel rows are not ensured to be white grayscale, the turn-on bias voltage changes for each frame, and therefore there is a problem in that the effect obtained by the turn-on bias voltage cannot be ensured.

[0088] Figure 5 is a diagram illustrating a pixel circuit according to an exemplary embodiment.

[0089] Reference Figure 5 , the pixel circuit PXij_a includes first to seventh transistors M1, M2, M3, M4, M5, M6, and M7, a storage capacitor Cst, and an organic light emitting diode OLED.

[0090] The first transistor M1 may include a source electrode, a drain electrode, and a gate electrode. The first transistor M1 may be referred to as a driving transistor.

[0091] A source electrode of the second transistor M2 may be connected to the data line Dj, a drain electrode of the second transistor M2 may be connected to the source electrode of the first transistor M1, and a gate electrode of the second transistor M2 may be connected to the first scan line Si. The second transistor M2 may be referred to as a scan transistor or a switch transistor.

[0092] The source electrode of the third transistor M3 may be connected to the drain electrode of the first transistor M1, the drain electrode of the third transistor M3 may be connected to the gate electrode of the first transistor M1, and the gate electrode of the third transistor M3 may be connected to the first scan line Si. In some embodiments, the third transistor M3 may include a plurality of sub-transistors connected in series to prevent or reduce leakage current.

[0093] The source electrode of the fourth transistor M4 may be connected to the gate electrode of the first transistor M1, the drain electrode of the fourth transistor M4 may be connected to the first initialization voltage line VINT1, and the gate electrode of the fourth transistor M4 may be connected to the second scan line S(i-1). In some embodiments, the fourth transistor M4 may include a plurality of sub-transistors connected in series to prevent or reduce leakage current.

[0094] A source electrode of the fifth transistor M5 may be connected to the first power voltage line ELVDD, a drain electrode of the fifth transistor M5 may be connected to the source electrode of the first transistor M1 , and a gate electrode of the fifth transistor M5 may be connected to the first emission line Ei.

[0095] A source electrode of the sixth transistor M6 may be connected to the drain electrode of the first transistor M1 , a drain electrode of the sixth transistor M6 may be connected to the anode electrode of the organic light emitting diode OLED, and a gate electrode of the sixth transistor M6 may be connected to the second emission line E(i−1).

[0096] A source electrode of the seventh transistor M7 may be connected to the anode electrode of the organic light emitting diode OLED, a drain electrode of the seventh transistor M7 may be connected to the second initialization voltage line VINT2 , and a gate electrode of the seventh transistor M7 may be connected to the third scan line S(i- 2 ).

[0097] One electrode of the storage capacitor Cst may be connected to the gate electrode of the first transistor M1 , and the other electrode of the storage capacitor Cst may be connected to the first power voltage line ELVDD.

[0098] An anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the seventh transistor M7 , and a cathode electrode of the organic light emitting diode OLED may be connected to the second power voltage line ELVSS.

[0099] The first transmission line Ei and the second transmission line E(i-1) may be located at different nodes. That is, the first transmission signal applied to the first transmission line Ei and the second transmission signal applied to the second transmission line E(i-1) may be different from each other. For example, the first transmission line Ei may be the i-th transmission line, and the second transmission line E(i-1) may be the i-1-th transmission line. Here, i is a natural number equal to or greater than 3 and equal to or less than o.

[0100] The first scan line Si and the second scan line S(i-1) may be located at different nodes. That is, the first scan signal applied to the first scan line Si and the second scan signal applied to the second scan line S(i-1) may be different from each other. For example, the first scan line Si may be the i-th scan line, and the second scan line S(i-1) may be the i-1-th scan line.

[0101] According to an embodiment, the third scan line S(i-2) may be located at a node different from the nodes of the first scan line S(i-1) and the second scan line S(i-2). That is, the third scan signal applied to the third scan line S(i-2) may be different from the first scan signal and the second scan signal. For example, the third scan line S(i-2) may be the i-2th scan line.

[0102] According to another exemplary embodiment, the third scan line S(i-2) may be located at the same node as the first scan line Si or the second scan line S(i-1). For example, the third scan line S(i-2) is a physically different line from the first scan line Si and the second scan line S(i-1), but may be located at a node electrically the same as the node of the first scan line Si or the second scan line S(i-1). The electrode in another layer may be used as a bridge electrode to electrically connect the third scan line S(i-2) to the first scan line Si or the second scan line S(i-1).

[0103] Hereinafter, for the convenience of description, a case is described in which the third scan line S(i-2) is located at a node different from those of the first scan line Si and the second scan line S(i-1).

[0104] The first initialization voltage line VINT1 and the second initialization voltage line VINT2 may be physically different lines. In some embodiments, the first initialization voltage line VINT1 and the second initialization voltage line VINT2 are located at different nodes, and therefore, the first initialization voltage and the second initialization voltage may be different from each other. In another exemplary embodiment, the first initialization voltage line VINT1 and the second initialization voltage line VINT2 are located at the same node, and therefore, the first initialization voltage and the second initialization voltage may be the same. Using an electrode in another layer as a bridge electrode, the first initialization voltage line VINT1 and the second initialization voltage line VINT2 may be connected to each other.

[0105] According to an exemplary embodiment, in the pixel circuit PX1j_a and the pixel circuit PX2j_a on the first row and the second row, respectively, each component is connected in substantially the same manner as the pixel circuit PXij_a except being connected to the second scan line S(i-1) and the third scan line S(i-2). According to an exemplary embodiment, in the pixel circuit PX1j_a of the first row, the m-th scan line Sm and the m-1-th scan line S(m-1) may be connected instead of the second scan line S(i-1) and the third scan line S(i-2). Specifically, in the pixel circuit PX1j_a, the gate electrode of the fourth transistor M4 may be connected to the m-th scan line Sm, and the gate electrode of the seventh transistor M7 may be connected to the m-1-th scan line S(m-1). According to an exemplary embodiment, in the pixel circuit PX2j_a of the second row, the m-th scan line Sm may be connected instead of the third scan line S(i-2). Specifically, in the pixel circuit PX2j_a, the gate electrode of the seventh transistor M7 may be connected to the m-th scan line Sm.

[0106] Figure 6 is a diagram illustrating a driving method of a pixel circuit according to an exemplary embodiment.

[0107] Reference Figure 6 , shows a first emission signal Eis applied to the first emission line Ei, a second emission signal E(i-1)s applied to the second emission line E(i-1), a first scan signal Sis applied to the first scan line Si, a second scan signal S(i-1)s applied to the second scan line S(i-1), and a third scan signal S(i-2)s applied to the third scan line S(i-2).

[0108] The phase of the first emission signal Eis may be delayed compared to the phase of the second emission signal E(i-1)s. The phase of the first scanning signal Sis may be delayed compared to the phase of the second scanning signal S(i-1)s. The phase of the second scanning signal S(i-1)s may be delayed compared to the phase of the third scanning signal S(i-2)s.

[0109] The on-level pulse of the first scanning signal Sis may overlap partially with the off-level pulse of the first emission signal Eis. The on-level pulse of the second scanning signal S(i-1)s may overlap partially with the off-level pulse of the second emission signal E(i-1)s. When the first emission signal Eis is at the on-level, the on-level pulse of the second scanning signal S(i-1)s may be generated. When the first emission signal Eis and the second emission signal E(i-1)s become on-level, the on-level pulse of the third scanning signal S(i-2)s may be generated.

[0110] First, when the third scan signal S(i-2)s becomes a turn-on level, the seventh transistor M7 is turned on. Therefore, the anode electrode of the organic light emitting diode OLED is connected to the second initialization voltage line VINT2, and the charges stored in the anode electrode are initialized to the second initialization voltage.

[0111] A current path connecting the first power voltage line ELVDD, the transistors M5, M1, M6, and M7, and the second initialization voltage line VINT2 is formed. Figure 3 Compared with the case of , the initialization voltage is not applied to the gate electrode of the first transistor M1, so the overcurrent does not flow in the formed current path. That is, because the data voltage corresponding to the corresponding grayscale is applied to the gate electrode of the first transistor M1, the current amount corresponding to the corresponding grayscale flows, and thus the power consumption does not increase.

[0112] Next, the second emission signal E(i-1)s becomes a cut-off level, so the sixth transistor M6 is turned off. In addition, the second scan signal S(i-1)s becomes a conduction level, so the fourth transistor M4 is turned on. The fifth transistor M5 is in a conduction state due to the first emission signal Eis of the conduction level. Therefore, the source electrode of the first transistor M1 is connected to the first power voltage line ELVDD, and the gate electrode of the first transistor M1 is connected to the first initialization voltage line VINT1. Therefore, the first transistor M1 is biased by conduction.

[0113] and Figure 3 Compared with the driving method of FIG. 1 , the sixth transistor M6 is in the off state, and the organic light emitting diode OLED does not emit light. Therefore, no unexpected emission occurs. Therefore, when representing the black grayscale, the black grayscale can be well represented without abnormality.

[0114] and Figure 4 Compared with the driving method of the embodiment, the data voltage of the pixel row before the previous pixel row and the pixel row before the previous pixel row that can be changed every frame is not applied to the gate electrode of the first transistor M1, but the first initialization voltage is always applied to the gate electrode of the first transistor M1. Therefore, the first transistor M1 can be stably turned on and biased.

[0115] Next, the first emission signal Eis becomes a cut-off level, so the fifth transistor M5 is turned off. In addition, the first scan signal Sis becomes a turn-on level, so the transistors M2 and M3 are turned on. Therefore, the data voltage is applied to one electrode of the storage capacitor Cst through the data line Dj and the transistors M2, M1 and M3, and the storage capacitor Cst records the difference between the data voltage and the first power voltage. The threshold voltage decrement of the first transistor M1 can be reflected to the recorded data voltage.

[0116] Next, because the second emission signal E(i-1)s and the first emission signal Eis are sequentially turned on, the sixth transistor M6 and the fifth transistor M5 are sequentially turned on. Therefore, a driving current path connecting the first power voltage line ELVDD, the transistor M5, the transistor M1 and the transistor M6, the organic light emitting diode OLED and the second power voltage line ELVSS is formed. The amount of driving current flowing through the driving current path can be determined according to the amount of voltage stored in the storage capacitor Cst and applied to the gate electrode of the first transistor M1.

[0117] According to an exemplary embodiment, except for the application of the second scan signal S(i-1)s and the third scan signal S(i-2)s, the pixel circuit PX1j_a and the pixel circuit PX2j_a on the first row and the second row, respectively, operate in substantially the same manner as the pixel circuit PXij_a; that is, the mth scan signal Sms and the m-1th scan signal S(m-1)s of the previous frame directly before the current frame may be applied instead of the second scan signal S(i-1)s and the third scan signal S(i-2)s, and the mth emission signal Ems of the previous frame may be applied instead of the second emission signal E(i-1).

[0118] and Figure 4 Compared with the driving method of the present invention, the scanning signal S(i-2)s, the scanning signal S(i-1)s and the scanning signal Sis do not need to include a plurality of pulses, and therefore, the cut-off level pulses of the emission signal E(i-1)s and the emission signal Eis do not need to be maintained for a long time. Therefore, the emission time of the organic light emitting diode OLED will not be reduced, and the power consumption of the emission driver 14 will not be increased.

[0119] Figure 7is a diagram illustrating a driving method of a pixel circuit according to another exemplary embodiment.

[0120] Reference Figure 7 , shows the first emission signal Eis' applied to the first emission line Ei, the second emission signal E(i-1)s' applied to the second emission line E(i-1), the first scan signal Sis' applied to the first scan line Si, the second scan signal S(i-1)s' applied to the second scan line S(i-1) and the third scan signal S(i-2)s' applied to the third scan line S(i-2).

[0121] The on-level pulse of the second scan signal S(i-1)s' may overlap the transition time portion of the off-level pulse of the first emission signal Eis'. For example, at time t5, the on-level pulse of the second scan signal S(i-1)s' may overlap the rising transition time portion of the first emission signal Eis'.

[0122] The on-level pulse of the third scan signal S(i-2)s' may overlap the transition time portion of the off-level pulse of the second emission signal E(i-1)s'. For example, at time t2, the on-level pulse of the third scan signal S(i-2)s' may overlap the rising transition time portion of the second emission signal E(i-1)s'.

[0123] First, during the period t1 to t2, the third scan signal S(i-2)s', the first emission signal Eis' and the second emission signal E(i-1)s' are at the on level, so the driving current flows through the second initialization voltage line VINT2 or the organic light emitting diode OLED. The flowing current can be changed according to the condition of each voltage. The initialization voltage is not applied to the gate electrode of the first transistor M1, but the data voltage corresponding to the grayscale is applied to the gate electrode of the first transistor M1. Therefore, the current consumption will not be increased.

[0124] Next, during the period t2 to t3, the second emission signal E(i-1)s' becomes a turn-off level, and the sixth transistor M6 is turned off. Therefore, the emission of the organic light emitting diode OLED stops, and the charges stored in the organic light emitting diode OLED are initialized.

[0125] Next, during the period t4 to t5, the second scan signal S(i-1)s' becomes a conduction level, so the fourth transistor M4 is turned on. The source electrode of the first transistor M1 is connected to the first power voltage line ELVDD through the fifth transistor M5, and the gate electrode of the first transistor M1 is connected to the first initialization voltage line VINT1 through the fourth transistor M4. Therefore, the first transistor M1 is biased by conduction.

[0126] Next, during the period t5 to t6, the first emission signal Eis' becomes a turn-off level, and thus the fifth transistor M5 is turned off. During the period t5 to t6, the charges stored in the storage capacitor Cst are initialized.

[0127] The driving method during the subsequent period refers to Figure 6 In addition, Figure 7 The effect of the embodiment is shown in FIG. Figure 6 Description.

[0128] According to an exemplary embodiment, the pixel circuits PX1j_a and PX2j_a on the first row and the second row, respectively, operate in substantially the same manner as the pixel circuit PXij_a, except for application of the second scan signal S(i-1)s' and the third scan signal S(i-2)s'; that is, the mth scan signal Sms' and the m-1th scan signal S(m-1)s' of the previous frame directly before the current frame may be applied instead of the second scan signal S(i-1)s' and the third scan signal S(i-2)s'.

[0129] Figure 8 , Fig. 9 and Fig.10 is a diagram showing an exemplary layout of a pixel circuit according to an exemplary embodiment.

[0130] Figure 8 yes Figure 5 An exemplary plan view of a pixel circuit PXij_a, Fig. 9 It is along Figure 8 The cross-sectional view taken along the section line I-I', Fig.10 It is along Figure 8 A cross-sectional view taken along section line II-II'.

[0131] The substrate SUB is a rigid substrate or a flexible substrate.

[0132] The rigid substrate may include a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0133] The flexible substrate may include a film substrate and a plastic substrate comprising a polymer organic material. For example, the flexible substrate may include one of polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC) and cellulose acetate propionate (CAP). In addition, the flexible substrate may include glass fiber reinforced plastic (FRP).

[0134] The buffer layer BUF may cover the substrate SUB. The buffer layer BUF may prevent or limit the diffusion of impurities from the substrate SUB into the active layer ACT. The buffer layer BUF may be an inorganic insulating layer. For example, the buffer layer BUF may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or any combination thereof. According to the material of the substrate SUB and process conditions, the buffer layer BUF may be omitted.

[0135] The active layer ACT may cover the buffer layer BUF. The active layer ACT may be formed of a semiconductor material. For example, the active layer ACT may be made of polysilicon, amorphous silicon, an oxide semiconductor, etc. The portion of the active layer ACT not doped with impurities may constitute the channels CH1 to CH7 of the first to seventh transistors M1, M2, M3, M4, M5, M6, and M7, and the portion of the active layer ACT doped with impurities may constitute electrodes SE1, SE2, SE3, SE4, SE5, SE6, and SE7 and DE1, DE2, DE3, DE4, DE5, DE6, and DE7 or lines. The impurity may be a p-type impurity. In some embodiments, the impurity may be at least one of a p-type impurity, an n-type impurity, and other metals.

[0136] The first gate insulating layer GI1 may cover the substrate SUB and the active layer ACT. The first gate insulating layer GI1 may cover the source electrodes SE1, SE2, SE3, SE4, SE5, SE6 and SE7, the drain electrodes DE1, DE2, DE3, DE4, DE5, DE6 and DE7 and the channels CH1 to CH7 of the first to seventh transistors M1, M2, M3, M4, M5, M6 and M7. The first gate insulating layer GI1 may be an inorganic insulating layer. For example, the first gate insulating layer GI1 may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or any combination thereof.

[0137] The gate electrodes GE1, GE2, GE3, GE4, GE5, GE6 and GE7 of the first to seventh transistors M1, M2, M3, M4, M5, M6 and M7, the first to third scan lines Si, S(i-1) and S(i-2), the first emission line Ei and the second emission line E(i-1), the first initialization voltage line VINT1 and the second initialization voltage line VINT2, and one electrode LE of the storage capacitor Cst may be located on the first gate insulating layer GI1. The electrodes and lines on the first gate insulating layer GI1 may be made of the same conductive material. The electrodes and lines on the first gate insulating layer GI1 may be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu) or any combination thereof.

[0138] The second gate insulating layer GI2 may cover: the first gate insulating layer GI1; the gate electrodes GE1, GE2, GE3, GE4, GE5, GE6 and GE7 of the first to seventh transistors M1, M2, M3, M4, M5, M6 and M7; the first to third scan lines Si, S(i-1) and S(i-2); the first emission line Ei and the second emission line E(i-1); the first initialization voltage line VINT1 and the second initialization voltage line VINT2; and one electrode LE of the storage capacitor Cst. The second gate insulating layer GI2 may be an inorganic insulating layer. For example, the second gate insulating layer GI2 may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or any combination thereof.

[0139] The other electrode UE of the storage capacitor Cst may be located on the second gate insulating layer GI2. For example, the other electrode UE of the storage capacitor Cst may be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu), or any combination thereof.

[0140] The interlayer insulating layer ILD may cover the second gate insulating layer GI2 and the other electrode UE of the storage capacitor Cst. The interlayer insulating layer ILD may be an inorganic insulating layer. For example, the interlayer insulating layer ILD may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or any combination thereof.

[0141] The first contact electrode CNT1 may be located on the interlayer insulating layer ILD and connected to the source electrode SE7 of the seventh transistor M7. The data line Dj and the first power voltage line ELVDD may be located on the interlayer insulating layer ILD. The electrodes and lines on the interlayer insulating layer ILD may be made of the same conductive material. For example, the electrodes and lines on the interlayer insulating layer ILD may be made of molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), copper (Cu) or any combination thereof.

[0142] The via layer VIA may cover the interlayer insulating layer ILD, the first contact electrode CNT1, the data line Dj, and the first power voltage line ELVDD. The via layer VIA may be an organic insulating layer. For example, the via layer VIA may include at least one of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyarylether (PAE), heterocyclic polymer, polyparaxylene, epoxy resin, benzocyclobutene (BCB), siloxane resin, and silane resin. In another exemplary embodiment, the via layer VIA may be an inorganic insulating layer and have a multilayer structure in which an organic insulating layer and an inorganic insulating layer are repeatedly stacked.

[0143] The anode electrode AE ​​of the organic light emitting diode OLED may be located on the via layer VIA. The anode electrode AE ​​may be connected to the source electrode SE7 of the seventh transistor M7 through the first contact electrode CNT1. For example, the anode electrode AE ​​may have a structure in which silver (Ag) and indium tin oxide (ITO) are stacked.

[0144] An emission region defining layer defining an emission region, an emission layer of an organic light emitting diode covering an opening of the emission region defining layer, and a cathode electrode covering the emission region defining layer and the emission layer may be formed on the anode electrode AE. The emission region of the organic light emitting diode OLED may be appropriately selected according to a product having an RGB stripe structure, a pentile structure, etc., and therefore, a description thereof will be omitted in this embodiment.

[0145] The third scan line S(i-2), the second emission line E(i-1), the second initialization voltage line VINT2, the first scan line Si, the second scan line S(i-1), the first emission line Ei, and the first initialization voltage line VINT1 may be sequentially located on the same layer in the first direction DR1. The third scan line S(i-2), the second emission line E(i-1), the second initialization voltage line VINT2, the first scan line Si, the second scan line S(i-1), the first emission line Ei, and the first initialization voltage line VINT1 may extend substantially in the second direction DR2.

[0146] The second initialization voltage line VINT2 may be vertically overlapped with a point where the source electrode SE6 of the sixth transistor M6 and the drain electrode DE1 of the first transistor M1 contact each other. In other words, the second initialization voltage line VINT2 may be vertically overlapped with a point where the source electrode SE6 of the sixth transistor M6 and the drain electrode DE3-2 of the third transistor M3 contact each other. In addition, the second initialization voltage line VINT2 may be connected to the drain electrode of the fourth transistor of the previous pixel circuit. The previous pixel circuit refers to the most adjacent pixel circuit located in the direction opposite to the first direction DR1. In addition, the third scan line S(i-2) may be connected to the gate electrode of the fourth transistor of the previous pixel circuit.

[0147] The first initialization voltage line VINT1 may be connected to the drain electrode of the seventh transistor of the next stage pixel circuit. The next stage pixel circuit refers to the most adjacent pixel circuit located in the first direction DR1.

[0148] The third transistor M3 may include a sub-transistor M3-1 and a sub-transistor M3-2 connected in series. The sub-transistor M3-1 may include a drain electrode DE3-1, a source electrode SE3-1, a gate electrode GE3-1, and a channel CH3-1. The sub-transistor M3-2 may include a drain electrode DE3-2, a source electrode SE3-2, a gate electrode GE3-2, and a channel CH3-2.

[0149] The fourth transistor M4 may include a sub-transistor M4-1 and a sub-transistor M4-2 connected in series. The sub-transistor M4-1 may include a drain electrode DE4-1, a source electrode SE4-1, a gate electrode GE4-1, and a channel CH4-1. The sub-transistor M4-2 may include a drain electrode DE4-2, a source electrode SE4-2, a gate electrode GE4-2, and a channel CH4-2.

[0150] Reference Fig.10 . Layout, compared with the prior art, the pixel circuit PXij_a can be constructed without adding a separate conductive layer or insulating layer.

[0151] Fig.11 is a diagram illustrating a pixel circuit according to another exemplary embodiment.

[0152] and Figure 5 Compared with the pixel circuit PXij_a, Fig.11 The seventh transistor M7 is omitted in the pixel circuit PXij_b.

[0153] when Figure 6 and Figure 7 When the driving method is applied to the pixel circuit PXij_b, even when the transistor M5 and the transistor M6 are turned on, the first power voltage line ELVDD, the transistors M5, M1, M6 and M7, and the Figure 5 . Therefore, current consumption can be reduced.

[0154] According to the present disclosure, a pixel circuit can prevent or reduce the occurrence of undesired emission and overcurrent by biasing a driving transistor to be turned on, and power consumption can be reduced.

[0155] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims, and various obvious modifications and equivalent arrangements will be apparent to those of ordinary skill in the art.

Claims

1. A pixel circuit, comprising: Organic light-emitting diodes; A first transistor including a source electrode, a drain electrode and a gate electrode; a second transistor having a source electrode connected to the data line, a drain electrode connected to the source electrode of the first transistor, and a gate electrode connected to the first scan line; a third transistor having a source electrode connected to the drain electrode of the first transistor, a drain electrode connected to the gate electrode of the first transistor, and a gate electrode connected to the first scan line; a fourth transistor having a source electrode connected to the gate electrode of the first transistor, a drain electrode connected to a first initialization voltage line, and a gate electrode connected to a second scan line; a fifth transistor having a source electrode connected to the first power voltage line, a drain electrode connected to the source electrode of the first transistor, and a gate electrode connected to the first emission line; a sixth transistor having a source electrode directly connected to the drain electrode of the first transistor, a drain electrode connected to the anode electrode of the organic light emitting diode, and a gate electrode connected to a second emission line; as well as a storage capacitor having a first electrode connected to the gate electrode of the first transistor and a second electrode connected to the first power voltage line, The first transmission line and the second transmission line are located at different nodes. The first transmission line and the second transmission line are configured to send a first transmission signal and a second transmission signal respectively. wherein the first transmit signal has a phase delayed compared to the phase of the second transmit signal, so that the cutoff level pulse of the first transmit signal is generated and terminated later than the cutoff level pulse of the second transmit signal within a single frame, The first scanning line and the second scanning line are configured to send a first scanning signal and a second scanning signal respectively, and The generation of the on-level pulse of the second scanning signal overlaps with the first emission signal having the on-level.

2. The pixel circuit according to claim 1, wherein: The first scan line and the second scan line are located at different nodes, wherein the first scanning signal has a phase delayed compared to a phase of the second scanning signal, and The on-level pulse of the first scanning signal and the off-level pulse of the first emission signal are temporarily overlapped.

3. The pixel circuit according to claim 2, wherein: The on-level pulse of the second scan signal and the off-level pulse of the second emission signal are temporarily overlapped.

4. The pixel circuit according to claim 3, wherein: A transition time portion of the on-level pulse of the second scan signal and the off-level pulse of the first emission signal overlaps.

5. The pixel circuit according to claim 1 , further comprising a seventh transistor having a source electrode connected to the anode electrode of the organic light emitting diode, a drain electrode connected to a second initialization voltage line, and a gate electrode connected to a third scan line, in, The on-level pulse of the third scan signal applied to the third scan line partially overlaps a transition time of the off-level pulse of the second emission signal applied to the second emission line.

6. The pixel circuit according to claim 5, further comprising: a first gate insulating layer, covering the source electrode, the drain electrode and the channel of the first transistor to the seventh transistor, The gate electrodes of the first to seventh transistors, the first to third scan lines, the first and second emission lines, the first and second initialization voltage lines, and the first electrode of the storage capacitor are located on the first gate insulating layer.

7. The pixel circuit according to claim 6, further comprising: a second gate insulating layer covering the first gate insulating layer, the gate electrodes of the first to seventh transistors, the first to third scan lines, the first emission line and the second emission line, the first initialization voltage line and the second initialization voltage line, and the first electrode of the storage capacitor, Wherein, the second electrode of the storage capacitor is located on the second gate insulating layer.

8. The pixel circuit according to claim 7, further comprising: an interlayer insulating layer covering the second gate insulating layer and the second electrode of the storage capacitor; as well as a first contact electrode, located on the interlayer insulating layer, the first contact electrode being connected to the source electrode of the seventh transistor, Wherein, the data line and the first power voltage line are located on the interlayer insulating layer, The pixel circuit further includes: a through-hole layer covering the interlayer insulating layer, the first contact electrode, the data line and the first power voltage line, The anode electrode of the organic light emitting diode is located on the through-hole layer and is connected to the source electrode of the seventh transistor through the first contact electrode. The third scan line, the second emission line, the second initialization voltage line, the first scan line, the second scan line, the first emission line and the first initialization voltage line are sequentially located on the same layer in the first direction. wherein the second initialization voltage line vertically overlaps a point where the source electrode of the sixth transistor and the drain electrode of the first transistor contact each other, wherein the second initialization voltage line vertically overlaps a point where the source electrode of the sixth transistor and the drain electrode of the third transistor contact each other, Wherein, the second initialization voltage line is connected to the drain electrode of the fourth transistor of the previous pixel circuit, The third scan line is connected to the gate electrode of the fourth transistor of the previous pixel circuit, and Wherein, the first initialization voltage line is connected to the drain electrode of the seventh transistor of the next-level pixel circuit.

Images