Method and apparatus for semantic transfer and optimization of features in deep learning

Abstract

Methods and apparatuses for discriminative semantic transfer and physically inspired optimization in deep learning are disclosed. The computational training method for convolutional neural networks (CNNs) involves receiving a sequence of training images in a first-level CNN to describe objects in a cluttered scene as semantic segmentation masks. Semantic segmentation masks are then received in a second-level semantic segmentation network to generate semantic features. Using weights from the first level as a feature extractor and weights from the second level as a classifier, the semantic features are used to identify edges in the cluttered scene.

Description

[0001] priority

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 62 / 509960, filed May 23, 2017, entitled “METHODS AND APPARATUS FORDISCRIMIATIVE SEMANTIC TRANSFER FEATURES IN DEEP LEARNING”, and U.S. Provisional Patent Application No. 62 / 509990, filed May 23, 2017, entitled “METHODS AND APPARATUS FORPHYSICS-INSPIRED OPTIMIZATION OF FEATURES IN DEEP LEARNING”, both of which are incorporated herein by reference and are jointly assigned. Technical Field

[0003] The embodiments generally relate to data processing, and more specifically to data processing via a general-purpose graphics processing unit. In particular, the embodiments relate to systems and methods for performing deep learning networks by leveraging discriminative semantic transfer and physically inspired optimization of features in deep learning. Background Technology

[0004] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed-function computing units to process graphics data; however, recently, some graphics processors have been made programmable, enabling such processors to support a wider range of operations for processing vertex and fragment data.

[0005] To further improve performance, graphics processing units (GPUs) typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel GPUs with a Single Instruction Multiple Thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of the software and hardware for a SIMT architecture can be found in Chapter 3, pages 37-51 (2013), of Shane Cook's CUDA Programming.

[0006] Machine learning has successfully solved a wide range of tasks. The computations involved in training and using machine learning algorithms (e.g., neural networks) are naturally well-suited for efficient parallel implementation. Therefore, parallel processors such as general-purpose graphics processing units (GPGPUs) have played a significant role in the practical implementation of deep neural networks. Parallel graphics processors with a single-instruction, multi-threaded (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. The efficiency offered by parallel machine learning algorithm implementations allows for the use of high-capacity networks and enables those networks to be trained on larger datasets.

[0007] Deep learning neural networks (DNNs) are typically constructed as convolutional neural networks and are used to perform complex associative tasks. After a training phase using known inputs, DNNs are able to recognize new inputs similar to the original training inputs. This is helpful in object detection techniques, automatic speech recognition, user authentication, image understanding, and machine vision applications, among others. Video sequences can be used for object tracking and recognition. Attached Figure Description

[0008] The accompanying drawings illustrate examples and are therefore exemplary embodiments and are not intended to be limiting in scope.

[0009] Figure 1 This is a block diagram illustrating a computer system configured to implement one or more aspects of the exemplary embodiments described herein.

[0010] Figures 2A-2D A parallel processor component according to an exemplary embodiment is shown.

[0011] Figures 3A-3B This is a block diagram of a graphics multiprocessor according to an exemplary embodiment.

[0012] Figures 4A-4F This illustrates an exemplary architecture in which multiple graphics processing units (GPUs) are communicatively coupled to multiple multi-core processors.

[0013] Figure 5 A graphics processing pipeline according to an exemplary embodiment is shown.

[0014] Figure 6 A machine learning software stack according to an exemplary embodiment is shown.

[0015] Figure 7 A highly parallel general-purpose graphics processing unit is shown according to an exemplary embodiment.

[0016] Figure 8 A multi-GPU computing system according to an exemplary embodiment is shown.

[0017] Figures 9A-9B The layer of an exemplary deep neural network is shown.

[0018] Figure 10 This demonstrates an exemplary recurrent neural network.

[0019] Figure 11 An exemplary embodiment of training and deploying a deep neural network is shown.

[0020] Figure 12 This is a schematic diagram illustrating distributed learning.

[0021] Figure 13 An exemplary reasoning on-chip system (SOC) suitable for performing reasoning using a trained model is shown.

[0022] Figure 14 It is an exemplary block diagram of storing RGB and CNN channel data as part of a depth channel image, and an exemplary block diagram of an image capture system that stores depth channel images using a convolutional neural network (CNN).

[0023] Figure 15 This is an overview diagram of the sequential operations on semantic transfer features in a deep learning network according to an exemplary embodiment.

[0024] Figure 16 It is a graph of probabilistic node connectivity for semantic transfer features according to an exemplary embodiment.

[0025] Figure 17 This is a diagram of a network design for semantic segmentation, semantic transfer, semantic feature space, and transfer weight visualization based on an exemplary embodiment.

[0026] Figure 18A The left side is a visualization of feature quality. From top to bottom: input, bg activation, wf activation, ww activation, wc activation, softmax result. The right side shows a comparison of feature quality.

[0027] Figure 18B It is a topological diagram of an interior layout from a test set based on an exemplary embodiment.

[0028] Figure 18C It is a diagram of the room, feature map, and the effects of force composition shown in the input image according to an exemplary embodiment, the feature map being constructed by treating the edges as springs and the feature map as a potential field, and relating the force applied at each point of the spring.

[0029] Figure 18DThe left side shows an example of qualitative results regarding the LSUN validation set when wf, ww, and wc are merged through a pixel-wise maximization operation on the visualized feature map, according to an exemplary embodiment. The right side shows typical failure cases according to an exemplary embodiment, in which erroneous topologies produce the lowest energy.

[0030] Figure 18E The left side shows an example of qualitative results for the Hedau validation set when wf, ww, and wc are merged by a pixel-wise maximization operation on the visualized feature map, according to an exemplary embodiment.

[0031] Figure 18F This is a graph showing the error versus window size for the LSUN validation set, based on an exemplary embodiment.

[0032] Figure 18G This is a diagram comparing two techniques for physical-inspired optimization based on exemplary embodiments.

[0033] Figure 19 A block diagram of a processing system according to an exemplary embodiment is shown.

[0034] Figure 20 An exemplary block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor is shown.

[0035] Figure 21 An exemplary block diagram of a graphics processor is shown.

[0036] Figure 22 A block diagram of a graphics processing engine of a graphics processor according to an exemplary embodiment is shown.

[0037] Figure 23 A block diagram showing another exemplary embodiment of a graphics processor is shown.

[0038] Figure 24 The diagram illustrates thread execution logic, which includes an array of processing elements employed in an exemplary embodiment of the graphics processing engine (GPE).

[0039] Figure 25 A block diagram illustrating a graphics processor instruction format according to an exemplary embodiment is shown.

[0040] Figure 26 A block diagram illustrating an exemplary embodiment of a graphics processor is shown.

[0041] Figure 27A A block diagram illustrating a graphics processor command format according to an exemplary embodiment is shown.

[0042] Figure 27B A block diagram illustrating a sequence of graphics processor commands according to an exemplary embodiment is shown.

[0043] Figure 28 An exemplary graphical software architecture of a data processing system according to an exemplary embodiment is shown.

[0044] Figure 29 A block diagram of an IP core development system, which can be used to manufacture integrated circuits (ICs) to perform operations, is shown according to an exemplary embodiment.

[0045] Figure 30 A block diagram is shown of an exemplary system-on-chip IC that can be fabricated using one or more IP cores according to an exemplary embodiment.

[0046] Figure 31 A block diagram of an exemplary graphics processor of a system-on-a-chip IC that can be fabricated using one or more IP cores according to an exemplary embodiment is shown.

[0047] Figure 32 A block diagram illustrating an exemplary additional graphics processor of a system-on-a-chip IC that can be fabricated using one or more IP cores according to an exemplary embodiment is shown. Detailed Implementation

[0048] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU and core can be integrated on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of the method used to connect the GPU, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0049] In some embodiments, the image capturing device is a stand-alone device. However, the image capturing device may be a subcomponent or part of another computing device that requires image capturing capabilities, such as a portable or handheld computing device with a digital camera for capturing images.

[0050] In the following description, numerous specific details are set forth to provide a more comprehensive understanding. However, it will be understood that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the exemplary embodiments.

[0051] Overview of computing systems

[0052] Figure 1 This is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors 102 communicating with the system memory 104 via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset assembly or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 enables a display controller to provide output to one or more display devices 110A, the display controller being included within the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0053] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to a memory hub 105 via a bus or other communication link 113. The communication link 113 can be any number of standards-based communication link technologies or protocols (such as, but not limited to, Fast PCI), or it can be a vendor-specific communication interface or communication architecture. In one embodiment, the one or more parallel processors 112 form a computationally centralized parallel or vector processing system including a large number of processing cores and / or processing clusters (such as integrated many-core (MIC) processors). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one or more display devices 110A coupled via an I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) for direct connection to one or more display devices 110B.

[0054] Within the I / O subsystem 111, system storage unit 114 can be connected to I / O hub 107 to provide a storage mechanism for computing system 100. I / O switch 116 can be used to provide an interface mechanism to enable connectivity between I / O hub 107 and other components, such as network adapter 118 and / or wireless network adapter 119, which can be integrated into the platform, and various other devices that can be added via one or more add-in devices 120. Network adapter 118 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless radios.

[0055] The computing system 100 may include other components not explicitly shown, including USB or other port connectors, optical storage drives, video capture devices, and the like, which may also be connected to the I / O hub 107. Figure 1 The communication paths for interconnecting the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., Fast PCI) or any other bus or point-to-point communication interface and / or protocol, such as NV-Link high-speed interconnect, or interconnect protocols known in the art.

[0056] In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated on a single integrated circuit along with one or more other system elements. For example, the one or more parallel processors 112, memory hub 105, processor(s) 102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may interconnect with other multi-chip modules to a modular computing system.

[0057] It will be appreciated that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connectivity topology can be modified as desired, including the number and arrangement of bridges, the number of processors(one or more) 102, and the number of parallel processors(one or more) 112. For example, in some embodiments, system memory 104 is connected directly to processors(one or more) 102 rather than via bridges, while other devices communicate with system memory 104 and processors(one or more) 102 via memory hub 105. In other alternative topologies, parallel processors(one or more) 112 are connected to I / O hub 107 or directly to one of the processors(one or more) 102, rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors 102 attached via multiple sockets, which may be coupled to two or more instances of parallel processors(one or more) 112.

[0058] Some of the specific components shown in this document are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, regarding... Figure 1 For components similar to those shown, different terminology may be used in some architectures. For example, in some architectures, memory hub 105 may be referred to as the Northbridge, while I / O hub 107 may be referred to as the Southbridge.

[0059] Figure 2A A parallel processor 200 according to an exemplary embodiment is shown. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). According to the exemplary embodiment, the illustrated parallel processor 200 is... Figure 1 Variations of one or more parallel processors 112 shown.

[0060] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 capable of communicating with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via a hub or switch interface (such as a memory hub 105). The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, wherein the host interface 206 receives commands for performing processing operations, and the memory crossbar 216 receives commands for performing memory operations.

[0061] When host interface 206 receives a command buffer via I / O unit 204, host interface 206 can direct work operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and active before tasks are distributed to the processing clusters of processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, enabling context switching and rapid preemption of threads executing on processing array 212. In one embodiment, host software can verify that workloads are scheduled on processing array 212 via one of multiple graphics processing doorbells. The workloads can then be automatically distributed across processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0062] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A-214N of processing cluster array 212 can execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to clusters 214A-214N of processing cluster array 212, which may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by scheduler 210 or may be partially assisted by compiler logic during compilation of the program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0063] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0064] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the performance of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from system memory for processing via I / O unit 204. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) and then written back to system memory.

[0065] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations across multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between the clusters 214A-214N for further processing.

[0066] During operation, the processing cluster array 212 may receive processing tasks to be executed via a scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include commands and status parameters defining how data should be processed (e.g., what program to execute) and an index of the data to be processed, such as indexes of surface (patch) data, primitive data, vertex data, and / or pixel data. The scheduler 210 may be configured to retrieve the index corresponding to the task or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batching buffer, a push buffer, etc.).

[0067] Each of one or more instances of parallel processing unit 202 may be coupled to parallel processor memory 222. Parallel processor memory 222 may be accessed via memory crossbar switch 216, which receives memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include multiple partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), each of which may be coupled to a portion (e.g., memory cell) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0068] In various embodiments, memory cells 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory cells 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that specific implementations of memory cells 224A-224N can vary and can be selected from a variety of conventional designs. Rendering targets, such as frame buffers or texture maps, may be stored across memory cells 224A-224N, thereby allowing partitioning cells 220A-220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be excluded to facilitate a unified memory design that utilizes system memory along with local cache memory.

[0069] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process any data to be written to memory cells 224A-224N within the parallel processor memory 222. The memory crossbar switch 216 can be configured to transfer the output of each cluster 214A-214N to any partition cell 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 via the memory crossbar switch 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar switch 216 has a connection to the memory interface 218 for communication with I / O unit 204, and a connection to a local instance of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use a virtual channel to separate traffic flows between clusters 214A-214N and partition units 220A-220N.

[0070] Although a single instance of the parallel processing unit 202 is shown within the parallel processor 200, any number of instances of the parallel processing unit 202 may be included. For example, multiple instances of the parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of the parallel processing unit 202 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, and in one embodiment, some instances of the parallel processing unit 202 may include higher-precision floating-point units relative to other instances. Systems that combine one or more instances of the parallel processing unit 202 or the parallel processor 200 can be implemented with various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0071] Figure 2B This is a block diagram of partitioning unit 220 according to an exemplary embodiment. In one embodiment, partitioning unit 220 is... Figure 2A An example of one of the partition units 220A-220N. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from memory crossbar switch 216 and ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer for processing via the frame buffer interface 225. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory, such as memory cells 224A-224N of FIG. 2 (e.g., within parallel processor memory 222)).

[0072] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil printing, z-testing, and blending. ROP 226 then outputs processed graphics data stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic utilizing one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, Δ color compression is performed on depth and color data on a tile-by-tile basis.

[0073] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2) rather than within partition unit 220. In such embodiments, read and write requests for pixel data, rather than pixel fragment data, are transmitted via memory crossbar switch 216. The processed graphics data can be displayed on a display device (e.g., Figure 1 Displayed on one or more display devices 110), routed for further processing by one or more processors 102, or routed for... Figure 2A One of the processing entities within the parallel processor 200 is used for further processing.

[0074] Figure 2C This is a block diagram of a processing cluster 214 within a parallel processing unit according to an exemplary embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. The processing cluster 214 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing cluster. Unlike the SIMD execution regime (where all processing engines typically execute the same instructions), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a subset of the functionality of the SIMT processing regime.

[0075] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and a data crossover switch 240 can be used to distribute the processed data to one of several possible destinations, including other shader units. The pipeline manager 232 can facilitate the distribution of processed data by specifying the destination for the processed data to be distributed via the data crossover switch 240.

[0076] Each graphics multiprocessor 234 within the processing cluster 214 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). The functional execution logic can be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. The functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0077] Instructions sent to processing cluster 214 constitute threads. A group of threads executing across a set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a loop in which the thread group is being processed. A thread group may also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed in a continuous clock cycle. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0078] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache and use a cache memory within the processing cluster 214 (e.g., L1 cache 248). Each graphics multiprocessor 234 also has access to an L2 cache within a partition unit (e.g., partition units 220A-220N of FIG. 2) that can be used to transfer data between threads and is shared across all processing clusters 214. The graphics multiprocessor 234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 202 may be used as global memory. Embodiments (where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234) may share common instructions and data, which may be stored in the L1 cache 248.

[0079] Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG2. The MMU 245 includes: a set of page table entries (PTEs) for mapping virtual addresses of tiles (more specifically tiling) to physical addresses; and optionally, a cache line index. The MMU 245 may include an address translation lookahead buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or the L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving within partitioned units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0080] In graphics and computing applications, processing cluster 214 may be configured such that each graphics multiprocessor 234 is coupled to texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data may be read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within graphics multiprocessor 234, and may be retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs a processed task to data crossover switch 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via memory crossover switch 216. PreROP 242 (e.g., a pre-raster operation unit) is configured to receive data from graphics multiprocessor 234 and direct the data to ROP units, which may be located alongside partitioning units as described herein (e.g., partitioning units 220A-220N of FIG. 2). The preROP 242 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0081] It will be appreciated that the core architecture described herein is illustrative and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessors 234, texture units 236, preROP 242, etc.) may be included within processing cluster 214. Furthermore, although only one processing cluster 214 is shown, the parallel processing units as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214, using separate and distinct processing units, L1 caches, etc.

[0082] Figure 2DA graphics multiprocessor 234 according to an exemplary embodiment is shown. In such embodiments, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to: an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0083] In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. The instructions are cached in instruction cache 252 and dispatched for execution by instruction unit 254. Instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread in the warp is assigned to a different execution unit within GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within a unified address space. Address mapping unit 256 can be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 266.

[0084] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 234. Register file 258 provides temporary storage for operands in data paths connected to functional units of graphics multiprocessor 234 (e.g., GPGPU core 262, load / store unit 266). In one embodiment, register file 258 is partitioned among each of the functional units, such that each functional unit is allocated a dedicated portion of register file 258. In another embodiment, register file 258 is partitioned among different thread bundles executed by graphics multiprocessor 234.

[0085] Each GPGPU core 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 234. According to embodiments, the GPGPU cores 262 may be architecturally similar or architecturally different. For example, in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or be capable of implementing variable-precision floating-point arithmetic. The graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units to perform specific functions (such as copying rectangles or pixel blending operations). In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0086] In one embodiment, GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or can be automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0087] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a cross-switch interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, resulting in very low latency for data transfer between the GPGPU core 262 and the register file 258. The shared memory 270 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 234. The cache memory 272 can be used, for example, as a data cache to cache texture data transferred between functional units and texture units 236. The shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU core 262 can programmatically store data in the shared memory other than the automatically cached data stored in the cache memory 272.

[0088] Figures 3A-3B An additional graphics multiprocessor according to an exemplary embodiment is shown. The illustrated graphics multiprocessors 325, 350 are... Figure 2C The graphics multiprocessor 234 is a variation of the graphics multiprocessor 325 and 350 shown. The graphics multiprocessors 325 and 350 shown can be configured as streaming multiprocessors (SM) capable of executing a large number of execution threads simultaneously.

[0089] Figure 3A A graphics multiprocessor 325 according to an additional exemplary embodiment is shown. The graphics multiprocessor 325 includes components related to... Figure 2D The graphics multiprocessor 234 may include multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and one or more texture units 344A-344B. The graphics multiprocessor 325 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0090] Various components can communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more crossbar switches to enable communication between various components of the graphics multiprocessor 325. In another embodiment, interconnect structure 327 is a separate high-speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 338A-338B can each communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation among components.

[0091] Figure 3B A graphics multiprocessor 350 according to an additional exemplary embodiment is shown. The graphics processor includes multiple sets of execution resources 356A-356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load memory units, such as... Figure 2D and Figure 3A As shown in the diagram, execution resources 356A-356D can operate in harmony with (one or more) texture units 360A-360D for texture operations, while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D can share instruction cache 354 and shared memory 362, as well as multiple instances of texture and / or data cache memories 358A-358B. Various components can be connected via a network similar to... Figure 3A The interconnection structure 327 communicates with the interconnection structure 352.

[0092] Those skilled in the art will understand that Figure 1 , 2A The architectures described in -2D and 3A-3B are descriptive and not limiting within the scope of the exemplary embodiments described herein. Therefore, the techniques described herein can be implemented on any properly configured processing unit without departing from the scope of the embodiments described herein, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as parallel processing unit 202 of FIG2), and one or more graphics processors or dedicated processing units.

[0093] In some embodiments, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In other embodiments, the GPU may be integrated with the core in the same package or on the same chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of the method used to connect the GPU, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0094] Technology for interconnecting GPUs and host processors

[0095] Figure 4A An exemplary architecture is illustrated, in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, depending on the implementation, the high-speed links 440-443 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the fundamental principles of the invention are not limited to any particular communication protocol or throughput.

[0096] Additionally, in one embodiment, two or more of GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 4A All communication between the various system components shown can be achieved using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the fundamental principle of the invention is not limited to any particular type of interconnect technology.

[0097] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and non-limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3DXPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory, and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0098] As described below, although the various processors 405-406 and GPUs 410-413 can be physically coupled to specific memories 401-402 and 420-423 respectively, a unified memory architecture can be achieved, in which the same virtual system address space (also known as the "effective address" space) is distributed across all the physical memories. For example, processor memories 401-402 can each include 64GB of system memory address space, and GPU memories 420-423 can each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0099] Figure 4B Additional details are shown regarding the interconnection between a multi-core processor 407 and a graphics acceleration module 446 according to an exemplary embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 and the processor 407 may be integrated in the same package or on the same chip.

[0100] The processor 407 shown includes multiple cores 460A-460D, each having a translational backstop 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetching units, branch prediction units, decoders, execution units, reordering buffers, etc.), which are not shown to avoid obscuring the fundamental principles of the invention. Caches 462A-462D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in a cache hierarchy and shared by multiple sets of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and graphics accelerator integrated module 446 are connected to the system memory 441, which may include processor memories 401-402.

[0101] Consistency of data and instructions stored in various caches 462A-462D, 456 and system memory 441 is maintained via inter-core communication through a coherence bus 464. For example, each cache may have associated cache coherency logic / circuit to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to listen for cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the fundamental principles of the invention.

[0102] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to join cache coherence protocols as a core peer. Specifically, interface 435 provides connectivity to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0103] In one implementation, accelerator integrated circuit 436 represents multiple graphics processing engines 431, 432, N of graphics acceleration module 446 to provide cache management, memory access, context management, and interrupt management services. Graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and bit engines. In other words, the graphics acceleration module can be a GPU with multiple graphics processing engines 431-432, N, or graphics processing engines 431-432, N can be individual GPUs integrated on a common package, line card, or chip.

[0104] In one embodiment, accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. MMU 439 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective to physical / real address translation. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431-432, N. In one embodiment, data stored in cache 438 and graphics memories 433-434, N is kept consistent with core caches 462A-462D, 456 and system memory 411. As mentioned, this can be achieved via proxy circuit 425, which represents cache 438 and memories 433-434, N to participate in cache coherency mechanisms (e.g., sending updates to cache 438 (related to modifications / accesses to cache lines on processor caches 462A-462D, 456) and receiving updates from cache 438).

[0105] A set of registers 445 stores context data for threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages the thread context. For example, context management circuitry 448 can perform save and restore operations during context switching to save and restore the context of various threads (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 448 can store the current register value into a region of memory (e.g., identified by a context pointer). It can then restore the register value upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from the system device.

[0106] In one implementation, the MMU 439 translates the virtual / effective address from the graphics processing engine 431 into a real / physical address in system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executing on processor 407, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which the resources of graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). These resources may be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with those VMs and / or applications.

[0107] Therefore, the accelerator integrated circuit 436 acts as a bridge to the system for the graphics acceleration module 446, and provides address translation and system memory caching services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage interrupts, memory management, and the virtualization of the graphics processing engine.

[0108] Because the hardware resources of graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of graphics processing engines 431-432, N, so that they appear as independent units to the system.

[0109] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are coupled to each of the graphics processing engines 431-432, N, respectively. Graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. Graphics memories 433-434, M can be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0110] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433-434, M is the data that will be used most frequently by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to store the data required by the cores (and preferably not graphics processing engines 431-432, N) in system memory 411 and the caches 462A-462D, 456 of the cores.

[0111] Figure 4C Another exemplary embodiment is shown, in which the accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via interface 437 and interface 435 (which again can utilize any form of bus or interface protocol) through high-speed link 440. The accelerator integrated circuit 436 can perform operations targeting... Figure 4B The operations described are the same, but potentially at higher throughput due to their close proximity to the coherence bus 462 and caches 462A-462D, 426.

[0112] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0113] In one embodiment of the dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process within a single operating system. A single application can funnel requests from other applications to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0114] In a dedicated process programming model, the graphics processing engine 431-432,N can be shared by multiple VM / application partitions. This shared model requires a hypervisor to virtualize the graphics processing engine 431-432,N to allow access by each operating system. For single-partition systems without a hypervisor, the graphics processing engine 431-432,N is owned by the operating system. In both cases, the operating system can virtualize the graphics processing engine 431-432,N to provide access to each process or application.

[0115] For a shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in system memory 441 and is addressable using the effective address to real address translation technique described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431-432, N (that is, calling system software to add the process element to the process element list). The lower 16 bits of the process handle may be the offset of the process element within the process element list.

[0116] Figure 4D An exemplary accelerator integration slice 490 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application-effective address space 482 within system memory 441 stores process elements 483. In one embodiment, process element 483 is stored in response to a GPU invocation 481 from an application 480 executing on processor 407. Process element 483 contains the process state of the corresponding application 480. A job descriptor (WD) 484 contained in process element 483 may be a single job requested by the application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application's address space 482.

[0117] The graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all or a subset of processes in the system. Embodiments of the invention include infrastructure for setting process states and sending WD484 to the graphics acceleration module 446 to initiate operations in a virtualized environment.

[0118] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 446 or an individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owned partition, and the operating system initializes the accelerator integrated circuit 436 for the owned process.

[0119] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an instruction for the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 may be stored in register 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 446, as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 may handle interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the MMU 439 translates the effective address 493 generated by the graphics processing engines 431-432, N into a real address.

[0120] In one embodiment, the same set of registers 445 is copied for each graphics processing engine 431-432, N, and / or graphics acceleration module 446, and this set of registers 445 can be initialized by a hypervisor or the operating system. Each of these copied registers can be included in the accelerator integration slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0121] Table 1 - Registers for Supervisor Initialization

[0122] 1 Slice Control Register 2 Real Address (RA) Scheduled Process Region Pointer 3 Permission masking overwrite register 4 Interruption vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) management accelerator utilizes record pointers 9 Storage description register

[0123] Table 2 shows exemplary registers that can be initialized by the operating system.

[0124] Table 2 - Registers for Operating System Initialization

[0125] 1 Process and thread identifiers 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual address (VA) accelerators utilize record pointers 4 Virtual address (VA) memory segment table pointer 5 Access masking 6 Job descriptor

[0126] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information required by the graphics processing engine 431-432, N to complete its work, or it may be a pointer to a memory location of a command queue in which a task has been set up to be completed.

[0127] Figure 4E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 498 in which a list of process elements 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496, which virtualizes the graphics acceleration module engine for operating system 495.

[0128] The shared programming model allows all processes or subsets of processes from all partitions or partitions in the system to use the graphics acceleration module 446. Two programming models exist where the graphics acceleration module 446 is shared by multiple processes and partitions: time-slice sharing and graphics-directed sharing.

[0129] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. For the graphics acceleration module 446 to support virtualization performed by the hypervisor 496, the graphics acceleration module 446 must meet the following requirements: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 446 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 446 must guarantee the completion of application job requests within a specified timeframe (including any transition failures), or the graphics acceleration module 446 must provide the ability to preempt job processing. 3) When operating in a directed shared programming model, fairness of the graphics acceleration module 446 among processes must be guaranteed.

[0130] In one embodiment, for the shared model, application 480 is required to make an operating system 495 system call using the graphics acceleration module 446 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the targeted acceleration function used for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Optionally, the hypervisor 496 may apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 483. In one embodiment, CSRP is one of the registers 445 that contains the effective address of a region in the applied address space 482 for use by the graphics acceleration module 446 to save and restore the context state. This pointer is optional if saving state between jobs or when a job is preempted is not required. The context save / restore region may be pinned system memory.

[0131] Upon receiving a system call, the operating system 495 verifies that application 480 has been registered and granted permission to use the graphics acceleration module 446. Then, the operating system 495 uses the information shown in Table 3 to invoke the hypervisor 496.

[0132] Table 3 – OS to Hypervisor Call Parameters

[0133] 1 Working Descriptor (WD) 2 The Authority Masking Register (AMR) value is potentially masked. 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual address (VA) accelerators utilize record pointers (AURP). 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interruption Service Number (LISN)

[0134] Upon receiving a hypervisor call, hypervisor 496 verifies that operating system 495 is registered and has been granted permission to use graphics acceleration module 446. Then, hypervisor 496 places process element 483 into the process element list corresponding to the graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0135] Table 4 - Process Element Information

[0136] 1 Working Descriptor (WD) 2 The Authority Masking Register (AMR) value is potentially masked. 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual address (VA) accelerators utilize record pointers (AURP). 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interruption Service Number (LISN) 8 Interrupt vector table exported from the hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) management accelerator utilizes record pointers 12 Storage Device Descriptor Register (SDR)

[0137] In one embodiment, the hypervisor initializes multiple accelerator integration slice 490 registers 445.

[0138] like Figure 4F As shown, an exemplary embodiment of the invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. This distributes the entire virtual / effective memory space (sometimes referred to as the effective address space) across each of processor memories 401-402 and GPU memories 420-423, thereby allowing any processor or GPU to access any physical memory (using a virtual address mapped to that memory).

[0139] In one embodiment, the bias / coherence management circuitry 494A-494E within one or more of the MMUs 439A-439E ensures cache coherence between the host processor (e.g., 405) and the cache of the GPUs 410-413, and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Although Figure 4FSeveral instances of bias / coherence management circuitry 494A-494E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0140] One embodiment allows the use of shared virtual memory (SVM) technology to access and map GPU-attached memories 420-423 as part of system memory without suffering the typical performance drawbacks associated with full system cache coherence. The ability of GPU-attached memories 420-423 to be accessed as system memory without the heavy overhead of cache coherence provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory access. Meanwhile, the ability to access GPU-attached memories 420-423 without cache coherence overhead can be critical for the execution time of offloaded computations. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offloading.

[0141] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure comprising 1 or 2 bits per GPU-attached memory page (i.e., controlled at the memory page level). The bias table can be implemented in the stolen memory range of one or more GPU-attached memories 420-423, where GPUs 410-413 may or may not have a bias cache (e.g., for caching frequently / recently used entries in the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0142] In one implementation, the bias table entries associated with each access to the GPU-attached memory 420-423 are accessed before the actual access to GPU memory, thereby prompting the following operations: First, local requests from GPUs 410-413 to find their pages in the GPU bias are directly forwarded to the corresponding GPU memory 420-423. Local requests from GPUs to find their pages in the host bias are forwarded to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, a request from processor 405 to find the requested page in the host processor bias completes like a normal memory read request. Alternatively, requests for pages for GPU bias can be forwarded to GPUs 410-413. Then, if the GPU is not currently using the page, the GPU can redirect the page to the host processor bias.

[0143] The page bias state can be changed by software-based mechanisms, hardware-assisted software-based mechanisms, or purely hardware-based mechanisms for a limited set of cases.

[0144] One mechanism for changing the bias state uses an API call (e.g., OpenCL), which in turn invokes the GPU's device driver, which then sends a message (or enqueue command descriptor) to the GPU, instructing it to change the bias state and perform a cache flushing operation in the host for some transitions. The cache flushing operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0145] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that are not cacheable by the host processor 405. To access these pages, the processor 405 may request access from the GPU 410, which may or may not grant access immediately (depending on the implementation). Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are those requested by the GPU but not by the host processor 405 (and vice versa).

[0146] Graphics processing pipeline

[0147] Figure 5 A graphics processing pipeline 500 according to an exemplary embodiment is shown. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein (such as the parallel processor 200 of FIG. 2), in one embodiment which is Figure 1Variations of the parallel processor(s) 112. Various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of parallel processing units as described herein (e.g., parallel processing unit 202 of FIG. 2). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3) can be configured to perform the functions of one or more of the vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers (506, 514, 518), tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines and corresponding partitioning units (e.g., partitioning units 220A-220N of FIG. 2) within a processing cluster (e.g., processing cluster 214 of FIG. 3). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 in FIG2) via a memory interface 528, which may be an instance of memory interface 218 of FIG2.

[0148] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light up and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data, and the vertex processing unit 504 can be programmed to transform the vertex data from an object-based coordinate representation to world space coordinate space or normalized device coordinate space.

[0149] The first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads stored vertex attributes as needed and constructs graphical primitives for processing by tessellation control processing unit 508. Graphical primitives include triangles, segments, points, patches, etc., supported by various graphics processing application programming interfaces (APIs).

[0150] The tessellation control processing unit 508 treats input vertices as control points for a geometric patch. These control points are transformed from an input representation of the patch (e.g., the patch's basis) to a representation suitable for use by the tessellation evaluation processing unit 512 in surface evaluation. The tessellation control processing unit 508 can also calculate tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantize the level of detail for dependent views associated with those edges. The tessellation unit 510 is configured to receive tessellation factors for the edges of the patch and subdivide the patch surface into multiple geometric primitives, such as lines, triangles, or quadrilaterals, which are then passed to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parametric coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with a geometric primitive.

[0151] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512 (which reads stored vertex attributes on demand) and constructs graphic primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphic primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphic primitives into one or more new graphic primitives and compute parameters for rasterizing the new graphic primitives.

[0152] In some embodiments, the geometry processing unit 516 may add or remove elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphic primitives to the primitive assembler 518. The primitive assembler 518 receives parameters and vertices from the geometry processing unit 516 and constructs graphic primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for use when processing geometric data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling, and outputs the processed graphic primitives to the rasterizer 522.

[0153] Rasterizer 522 can perform depth picking and other depth-based optimizations. Rasterizer 522 also performs scan transformations on new graphic primitives to generate fragments and outputs those fragments and associated overlay data to fragment / pixel processing unit 524. Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform the following operations to produce shaded fragments or pixels output to raster operation unit 526, including but not limited to texture mapping, shading, blending, texture correction, and perspective correction. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. Fragment or pixel shader programs can be configured to shade at samples, pixels, tiles, or other granularities, depending on the sampling rate configured for the processing unit.

[0154] Raster operation unit 526 is a processing unit that performs raster operations, including but not limited to stencil printing, z-testing, blending, etc., and outputs pixel data as processed graphic data for storage in a graphics memory (e.g., parallel processor memory 222 as shown in FIG2 and / or such as...). Figure 1 The data is stored in the system memory 104, and thus displayed on the one or more display devices 110, or further processed by one or more parallel processors 112 or one or more processors 102. In some embodiments, the raster operation unit 526 is configured to compress z or color data written to the memory and decompress z or color data read from the memory.

[0155] Machine Learning Overview

[0156] Machine learning algorithms are algorithms that can learn from datasets. Implementations of machine learning algorithms can be designed to model high-level abstractions within the dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output numerical values ​​given an input; and pattern recognition algorithms can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0157] A demonstrative type of machine learning algorithm is the neural network. There are many types of neural networks; a simple type is the feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology consists of an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. Network nodes are fully connected via edges to nodes in adjacent layers, but there are no edges between nodes within a single layer. Data received at the nodes in the input layer of the feedforward network is propagated (i.e., "fedforward") to the nodes in the output layer via an activation function that calculates the state of each node in each successive layer of the network based on coefficients ("weights") associated with each edge connecting the layers. Depending on the specific model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0158] Before a machine learning algorithm can be used to model a specific problem, it is trained using a training dataset. Training a neural network involves selecting a network topology, using a set of training data representing the problem being modeled by the network, and adjusting the weights until the network model performs with minimum error on all instances of the training dataset. For example, during supervised learning training of a neural network, the network's output in response to instances in the training dataset is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize the error signal as it propagates back through the network layers. The network is considered "trained" when the error in the outputs generated for each instance from the training dataset is minimized.

[0159] The accuracy of machine learning algorithms can be significantly affected by the quality of the dataset used to train them. The training process can be computationally intensive and may take a considerable amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed in adjusting the coefficients in the neural network naturally facilitate parallel implementation. Specifically, many machine learning algorithms and software applications are well-suited to utilizing parallel processing hardware within general-purpose graphics processing units.

[0160] Figure 6This is a general diagram of the machine learning software stack 600. Machine learning application 602 can be configured to train neural networks using training datasets or to achieve machine intelligence using trained deep neural networks. Machine learning application 602 may include training and inference functionalities for neural networks and / or dedicated software that can be used to train neural networks prior to deployment. Machine learning application 602 can achieve any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0161] Hardware acceleration for machine learning applications 602 can be enabled via machine learning framework 604. Machine learning framework 604 provides a library of machine learning primitives. Machine learning primitives are fundamental operations commonly performed by machine learning algorithms. Without machine learning framework 604, developers of machine learning algorithms would need to create and optimize the main computational logic associated with their algorithms, and then re-optimize that logic when developing new parallel processors. Instead, machine learning applications can be configured to use the primitives provided by machine learning framework 604 to perform the necessary computations. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). Machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines, such as matrix and vector operations, performed by many machine learning algorithms.

[0162] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate input for the computing framework 606. The computing framework 606 can extract low-level instructions provided to the GPGPU driver 608, enabling the machine learning framework 604 to utilize hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to have in-depth knowledge of the GPGPU hardware 610's architecture. Furthermore, the computing framework 606 can implement hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610.

[0163] GPGPU Machine Learning Acceleration

[0164] Figure 7 A highly parallel general-purpose graphics processing unit (GPGPU) 700 is illustrated according to an exemplary embodiment. In one embodiment, the GPGPU 700 can be configured to be particularly efficient in handling the type of computational workload associated with training deep neural networks. Additionally, the GPGPU 700 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster to improve training speed for specific deep neural networks.

[0165] The GPGPU 700 includes a host interface 702 for connecting to a host processor. In one embodiment, the host interface 702 is a Fast PCI interface. However, the host interface can also be a vendor-specific communication interface or communication structure. The GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute the execution threads associated with those commands to a group of compute clusters 706A-H. The compute clusters 706A-H share a cache memory 708. The cache memory 708 can act as a higher-level cache for the cache memory within the compute clusters 706A-H.

[0166] The GPGPU 700 includes memory 714A-B coupled to computing clusters 706A-H via a set of memory controllers 712A-B. In various embodiments, memory 714A-B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory. In one embodiment, memory cells 224A-N may also include 3D stacked memory, including but not limited to high-bandwidth memory (HBM).

[0167] In one embodiment, each computing cluster 706A-H includes a set of graphics multiprocessors, for example Figure 4A The graphics multiprocessor 400 of the computing cluster includes various types of integer and floating-point logic units that can perform computational operations within a certain precision range suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating-point units in each of the computing clusters 706A-H can be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units can be configured to perform 64-bit floating-point operations.

[0168] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanisms used for synchronization and data exchange in this computing cluster vary depending on the embodiment. In one embodiment, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 707 that couples GPGPU 700 to GPU link 710, which enables direct connections to other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 reside in an independent data processing system and communicate via a network device accessible via host interface 702. In one embodiment, in addition to host interface 702 or as an alternative to host interface 702, GPU link 710 can be configured to enable connectivity to a host processor.

[0169] While the illustrated configuration of the GPGPU 700 can be configured to train neural networks, one embodiment provides alternative configurations of the GPGPU 700 that can be configured for deployment within high-performance or low-power inference platforms. In the inference configuration, the GPGPU 700 includes fewer compute clusters 706A-H compared to the training configuration. Additionally, the memory technology associated with the memories 714A-B can differ between the inference and training configurations. In one embodiment, the inference configuration of the GPGPU 700 can support inference-specific instructions. For example, the inference configuration can support one or more 8-bit integer dot product instructions typically used during inference operations on a deployed neural network.

[0170] Figure 8 A multi-GPU computing system 800 according to an exemplary embodiment is shown. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-D via a host interface switch 804. In one embodiment, the host interface switch 804 is a fast PCI switch device that couples the processor 802 to a fast PCI bus through which the processor 802 can communicate with a group of GPGPUs 806A-D. Each of the plurality of GPGPUs 806A-D may be... Figure 7 An example of the GPGPU700. The GPGPU 806A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. These high-speed GPU-to-GPU links can be connected via dedicated GPU links (such as...). Figure 7The P2P GPU link 816 connects to each of the GPGPUs 806A-D via GPU link 710. P2P GPU link 816 enables direct communication between each of the GPGPUs 806A-D without requiring communication on the host interface bus to which the processor 802 is connected. Utilizing the GPU-to-GPU traffic routed to the P2P GPU link, the host interface bus can still be used for system memory access or, for example, communication with other instances of the multi-GPU computing system 800 via one or more network devices. While in the illustrated embodiment, the GPGPUs 806A-D are connected to the processor 802 via host interface switch 804, in one embodiment, the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A-D.

[0171] Machine learning neural network implementation

[0172] The computational architectures provided by the embodiments described herein can be configured to perform the kind of parallel processing particularly well-suited for training and deploying neural networks for machine learning. Neural networks can be broadly categorized as networks that function as graph relationships. As is well known in the art, there are various types of neural network implementations used in machine learning. An exemplary type of neural network is the feedforward network, as previously described.

[0173] The second exemplary type of neural network is the Convolutional Neural Network (CNN). CNNs are specialized feedforward neural networks designed for processing data with known grid-like topologies, such as image data. Therefore, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by the receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computation for a CNN involves applying convolutional mathematics to each filter to produce its output. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function to the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer could be data from a multidimensional array defining various color components of an input image. The convolution kernel could be the parameters of a multidimensional array, where these parameters are adapted for the neural network by the training process.

[0174] Recurrent Neural Networks (RNNs) are a family of feedforward neural networks that include feedback connections between layers. RNNs enable modeling sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. A loop represents the effect of the current value of a variable on its own value at future times, because at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature in which language data can be composed.

[0175] The diagrams described below present exemplary feedforward, CNN, and RNN networks, and describe the general processes for training and deploying each of those types of networks respectively. It will be understood that these descriptions are illustrative and non-limiting regarding any particular embodiment described herein, and the concepts shown can generally be applied to deep neural networks and machine learning techniques in general.

[0176] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning that uses deep neural networks. The deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers, as opposed to shallow neural networks that only include a single hidden layer. Deeper neural networks are typically more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which leads to a reduction in output error compared to shallow machine learning techniques.

[0177] Deep neural networks used in deep learning typically include a front-end network coupled to a back-end network for performing feature recognition. This back-end network represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without requiring manual feature engineering of the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be fed to a mathematical model, which can map the detected features to the output. The mathematical models used by the network are generally specific to the task at hand, and different models will be used to perform different tasks.

[0178] Once a neural network is constructed, a learning model can be applied to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Error backpropagation is a common method used to train neural networks. An input vector is presented to the network for processing. The network's output is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then backpropagated until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using algorithms such as stochastic gradient descent to update the neural network's weights.

[0179] Figures 9A-9B This demonstrates an exemplary convolutional neural network. Figure 9A This illustrates the various layers within a CNN. (For example, in...) Figure 9A The exemplary CNN shown here, used for modeling image processing, can receive input 908, which describes the red, green, and blue (RGB) components of the input image. Input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from the multiple convolutional layers can optionally be processed by a set of fully connected layers 908. Neurons in fully connected layers have full connections to all activations in previous layers, as previously described for feedforward networks. The output from fully connected layers 908 can be used to generate output from the network. Activations within fully connected layers 908 can be computed using matrix multiplication instead of convolution. Not all CNN implementations utilize fully connected layers 906. For example, in some implementations, convolutional layers 906 are capable of generating output for the CNN.

[0180] Convolutional layers are sparsely connected, unlike the configuration found in fully connected layers (908) of traditional neural networks. Traditional neural network layers are fully connected, causing each output unit to interact with every input unit. However, as shown, convolutional layers are sparsely connected because the output of a field's convolution is the input to nodes in subsequent layers (rather than the corresponding state value of each node in the field). The kernels associated with convolutional layers perform convolution operations, and their outputs are fed to the next layer. Dimensionality reduction performed within convolutional layers is one aspect that enables CNNs to scale to handle large images.

[0181] Figure 9B This illustrates a demonstrative computational stage within a convolutional layer of a CNN. The input to convolutional layer 912 of the CNN can be processed in three stages of convolutional layer 914. These three stages can include convolutional stage 916, detector stage 918, and pooling stage 920. Convolutional layer 914 can then output data to successive convolutional layers. The final convolutional layer of the network can generate output feature map data or provide input to fully connected layers, for example, to generate classification values ​​from the input to the CNN.

[0182] In convolutional stage 916, convolutional layers 914 can perform several convolutions in parallel to produce a set of linear activations. Convolutional stage 916 can include affine transformations, which are any transformations that can be specified as linear transformations plus translations. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolutional stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron computes the dot product between the neuron's weights and the regions in its local input to which the neuron is connected. The output from convolutional stage 916 defines a set of linear activations processed by successive stages of convolutional layers 914.

[0183] Linear activations can be processed by detector-level 918. In detector-level 918, each linear activation is processed by a nonlinear activation function. This nonlinear activation function increases the nonlinearity of the overall network without affecting the corresponding fields of the convolutional layers. Several types of nonlinear activation functions can be used. One specific type is the Rectified Linear Unit (ReLU), which is defined as... The activation function is such that the activation threshold is zero.

[0184] Pooling stage 920 uses a pooling function that replaces the output of convolutional layer 906 with a summary statistic of nearby outputs. Pooling functions can be used to introduce translation invariance into neural networks, ensuring that small translations of the input do not change the pooling output. Local translation invariance can be useful in scenarios where the presence of features in the input data is more important than the precise location of those features. Various types of pooling functions can be used during pooling stage 920, including max pooling, average pooling, and L2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations replace an additional convolutional stage with an increased stride relative to the preceding convolutional stage.

[0185] The output from convolutional layer 914 can then be processed by the next layer 922. The next layer 922 can be either an additional convolutional layer or a fully connected layer 908. For example, Figure 9A The first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer of the fully connected layer 908.

[0186] Figure 10An exemplary recurrent neural network 1000 is shown. In a recurrent neural network (RNN), the network's previous states influence the output of the network's current state. RNNs can be constructed in various ways using various functions. The use of RNNs generally revolves around using mathematical models to predict the future based on a prior sequence of inputs. For example, given a previous word sequence, an RNN can be used to perform statistical language modeling to predict an upcoming word. The RNN 1000 shown can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 that implements recursion, a feedback mechanism 1005 that enables 'memory' of previous states, and an output layer 1006 that outputs the result. The RNN 1000 operates based on time steps. The state of the RNN at a given time step is influenced by previous time steps via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input of the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x1). Given a state, it can be computed as... Where U and W are parameter matrices. The function f is generally nonlinear, such as the hyperbolic tangent function (Tanh) or the rectified function. A variation of the RNN 1000. However, the specific mathematical functions used in hidden layer 1004 can vary depending on the specific implementation details of the RNN 1000.

[0187] In addition to the basic CNN and RNN networks described, variations on these networks can be enabled. An example RNN variant is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies, which is necessary for processing longer language sequences. A variation of CNNs is the Convolutional Deep Trust Network, which has a similar structure to CNNs and is trained in a similar manner. Deep Trust Networks (DBNs) are generative neural networks consisting of multiple layers of probabilistic (random) variables. DBNs can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining the optimal initial set of weights for the neural network.

[0188] Figure 11 Demonstration training and deployment of deep neural networks are shown. Once a given network has been constructed for the task, the neural network is trained using a training dataset 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6The machine learning framework 604 can be configured as a training framework 604. The training framework 604 can hook into an untrained neural network 1106 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1108.

[0189] To begin the training process, initial weights can be selected randomly or by using pre-training of a deep trust network. Then, training loops are performed in a supervised or unsupervised manner.

[0190] Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training dataset 1102 includes inputs paired with the expected output of the input, or when the training dataset includes inputs with known outputs and the output of the neural network is manually graded. The network processes the inputs and compares the resulting output with a set of expected or desired outputs. The error is then backpropagated through the system. The training framework 1104 can be tuned to adjust the weights controlling the untrained neural network 1106. The training framework 1104 can provide tools to monitor the extent to which the untrained neural network 1106 converges to a model suitable for generating correct responses based on known input data. The training process iterates as the network weights are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches the statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0191] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training dataset 1102 will include input data without any associated output data. An untrained neural network 1106 can learn groupings within the unlabeled input and can determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate self-organizing graphs, which are a class of trained neural networks 1108 capable of performing operations useful for dimensionality reduction of data. Unsupervised training can also be used to perform anomaly detection, allowing the identification of data points in the input dataset that deviate from the normal patterns of the data.

[0192] Variations regarding supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1102 comprises a mixture of labeled and unlabeled data with the same distribution. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled within the network during the initial training.

[0193] Whether supervised or unsupervised, training, especially for deep neural networks, can be computationally too intensive for a single computing node. Instead of using a single computing node, a distributed network of computing nodes can be used to accelerate the training process.

[0194] Figure 12 This is an exemplary block diagram illustrating distributed learning. Distributed learning is the training of a neural network model using multiple distributed computing nodes to perform supervised or unsupervised training. Distributed computing nodes may each include one or more host processors and one or more general-purpose processing nodes, such as... Figure 7 The highly parallel general-purpose graphics processing unit 700 is used. As shown, distributed learning can be a combination of the model-parallel structure 1202, the data-parallel structure 1204, or the model-and-data-parallel structure 1206 performed.

[0195] In the model-parallel architecture 1202, different computing nodes in a distributed system can perform training computations on different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes in the distributed system. Benefits of the model-parallel architecture include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables the training of very large neural networks where the weights of all layers would not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0196] In the data-parallel architecture 1204, different nodes in a distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different methods are possible for data-parallel architectures, all data-parallel training methods require techniques to combine the results and synchronize the model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data-parallel architectures. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data-parallel architectures are similar to parameter averaging, except that updates to the model are transmitted, rather than transmitting parameters from nodes to a parameter server. Furthermore, update-based data-parallel architectures can be implemented in a distributed manner, where updates are compressed and transmitted between nodes.

[0197] The combined model and data-parallel architecture 1206 can be implemented, for example, in a distributed system where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with independent GPUs within each node used to train different parts of the model.

[0198] Distributed training incurs increased overhead compared to training on a single machine. However, the parallel processors and GPGPUs described in this paper can each implement various techniques to reduce the overhead of distributed training, including techniques for achieving high-bandwidth GPU-to-GPU data transfer and accelerating remote data synchronization.

[0199] Exemplary machine learning applications

[0200] Machine learning can be applied to solve a wide range of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Traditionally, computer vision has been one of the most active research areas for machine learning applications. The scope of computer vision applications ranges from reproducing human visual abilities (such as facial recognition) to creating new categories of visual abilities. For example, a computer vision application can be configured to identify sound waves from vibrations evoked by objects visible in a video. Parallel processors accelerate machine learning, enabling computer vision applications to be trained on significantly larger training datasets than previously feasible and allowing inference systems to be deployed using low-power parallel processors.

[0201] Parallel processors accelerate machine learning for autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described in this paper enable rapid training of increasingly complex neural networks for autonomous driving solutions and facilitate the deployment of low-power inference processors suitable for integration into mobile platforms within autonomous vehicles.

[0202] Parallel processors accelerate deep neural networks to enable machine learning methods for automatic speech recognition (ASR). ASR involves creating functions that, given an input speech sequence, compute the most probable language sequence. Accelerated machine learning using deep neural networks has replaced previously used Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) for ASR.

[0203] Parallel processors can accelerate machine learning and also be used to accelerate natural language processing. Automated learning procedures can leverage statistical inference algorithms to generate models robust to errors or unfamiliar inputs. Exemplary natural language processor applications include automated machine translation between human languages.

[0204] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include... Figure 7 Highly parallel general-purpose graphics processing unit 700 and Figure 8The multi-GPU computing system 800. In contrast, the deployed machine learning platforms generally include lower-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0205] Figure 13 An exemplary inference system-on-a-chip (SOC) 1300 suitable for performing inference using a trained model is shown. SOC 1300 may integrate processing components including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. SOC 1300 may additionally include on-chip memory 1305, which can implement a shared on-chip data pool accessible to each of the processing components. The processing components can be optimized for low-power operation to enable deployment on various machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of SOC 1300 can be used as part of the main control system of an autonomous vehicle. When SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards governing the deployment.

[0206] During operation, the media processor 1302 and the vision processor 1304 can work together to accelerate computer vision operations. The media processor 1302 can perform low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video when they are ready to be processed using a trained image recognition model. For example, the vision processor 1304 can accelerate convolution operations for a CNN used to perform image recognition on high-resolution video data, while the back-end model computation is performed by the GPGPU 1306.

[0207] The multi-core processor 1308 may include control logic to assist in the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor to execute software applications that can utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may directly issue computational workloads to the GPGPU 1306 or may offload computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0208] The GPGPU 1306 may include compute clusters, such as low-power configurations of compute clusters 706A-706H within the highly parallel general-purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 can support instructions specifically optimized for performing inference computations on trained neural networks. For example, the GPGPU 1306 can support instructions for performing low-precision computations such as 8-bit and 4-bit integer vector operations.

[0209] Figure 14 An exemplary image capture system for an image capture device is illustrated. In some embodiments, the image capture device is a standalone device, such as a digital camera. In other embodiments, the image capture device is part of or a sub-component of another computing device that requires image capture capability, such as a portable or handheld computing device with a digital camera for capturing images. In exemplary embodiments, the image capture device is integrated with convolutional neural network (CNN) computational processing, such as a deep learning neural network (DNN), which can provide DNN data in real time or simultaneously with or at the same time as image capture and storage performed by the image capture device. Thus, the image capture device disclosed herein can provide both image and color information, as well as deep machine learning information such as feature detection using a CNN.

[0210] Figure 14 An exemplary diagram is also shown, illustrating the storage of RGB and CNN channel data as part of a depth channel image. The exemplary system is shown as having a depth channel camera 1400 and a depth channel memory 1420. The depth channel camera 1400 includes a color sensor 1402 and an FPGA unit 1404. The color sensor 1402 includes multiple sensors arranged in an array to capture color data of an image 1403A. Image 1403A can be an RGB image or a YUV image. The color sensor 1402 outputs image values ​​or data to the depth channel memory 1420 and the FPGA unit 1404.

[0211] A color sensor can be any type of light sensor, photodetector, CMOS sensor, or pixel array, having a light sensor array to detect the light energy that forms a color image captured by the color sensor array. Alternatively, a color sensor can be configured to detect non-color images. Data or values ​​for each color component form an independent output channel, such as RGB color channels 1414.

[0212] In one embodiment, the output of the color sensor array 1402 is the input to a programmed neural network 1406 in the FPGA 1404. The network can be any type of network with any number of convolutional layers and nodes at each layer, capable of performing actions such as those described in [the context of...]. Figure 9A and 9BThe exemplary embodiments disclose neural network processing. In other examples, hardwired circuitry or programmable logic arrays (PLAs) can be used instead of FPGA 1404, where the neural network is programmed or hardwired in the corresponding circuitry or array in the same manner. In other embodiments, FPGA 1404 can be used as in... Figure 6 The hardware acceleration described in the document is used for programming machine learning applications 602, machine learning framework 604, and computing framework 606.

[0213] In one embodiment, FPGA unit 1404 is programmed with a standard very deep CNN, such as the Visual Geometric Group (VGG) CNN, labeled as standard VGG network 1406. In other embodiments, other types of CNNs, such as DNNs, can be programmed in FPGA unit 1404 as disclosed herein. In this example, VGG network 1406 is programmed with five (5) convolutional layers labeled “Conv1” through “Conv5”. Each convolutional layer Conv2 through Conv5 includes a data “pool” that provides summary statistics of nearby outputs. In other embodiments, any number of convolutional layers can be used, including a single convolutional layer. Each Conv1 through Conv5 layer performs a convolution operation, providing feature map data or filtered images labeled “Conv1 data” through “Conv5 data”. In this feedforward CNN network, the output of each convolutional layer is passed to the next layer until the final prediction layer 1425. At prediction layer 1425, classification 1430 can be performed, such as determining the type of an image based on CNN processing and CNN data.

[0214] The depth channel memory 1420 stores image 1403B for RGB channels 1414 derived from image 1403A. Data for Conv1 (1410A) to Conv5 (1410E) is stored for CNN channels 1418. In this embodiment, each convolutional channel Conv1 to Conv5 represents a CNN channel with five channels for CNN channel 1418. The data for Conv1 (1410A) to Conv5 (1410E) can be different filtered images or feature maps of image 1403A, depending on the convolutional processing performed at each layer. In the depth channel memory 1420, images for RGB color channels 1414 and CNN channels are stored in adjacent memories or cascaded together.

[0215] Deep learning with discriminative semantic transfer and physics-inspired optimization

[0216] As in Figure 12 and 14In the context described above, deep learning networks have multiple nodes spanning several different domains. Given an input image, this describes a deep learning-based classification model that can handle pixel-by-pixel scene parsing in a specific domain. Specifically, this domain-specific pixel-by-pixel scene parsing (e.g., predicting pixel-by-pixel wall-to-floor, wall-to-wall, and wall-to-ceiling edges, especially in cluttered interior scenes) differs significantly from convolutional domain scene parsing (e.g., pixel-by-pixel object classification or segmentation). Furthermore, the data used to train such a specific task is very limited (only a few thousand levels) and severely imbalanced.

[0217] refer to Figures 15 to 18G The following examples and embodiments disclose a technique that provides good transfer across multiple domains and addresses severely imbalanced training data with only a very limited number of samples (only a few thousand levels). The disclosed technique can be considered in three aspects: (1) integrating the relationship between scene clutter in one domain and room layout in another domain into a formula within a convolutional neural network (CNN) (room layout is an example, and the technique can be applied to other types of domains); (2) a lightweight CNN architecture that can be trained end-to-end using a 3-level incremental training method; and (3) a practical strategy for initializing the weights for very deep CNNs under a limited and imbalanced training data distribution.

[0218] These publicly disclosed techniques are optimized using a reasoning scheme termed physics-inspired optimization in this paper, where room layout estimation is formulated to naturally integrate observed characteristics of the phenomenon into a mechanics concept. For example, two theoretically elegant and practically easily optimized techniques are presented, striking a clever balance between efficiency and accuracy, thus demonstrating leading accuracy and real-time processing speed. Using these techniques, from the perspective of a purely optimization task, room layout estimation can be flexibly cast and solved compared to mainstream methods that primarily rely on computationally intensive proposal and reordering strategies.

[0219] The disclosed technique can be used as part of a room layout estimation system, operating with an overwhelming margin in speed and accuracy compared to other estimation systems designed for machine / deep learning and computer vision in artificial intelligence. The described discriminative semantic transfer technique has broad applications, including but not limited to image classification, pixel-by-pixel scene parsing, semantic image segmentation, object detection, room layout estimation, and robot localization and tracking. It can also be applied to any kind of semantic transfer task in contexts other than deep learning or convolutional learning methods.

[0220] (introduce)

[0221] Semantic transfer (ST) has three characteristics that offer three distinct perspectives: (1) as a discriminative model, it integrates the relationship between room layout and scene clutter into the FCN. (2) as an architecture, it benefits from end-to-end training. (3) as a training strategy, it provides better network initialization and allows training of very deep networks under imbalanced training data distributions. Therefore, semantic transfer offers highly robust features across all sorts of different scenarios.

[0222] Semantic transfer and physics-inspired optimization techniques are discussed below. Figure 15-18G As detailed below. The numbers in parentheses refer to named citations identified in the following quotation paragraphs.

[0223] Given an input RGB image, the room layout estimation algorithm should output all wall-to-floor, wall-to-wall, and wall-to-ceiling edges (e.g., by...). Figure 15 (Description). This is a fundamental indoor scene understanding task because it provides strong prior knowledge for other tasks such as depth recovery from a single RGB image shown in references [6] and [7] or pose estimation of indoor objects shown in references [9],

[22] and

[23] . Furthermore, room layout itself provides a high-level representation of indoor scenes for emerging applications such as intelligent robotics and augmented reality. The problem has garnered sustained attention due to the publication of the groundbreaking work described in reference

[11] , and has two lines of followers:

[0224] like Figure 15 As shown in the upper part, the conventional approach follows a proposal-ranking scheme. Typically, the proposal part consists of three sub-modules: edge detection, vanishing point voting, and ray sampling. Utilizing handcrafted features and structured reasoning techniques, the ranking part sometimes outputs the optimal layout proposal along with a messy representation.

[0225] The recent methods disclosed in references [3],

[17] , and

[27] achieve remarkable performance improvements via features generated by fully convolutional networks (FCNs). References

[17] and

[27] also still follow the traditional proposal-ranking scheme. Reference [3] is a proposal-free approach in which all those steps related to proposal generation are eliminated. And instead of proposal-ranking, in reference [3], inference is implemented through an optimization module.

[0226] refer to Figure 15 Above the dashed line, the figure depicts an overview of conventional methods, and below the dashed line, the figure depicts an overview of the disclosed techniques using semantic transfer and physically inspired optimization.

[0227] Conventional methods. Conventional methods offer many useful insights into understanding interior scenes. For example, reference

[11] and other references [4], [5],

[20] ,

[21] ,

[25] and

[29] explore different ways to model the relationship between room layout and scene clutter. This input is reasonable because the main challenge in room layout estimation lies in this. For example, returning to reference Figure 15 More than 50% of the wall-floor edge pixels are obscured by the bed. If the bed were not present, the task could be simplified. However, these insights have not been addressed in recent work on FCN-based room layout estimation. For example, recent work treats the FCN as a black box when designing the network, without considering scene clutter information. Because modeling meaningful concepts using neural networks is always difficult, the techniques presented explore the possibility of describing scene clutter within the FCN.

[0228] The FCN-based approach. Unlike references

[17] and

[27] , which still follow the proposal-ranking scheme, reference [3] presents a framework with attractive compactness. However, its optimization is primitive, in which the sampled solution space is exhaustively searched without gradient modeling. Thus, the disclosed technique provides a principled, gradient-based, and efficient optimization algorithm and process for deep networks.

[0229] The disclosed examples and embodiments provide a semantic transfer (ST) technique that includes three features from three different perspectives: (1) as a distinguishing model, the disclosed ST technique integrates the relationship between room layout and scene clutter into the FCN. (2) as an architecture, the disclosed ST technique enjoys the benefits of end-to-end training. (3) as a training strategy, the disclosed ST technique provides better network initialization and allows training of very deep networks under imbalanced training data distributions. The disclosed ST technique provides highly robust features in all kinds of situations.

[0230] Furthermore, to address the computational redundancy hidden within these features, the disclosed examples and embodiments also propose a Physically Inspired Optimization (PIO) technique. The disclosed ST and PIO techniques play distinct but closely interdependent roles, as the core idea of ​​PIO is to use mechanical concepts to formulate a phenomenon observed in the ST feature map.

[0231] (Related work)

[0232] Conventional methods. These methods follow the standard definition of room layout estimation, which is introduced by reference

[11] . Based on the well-known Manhattan hypothesis described in reference [2], such estimation causes edges to cluster into lines that connect at three vanishing points. Ray sampling has been used, and many proposals have also been published. Handcrafted features are used to learn the regressor for the proposal ranking. Other works attempt to improve the framework. For example, reference

[19] detects connections instead of edges and modifies proposal generation and ranking accordingly. When ranking room layouts, reference

[25] simultaneously estimates clutter masking. Reference

[21] aims to improve the inference efficiency of methods like reference

[25] . In addition to estimating clutter masking, reference

[20] also estimates 3D bounding boxes of objects and room layouts during inference. In addition to the learned clutter representation, reference [4] incorporates prior knowledge of furniture shapes. In reference [5], furniture is modeled using parts instead of boxes. Reference

[29] goes further by modeling furniture relationships using scene grammar. These references form a good tradition of utilizing the relationship between room layout and scene clutter. However, these conventional methods are lacking in recent FCN-based approaches.

[0233] FCN-based methods. Recently, reference

[17] describes training an FCN for pixel-wise edge markers, where each pixel is assigned a marker from the four-class set S {background(bg), wall-floor edge(wf), wall-wall edge(ww), wall-ceiling edge(wc)}.

[0234] (1)

[0235] The activations of the final layer are incorporated into the regular inference framework as features. Reference [3] uses another formula where each pixel can be assigned a label from a 5-class set {floor, left wall, middle wall, right wall, ceiling}. This 5-class formula has a fuzziness problem because the patterns of the three types of walls are essentially indistinguishable. FCN is coordinate invariant because the convolutional layer actually performs a sliding window search, so it is not suitable for informing the difference between the left and right walls. Thus, reference [3] uses an additional fuzziness clarification step. Reference

[27] uses two formulas for FCN training. These FCN-based works show remarkable performance improvements, but their inference schemes remain conventional or primitive. It is possible to design more principled and efficient inference schemes by leveraging robust FCN features.

[0236] More extensive literature. Such literature describes other scene understanding tasks that are broadly the same or similar to room layout estimation. For example, reference

[18] attempts to understand layouts with horizons, urban scenes, corridors, and other natural scenes for which room layout estimation is only a special case. Another special case of reference

[18] is outdoor urban layout estimation, as described in references [1] and

[13] . Such estimations are often considered as graphical applications in the name of photo pop-ups and evaluated using subjective user studies. Reference

[14] attempts to recover room layouts in more detail than boxes and evaluates them using wall-floor edge errors. Because these works utilize the techniques built upon by reference

[11] , these references may therefore potentially benefit from the examples and embodiments disclosed herein.

[0237] Similar concepts to ST and PIO. Looking at even the broader literature, concepts somewhat similar to ST and PIO have been discussed. Under the guise of label transfer, references

[16] and

[28] address semantic segmentation in a nonparametric manner. ST differs from such literature primarily as a unified deep architecture (and certainly in terms of its parametric nature). Reference [8] and its successors are known for describing human limbs as springs. PIO differs from such literature primarily as an efficient approximation inspired by mechanical concepts.

[0238] (Semantic transfer)

[0239] Examples and implementations of the disclosed semantic transfer (ST) technology include, for example Figure 16 As shown in the diagram, it is proposed. In one embodiment, the ST technique is proposed in level 3. For ease of understanding, level four (which is the inference stage) can be considered as the inference stage, which is the ultimate goal of FCN—i.e., pixel-by-pixel edge marking. Figure 16 The four-panel diagram illustrates the extraction of four pixel-wise activation maps from the input image, each corresponding to a label from S (set 1). For example, in the wf activation map, a higher color temperature indicates a higher probability of wf being present.

[0240] refer to Figure 16 The top part depicts the probabilistic node connectivity in our formula, while the bottom part depicts the semantic transfer (ST) in the three levels. Level 1 refers to the pre-trained semantic segmentation. Level 2 refers to the edge classification using pixel-wise semantic features. Level 3 refers to the fine-tuning of end-to-end edge labeling. In Level 3, the pre-trained network refers to the one outlined by the dashed box in Level 1. In Level 4, the pixel-wise edge labeling network refers to the one outlined by the dashed box in Level 3.

[0241] Figure 17 This is a diagram of a network design for semantic segmentation, semantic transfer, semantic feature space, and transfer weight visualization based on an exemplary embodiment. Figure 17 The results are divided into four parts (a) through (d). Part (a) shows the network design for ST in level one. Part (b) shows the qualitative results of semantic segmentation on the LSUN dataset. Part (c) shows a visualization of the unsupervised structure of the semantic feature space. Part (d) shows a visualization of the semantic weights. For one embodiment, LSUN does not provide ground truth for semantic segmentation for quantitative evaluation. Regarding... Figure 17 The different parts, top left, top right, bottom left and bottom right, can be called background (bg), wall-to-floor edge (wf), wall-to-wall edge (ww) and wall-to-ceiling edge (wc).

[0242] Figure 18A The image on the left of the feature quality visualization is shown. From top to bottom: input, bg activation, wf activation, ww activation, wc activation, softmax result. The right side shows the feature quality comparison. In this example, each feature map is numerically normalized independently. For one embodiment, the feature maps produced by these disclosed techniques can be processed in the style described in reference

[17] .

[0243] In one embodiment, at level one, an FCN can be trained on 37 semantic segmentation classes on the SUNRGBD dataset to maximize the description of cluttered scenes. These 37 classes can cover most of the objects and furniture that typically appear in indoor scenes, such as walls, ceilings, chairs, or windows. The FCN can be built on the recently introduced architecture ResNet-101, as described in reference

[10] .

[0244] refer to Figure 17 Part (a) can utilize the aperture mechanism described in reference

[15] (in the name of dilated convolution in reference

[26] ) to perform net surgery on the last two groups of bottlenecks in the original ResNet-101. The input to this network (RGB image) is actually a random variable X taking values ​​from [0, 255]. X is determined by a hidden random variable Y taking values ​​from semantic labels [1, 37]. Thus, the network describes the posterior distribution P(Y|X).

[0245] In Level 2, the LSUN room layout dataset is fed through a semantic segmentation network to generate pixel-by-pixel 37-channel semantic features. As an indoor scene understanding dataset, the model trained on SUNRGBD generalizes well on LSUN. (Reference) Figure 17Part (b) shows the qualitative results of LSUN, which are generated entirely by softmax operations without post-processing techniques such as conditional random fields. Each pixel is then treated as a sample, and fully connected layers can be learned to bridge the gap between the 37-channel semantic features and the four-class edge markers. To demonstrate that the semantic features are discriminative for this task, standard unsupervised analysis can be implemented using t-SNE, as described in reference

[24] . References Figure 17 Part (c) shows samples of wall-ceiling edges (wc) and wall-floor edges (wf) forming distinct clusters in the embedded space. Some samples of wall-wall edges (ww) and background (bg) are also scattered among each other. In this level, Y is determined by a hidden random variable Z that takes values ​​from edge markers as described in references [1] and [4] (set 1). Thus, this fc layer describes the posterior distribution P(Z|Y).

[0246] P(Z|Y) is a parameterized representation of the relationship between room layout and scene clutter. Unlike pioneering work, the disclosed technique models this relationship directly in a neural network. This is inspired by the understanding of room layout. Figure 16 The Level 2 panel illustrates how the network in Level 1 extracts 37 channels of semantic features from the scene. Only the top stacked channels are fully shown, and these channels correspond to windows. This channel can roughly indicate the location and extent of three windows in the scene. The examples and embodiments disclosed, illustrating how the human brain resolves room layout from semantic features like these, assume decisions based on rules such as: wall-floor edges cannot pass through windows, therefore they are unlikely to appear in areas with high window scores.

[0247] To verify this hypothesis, for one embodiment, the transfer weights can be visualized in the fully connected (FC) layer. These weights can be learned independently 100 times and organized as shown in... Figure 17 The diagram is shown in section (d). Unsurprisingly, the semantic features of the wall, floor, and ceiling channels contribute the most to ww, wf, and wc, respectively. Generally, smaller boxes with higher scores indicate stronger relevance. Taking wc as an example, besides the ceiling, the top four transition weights are cabinet, picture, sofa, and whiteboard.

[0248] Based on common scenarios, cabinets, pictures, and whiteboards tend to appear in the corresponding field of the wc pixel because they are tall in the vertical direction in physical space. Sofas are usually lower, so their variation (described by the frame size) is twice that of pictures. Whiteboards are rare, which explains why their variation is also large.

[0249] In Level 3, for one embodiment, the learned 37×4 fully connected (FC) layer is reshaped into a 1×1×37×4 convolutional layer and added on top of the network trained in Level 1. For one embodiment, the weights from Level 1 act as feature extractors, and the weights from Level 2 act as classifiers. The weights can form a pixel-wise edge labeling network, described as P(Z|Y)P(Y|X)=P(Z|X). On one hand, this network can be fine-tuned end-to-end on LSUN for edge labeling, the ultimate goal mentioned at the beginning of this section. On the other hand, it elegantly incorporates the relationship between scene clutter and room layout, which is a factor in the disclosed technique.

[0250] Besides end-to-end training and cluttered scene modeling, semantic transfer offers the advantage of better initialization for extremely imbalanced training data. Using ResNet FCN ( Figure 17 Part (a) of the network directly trains the pixel-wise edge marker network, which can be done without ST. However, the output of the first batch normalization (BN) layer is prone to overflow, leading to training failure. The training problem is also reported in section 3.2 of

[17] , which describes that the network must be pre-trained on NYUd2 and pre-trained on PASCAL, which leads to poor results. This problem can be caused by the extremely imbalanced distribution of edge markers. Figure 16 As shown in the second-level panel, over 99% of the markers are background. Similar to the classic approach of initializing the autoencoder using multiple restricted Boltzmann machines (see, for example, reference

[12] ), the disclosed pixel-wise edge marker network is initialized in the first two levels such that ST overflow is no longer observed. In one embodiment, the connectivity of the probability nodes is determined by… Figure 16 The upper part is shown.

[0251] (optimization)

[0252] In one embodiment, the disclosed pixel-by-pixel edge labeling network produces highly robust features in all types of scenarios, such as those generated by... Figure 18A The left panel is visualized as shown. Samples can be collected from the LSUN test set, thus covering different types of scene clutter, layout configurations, and lighting conditions. For one embodiment, feature quality comparisons can be provided for failure cases cited

[17] , as by Figure 18A As shown in the right panel of Figure 18-1. The three scenes in Figure 18-1 are challenging because almost all edge pixels are obscured by clutter such as sofas, tables, or beds. Reference networks

[17] that do not take into account the relationship between room layout and scene clutter fail to extract reliable edge features compared to publicly available networks and techniques that properly handle them.

[0253] As by Figure 18AAs illustrated, in one embodiment, it is possible to directly estimate the room layout using image processing techniques on these features. Qualitative results can be good by applying a Hough transform to the weakened softmax result. However, using a series of image processing modules for inference is not a good choice because many threshold parameters related to weakening or the Hough transform must be tuned. Instead, an optimized parametric layout can be used.

[0254] Figure 18B This is a topology diagram of room layouts from a test set based on an exemplary embodiment. The diagram can illustrate a sixth topology cut from the LSUN specification representation having those characteristics. The disclosed techniques propose two distinct implementations: Naive Optimization (NO) and Physically Inspired Optimization (PIO).

[0255] (Symbols and Formulas)

[0256] Topology. For one embodiment, there can be 11 different possible room layout topologies in a 2D image, as demonstrated in the supplementary material. We denote them as T. i (i∈[1,11]).

[0257] Connection. In one embodiment, each topology can be connected via an edge connection set. And parameterization, where each P ij As 2D coordinates and nC as the number of connections.

[0258] Edges. In one embodiment, connectivity can be determined by an edge set. Define , where nE is the edge number. S is set 1.

[0259] Taking the sixth topology as an example ( Figure 18B ), parameterized representation is and Since nC=6 and nE=5.

[0260] Edge marker diagram. For one embodiment, P i and E i It can be converted into a pixel-by-pixel edge marker map, which is similar to... Figure 15 The output is similar to that in [the previous section]. This transformation is represented as [the current one]. And we will omit E from here on. i Because it is for a certain topology T i No change. When a certain connection P ij When considering, refer to the join set P. i and M[P ij When generating graph M, you can also use M[P]i C is implemented by assigning corresponding tags from S (set 1) to the pixels between two connections.

[0261] In one embodiment, the features generated by the pixel-by-pixel edge marking network are represented as follows: In one embodiment, M and F l All have the same size as the input image, indicated by (w,h). For one embodiment, the consistency objective (CO) and its corresponding energy format (e) can be defined with respect to (w,h):

[0262] (2)

[0263] (3)

[0264] in, If Then set the pixel to one, otherwise set it to zero, and generate a binary mask from M. For each different topology T i In one embodiment, the optimal parameterization representation P i It can be found by minimizing e:

[0265] (4)

[0266] In most cases, starting with a right-hand topology leads to the lowest energy value, while an incorrect topology results in a higher energy value. Failure cases do exist, and we will visualize them later. For one embodiment, the optimized implementation detailed below starts from P. i Average state initialization of the set (e.g.) Figure 18B The one shown in the left image (of the image).

[0267] (Naive optimization)

[0268] In one embodiment, when solving equation 4, a possible solution is obtained by adjusting P near the initialization state. i Sampling and full search to generate P with the lowest e i To simulate the scheme presented in reference [3]. The method in reference [3] does not model any gradients and has a constrained solution space. In contrast, a gradient-based optimization module can be built that iteratively approaches the right layout from the average initialization. For one embodiment, NO can be calculated and implemented as follows:

[0269] (5)

[0270] (6)

[0271] (7)

[0272]

[0273] Where α is the scaling factor and ∆ x (= ∆ y ) is the window size. For joins at image boundaries (e.g., Figure 18B P in the left figure 62 ), can be achieved by using ∆ P ij The corresponding component is set to zero to impose additional constraints. In one embodiment, if the connection is moved to an image corner, ∆ P ij This is considered a special case to allow the connection to move to another boundary or simply remain at that corner. NO's convergence performance can be good, but it is very slow, so we introduce PIO as an efficient alternative.

[0274] (Analysis and Motivation)

[0275] For one embodiment, the efficiency bottleneck of NO can be analyzed. When calculating equation 5 (and similarly equation 6),

[0276] (8)

[0277] (9)

[0278] Figure 18C This is a diagram illustrating a room, a feature map, and the effects of force composition in an input image, according to an exemplary embodiment. The feature map is constructed by treating the edges as springs and the feature map as a potential field, and by relating the forces applied at each point of the springs. (Reference) Figure 18C , (ag) ;(ah) ;(ai) (b) and (c / d) are the input images. If we consider the edges as springs and the feature map as a potential field, then the force applied to each point of the spring is related. (e / f) The effect of force composition. In Equation 9, m and n can be omitted; their meaning is explained in Equation 2. Calculation It is an efficiency bottleneck, which means The gradient, and intuitively we use Figure 18C To explain part (a) (l=2, because the wall-floor edge is the second marker from S, set 1). It actually subtracts two pixel-wise masks, where Depend on Figure 18C AI shows and Depend on Figure 18C ag is shown.

[0279] In one embodiment, M is generated by transforming C. In another embodiment, C can be implemented by iterating through each pixel to determine its label. In another embodiment, the ratio of w and h can be indicated by N, and the complexity of this implementation (hereinafter referred to as NOA) is for each computation of equation 5 or 6. O ( N 2 This can run on an image for tens of minutes.

[0280] In one implementation, the improved C implementation (hereinafter referred to as NOB) calculates the pixel coordinates between two joins and directly accesses the corresponding mask elements. Its complexity is O(N), and it runs for approximately 30 seconds on an image. The idea of ​​further reducing the complexity to O(1) led us to introduce PIO.

[0281] In one embodiment, each edge is considered as a spring that can translate, rotate, and change its length. In NO, the movement of the edges is determined by each pixel on them, but there is computational redundancy. (As per...) Figure 18C As shown in parts (c) and (d), the feature map can be used as a potential field to analyze how points on the edge move. Unsurprisingly, their movement is not independent and can originate from both endpoints of the edge (which is Q). ka and Q kb The moving coarse interpolation of ). For one embodiment, based on this observation, it can be used in P i Instead The gradient defined above is used to approximate ∆ P ij Because of the connection P i The number of _n_C_ is constant, and the complexity is O(1). This is the first key concept of PIO.

[0282] Force composition is the second key concept in PIO. For example, by... Figure 18C As shown in part (e), considering the endpoints of edges j and k instead of every point on them, they will move toward a local minimum state. This will be corrected by calculating the movement of edge 1 (see [reference]). Figure 18C In part (f), another feature map (wall-wall edge) will be used as the potential field. Therefore, the movement of each connection should be determined by the force applied to each edge connected to that connection. Clearly, adding two gradient vectors (such as...) Figure 18C and Figure 18C The parts (e) and (f) in the equation naturally follow the parallelogram law of force composition.

[0283] (Physics-inspired optimization)

[0284] For the first concept, a new consistency target can be defined for each endpoint of the edge. :

[0285] (10)

[0286] (11)

[0287] As a hint, the meanings of E and F are explained at the beginning of this chapter.

[0288] Calculating the gradient at a point in a potential field is simple, as follows:

[0289] (12)

[0290] (13)

[0291] (14)

[0292] In this physics-inspired optimization, Considered as being applied to the spring-shaped edge E ik endpoint Q ka The force on the surface. As for the second concept of force composition, we define... E i A subset of. And when considering different edges, apply to P ij The force on can be expressed as .thereby The following can be used to approximate it:

[0293] (15)

[0294]

[0295] As mentioned earlier, Equation 15 naturally follows the parallelogram law of force composition. In potentially chaotic situations, and All calculations are based on Equation 14 (k is E). i The index in and o is E i subset of (Index in). And to summarize, the efficiency of PIO mainly comes from the O(1) complexity of Equation 10, while that of Equation 2 is at least O(N) (NOB).

[0296] Figure 18D Left: Qualitative results on the LSUN validation set. The visualized feature maps merge wf, ww, and wc through pixel-wise maximization operations, but they are used independently in PIO. Right: Typical failure cases where the faulty topology produces the lowest energy.

[0297] Method ep(%) ec(%)

[0298] Hedau et al. (2009)

[11] 24.23 15.48

[0299] Mallya et al. (2015)

[17] 16.71 11.02

[0300] Dasgupta et al. (2016) [3] 10.63 8.20

[0301] Ren et al. (2016)

[27] 7.57 5.23

[0302] Our 5.29 3.84

[0303] Table 1: Qualitative Results of the LUSUN Test Set

[0304] (experiment)

[0305] LSUN results

[0306] LSUN is a room layout estimation dataset consisting of 4000 training iterations, 394 validation iterations, and 1000 maintenance test samples. Two standard metrics are used for evaluation: (1) e conner The corner (connection) error is P. i The Euclidean distance between the estimated coordinates and the ground truth. Because of resolution diversity, e conner Normalized by the length of the image diagonal. (2) e pixel By using P i Convert to like Figure 18D The mask representation, such as the ground truth in the image, is used to measure the pixel error as the ratio of incorrectly labeled pixels to all pixels. (For e) pixel To address the issue of blurred markers, LSUN's official evaluation code automatically maximizes overlap.

[0307] For large-scale evaluations, both metrics are averaged on the images. On the validation set, the official evaluation code provided by the LSUN committee is used. Third-party evaluation results for the test set are reported in Table 1. Regarding the two metrics, the proposed method outperforms conventional methods

[11] and FCN-based methods

[17] [3]

[27] . Qualitative results and failure cases on the validation set are provided by […]. Figure 18D exhibit.

[0308] Figure 18D The left side shows an example of qualitative results regarding the LSUN validation set when wf, ww, and wc are merged through a pixel-wise maximization operation on the visualized feature map, according to an exemplary embodiment. The right side shows a typical failure case where an erroneous topology produces the lowest energy, according to an exemplary embodiment. Reference Figure 18DPart (a) shows a typical simplified case where most edge pixels are visible and the feature map accurately captures their positions. In one embodiment, the visualized edge map is temporarily distorted near the 30th iteration due to force composition, and PIO eventually aligns it with the true layout.

[0309] Figure 18D Parts (b)-(d) show that the feature map cannot accurately locate the edge where the black circle is located, resulting in a relatively high e. conner Some of these situations are due to various reasons, such as severe occlusion (b), insufficient feature map resolution (c), and misleading textures (d).

[0310] Method ep(%)

[0311] Hedau et al. (2009)

[11] 21.20

[0312] Del Pero et al. (2013) [5] 12.70

[0313] Mallya et al. (2015)

[17] 12.83

[0314] Dasgupta et al. (2016) [3] 9.73

[0315] Ren et al. (2016)

[27] 8.67

[0316] Our 6.60

[0317] Table 2: Qualitative Results of the Hedau Test Set

[0318] NOB PIO

[0319] artpf(s) 35.41 1.79

[0320] ep(%) 5.42 5.48

[0321] ec(%) 3.88 3.95

[0322] Table 3: Average runtime for each frame (artpf) comparison

[0323] refer to Figure 18D In part (e), if we consider the cabinets as part of the wall, the room is no longer strictly framed. In fact, those separate wall-ceiling edges are successfully captured by the feature map and aligned via PIO. However, the annotation protocol treats the cabinets as occlusions. Figure 18DPart (f) illustrates a case of severe occlusion. In one embodiment, semantic transfer allows the network to infer the existence of a wall-floor edge behind the bed, but the connection in the black circle is not accurately located.

[0324] Although not 100% accurate, Figure 18D Parts (a)-(f) in the output are considered success cases because the output topology is correct. Figure 18D The parts (g)-(h) in the diagram are two typical failure cases, where the faulty topology produces the lowest energy. Figure 18D The failure in part (g) is caused by overfitting. The network infers that there is a wall-floor edge behind the bed, but the annotation protocol does not. Figure 18D The section (h) illustrates another type of failure caused by structural ambiguity. Furthermore, the scenario is no longer a strict box because some sections of the walls protrude outwards. The network identifies these as ceilings, but the annotation protocol does not, resulting in PIO displaying an incorrect topology.

[0325] (Hedau results)

[0326] The Hedau dataset is presented in reference

[11] , consisting of 209 training samples and 105 test samples. On the Hedau test set, for one embodiment, a model trained with the LSUN training set can be directly evaluated. Figure 18E The left side shows an example of qualitative results regarding the Hedau validation set when wf, ww, and wc are merged through a pixel-wise maximization operation on the visualized feature map, according to an exemplary embodiment. Figure 18E As shown, the model extracts reliable features across datasets. Consistent with the literature, pixel error can be a quantitative measure. The disclosed technique can report better results than conventional methods like those described in references [5] and

[11] and FCN-based methods like those in references [3],

[17] and

[27] (Table 2). The overall pixel error on the Hedau test set (6.60%) is higher than that on the LSUN test set (5.29%), because the ground truth annotated by the Hedau dataset is more rigorous (usually by...). Figure 18E Part (j) is shown in the middle.

[0327] (Hyperparameters and efficiency)

[0328] In Algorithm 2, whether e decreases is determined by a threshold of 10⁻⁶. This threshold is related to the numerical scalability of e. During implementation, for one embodiment, due to equivalence, e = -CO instead of e = exp(-CO), and the numerical scalability of e is approximately -15, which has already been shown in the video mentioned above. (2) The scaling factor α is adaptive to ensure that the length of the gradient (force) is between 1 and 3. This limits the connection to only a small movement in one iteration, as shown in the video. (3) Window size The impact was evaluated on the LSUN validation set, and the quantitative results were obtained by... Figure 18F exhibit. Figure 18F This is a graph of error vs. window size on the LSUN validation set according to an exemplary embodiment. Both metrics show an increasing trend as the window size increases from 1 pixel to 10 pixels. This is not surprising because PIO can be viewed as an alignment algorithm, as computing gradients in larger window sizes leads to a weaker ability to accurately capture local structures.

[0329] For one embodiment, the average runtime per frame on the LSUN validation set can be evaluated using NOB and PIO. NOA was not evaluated due to its unsolvability. The results are provided in Table 3, showing that PIO provides a significant speedup for NOB without causing a noticeable decrease in accuracy. The evaluation can be implemented using MATLAB, and the disclosed techniques can be used with real-time applications.

[0330] Figure 18G This is a diagram comparing two techniques for physics-inspired optimization based on exemplary embodiments. Specifically, Figure 18G This illustrates a comparison between naive and physics-inspired optimization. The optimization operations are presented as steps, and squares indicate operations within five boxes. The first two boxes, ST features and tie-point coordinates, are the inputs for both processes. The third box, the energy objective, is performed for both steps 1. The next operation, labeled step 3, is as follows: The two optimizations differ in that the gradient operations, as described above, are different. The remaining operations are updates and repetitions until the optimization is complete.

[0331] (Summarize)

[0332] The disclosed examples and embodiments implement alternative methods for room layout estimation. Reliable edge features can be extracted across various scenarios using a very deep semantic transfer FCN. A novel inference scheme inspired by mechanical concepts is also provided. The effectiveness of the disclosed methods can be demonstrated through extensive quantitative experiments on public datasets.

[0333] (Quote)

[0334] References [1] through

[29] cited in this detailed description are identified as follows.

[0335] [1] Fast automatic singleview 3-d reconstruction of urban scenes, published by O. Barinova, V. Konushin, A. Yakubenko, K. Lee, H. Lim and A. Konushin in ECCV, March 2008.

[0336] [2] JM Coughlan and AL Yuille published Manhattanworld: Compass direction from a single image by bayesian inference in ICCV in February 1999.

[0337] [3] S. Dasgupta, K. Fang, K. Chen and S. Savarese. Delay: Robust spatial layout estimation for cluttered indoor scenes. Published in CVPR in January, February, March, August, November and December 2016.

[0338] [4] L. Del Pero, J. Bowdish, D. Fried, B. Kermgard, E. Hartley and K. Barnard. Geometric modeling of indoor scenes, Bayesian, published at CVPR on February 3, 2012.

[0339] [5] L. Del Pero, J. Bowdish, B. Kermgard, E. Hartley and K. Barnard, in their paper "Understanding Bayesian Rooms Using Composite 3D Object Models", published in CVPR in February, March and December 2013.

[0340] [6] D. Eigen and R. Fergus published their paper "Predicting depth, surface normals and semantic labels with a common multiscale convolutional architecture" at CVPR in January 2015.

[0341] [7] D. Eigen, C. Puhrsch, and R. Fergus published in NIPS in January 2014, Depth mapprediction from a single image using a multi-scale deep network.

[0342] [8] Pictorial structures for object recognition, published by PF Felzenszwalb and DP Huttenlocher in IJCV in March 2005.

[0343] [9] Aligning 3d models to rgb-d images of cluttered scenes, S. Gupta, P. Arbelaez, R. Girshick and J. Malik, presented at CVPR in January 2015.

[0344]

[10] K. He, X. Zhang, S. Ren and J. Sun, Deepestial learning for image recognition, published at CVPR in May 2016.

[0345]

[11] V. Hedau, D. Hoiem and D. Forsyth, Recovering the spatial layout of cluttered rooms, presented at CVPR 2009.

[0346]

[12] GE Hinton and RRSalakhutdinov published in Science in June 2006, "Reducing the dimensionality of data with neural networks".

[0347]

[13] D. Hoiem, AA Efros and M. Hebert, Recovering surface layout from an image, published in IJCV in March 2007.

[0348]

[14] Geometric reasoning for single image structure recovery, presented by DC Lee, M. Hebert and T. Kanade in CVPR in March 2009.

[0349]

[15] C. Liang-Chieh, P. George, K. Iasonas, M. Kevin and LY Alan published in ICLR in May 2015, Semantic image segmentation with deep convolutional nets and fully connected crfs.

[0350]

[16] C. Liu, J. Yuen and A. Torralba, Nonparametric scene parsing: Label transfer via dense scene alignment, published in CVPR in March 2009.

[0351]

[17] A. Mallya and S. Lazebnik’s Learning informative edge maps for indoor scene layout prediction, published in ICCV in January, February, March, May, June, November and December 2015.

[0352]

[18] Depthinformation by stage classification, published by V. Nedovic, AW Smeulders, A. Redert and J.-M. Geusebroek in ICCV, March 2007.

[0353]

[19] Manhattanjunction catalogue for spatial reasoning of indoor scenes, presented by S. Ramalingam, JK Pillai, A. Jain and Y. Taguchi at CVPR in February 2013.

[0354]

[20] AG Schwing, S. Fidler, M. Pollefeys and R. Urtasun, Box in the box: Joint 3d layout and object reasoning from singleimages, published at ICCV on February 3, 2013.

[0355]

[21] AG Schwing, T. Hazan, M. Pollefeys and R. Urtasun published Efficient structured prediction for 3d indoor scene understanding at CVPR on February 3, 2012.

[0356]

[22] S. Song and J. Xiao published Deep slidingshapes for amodal 3d object detection in rgb-d images in CVPR in January 2016.

[0357]

[23] S. Song and J. Xiao published Sliding shapes for 3d object detection in depth images in ECCV in January 2014.

[0358]

[24] Visualizing data using t-sne, published by L. Van der Maaten and G. Hinton in the Journal of Machine Learning Research in May 2008.

[0359]

[25] H. Wang, S. Gould and D. Koller published Discriminative learning with latent variables for cluttered indoor scene understanding in ECCV on February 3, 2010.

[0360]

[26] F. Yu and V. Koltun, Multi-scale context aggregation by dilated convolutions, published in ICLR in May 2016.

[0361]

[27] R. Yuzhuo, C. Chen, L. Shangwen and KC-C. Jay published a coarse-to-fine indoor layout estimation (cfile) method in ACCV in January, February, March, November and December 2016.

[0362]

[28] H. Zhang, J. Xiao and L. Quan published "Supervisedlabel transfer for semantic segmentation of street scenes" in ECCV in March 2010.

[0363]

[29] Y. Zhao and S.-C. Zhu published Scene parsing by integrating function, geometry and appearance models at CVPR on February 3, 2013.

[0364] Overview of the graphics system

[0365] Figure 19 This is a block diagram of a processing system 1900 according to an exemplary embodiment. In various embodiments, system 1900 includes one or more processors 1902 and one or more graphics processors 1908, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1902 or processor cores 1907. In one embodiment, system 1900 is a processing platform integrated within a system-on-a-chip (SoC) integrated circuit for use by mobile devices, handheld devices, or embedded devices.

[0366] Embodiments of system 1900 may include, or may incorporate within, the following: a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1900 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. Data processing system 1900 may also include, be coupled to, or be integrated within, wearable devices, such as smartwatches, smart glasses, augmented reality devices, or virtual reality devices. In some embodiments, data processing system 1900 is a television or set-top box device having one or more processors 1902 and a graphical interface generated by one or more graphics processors 1908.

[0367] In some embodiments, one or more processors 1902 each include one or more processor cores 1907 for processing instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 1907 is configured to process a particular instruction set 1909. In some embodiments, the instruction set 1909 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). Multiple processor cores 1907 may each process different instruction sets 1909, which may include instructions for facilitating emulation of other instruction sets. Processor cores 1907 may also include other processing means, such as digital signal processors (DSPs).

[0368] In some embodiments, processor 1902 includes cache memory 1904. Depending on the architecture, processor 1902 may have a single internal cache or multi-level internal caches. In some embodiments, cache memory is shared among various components of processor 1902. In some embodiments, processor 1902 also uses external caches (e.g., level 3 (L3) caches or last-level caches (LLCs)) (not shown), which can be shared among processor cores 1907 using known cache coherence techniques. Register file 1906 is additionally included in processor 1902, and the register file may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general-purpose registers, while others may be specific to the design of processor 1902.

[0369] In some embodiments, processor 1902 is coupled to processor bus 1910 to transmit communication signals (such as address, data, or control signals) between processor 1902 and other components in system 1900. In one embodiment, system 1900 uses an exemplary 'hub' system architecture, including memory controller hub 1916 and input / output (I / O) controller hub 1930. Memory controller hub 1916 facilitates communication between memory devices and other components of system 1900, while I / O controller hub (ICH) 1930 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller hub 1916 is integrated within the processor.

[0370] Memory device 1920 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or any other memory device with suitable performance to serve as process memory. In one embodiment, memory device 1920 may function as system memory for system 1900 to store data 1922 and instructions 1921 for use when the one or more processors 1902 execute an application or process. Memory controller hub 1916 is also coupled to an optional external graphics processor 1912, which may communicate with one or more graphics processors 1908 in processors 1902 to perform graphics and media operations.

[0371] In some embodiments, ICH 1930 enables peripherals to connect to memory device 1920 and processor 1902 via a high-speed I / O bus. I / O peripherals include, but are not limited to: an audio controller 1946, a firmware interface 1928, a wireless transceiver 1926 (e.g., Wi-Fi, Bluetooth), a data storage device 1924 (e.g., hard disk drive, flash memory, etc.), and a conventional I / O controller 1940 for coupling conventional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1942 connect input devices, such as a keyboard and mouse combination 1944. A network controller 1934 may also be coupled to ICH 1930. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1910. It will be appreciated that the illustrated system 1900 is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, the I / O controller hub 1930 may be integrated within one or more processors 1902, or the memory controller hub 1916 and the I / O controller hub 1930 may be integrated into a discrete external graphics processor (such as external graphics processor 1912).

[0372] Figure 20 This is a block diagram of an exemplary embodiment of a processor 2000, which has one or more processor cores 2002A-2002N, an integrated memory controller 2014, and an integrated graphics processor 2008. Figure 20Those elements having the same reference numerals (or names) as elements in any other figure herein are capable of operating or functioning in any manner similar to, but not limited to, those described elsewhere herein. Processor 2000 may include, and include, additional cores 2002N, indicated by dashed boxes. Each of processor cores 2002A-2002N includes one or more internal cache units 2004A-2004N. In some embodiments, each processor core also has access to one or more shared cache units 2006.

[0373] Internal cache units 2004A-2004N and shared cache unit 2006 represent cache memory hierarchies within processor 2000. A cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level cache preceding external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 2006 and 2004A-2004N.

[0374] In some embodiments, the processor 2000 may further include a set of one or more bus controller units 2016 and a system agent core 2010. The one or more bus controller units 2016 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, Fast PCI). The system agent core 2010 provides management functionality for various processor components. In some embodiments, the system agent core 2010 includes one or more integrated memory controllers 2014 to manage access to various external memory devices (not shown).

[0375] In some embodiments, one or more of the processor cores 2002A-2002N include support for simultaneous multithreading. In such an embodiment, the system agent core 2010 includes components for coordinating and operating the cores 2002A-2002N during multithreaded processing. The system agent core 2010 may additionally include a power control unit (PCU) including logic and components for regulating the power states of the processor cores 2002A-2002N and the graphics processor 2008.

[0376] In some embodiments, processor 2000 further includes a graphics processor 2008 for performing graphics processing operations. In some embodiments, graphics processor 2008 is coupled to a set of shared cache units 2006 and a system proxy core 2010 (including one or more integrated memory controllers 2014). In some embodiments, display controller 2011 is coupled to graphics processor 2008 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 2011 may be a separate module coupled to graphics processor via at least one interconnect, or it may be integrated within graphics processor 2008 or system proxy core 2010.

[0377] In some embodiments, a ring-based interconnect unit 2012 is used to couple the internal components of the processor 2000. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art, may be used. In some embodiments, the graphics processor 2008 is coupled to the ring interconnect 2012 via I / O link 2013.

[0378] Exemplary I / O link 2013 represents at least one of a variety of I / O interconnects, including on-package I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2018 (such as eDRAM modules). In some embodiments, each of processor cores 2002A-2002N and graphics processor 2008 uses embedded memory modules 2018 as a shared final-level cache.

[0379] In some embodiments, processor cores 2002A-2002N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 2002A-2002N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 2002A-2002N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 2002A-2002N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, processor 2000 can be implemented on one or more chips or implemented as a SoC integrated circuit having, among other components, the components shown.

[0380] Figure 21This is a block diagram of a graphics processor 2100, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 2100 includes a memory interface 2114 for accessing memory. The memory interface 2114 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0381] In some embodiments, the graphics processor 2100 further includes a display controller 2102 for driving display output data to the display device 2120. The display controller 2102 includes a composition of multi-layer video or user interface elements and hardware for one or more overlapping planes of the display. In some embodiments, the graphics processor 2100 includes a video codec engine 2106 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Decoding (AVC) formats (such as H.264 / MPEG-4 AVC), and SMPTE 421M / VC-1, and Joint Picture Experts Group (JPEG) formats, such as JPEG and Motion JPEG (MJPEG).

[0382] In some embodiments, graphics processor 2100 includes a block image transfer (BLIT) engine 2104 for performing two-dimensional (2D) rasterizer operations, such as bit boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 2110. In some embodiments, GPE 2110 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0383] In some embodiments, GPE 2110 includes a 3D pipeline 2112 for performing 3D operations, such as rendering 3D images and scenes using processing functions acting on the shapes of 3D primitives (e.g., rectangles, triangles, etc.). The 3D pipeline 2112 includes programmable and fixed-function elements that perform various tasks within the elements and / or generate execution threads for the 3D / media subsystem 2115. While the 3D pipeline 2112 can be used to perform media operations, embodiments of GPE 2110 also include a media pipeline 2116 specifically designed for performing media operations, such as video post-processing and image enhancement.

[0384] In some embodiments, the media pipeline 2116 includes fixed-function or programmable logic units for performing one or more specialized media operations (such as video decoding acceleration, video deinterleaving, and video encoding acceleration) in place of or on behalf of the video codec engine 2106. In some embodiments, the media pipeline 2116 further includes a thread generation unit to generate threads for execution on the 3D / media subsystem 2115. The generated threads perform calculations on the media operations within one or more graphics execution units included in the 3D / media subsystem 2115.

[0385] In some embodiments, the 3D / media subsystem 2115 includes logic for executing threads generated by the 3D pipeline 2112 and the media pipeline 2116. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 2115, which includes thread scheduling logic for arbitrating available thread execution resources and scheduling various requests. Execution resources include a graphics execution unit array for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2115 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0386] Graphics processing engine

[0387] Figure 22 This is a block diagram of a graphics processing engine 2210 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2210 is... Figure 21 The version of GPE 2210 shown is shown. Figure 22 Elements having the same reference numerals (names) as elements in any other figure herein are capable of operating or functioning in any manner similar to, but not limited to, those described elsewhere herein. For example, shown Figure 21 The 3D pipeline 2212 and media pipeline 2216. The media pipeline 2216 is optional in some embodiments of the GPE 2210 and may not be explicitly included in the GPE 2210. For example, and in at least one embodiment, a separate media and / or image processor is coupled to the GPE 2210.

[0388] In some embodiments, GPE 2210 is coupled to or includes command streamer 2203, which provides a command stream to 3D pipeline 2212 and / or media pipeline 2116. In some embodiments, command streamer 2203 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 2203 receives commands from memory and sends commands to 3D pipeline 2112 and / or media pipeline 2116. Commands are instructions taken from a ring buffer that stores commands for 3D pipeline 2112 and media pipeline 2116. In one embodiment, the ring buffer may additionally include a batch command buffer that stores multiple commands in batches. Commands for 3D pipeline 2112 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2112 and / or image data and memory objects for media pipeline 2116. The 3D pipeline 2112 and the media pipeline 2116 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2214.

[0389] In various embodiments, by processing instructions and dispatching execution threads to the graphics core array 2214, the 3D pipeline 2112 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs. The graphics core array 2214 provides a unified block of execution resources. The multipurpose execution logic (e.g., execution units) within the graphics core array 2214 includes support for various 3D API shader languages ​​and can execute concurrent threads associated with multiple shaders.

[0390] In some embodiments, the graphics core array 2214 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution unit further includes general-purpose logic, which is programmable to perform parallel general-purpose computational operations in addition to graphics processing operations. The general-purpose logic can be related to… Figure 19 One or more processor cores 1907 or such Figure 20 The general logic within the cores 2002A-2002N performs processing operations in parallel or in combination.

[0391] Output data generated by threads executing on the graphics core array 2214 can be output to memory in a unified return buffer (URB) 2218. The URB 2218 can store data from multiple threads. In some embodiments, the URB 2218 can be used to send data between different threads executing on the graphics core array 2214. In some embodiments, the URB 2218 can also be used for synchronization and sharing of fixed-function logic within the functional logic 2220 between threads on the graphics core array.

[0392] In some embodiments, the graphics core array 2214 is scalable, such that the array includes a variable number of graphics cores, each with a variable number of execution units for a target power and performance level based on GPE 2210. In one embodiment, the execution resources are dynamically scalable, such that the execution resources can be enabled or disabled as needed.

[0393] The graphics core array 2214 is coupled to shared functionality logic 2220, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functionality within the shared functionality logic 2220 is a hardware logic unit that provides specialized supplementary functionality to the graphics core array 2214. In various embodiments, the shared functionality logic 2220 includes, but is not limited to, sampler 2221, math 2222, and inter-thread communication (ITC) 2223 logic. Additionally, some embodiments implement one or more caches 2225 within the shared functionality logic 2220. Shared functionality is implemented when the need for a given specialized function is insufficient to include it within the graphics core array 2214. Instead, a single instantiation of the specialized function is implemented as a separate entity within the shared functionality logic 2220 and shared among the execution resources within the graphics core array 2214. The exact set of functions shared between and included within the graphics core array 2214 varies depending on the embodiment.

[0394] Figure 23 This is a block diagram of another exemplary embodiment of the graphics processor 2300. Figure 23 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0395] In some embodiments, the graphics processor 2300 includes a ring interconnect 2302, a pipeline front-end 2304, a media engine 2337, and graphics cores 2380A-2380N. In some embodiments, the ring interconnect 2302 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0396] In some embodiments, the graphics processor 2300 receives multiple batches of commands via a ring interconnect 2302. The incoming commands are interpreted by a command streamer 2303 in a pipeline front-end 2304. In some embodiments, the graphics processor 2300 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2380A-2380N. For 3D geometry processing commands, the command streamer 2303 supplies commands to a geometry pipeline 2336. For at least some media processing commands, the command streamer 2303 supplies commands to a video front-end 2334, which is coupled to a media engine 2337. In some embodiments, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2333 for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2336 and the media engine 2337 each generate an execution thread for thread execution resources provided by at least one graphics core 2380A.

[0397] In some embodiments, the graphics processor 2300 includes scalable thread execution resources characterized by modular cores 2380A-2380N (sometimes referred to as core slices), each modular core having multiple sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2300 may have any number of graphics cores 2380A up to 2380N. In some embodiments, the graphics processor 2300 includes a graphics core 2380A, which has at least a first sub-core 2350A and a second sub-core 2360A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2350A). In some embodiments, the graphics processor 2300 includes multiple graphics cores 2380A-2380N, each graphics core including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. Each of the first set of sub-cores 2350A-2350N includes at least a first set of execution units 2352A-2352N and media / texture samplers 2354A-2354N. Each of the second set of sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In some embodiments, each sub-core 2350A-2350N and 2360A-2360N shares a set of shared resources 2370A-2370N. In some embodiments, these shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0398] Execution unit

[0399] Figure 24 The thread execution logic 2400 is shown, including an array of processing elements used in some exemplary embodiments of GPE. Figure 24 Those elements that have the same reference numerals (or names) as elements in any other figure herein are capable of operating or functioning in any manner similar to, but not limited to, those described elsewhere herein.

[0400] In some embodiments, thread execution logic 2400 includes a shader processor 2402, a thread dispatcher 2404, an instruction cache 2406, a scalable execution unit array (including a plurality of execution units 2408A-2408N), a sampler 2410, a data cache 2412, and a data port 2414. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2408A, 2408B, 2408C, 2408D to 2408N-1 and 2408N) based on workload computational requirements. In one embodiment, the included components are interconnected via an interconnect structure linking each of the components. In some embodiments, thread execution logic 2400 includes one or more connections to memory (e.g., system memory or cache memory) via one or more of the instruction cache 2406, data port 2414, sampler 2410, and execution unit arrays 2408A-2408N. In some embodiments, each execution unit (e.g., 2408A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads, processing multiple data elements in parallel for each thread. In various embodiments, the execution unit arrays 2408A-2408N are scalable to include any number of individual execution units.

[0401] In some embodiments, the execution unit arrays 2408A-2408N are primarily used to execute "shader" programs. The shader processor 2402 can handle various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher 2404. In one embodiment, the thread dispatcher includes logic for arbitrating thread initiation requests from the graphics and media pipeline and instantiating the requested thread on one or more execution units in the execution units 2408A-2408N. For example, a geometry pipeline (e.g., Figure 23 2336) can execute logic 2400 on the thread. Figure 24 It dispatches vertex, tessellation, or geometry shaders for processing. In some embodiments, thread dispatcher 2404 may also handle requests generated by runtime threads executing shader programs.

[0402] In some embodiments, execution units 2408A-2408N support instruction sets including native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct3D and OpenGL) with minimal transformation. Execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., computation and media shaders). Each of the execution units 2408A-2408N is capable of multiple-issue single-instruction multiple-data (SIMD) execution and multithreaded operation, enabling an efficient execution environment in the face of high-latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock cycle to a pipeline capable of integer, single and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other hybrid operations. While waiting for data from memory or a shared function, dependency logic within the execution units 2408A-2408N causes the waiting thread to sleep until the requested data has been returned. While waiting threads are sleeping, hardware resources can focus on processing other threads. For example, during the delay associated with vertex shader operations, the execution unit can perform operations on the pixel shader, fragment shader, or another type of shader program (which includes different vertex shaders).

[0403] Each execution unit in the execution unit arrays 2408A-2408N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels used for instructions. An execution channel is a logical unit used for flow control, data element access, and masking execution within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2408A-2408N support both integer and floating-point data types.

[0404] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process these elements based on their data size. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in registers, and the execution unit operates on the vector as four individual 64-bit compact data elements (four times the word length (QW) size), eight individual 32-bit compact data elements (double the word length (DW) size), sixteen individual 16-bit compact data elements (word length (W) size), or thirty-two individual 8-bit data elements (byte (B) size). However, different vector widths and register sizes are possible.

[0405] One or more internal instruction caches (e.g., 2406) are included in thread execution logic 2400 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2412) are included to cache thread data during thread execution. In some embodiments, sampler 2410 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2410 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0406] During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 2400 via thread creation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within pixel shader 2402 is invoked to further compute output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated across rasterized objects. In some embodiments, the pixel processor logic within shader processor 2402 then executes a pixel or fragment shader program provided by an application programming interface (API). To execute the shader program, shader processor 2402 dispatches threads to execution units (e.g., 2408A) via thread dispatcher 2404. In some embodiments, pixel shader 2402 uses texture sampling logic in sampler 2410 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and input geometry data compute the pixel color data for each geometric fragment, or discard one or more pixels from further processing.

[0407] In some embodiments, data port 2414 provides a memory access mechanism for causing thread execution logic 2400 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2414 includes or is coupled to one or more cache memories (e.g., data cache 2412) to cache data for memory access via the data port.

[0408] Figure 25This is a block diagram illustrating a graphics processor instruction format 2500 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions employing multiple formats. Solid lines block components that are typically included in the execution unit instructions, while dashed lines include components that are optional or included only in a subset of the instructions. In some embodiments, the instruction format 2500 described and illustrated are macro instructions, in that they are instructions supplied to the execution unit, as opposed to the micro-operations derived from the decoded instructions (once the instructions are processed).

[0409] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit format 2510. A 64-bit compact instruction format 2530 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format 2510 provides access to all instruction options, while some options and operations are restricted to the 64-bit instruction format 2530. The native instructions available in 64-bit instruction format 2530 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in index field 2513. The execution unit hardware references a set of compact tables based on these index values ​​and uses the compact table output to reconstruct the native instructions in 128-bit format 2510.

[0410] For each format, instruction opcode 2512 defines the operation that the execution unit will perform. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs simultaneous addition across each color channel representing a texture element or image element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, instruction control field 2514 enables control over certain execution options such as channel selection (e.g., prediction) and data channel order (e.g., tuning). For instructions in 128-bit instruction format 2510, execution size field 2516 limits the number of data channels that will be executed in parallel. In some embodiments, execution size field 2516 is not available for 64-bit compact instruction format 2530.

[0411] Some execution unit instructions have up to three operands, including two source operands src0 2520 and src12 522 and a destination 2518. In some embodiments, the execution unit supports dual-destination instructions, where one of these destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC22 524), where the instruction opcode 2512 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed through the instruction.

[0412] In some embodiments, the 128-bit instruction format 2510 includes an access / addressing mode field 2526, which specifies, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction 2510.

[0413] In some embodiments, the 128-bit instruction format 2510 includes an access / addressing mode field 2526, which specifies the addressing mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for both the source and destination operands, and when in a second mode, the instruction 2510 may use 16-byte aligned addressing for all source and destination operands.

[0414] In one embodiment, the addressing mode portion of the access / addressing mode field 2526 determines whether the instruction will use direct or indirect addressing. When using direct register addressing mode, bits in the instruction directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address immediate field and address register value in the instruction.

[0415] In some embodiments, instructions are grouped based on the 2512-bit opcode field to simplify opcode decoding 2540. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, move and logic opcode group 2542 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group 2542 shares five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb, and logic instructions are in the form of 0001xxxxb. Flow control instruction group 2544 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). Promiscuous instruction group 2546 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel math instruction group 2548 includes component-wise arithmetic instructions (e.g., addition, multiplication (mul)) in the form 0100xxxxb (e.g., 0x40). Parallel math group 2548 performs arithmetic operations in parallel across data channels. Vector math group 2550 includes arithmetic instructions (e.g., dp4) in the form 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic such as calculating the dot product of vector operands.

[0416] Graphics Pipeline

[0417] Figure 26 This is a block diagram of another embodiment of the graphics processor 2600. Figure 26 Elements having the same reference numerals (or names) as elements in any other figure herein are capable of operating or functioning in any manner similar to, but not limited to, those described elsewhere herein.

[0418] In some embodiments, graphics processor 2600 includes a graphics pipeline 2620, a media pipeline 2630, a display engine 2640, thread execution logic 2650, and a rendering output pipeline 2670. In some embodiments, graphics processor 2600 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 2600 via ring interconnect 2602. In some embodiments, ring interconnect 2602 couples graphics processor 2600 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 2602 are interpreted by command streamer 2603, which supplies instructions to individual components of graphics pipeline 2620 or media pipeline 2630.

[0419] In some embodiments, command streamer 2603 directs the operation of vertex fetcher 2605, which reads vertex data from memory and executes vertex processing commands provided by command streamer 2603. In some embodiments, vertex fetcher 2605 provides vertex data to vertex shader 2607, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 2605 and vertex shader 2607 execute vertex processing instructions by dispatching execution threads to execution units 2652A and 2652B via thread dispatcher 2631.

[0420] In some embodiments, execution units 2652A and 2652B are arrays of vector processors having instruction sets for performing graphics and media operations. In some embodiments, execution units 2652A and 2652B have attached L1 caches 2651 specifically for each array or shared between arrays. The caches may be configured as data caches, instruction caches, or single caches, which are partitioned to contain data and instructions in different partitions.

[0421] In some embodiments, the graphics pipeline 2620 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable shell shader 2611 configures the tessellation operation. A programmable domain shader 2617 provides back-end evaluation of the tessellation output. A tessellation 2613 operates in the direction of the shell shader 2611 and includes dedicated logic for generating a set of detailed geometric objects based on a rough geometry model that is provided as input to the graphics pipeline 2620. In some embodiments, if tessellation is not used, the tessellation components (e.g., shell shader 2611, tessellation 2613, domain shader 2617) can be bypassed.

[0422] In some embodiments, the complete geometry object can be processed by the geometry shader 2619 via one or more threads dispatched to execution units 2652A, 2652B, or can proceed directly to the clipper 2629. In some embodiments, the geometry shader operates on the entire geometry object rather than on patches of vertices or vertices as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2619 receives input from the vertex shader 2607. In some embodiments, if the tessellation unit is disabled, the geometry shader 2619 can be programmed by a geometry shader program to perform geometric tessellation.

[0423] Prior to rasterization, clipper 2629 processes vertex data. Clipper 2629 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader capabilities. In some embodiments, the rasterizer and depth testing component 2673 in the rendering output pipeline 2670 dispatch pixel shaders to convert geometric objects into their pixel-wise representations. In some embodiments, pixel shader logic is included in thread execution logic 2650. In some embodiments, the application can bypass the rasterizer and depth testing component 2673 and access the unrasterized vertex data via stream outunit 2623.

[0424] The graphics processor 2600 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be transferred among the main components of the processor. In some embodiments, execution units 2652A-2652B and one or more associated caches 2651, texture and media samplers 2654, and texture / sampler cache 2658 are interconnected via data port 2656 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2654, caches 2651, 2658, and execution units 2652A-2652B each have a separate memory access path.

[0425] In some embodiments, the rendering output pipeline 2670 includes a rasterizer and a depth testing component 2673 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / mask unit for performing fixed-function triangle and line rasterization. Associated rendering cache 2678 and depth cache 2679 are also available in some embodiments. Pixel manipulation component 2677 performs pixel-based operations on the data, although in some examples, pixel operations associated with 2D operations (e.g., bit-block images are transported using blending) are performed by the 2D engine 2641, or at display time by the display controller 2643 using an overlay display plane. In some embodiments, a shared L3 cache 2675 is available to all graphics components, allowing data to be shared without using main system memory.

[0426] In some embodiments, the graphics processor media pipeline 2630 includes a media engine 2637 and a video front-end 2634. In some embodiments, the video front-end 2634 receives pipeline commands from a command streamer 2603. In some embodiments, the media pipeline 2630 includes a separate command streamer. In some embodiments, the video front-end 2634 processes media commands before sending the commands to the media engine 2637. In some embodiments, the media engine 2637 includes thread generation functionality for generating threads for dispatching to thread execution logic 2650 via a thread dispatcher 2631.

[0427] In some embodiments, the graphics processor 2600 includes a display engine 2640. In some embodiments, the display engine 2640 is external to the processor 2600 and coupled to the graphics processor via a ring interconnect 2602 or some other interconnect bus or structure. In some embodiments, the display engine 2640 includes a 2D engine 2641 and a display controller 2643. In some embodiments, the display engine 2640 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2643 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0428] In some embodiments, the graphics pipeline 2620 and media pipeline 2630 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any single application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for OpenGL and OpenCL graphics and / or Vulkan graphics and computing APIs, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, combinations of these libraries may also be supported. Support may also be provided for the open-source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a pipeline mapping from future APIs to the graphics processor is possible.

[0429] Graphical Pipeline Programming

[0430] Figure 27A This is a block diagram of a graphics processor command format 2700 according to some embodiments. Figure 27B This is a block diagram of a graphics processor command sequence 2710 according to an embodiment. Figure 27ASolid lines in the diagram indicate components that are generally included in the drawing command, while dashed lines indicate components that are optional or included only in a subset of the drawing command. Figure 27A An exemplary graphics processor command format 2700 includes data fields for identifying the target client 2702 of the command, a command operation code (opcode) 2704, and related data 2706 for the command. Some commands also include a sub-opcode 2705 and a command size 2708.

[0431] In some embodiments, client 2702 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads opcode 2704 and (if present) sub-opcode 2705 to determine the operation to be performed. The client unit uses information in data field 2706 to execute the command. For some commands, an explicit command size 2708 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned via multiples of double word length.

[0432] Figure 27B The flowchart illustrates an exemplary graphics processor command sequence 2710. In some embodiments, software or firmware of a data processing system characterized by an embodiment of the graphics processor uses a version of the illustrated command sequence to establish, execute, and terminate a set of graphics operations. Sample command sequences are shown and described for illustrative purposes only, as embodiments are not limited to these specific commands or this command sequence. Furthermore, the commands may be issued as a batch of commands in a command sequence, such that the graphics processor will process the command sequence in at least partially simultaneous manner.

[0433] In some embodiments, the graphics processor command sequence 2710 may begin with a pipeline flush command 2712 to cause any active graphics pipeline to complete any currently pending commands for that pipeline. In some embodiments, the 3D pipeline 2722 and the media pipeline 2724 do not operate simultaneously. A pipeline flush is performed to cause any pending commands for the active graphics pipeline to complete. In response to the pipeline flush, the command parser for the graphics processor suspends command processing until the active graphics engine completes its pending operations and the associated read cache is invalidated. Optionally, any data marked as 'dirty' in the render cache may be flushed and dumped to memory. In some embodiments, the pipeline flush command 2712 may be used for pipeline synchronization or before placing the graphics processor in a low-power state.

[0434] In some embodiments, a pipeline selection command 2713 is used when a sequence of commands requires the graphics processor to make an explicit switch between pipelines. In some embodiments, the pipeline selection command 2713 is requested only once within the execution context before a pipeline command is issued, unless the context needs to issue a command for two pipelines. In some embodiments, a pipeline flush command 2712 is requested immediately before the pipeline switch via the pipeline selection command 2713.

[0435] In some embodiments, pipeline control command 2714 configures a graphics pipeline for operation and is used to program the 3D pipeline 2722 and the media pipeline 2724. In some embodiments, pipeline control command 2714 configures the pipeline state for an active pipeline. In one embodiment, pipeline control command 2714 is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

[0436] In some embodiments, return buffer state command 2716 is used to configure a set of return buffers for causing corresponding pipelined write data. Some pipelined operations require allocating, selecting, or configuring one or more return buffers that write intermediate data to said return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring return buffer state 2716 includes selecting the size and number of return buffers to use for a set of pipelined operations.

[0437] The remaining commands in the command sequence differ based on the active pipeline used for the operation. Based on pipeline determination 2720, the command sequence is customized for either the 3D pipeline 2722 or the media pipeline 2724, the 3D pipeline starting at 3D pipeline state 2730, and the media pipeline starting at media pipeline state 2740.

[0438] Commands configuring 3D pipeline states 2730 include 3D state setting commands for: vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 2730 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0439] In some embodiments, the 3D primitive 2732 command is used to submit 3D primitives for processing by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2732 command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 2732 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 2732 command is used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 2722 dispatches shader execution threads to the graphics processor execution unit.

[0440] In some embodiments, the 3D pipeline 2722 is triggered by executing command 2734 or an event. In some embodiments, register writing triggers command execution. In some embodiments, execution is triggered by a 'go' or 'kick' command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution to clear the command sequence through the graphics pipeline. The 3D pipeline performs geometric processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0441] In some embodiments, when performing media operations, the graphics processor command sequence 2710 follows the media pipeline 2724 path. Generally, the way the media pipeline 2724 is programmed and its specific use depends on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and media decoding can be performed wholly or partially (using resources provided by one or more general-purpose processing cores). In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly associated with the rendering of graphics primitives.

[0442] In some embodiments, the media pipeline 2724 is configured in a manner similar to that of the 3D pipeline 2722. A set of commands configuring the media pipeline state 2740 is dispatched to or placed in a command queue prior to the media object command 2742. In some embodiments, the commands for the media pipeline state 2740 include data for configuring media pipeline elements that will be used to process media objects. This includes data (such as encoding or decoding formats) for configuring video decoding and video encoding logic within the media pipeline. In some embodiments, the commands for the media pipeline state 2740 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0443] In some embodiments, media object command 2742 supplies pointers to media objects to be processed by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 2742. Once the pipeline states are configured and media object command 2742 is queued, media pipeline 2727 is triggered via execution command 2744 or an equivalent execution event (e.g., register write). The output from media pipeline 2724 can then be post-processed using operations provided by 3D pipeline 2722 or media pipeline 2724. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0444] Graphical software architecture

[0445] Figure 28 An exemplary graphics software architecture for a data processing system 2800 is illustrated according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2810, an operating system 2820, and at least one processor 2830. In some embodiments, the processor 2830 includes a graphics processor 2832 and one or more general-purpose processor cores 2834. The graphics application 2810 and the operating system 2820 each execute in the system memory 2850 of the data processing system.

[0446] In some embodiments, the 3D graphics application 2810 includes one or more shader programs, which include shader instructions 2812. The shader language instructions may employ a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2814 employing machine language suitable for execution by a general-purpose processor core 2834. The application also includes graphics objects 2816 defined by vertex data.

[0447] In some embodiments, the operating system 2820 is a Microsoft® Windows® operating system, a proprietary Unix-like operating system, or an open-source Unix-like operating system from Microsoft Corporation, using a variant of the Linux kernel. The operating system 2820 may support graphics APIs 2822, such as the Direct3D API, OpenGL API, or Vulkan API. When the Direct3D API is used, the operating system 2820 uses a front-end shader compiler 2824 to compile any shader instructions 2812 employing HLSL into a lower-level shader language. This compilation may be just-in-time (JIT) compilation or application-executable shader pre-compilation. In some embodiments, higher-level shaders are compiled into lower-level shaders during the compilation of the 3D graphics application 2810. In some embodiments, the shader instructions 2812 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0448] In some embodiments, the user-mode graphics driver 2826 includes a back-end shader compiler 2827 for translating shader instructions 2812 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2812 in the GLSL high-level language are passed to the user-mode graphics driver 2826 for compilation. In some embodiments, the user-mode graphics driver 2826 communicates with a kernel-mode graphics driver 2829 using an operating system kernel-mode feature 2828. In some embodiments, the kernel-mode graphics driver 2829 communicates with a graphics processor 2832 to dispatch commands and instructions.

[0449] IP core implementation

[0450] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within a processor. When read by a machine, these instructions can cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as “IP cores”) are reusable units of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model onto manufacturing machines that produce integrated circuits. Integrated circuits can be manufactured such that the circuits perform the operations described in association with any of the embodiments described herein.

[0451] Figure 29This is a block diagram illustrating an IP core development system 2900 according to an embodiment, which can be used to manufacture integrated circuits to perform operations. The IP core development system 2900 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). Design facility 2930 can generate software simulation 2910 of the IP core design using a high-level programming language (e.g., C / C++). Software simulation 2910 can be used to design, test, and verify the behavior of the IP core using simulation model 2912. Simulation model 2912 can include functional, behavioral, and / or timing simulations. Register transfer level (RTL) design 2915 can then be created or synthesized according to simulation model 2912. RTL design 2915 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including associated logic executed using modeled digital signals. In addition to RTL design 2915, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Therefore, specific details of the initial design and simulation can vary.

[0452] The RTL design 2915 or its equivalent can be further synthesized into a hardware model 2920 by the design facility, which may employ a hardware description language (HDL) or some other representation of the physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored in non-volatile memory 2940 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2965. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 2950 or a wireless connection 2960. The manufacturing facility 2965 can then fabricate an integrated circuit at least partially based on the IP core design. The fabricated integrated circuit can be configured to perform operation according to at least one embodiment described herein.

[0453] Exemplary System-on-Chip Integrated Circuits

[0454] Figure 30-32 Exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein are shown. In addition to those shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0455] Figure 30This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 3000 according to an embodiment. The system-on-a-chip integrated circuit 3000 can be fabricated using one or more IP cores. The exemplary integrated circuit 3000 includes one or more application processors 3005 (e.g., CPU), at least one graphics processor 3010, and may additionally include an image processor 3015 and / or a video processor 3020, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3000 includes peripheral or bus logic, including a USB controller 3025, a UART controller 3030, an SPI / SDIO controller 3035, and an I / O controller 3020. 2 S / I 2 C controller 3040. Additionally, the integrated circuit may include a display device 3045 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 3050 and a Mobile Industry Processor Interface (MIPI) display interface 3055. Storage may be provided by a flash memory subsystem 3060 (including flash memory and a flash memory controller). A memory interface for accessing SDRAM or SRAM memory devices may be provided via a memory controller 3065. Some integrated circuits also include an embedded security engine 3070.

[0456] Figure 31 This is a block diagram illustrating an exemplary graphics processor 3110, a system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3110 may be... Figure 30 A variant of the graphics processor 3010. The graphics processor 3110 includes a vertex processor 3105 and one or more fragment processors 3115A-3115N (e.g., 3115A, 3115B, 3115C, 3115D to 3115N-1 and 3115N). The graphics processor 3110 can execute different shader programs via independent logic, such that the vertex processor 3105 is optimized to perform the operations of the vertex shader program, while the one or more fragment processors 3115A-3115N perform fragment (e.g., pixel) shading operations of the fragment or pixel shader program. The vertex processor 3105 executes the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors (one or more) 3115A-3115N use the primitive and vertex data generated by the vertex processor 3105 to produce framebuffers for display on a display device. In one embodiment, one or more fragment processors 3115A-3115N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs as provided in the Direct 3D API.

[0457] The graphics processor 3110 further includes one or more memory management units (MMUs) 3120A-3120B, caches 3125A-3125B, and one or more circuit interconnects 3130A-3130B. The one or more MMUs 3120A-3120B provide virtual-to-physical address mapping for the graphics processor 3110 (which includes a vertex processor 1305 and / or one or more fragment processors 3115A-3115N), allowing these processors to reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 3125A-3125B. In one embodiment, the one or more MMUs 3120A-3120B can be synchronized with other MMUs within the system, including those related to... Figure 30 One or more application processors 3005, image processors 3015, and / or video processors 3020 are associated with one or more MMUs, enabling each processor 3005-3020 to participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 3130A-3130B enable the graphics processor 3110 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0458] Figure 32 This is a block diagram illustrating an additional exemplary graphics processor 3210 of a system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3210 may be... Figure 30 A variant of the graphics processor 3010. The graphics processor 3210 includes... Figure 31 The integrated circuit 3100 includes one or more MMUs 3120A-3120B, one or more caches 3125A-3125B, and circuit interconnects 3130A-3130B.

[0459] The graphics processor 3210 includes one or more shader cores 3215A-3215N (e.g., 3215A, 3215B, 3215C, 3215D, 3215E, 3215F to 3215N-1 and 3215N) that provide a unified shader core architecture, where a single core or a single type of core can execute all types of programmable shader code (including shader program code) to implement a vertex shader, fragment shader core, and / or compute shader. The exact number of shader cores present can vary between embodiments and implementations. Additionally, the graphics processor 3210 includes an inter-core task manager 3205 that acts as a thread dispatcher to accelerate tiled operations for tile-based rendering by allocating resources to one or more shader cores 3215A-3215N and a tile unit 3218, where rendering operations for a scene are finely divided in the image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0460] Examples and embodiments of the present invention include methods and apparatus for discriminative semantic transfer and physically inspired optimization in deep learning.

[0461] According to one example, a pipeline framework for running deep learning training includes three stages: a first stage, a second stage, and a third stage. The first stage is configured to receive a sequence of training images in a convolutional neural network (CNN) to describe objects in a cluttered scene as semantic segmentation masks. The second stage is configured to receive the semantic segmentation masks in a semantic segmentation network and generate semantic features. The third stage is configured to use weights from the first stage as a feature extractor and weights from the second stage as a classifier to identify edges in the cluttered scene using the semantic features.

[0462] In one example, the third stage is further configured to fine-tune the CNN that receives training images and identifies the edges of cluttered scenes.

[0463] In one example, the second level is further configured to use a softmax operation in the semantic segmentation network.

[0464] In one example, the objects in the cluttered scene are part of a room layout dataset.

[0465] In one example, the room layout dataset consists of pixels, and the second level is configured to treat each pixel of the room layout dataset as a sample in a fully connected layer of the semantic segmentation network.

[0466] In one example, the second level is further configured to model the relationship between the room layout dataset and objects in the CNN.

[0467] In one example, the third level is further configured to mark the edges of a cluttered scene.

[0468] According to one example, the data processing system includes a processing core, an I / O hub controller, and a graphics processor. The processing core is configured with a convolutional neural network (CNN). The I / O hub controller is coupled to the processing core and configured to provide network, data storage, and access to the processing core. The graphics processor is coupled to the I / O hub controller and configured to implement three levels: a first level, a second level, and a third level. The first level is configured to receive a sequence of training images in the CNN to describe objects in a cluttered scene as semantic segmentation masks. The second level is configured to receive the semantic segmentation masks in the semantic segmentation network and generate semantic features. The third level is configured to use weights from the first level as a feature extractor and weights from the second level as a classifier to identify edges of the cluttered scene using the semantic features.

[0469] In one example, the third stage is further configured to fine-tune the CNN that receives training images and identifies the edges of cluttered scenes.

[0470] In one example, the second level is further configured to use a softmax operation in the semantic segmentation network.

[0471] In one example, the objects in the cluttered scene are portions of a dataset of room layouts that include pixels.

[0472] In one example, the second level is further configured to treat each pixel of the room layout dataset as a sample in a fully connected layer of the semantic segmentation network.

[0473] In one example, the second level is further configured to model the relationship between the room layout dataset and objects in the CNN.

[0474] In one example, the third level is further configured to mark the edges of a cluttered scene.

[0475] According to one example, a computational training method for a convolutional neural network (CNN) includes receiving a sequence of training images in a first-level CNN to describe objects in a cluttered scene as semantic segmentation masks; receiving the semantic segmentation masks in a second-level semantic segmentation network to generate semantic features; and using weights from the first level as a feature extractor and weights from the second level as a classifier in a third level to use the semantic features to identify edges in the cluttered scene.

[0476] In one example, the CNN was fine-tuned in the third stage.

[0477] In one example, the softmax operation is used in the second-level semantic segmentation network.

[0478] In one example, the objects in the cluttered scene are portions of a dataset of room layouts that include pixels.

[0479] In one example, each pixel in the room layout dataset is treated as a sample in the fully connected layer of the second-level semantic segmentation network.

[0480] In one example, the relationship between the room layout dataset and objects in the CNN is modeled in the second level.

[0481] In one example, the edges of the cluttered scene are marked pixel-by-pixel in the third level.

[0482] According to one example, a method for training a deep learning-based classification model includes: receiving multiple input images; and training a deep learning-based classification model based on the received input images to perform domain-by-pixel scene parsing of cluttered scenes.

[0483] In one example, domain-by-pixel scene parsing is used for specific domains in cluttered scenes.

[0484] In one example, a cluttered scene includes a room layout.

[0485] In one example, the wall-to-floor, wall-to-wall, or wall-to-ceiling domains of the room layout are predicted pixel by pixel.

[0486] In one example, the relationships between domains of room layout are integrated into a convolutional neural network (CNN).

[0487] In one example, the CNN is trained in three incremental levels.

[0488] According to one example, a deep learning system includes a sensor array, an input buffer, a network actuator, and a training pipeline. The sensor array is configured to capture a sequence of images. The input buffer is configured to receive the sequence of images. The network actuator has multiple cores and is configured to execute a deep learning network on those cores. The training pipeline framework is configured to operate according to any one or more of the operations described in the example above.

[0489] As one example, a machine-readable medium includes instructions that, when operated by the machine, cause the machine to perform any or more of the actions described in the examples above.

[0490] According to one example, a device includes a memory, a neural network, and a processor. The memory is configured to store initial, intermediate, and final inputs. The processor is configured to enable, optimize, or configure the neural network to perform any or more operations as described in the example above.

[0491] According to one example, a device includes a memory component for storing initial, intermediate, and final results of input, and a logic component for performing operations according to any one or more of the examples above.

[0492] According to one example, a method for optimizing the operation of a fully connected network includes: receiving features of a scene and multiple locations of connection points in the scene as features; determining gradients for an energy target of the scene; and updating the locations of the connection points based on these gradients.

[0493] In one example, the energy objective is a comparison of the topology of the connection points with the scene's image.

[0494] In one example, features and connection points are transformed into an edge-marked map of the scene's image.

[0495] In one example, the topological representation of an image of a scene is a set of possible arrangements of scene features.

[0496] In one example, the gradient iteratively approaches the minimum energy from the average value of the connection points at different locations.

[0497] In one example, the gradient is applied to the endpoints of the feature as a force applied to the spring-like edge.

[0498] In one example, the endpoints are used to approximate the gradient across the entire edge.

[0499] According to one example, optimization methods for convolutional neural networks (CNNs) include: receiving a sequence of training images in the CNN to describe objects in a cluttered scene as a room layout dataset; identifying features corresponding to potential edges of objects in the cluttered scene; and considering each potential edge as a spring that can be translated, rotated, and have its length changed.

[0500] In one example, the spring movement is approximated by interpolation at the endpoints of each corresponding edge.

[0501] In one example, interpolation is approximated using a gradient.

[0502] In one example, approximation interpolation involves determining the gradient of the endpoints of the simulated edge as the particle moves through the potential field.

[0503] In one example, the force of the spring is applied to a different potential field at each edge.

[0504] According to one example, a machine-readable medium includes instructions that, when operated by the machine, cause the machine to perform any or more of the actions described in the examples above.

[0505] According to one example, a device includes a memory configured to store initial, intermediate, and final inputs; a neural network; and a processor that enables, optimizes, or configures the neural network to perform any one or more operations as described in the example above.

[0506] According to one example, a device includes a memory component for storing initial, intermediate, and final results of input; and a logic component for performing any one or more of the methods described in the example above.

[0507] According to one example, the data processing system includes a processing core, an I / O hub controller, and a graphics processor. The processing core is configured with a convolutional neural network (CNN). The I / O hub controller is coupled to the processing core and configured to provide network, data storage, and access to the processing core. The graphics processor is coupled to the I / O hub controller and configured to receive features of a scene and multiple locations of connection points in the scene as features; determine gradients for an energy target of the scene; and update the locations of the connection points based on the gradients.

[0508] In one example, the energy objective is a comparison of the topology of the connection points with the scene's image.

[0509] In one example, the graphics processor is further configured to transform features and connection points into an edge-marked map of the scene.

[0510] In one example, the topological representation of an image of a scene is a set of possible arrangements of scene features.

[0511] In one example, the gradient iteratively approaches the minimum energy from the average value of the connection points at different locations.

[0512] In one example, the gradient is applied to the endpoints of the feature as a force applied to the spring-like edge.

[0513] In one example, the endpoints are used to approximate the gradient across the entire edge.

[0514] The foregoing description and figures are to be regarded in an illustrative rather than restrictive sense. Various modifications and changes may be made to the examples and embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

Claims

1. A pipeline apparatus for running deep learning training, the pipeline apparatus comprising: The first stage is configured to receive a sequence of training images in a convolutional neural network (CNN) to describe objects in a cluttered scene as semantic segmentation masks. The second level is configured to receive the semantic segmentation mask and generate semantic features in the fully connected layer of the semantic segmentation network; as well as The third level is configured to use weights from the first level as a feature extractor and weights from the second level as a classifier to use the semantic features to identify the edges of the cluttered scene, wherein the weights from the first level and the weights from the second level form a pixel-wise edge labeling network.

2. The pipeline apparatus of claim 1, wherein the third stage is further configured to fine-tune the CNN that receives the training images and identifies the edges of the cluttered scene.

3. The pipeline apparatus of claim 1, wherein the second stage is further configured to use a softmax operation in the semantic segmentation network.

4. The assembly line apparatus of claim 1, wherein the object of the cluttered scene is a portion of a room layout dataset.

5. The pipeline apparatus of claim 4, wherein the room layout dataset comprises pixels and wherein the second level is configured to treat each pixel of the room layout dataset as a sample in a fully connected layer of the semantic segmentation network.

6. The pipeline apparatus of claim 4, wherein the second stage is further configured to model the relationship between the room layout dataset and objects in the CNN.

7. The assembly line apparatus of claim 1, wherein the third stage is further configured to mark the edges of the cluttered scene.

8. A data processing system, comprising: Processing kernel, the processing kernel being configured to implement a convolutional neural network (CNN); An I / O hub controller is coupled to the processing core and configured to provide networking, data storage, and access to the processing core; A graphics processor, coupled to the I / O hub controller and configured to implement: The first stage is configured to receive a sequence of training images in a convolutional neural network (CNN) to describe objects in a cluttered scene as semantic segmentation masks. The second level is configured to receive the semantic segmentation mask and generate semantic features in the fully connected layer of the semantic segmentation network; as well as The third level is configured to use weights from the first level as a feature extractor and weights from the second level as a classifier to use the semantic features to identify the edges of the cluttered scene, wherein the weights from the first level and the weights from the second level form a pixel-wise edge labeling network.

9. The data processing system of claim 8, wherein the third stage is further configured to fine-tune the CNN that receives the training images and identifies the edges of the cluttered scene.

10. The data processing system of claim 8, wherein the second stage is further configured to use a softmax operation in the semantic segmentation network.

11. The data processing system of claim 8, wherein the object of the cluttered scene is a portion of a room layout dataset comprising pixels.

12. The data processing system of claim 11, wherein the second stage is further configured to treat each pixel of the room layout dataset as a sample in a fully connected layer of the semantic segmentation network.

13. The data processing system of claim 11, wherein the second stage is further configured to model the relationship between the room layout dataset and objects in the CNN.

14. The data processing system of claim 8, wherein the third level is further configured to mark the edges of the cluttered scene.

15. A computational training method for convolutional neural networks (CNNs), comprising: In the first stage of the CNN, a sequence of training images is received to describe objects in a cluttered scene as semantic segmentation masks; The semantic segmentation mask is received in the fully connected layer of the second-level semantic segmentation network to generate semantic features; as well as In the third level, weights from the first level are used as a feature extractor and weights from the second level are used as a classifier to identify the edges of the cluttered scene using the semantic features. The weights from the first level and the weights from the second level form a pixel-wise edge labeling network.

16. The method of claim 15, further comprising: The CNN is fine-tuned in the third level.

17. The method of claim 15, further comprising: The softmax operation is used in the semantic segmentation network at the second level.

18. The method of claim 17, wherein the object of the cluttered scene is a portion of a room layout dataset comprising pixels.

19. The method of claim 18, further comprising: Each pixel in the room layout dataset is considered as a sample in the fully connected layer of the semantic segmentation network at the second level.

20. The method of claim 18, further comprising: In the second level, the relationship between the room layout dataset and the objects in the CNN is modeled.

21. The method of claim 15, further comprising: In the third level, the edges of the cluttered scene are marked pixel by pixel.

Images