Semiconductor device with metal contact comprising crystalline alloy

Abstract

Disclosed are techniques for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes that include crystalline alloys containing transition metals. The crystalline alloys help reduce contact resistance to the semiconductor devices. In some embodiments of the disclosure, this reduction in contact resistance is achieved by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that the Schottky barrier height associated with the interface between the crystalline alloy and the source region and the interface between the crystalline alloy and the drain region is in the range of less than or equal to 0.3 eV.

Description

Background Technology

[0001] Semiconductor devices are electronic components that utilize the electronic properties of semiconductor materials such as silicon, germanium, and gallium arsenide. A field-effect transistor (FET) is a semiconductor device comprising three terminals (gate, source, and drain). An FET uses an electric field applied through the gate to control the conductivity of the channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. When the charge carriers are electrons, the FET is called an n-channel device, and when the charge carriers are holes, the FET is called a p-channel device. Some FETs have a fourth terminal, called the body or substrate, which can be used to bias the transistor. Furthermore, a metal-oxide-semiconductor FET (MOSFET) includes a gate dielectric between the gate electrode and the channel region. MOSFETs can also be called metal-insulator-semiconductor FETs (MISFETs) or insulated-gate FETs (IGFETs). Complementary MOS (CMOS) structures use a combination of p-channel MOSFETs (PMOS) and n-channel MOSFETs (NMOS) to implement logic gates and other digital circuits.

[0002] A finFET is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin). The conductive channel of this device exists within the fin adjacent to the gate dielectric. Because the conductive channel of such a construction comprises three distinct planar regions of the fin, this construction has been called a finFET and a tri-gate transistor. Other types of fin constructions can also be used, such as the so-called dual-gate FinFET, where the conductive channel primarily comprises only two sidewalls of the fin (and excludes, for example, the top of the fin). Gate-all-around (GAA) transistors (sometimes called nanowire or nanoribbon transistors) are configured similarly to fin-based transistors, but instead of the fin channel regions with the gate situated on three sections (and thus having three effective gates), they have one or more nanowires / nanoribbons for the channel regions, and the gate material substantially surrounds each nanowire / nanoribbon.

[0003] Improving the performance of circuit devices, including transistors, diodes, resistors, capacitors, and other passive and active electronic devices formed on semiconductor substrates, is often a primary consideration during the design, fabrication, and operation of these devices. For example, during the design and fabrication or formation of MOSFET devices (e.g., those used in CMOS structures), it is often desirable to improve the mobility of electrons in the contact region of n-channel devices and holes in the contact region of p-channel devices. Such improved mobility can be achieved by reducing contact resistance. At the contact region between the source and drain, conductive material is deposited on the doped surfaces of the source / drain material, thus providing the contact. The interaction between the conductive material and the doped semiconductor surface creates a semiconductor junction. The resulting semiconductor junction is characterized by the height of the Schottky barrier between the conduction band and the Fermi level. The conduction of electrons across the Schottky barrier is limited by this barrier height and results in contact resistance. Attached Figure Description

[0004] Figure 1 This is a diagram illustrating the resistive component of a MOS device that is susceptible to high contact resistance.

[0005] Figure 2 A method for forming an integrated circuit structure including one or more of a source contact, a drain contact, and a gate electrode (which includes a crystalline alloy containing a transition metal) according to one or more embodiments of the present disclosure is shown.

[0006] Figure 3A A perspective view of a semiconductor substrate including fins is shown after trench isolation material is deposited in a trench according to an embodiment and the trench isolation material is etched to recess it below the level of the fins.

[0007] Figure 3B This illustrates a dummy gate-containing structure after forming a dummy gate on the fin, according to an embodiment. Figure 3A A perspective view of the structure.

[0008] Figure 3C This illustrates a configuration including an insulating layer after depositing and polishing the insulating layer to the top of the dummy gate, according to an embodiment. Figure 3B A perspective view of the structure.

[0009] Figure 3D This illustrates the region to be opened after photolithography has defined the dummy gate structure according to an embodiment. Figure 3C A perspective view of the structure.

[0010] Figure 3E The illustration shows the channel region of the fin after the dummy gate structure has been removed from the opened area to re-expose it, according to an embodiment. Figure 3DA perspective view of the structure.

[0011] Figure 3F It shows Figure 3E The top view of the structure shown.

[0012] Figure 3G It shows perpendicular to the fin and through Figure 3F The diagram shows a frontal cross-sectional view of the channel region of the structure.

[0013] Figure 3H This illustrates the process after additional processing to form a semiconductor device, according to one or more embodiments. Figure 3G A perspective view of the structure.

[0014] Figure 4A An energy band diagram of an NMOS gate according to one or more embodiments is shown.

[0015] Figure 4B An energy band diagram of a PMOS gate according to one or more embodiments is shown.

[0016] Figure 5 It shows the effect on Co2FeAl x Si 1-x The density of states (states / eV) as a function of energy (eV) for (0≤x≤l).

[0017] Figure 6A Energy band diagrams of p-doped source and p-doped drain regions according to one or more embodiments are shown.

[0018] Figure 6B Energy band diagrams of n-doped source and n-doped drain regions according to one or more embodiments are shown.

[0019] Figure 7 The lattice parameters of a class of manganese (Mn)-based Hessler alloys are shown.

[0020] Figure 8 A front cross-sectional view of a transistor device including a source contact and a drain contact (which comprises a crystalline alloy containing a transition metal) according to another embodiment is shown.

[0021] Figure 9 This is a diagram of a computing system configured according to an embodiment of the present disclosure.

[0022] For illustrative purposes only, the accompanying drawings depict various embodiments of the present disclosure. In the drawings, each equivalent or nearly equivalent component shown in the various figures can be indicated by similar reference numerals. For clarity, not every component is labeled in every figure. It should be understood that the drawings are not necessarily drawn to scale and are not intended to limit the present disclosure to the specific constructions shown. For example, while some figures generally indicate straight lines, right angles, and smooth surfaces, actual implementations of transistor structures may have less ideal straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given the real-world limitations of the processing devices and technologies used. In short, the drawings are provided merely to illustrate exemplary structures. Various variations, constructions, and other embodiments will become apparent from the detailed discussion below. Detailed Implementation

[0023] Techniques for forming semiconductor integrated circuits including one or more of source contacts, drain contacts, and gate electrodes (which comprise a crystalline alloy containing a transition metal) are disclosed. The crystalline alloy helps reduce contact resistance in semiconductor devices. In some embodiments of this disclosure, this reduction in contact resistance is achieved by aligning the work function of the crystalline alloy with the work functions of the source and drain regions, such that the Schottky barrier heights associated with the interfaces between the crystalline alloy and the source region and between the crystalline alloy and the drain region are in the range of less than or equal to 0.3 eV.

[0024] It should also be recognized that the disclosed technology can provide various advantages over standard MOSFETs, such as reduced contact resistance in scaled devices, which can enable the entire device to operate at lower voltages with higher performance and higher efficiency.

[0025] General Overview

[0026] like Figure 1 As shown, a MOS device (e.g., a PMOS or NMOS transistor 100) formed on substrate 105 includes a source contact 110, a doped source region 120, a gate spacer 130 between the source contact 110 and the gate stack (including a gate dielectric 145 and a gate electrode 140), a channel region 150 below the gate dielectric 145, a doped drain region 160, a drain contact 170, and a gate spacer 180 between the drain contact 170 and the gate stack. The total resistance of transistor 100 includes the contact resistance R. contact Spacer resistance R spacer and channel resistance R channelThe contribution of the source and drain contacts is significant. Because the dimensions of the source and drain contacts are close to the mean free path of electrons, the source and drain contact resistances can increase significantly in scaled CMOS transistors. This increased contact resistance and increased connection resistance R... ext (R ext =R contact +R spacer This can slow down transistors and reduce their efficiency. Due to technological scaling that continuously reduces all dimensions of devices, as the length of the channel region is continuously reduced, the contribution of channel resistance to the total resistance decreases, and the contribution of contact resistance as a percentage of the total device resistance can potentially increase and become greater than that of the channel resistance. Existing contact strategies for transistor devices (especially III-V transistor devices) are plagued by large Schottky barrier heights relative to metal contacts, partly due to Fermi level pinning, which, if not properly managed, in turn causes high contact resistance. Embodiments of this disclosure recognize this problem and are configured to help mitigate or otherwise reduce contact resistance, as will be appreciated.

[0027] Methods and Architecture

[0028] Figure 2 A method 200 for forming an integrated circuit structure including one or more source contacts, drain contacts, and gate electrodes (which comprise a crystalline alloy containing a transition metal) according to one or more embodiments of the present disclosure is illustrated. As will be apparent from this disclosure, the formation of the source and drain contacts is described herein in the context of an alternative metal gate (RMG) process. However, in some embodiments, the formation of the source and drain contacts may be performed prior to gate (or dummy gate) deposition, which will be discussed in more detail below. Figures 3A-3H The following are shown according to some embodiments: Figure 2 An exemplary structure formed by executing the process flow or method 200. Although this document is in the context of forming a fin transistor structure (e.g., a tri-gate or finFET device). Figure 2 Method 200 and Figures 3A-3H The structures shown are depicted and described, but similar principles and techniques described herein in various ways can be used in other transistor constructions, including, for example, dual-gate, all-around gate (e.g., nanowire / nanobelt) planar, and other semiconductor device constructions (such as ferroelectric or magnetoelectric devices), as will be apparent from this disclosure.

[0029] Figure 3AA perspective view of a semiconductor substrate 300 including fins 310 and 320 after forming 210 fins 310 and 320 on barrier layer 301 and substrate 300 according to an embodiment is shown. Substrate 300 may be formed using various other suitable techniques for forming silicon substrates or bases (e.g., silicon single-crystal wafers). For example, substrate 300 may be implemented with bulk silicon, silicon-on-insulator (SOI) construction, or a multilayer structure. In other embodiments, substrate 300 may be formed using alternative materials that may or may not be bonded to silicon, such as germanium, silicon-germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, indium gallium arsenide (e.g., In...). 0.7 Ga 0.3 Gallium arsenide (GaAs), gallium arsenide (GaAs), or gallium antimonide (GaAs) are just a few examples. In a more general sense, any material that can serve as the basis for building semiconductor devices can be used according to embodiments of this disclosure. In some embodiments, fins 310 and 320 may be formed on and from substrate 300, such that the barrier layer 301 is absent in such embodiments. The barrier layer 301 may be formed using various suitable materials for forming barrier layers; for example, in the case of III-V transistors (e.g., GaAs or InGaAs transistors), the material may be indium aluminum arsenide (InAlAs), to name just one example.

[0030] Further reference Figure 3AFins 310 and 320 may be grown (e.g., epitaxially) from trenches formed in isolation material 302 after the removal of sacrificial fins, and fins 310 and 320 are formed by depositing a desired semiconductor material into the trenches formed in isolation material 302. Some such aspect ratio trapping (ART)-based fin formation techniques are provided in U.S. Patent Application Publication 2014 / 0027860. In some such ART-based cases, alternative fin materials may be provided in the context of a multilayer stack comprising alternating layers of desired channel material and sacrificial / passive material, for example, as described in U.S. Patent Application Publication 2016 / 0260802. Such multilayer fins are particularly useful for all-around gate transistors. In some ART-based cases, a first set of fins is formed using a first semiconductor material system (e.g., for p-type devices), and a second set of fins is formed using a second semiconductor material system (e.g., for n-type devices). Exemplary fin materials include group IV semiconductor materials (e.g., silicon (Si), germanium (Ge)) and group III-V semiconductor materials (e.g., gallium arsenide (GaAs), indium gallium arsenide (e.g., InGaAs)) and XY alloys, wherein X may be gallium (Ga) or indium (In), and Y may be phosphorus (P), arsenic (As), or antimony (Sb). Based on this disclosure, it will be understood that a transistor formed from a given fin includes the fin material at least in the channel region of the transistor, such that the transistor may be a Si, SiGe, Ge, and / or III-V transistor. For example, as will be apparent from this disclosure, the techniques described herein can be used to form Ge NMOS, Ge PMOS, SiGe NMOS, SiGe PMOS, GaAs NMOS, GaAs PMOS, InGaAs NMOS, InGaAs PMOS, and / or any other suitable transistor device. In some embodiments, the techniques can be used to benefit one or both of NMOS and PMOS devices in a CMOS circuit. In a particular exemplary embodiment, the substrate 300 is silicon, the barrier layer 301 is InAlAs, and the fins 310 and 320 are made of InGaAs.

[0031] Generally, the term "Group IV semiconductor materials" (or "Group IV materials" or "IV" in general) as used herein includes at least one Group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), etc. The term "III-V semiconductor materials" (or "III-V materials" or "III-V" in general) as used herein includes at least one Group III element (e.g., aluminum, gallium, indium) and at least one Group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), etc. Note that, for example, Group III can also be referred to as the boron group or IUPAC group13, Group IV can also be referred to as the carbon group or IUPAC group14, and Group V can also be referred to as the nitrogen group or IUPAC group15.

[0032] from Figure 3A As can be seen, for ease of description, fins 310 and 320 are depicted as rectangular in shape. However, the fins described herein in various ways are not necessarily limited to this. For example, in other embodiments, the fin formed at 210 may have a rounded top, a triangular or tapered shape, or some other suitable fin shape that will become apparent from this disclosure. It will also be apparent from this disclosure that, for example, fins 310 and 320 may be used in n-type MOS devices (NMOS), p-type MOS devices (PMOS), or CMOS devices (e.g., where fin 310 is an n-type MOS and fin 320 is a p-type MOS). It should also be noted that although only two fins 310 and 320 are shown for ease of description, it is conceivable that any number of similar fins and trenches can be formed on substrate 300 (e.g., hundreds of fins, thousands of fins, millions of fins, billions of fins, etc.) and benefit from the techniques described herein.

[0033] Figure 3AThe illustration further illustrates shallow trench isolation (STI) provided by isolation region 302 after trench isolation material 220 is deposited in the trench according to an embodiment and the trench isolation material is etched to recess it below the level of fins 310 and 320. Deposition 220 for forming isolation region 302 may include atomic layer deposition (ALD), chemical vapor deposition (CVD), spin-on deposition (SOD), high-density plasma (HDP), plasma-enhanced chemical deposition (PECVD), and / or some other suitable techniques. For example, isolation region 302 may include a dielectric such as silicon dioxide (SiO2). However, isolation region 302 may be any insulating, oxide, or interlayer dielectric (ILD) material that provides the desired amount of electrical isolation for a given target application or end use, as will be apparent from this disclosure. In the case where fins 310 and 320 are formed using a patterned hard mask, the hard mask may be removed prior to depositing the trench isolation material. In some cases, the trench isolation material can be polished to be flush with the top of the fins 310 and 320 before etching it to recess it below the level of the fins 310 and 320. And as... Figure 3A As shown, recessing the trench isolation material below the level of fins 310 and 320 will create a fin height H above the isolation zone 302. Fin Non-planar semiconductor devices (e.g., FinFETs) have H... Fin >0, while planar semiconductor devices (e.g., transistors) have H. Fin =0.

[0034] Figure 3B This illustrates a configuration including dummy gates 330 after forming 230 dummy gates 330 on fins 310 and 320 according to an embodiment. Figure 3A A perspective view of the structure. As previously described, the techniques disclosed herein for forming transistors including source and drain contacts (which comprise a crystalline alloy containing a transition metal) can be performed during a replacement gate process (also known as a replacement metal gate (RMG) process). In this embodiment, a dummy gate structure 330 can be deposited first by depositing a dummy gate dielectric / oxide (e.g., silicon dioxide) and a dummy gate electrode 332 (e.g., dummy polysilicon). The resulting structure can be patterned, and spacer material 340 can be deposited and etched to form Figure 3BThe dummy gate structure is shown. Such deposition, patterning, and etching can be performed using any suitable technique, as will be apparent from this disclosure. Note that in this exemplary embodiment, the dummy gate oxide is not shown because it is beneath the dummy electrode / polysilicon layer 332. It should also be noted that, for ease of reference, the dummy gate structure 330 is indicated as being on top of the spacer material 340, and the dummy gate structure 330 (which includes the dummy gate oxide and the dummy electrode / polysilicon layer 332) referred to herein may or may not include the spacer material 340. For example, the spacer material 340 may be formed using a standard gate spacer material (e.g., silicon dioxide, silicon nitride, or other suitable spacer material). The width of the spacer material 340 can generally be selected based on the design requirements of the transistor being formed.

[0035] Figure 3C This illustrates a structure including the insulating layer 350 after the insulating layer 350 is deposited and polished to the top of the dummy gate structure 330, according to an embodiment. Figure 3B A perspective view of the structure. The insulating layer 350 may comprise any suitable filler material, including dielectric materials such as oxides of silicon (e.g., SiO2), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials (e.g., porous silica), and combinations thereof, said filler material being deposited by ALD, CVD, SOD, HDP, PECVD, and / or some other suitable techniques, as will be apparent in light of this disclosure.

[0036] Figure 3D This illustrates the region to be opened after photolithography defines the dummy gate structure 330 250, according to an embodiment. Figure 3C A perspective view of the structure. In this exemplary embodiment, defining the area to be opened 250 by photolithography includes hard masking and patterning processes to obtain the illustrated hard mask 370 pattern. The hard mask layer 370 can have any desired construction and thickness, and in some cases can be provided as a substantially conformal layer or multilayer structure. The hard mask layer 370 can be formed using, for example, CVD, SOD, and / or any other process suitable for providing a hard mask material layer, as will be apparent from the present disclosure. Moreover, in some embodiments, the hard mask layer 370 may include, for example, nitrides, such as silicon nitride (Si3N4). However, the hard mask layer 370 is not limited by material composition, and more generally, the hard mask layer 370 can be any hard mask material construction that is sufficiently adaptable to a given target application or end use, as will be apparent from the present disclosure.

[0037] Figure 3E The diagram illustrates the channel region 306 (or the region that can become a channel region once the device is fully fabricated) after removing the dummy gate structure 330 260 to re-expose the fins 310 and 320, according to an embodiment. Figure 3D A perspective view of the structure. Removing the dummy gate structure 330 may include removing any capping layer on top of the dummy gate (e.g., formed by spacer material 340), and then removing the dummy gate electrode / polysilicon 332 and the dummy gate dielectric. Such removal may be performed using any suitable etching, polishing, and / or cleaning process, as will be apparent from this disclosure.

[0038] Figure 3F It shows Figure 3E The diagram shows a top view of the structure. From this top view, it can be seen that the channel regions 306 of fins 310 and 320 have been re-exposed. Furthermore, it can be seen, and as discussed in more detail below, that both fins 310 and 320 have a width W. Fin In some embodiments, W Fin It can be in the range between 1nm and 30nm, for example, 7nm, 10nm, 15nm or 20nm.

[0039] Figure 3G Only shown Figure 3F The diagram shows a front view of the channel region 306 of the structure. Figure 3G It can be seen that fins 310 and 320 both have a width W Fin and height H Fin Although fins 310 and 320 do not necessarily have the same width W Fin and the same height H Fin However, in this embodiment they are the same for ease of description. In some embodiments, and as will be apparent from this disclosure, the width W Fin This can be determined by trench etching 210 performed to form fins 310 and 320 on substrate 300. Note that the height H used herein... Fin It is the distance from the top of the isolation zone 302 to the top of the fins 310 and 320. In some embodiments, H Fin It falls within the range of 20nm and 75nm, for example, 25nm, 30nm, or 50nm.

[0040] refer to Figure 3HIn this embodiment, a gate electrode 362 is deposited / formed to replace the dummy gate electrode 332, and a gate dielectric 360 is formed directly below the gate electrode 362 to form a 270 gate stack. It can also be seen that a spacer 340 can be formed around the gate stack, and the gate stack also has a hard mask 380 formed thereon (the hard mask 380 can be removed to form metal gate contacts). The gate dielectric 360 can be formed using any suitable technique and from any suitable material. The gate dielectric 360 can be, for example, any suitable oxide, such as silicon dioxide (SiO2) or a high-k gate dielectric material. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum alumina, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k material, an annealing process may be performed on the gate dielectric 360 to improve its quality. In some embodiments, additional processing (e.g., annealing) may be performed on the high-k gate dielectric to improve the quality of the high-k material. In some embodiments, the gate dielectric 360 and / or the gate electrode 362 may comprise a multilayer structure consisting of two or more material layers or portions thereof. For example, the gate dielectric 360 structure may comprise a silicon dioxide layer on the channel region 306 of the fin and a hafnium oxide layer on the silicon dioxide layer.

[0041] In some embodiments, the gate electrode 362 comprises a first crystalline alloy containing a transition metal, which is also referred to herein as a Hessler alloy. Because Hessler alloys are ferromagnetic metal alloys, in some embodiments, the crystalline alloys containing transition metals described herein in various ways may also be considered ferromagnetic metal alloys. In these embodiments, the gate electrode 362 is crystalline due to the presence of the first crystalline alloy. The first crystalline alloy may include a cobalt-iron-aluminum-silicon alloy (Co2FeSi, Co2FeAl...). x Si 1-x (0≤x≤l), cobalt-manganese-silicon alloy (Co2MnSi), cobalt-iron-silicon-germanium alloy (Co2FeSiGe), cobalt-chromium-iron-aluminum alloy (Co2CrFeAl, Co2Cr) 0.5 Fe 0.5 Al), cobalt-iron-germanium-gallium alloy (Co2FeGeGa), manganese-gallium alloy (Mn3Ga), manganese-germanium alloy (Mn3Ge), manganese-germanium-gallium alloy (Mn3GeGa), or iron-manganese-silicon alloy (Fe). 3-x Mn xAt least one of Si (0≤x≤1.5). In other embodiments, the first crystalline alloy may include at least one of M-manganese-germanium alloy (M2MnGe), M-manganese-gallium alloy (M2MnGa), M-manganese-aluminum alloy (M2MnAl), M-manganese-antimony alloy (MMnSb), or M-manganese-indium alloy (M2MnIn), wherein M is one of cobalt (Co), nickel (Ni), copper (Cu), rhodium (Rh), palladium (Pd), or platinum (Pt). For example, for NMOS devices... Figure 4A And for PMOS devices Figure 4B As shown, the work function of the Hessler alloy is aligned with the work function of the channel semiconductor material, resulting in a threshold voltage for the non-planar semiconductor device in the range of 0.2V to 0.7V, for example, 0.3V, 0.4V, 0.5V, or 0.6V. For NMOS devices, the threshold voltage V... T Obtained from the following formula:

[0042]

[0043] Furthermore, for PMOS devices, the threshold voltage V T Obtained from the following formula:

[0044]

[0045] in,

[0046] V FB -Φ H -Φ S (3)

[0047] and

[0048]

[0049] Where, φ F It is half the contact potential, k is Boltzmann's constant, T is the temperature, q is the absolute value of the electron's charge, and N is the contact potential. B It is the doping in the bulk of the channel, N i Q is the intrinsic carrier density of a semiconductor. i It is the surface charge density of the interface trap, C ox It is the capacitance per unit area of ​​the gate dielectric oxide, Φ H It is the work function of the metal (Hessler alloy), Φ S It is the work function of the semiconductor, and ε s It is the dielectric constant of a semiconductor.

[0050] In a specific exemplary embodiment, the first crystalline alloy is Co2FeAl. x Si 1-x , 0≤x≤l. For example... Figure 5 As shown, changing the stoichiometry by altering the value of x will shift the Fermi level of the Hessler alloy by approximately 1 eV. The difference in valence electrons between Si and Al causes a change in the relative position of the Fermi level within the minority carrier bandgap. This shift in the Fermi level will change the work function of the gate electrode, thereby aligning the work function of the Hessler alloy with that of the channel semiconductor material. Figure 5 The approximately 1 eV shift shown from x = 0 (Si system) to x = 1 (Al system) represents the practical range between p-type work function metals and n-type work function metals.

[0051] In some embodiments, such as Figure 3H As shown, the gate stack includes a first layer 361 directly between the gate dielectric 360 and the gate electrode 362. The first layer 361 includes at least one of magnesium oxide (MgO), magnesium aluminum oxide (MgAlO), strontium titanate (SrTiO3), aluminum oxide (Al2O3), dysprosium scandium oxide (DyScO3), niobium scandium oxide (NbScO3), or niobium strontium titanate (NbSrTiO3). In an exemplary embodiment, the first layer 361 is magnesium oxide. The first layer 361 is a template promoting layer that is lattice-matched to a first crystalline alloy. As used herein, lattice matching means that, in some embodiments, the first layer 361 has a first lattice parameter and the first crystalline alloy has a second lattice parameter that is within + / -2% of the first lattice parameter, for example, within + / -1.5%, + / -1.0%, or + / -0.5%. In other embodiments, the first layer 361 has a first lattice parameter, and the first crystalline alloy has a second lattice parameter within the tolerance of the first lattice parameter, thereby creating lattice continuity across the entire interface between the first layer 361 and the first crystalline alloy.

[0052] The gate electrode 362, comprising a first crystalline alloy, can be formed using any of a wide range of processes, including CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and / or any combination thereof. In an exemplary embodiment employing PVD at a basic pressure less than or equal to 1E-8 Torr, argon can be used as the sputtering gas at a substrate temperature ranging from -150°C to 600°C and a pressure ranging from 1 mTorr to 5 mTorr, wherein the sputtering target-to-wafer spacing is greater than 10 mean free path lengths, followed by post-deposition annealing at a temperature ranging from 300°C to 700°C to form a crystalline Hessler phase. Many gate dielectric and gate electrode configurations can be used, as will be apparent. Other suitable configurations, materials, and processes for forming replacement gates or replacement metal gates (RMGs) will depend on the given application, and this will become apparent from the present disclosure.

[0053] Further reference Figure 3H As shown in the figure, an etching process (e.g., any suitable wet or dry etching process) is performed to expose the source / drain regions 308 and 309 of the fin 310 and remove any native oxide. The method 200 for forming an integrated circuit device then continues to form source contacts 311 and drain contacts 312, respectively, on the source regions 308 and 309. In some embodiments, the source contacts 311 and drain contacts 312 comprise a first crystalline alloy and a second crystalline alloy, respectively. In these embodiments, the source contacts 311 and drain contacts 312 are crystalline due to the presence of the first and second crystalline alloys. The deposition and annealing conditions for the first and second crystalline alloys are the same as those discussed above for the first crystalline alloy and will not be repeated for brevity.

[0054] like Figure 6A The n-type doped source region 308 and drain region 309 are shown in the figure and as shown in the figure. Figure 6B As shown in the diagram for the p-type doped source region 308 and drain region 309, the work function of the first crystalline alloy is aligned with the work function of the semiconductor material in the source region, such that the Schottky barrier height associated with the interface between the first crystalline alloy and the source region ( Figure 6A Φn and Figure 6B The work function of the second crystalline alloy is less than or equal to 0.3 eV, for example, 0.2 eV, 0.1 eV, or 0 eV, and the work function of the second crystalline alloy is aligned with the work function of the semiconductor material of the drain region, such that the Schottky barrier height associated with the interface between the second crystalline alloy and the drain region is less than or equal to 0.3 eV, for example, 0.2 eV, 0.1 eV, or 0 eV. Figure 6BAs shown, the Schottky barrier height Φp can be negative, for example -0.1 eV, -0.2 eV, -0.3 eV, -0.4 eV, or -0.5 eV. An exemplary embodiment of a negative Schottky barrier height is in GaAs and Co2Cr 0.5 Fe 0.5 At the interface between Al. Suitable alternatives to the Schottky barrier height can be at most 0.5 eV, or at most 0.4 eV, or at most 0.3 eV, or at most 0.2 eV, or at most 0.1 eV. In a first specific exemplary embodiment, the n-type source region 308 and the n-type drain region 309 are germanium doped with phosphorus or arsenic, and the source contact 311 and the drain contact 312 are Co2CoAl. In a second specific exemplary embodiment, the p-type source region 308 and the p-type drain region 309 are silicon doped with boron, and the source contact 311 and the drain contact 312 are Ni2VSi. In a third specific exemplary embodiment, the channel region, source region, and drain region are GaAs, and the crystalline alloy contact is Co2CrFeAl.

[0055] In an exemplary embodiment, the first crystalline alloy is lattice-matched with the source region, and the second crystalline alloy is lattice-matched with the drain region. Figure 7 As shown, Hessler alloys based on manganese (Mn) can be lattice-matched with group III-V semiconductor materials. For example, NiMnSb has a lattice parameter equal to or slightly less than 6.1 Å, and is therefore lattice-matched with GaSb. Moreover, as Figure 7 As shown, several M2MnGa, MMnSb, and M2MnGe crystalline alloys (where M is Co, Ni, Cu, and Rh) can be combined with Ga. 1-x In x As (0≤x≤l) or InP lattice matching. An example of near-ideal lattice matching is the source, drain, and channel regions of GaAs with their corresponding contacts in Co2MnSi, both having the same lattice parameters of approximately 5.65 Å. In another exemplary embodiment, by adjusting the value of x from a lattice parameter of 0.563 nm (x=0) to 0.5635 nm (x=0.6), 0.565 nm (x=1.0), and 0.567 nm (x=1.4), Fe can be made... 3-x Mn x Si (0≤x≤1.4) crystalline alloys are matched with or used as templates for Si (111) surface lattices with a lattice parameter of 0.543 nm.

[0056] In embodiments where the given source / drain contacts do not include Hessler alloy contacts, the given S / D contacts may include any other suitable metal or metal alloy (e.g., aluminum or tungsten), although any suitable conductive metal or metal alloy (or other suitable conductive material) may be used, such as silver, nickel-platinum, or nickel-aluminum. For example, in some embodiments, only one of the source / drain contact pairs may include Hessler alloy, while the other of the source / drain contact pair does not. In some embodiments, the formation of the S / D contacts may include silicide, germanide, III-V grouping, and / or annealing processes, wherein such processes can be performed to form an intermediate contact layer, for example, before the body contacts the metal structure. In some embodiments, for example, one or more of the S / D contacts may include a resistance-lowering metal and a contact plug metal, or only a contact plug. Exemplary contact resistance-lowering metals include, for example, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel-aluminum and / or other such resistance-lowering metals or alloys. Exemplary contact plug metals include, for example, aluminum, copper, nickel, platinum, titanium, or tungsten or alloys thereof, although any suitable conductive contact metal or alloy may be used. In some embodiments, depending on the specific construction, the S / D contact portion may be made of one or more low work function metal materials and / or one or more high work function metal materials. In some embodiments, one or more additional layers, such as an adhesive layer (e.g., titanium nitride) and / or a liner or barrier layer (e.g., tantalum nitride), may be present in the S / D contact area, if desired.

[0057] In another embodiment, such as Figure 8As shown, a transistor device, such as a PMOS or NMOS transistor 800, is formed on a substrate 805 and an insulator 810, and includes a source contact 820, a gate dielectric 845, a gate electrode 840, a channel region 850 beneath the gate dielectric 845, and a drain contact 860. The three-dimensional channel region 850 comprises a 2D material of a 2D dichalcogenide group including MX2, wherein M is molybdenum (Mo), tungsten (W), or titanium (Ti), and X is a chalcogenide, sulfur (S), or selenium (Se). The source contact 820 comprises a first crystalline alloy containing a transition metal, and the drain contact 860 comprises a second crystalline alloy containing a transition metal. The work function of the first and second crystalline alloys is adjusted to match the work function of the MX2 channel region 850 by adjusting the alloy composition as described above. It will be appreciated that the discussion above regarding the gate dielectric also applies here. The gate electrode 840 may comprise any material from a wide range of materials, such as polysilicon or various suitable metals (e.g., aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), or any other suitable metal or alloy). The gate electrode 840 may include a plug portion, one or more work function portions, a resistance reduction portion, and / or a substrate portion. Many gate dielectric and gate electrode configurations can be used, as will be readily apparent.

[0058] As previously mentioned, for ease of illustration, method 200 and Figures 3A-3HThe structures illustrated are depicted and described in the context of a fin transistor construction (e.g., a tri-gate or finFET) having one or more source and drain contacts and a gate electrode (which includes a crystalline alloy containing a transition metal). However, the principles and techniques described herein in various ways can be used to form other semiconductor devices and transistor constructions on a single substrate, including, for example, dual-gate, full-ring gate (e.g., nanowire / nanoribbon), planar, and other suitable transistor constructions. Moreover, recall that, depending on the specific construction, the structures described herein can be used to form PMOS, NMOS, or CMOS devices. It should also be noted that in some embodiments, the channel region described herein is located within at least a portion of at least one feature or body of the transistor, wherein said at least one feature / body comprises a semiconductor material, and said semiconductor material may optionally include corresponding impurities / dopants (e.g., such that the semiconductor material has a net doping type of n-type or p-type). In some such embodiments, said at least one feature / body may be fin-like, nanowire-like, nanoribbon-like, combinations thereof, and / or any other suitable shape that can be understood based on this disclosure. Furthermore, the location of the channel region within at least a portion of at least one feature / body can be determined based on other adjacent or proximate features of the transistor (e.g., source region, drain region, and / or gate structure). It should also be noted that in some such embodiments, the channel region can be generally considered as a transport region through which charge carriers (e.g., electrons or holes) can move. Many variations and constructions will be apparent in light of this disclosure.

[0059] The use of the techniques and structures provided herein can be detected using tools such as: electron microscopy including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), and reflection electron microscopy (REM); composition mapping; X-ray crystallography or diffraction (XRD); X-ray photoelectroluminescence spectrometry (XPS); energy-dispersive X-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atomic probe imaging or tomography; local electrode atomic probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, these being just a few suitable exemplary analytical tools. Specifically, in some embodiments of this disclosure, such tools can indicate the presence of a non-planar semiconductor device as described herein in various ways, having one or more of a source contact and a drain contact, and a gate electrode (which includes a crystalline alloy containing a transition metal).

[0060] Note that, as used herein, the expression "X includes at least one of A and B" means that X may include only A, only B, or both A and B. Therefore, X including at least one of A and B should not be construed as requiring X for each of A and B unless explicitly stated otherwise. For example, the expression "X includes A and B" means X that explicitly includes both A and B. Furthermore, this is true for any number of terms greater than two, where "at least one" of these terms is included in X. For example, the expression "X includes at least one of A, B, or C" as used herein means that X may include only A, only B, only C, only A and B (and no C), only A and C (and no B), only B and C (and no A), or each of A, B, and C. This is true even if any of A, B, or C happens to include multiple types or variations. Therefore, X that includes at least one of A, B, or C should not be understood to require X for each of A, B, and C unless explicitly stated otherwise. For example, the statement "X includes A, B, and C" means X that explicitly includes each of A, B, and C. Similarly, the statement "X that is included in at least one of A or B" means X that may (for example) be included only in A, only in B, or included in both A and B. It should be recognized that the discussion above relating to "X includes at least one of A or B" also applies here.

[0061] Exemplary System

[0062] Figure 9 This is an exemplary computing system implemented according to some embodiments of the present disclosure, having one or more of the integrated circuit structures disclosed herein. It can be seen that the computing system 900 houses a motherboard 902. The motherboard 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906, each of which may be physically and electrically coupled to the motherboard 902, or otherwise integrated into the motherboard 902. It should be understood that the motherboard 902 may be, for example, any printed circuit board, whether it is a motherboard, a daughterboard mounted on a motherboard, or the sole board of the system 900, etc.

[0063] Depending on its application, the computing system 900 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 902. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact disks (CDs), digital universal disks (DVDs), etc.). Any component included in the computing system 900 may include one or more integrated circuit structures or devices configured according to exemplary embodiments (e.g., to include one or more non-planar semiconductor devices having one or more source contacts and drain contacts and gate electrodes (which include crystalline alloys containing transition metals) as provided herein in various ways). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communication chip 906 may be part of or otherwise integrated into the processor 904).

[0064] The communication chip 906 enables wireless communication for transmitting data to and from the computing system 900. The term "wireless" and its derivatives can be used to describe circuits, apparatuses, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation over a non-solid medium. This term does not imply that the apparatus contains no wiring, although in some embodiments they may be wiring-free. The communication chip 906 can implement any of many wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), Global Microwave Access Interoperability (WiMAX) (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), 1x Evolution Data Optimized (EV-DO), High Speed ​​Packet Access (HSPA+), High Speed ​​Downlink Packet Access (HSDPA+), High Speed ​​Uplink Packet Access (HSUPA+), Enhanced Data Rate GSM Evolution (EDGE), Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher generations. The computing system 900 may include multiple communication chips 906. For example, the first communication chip 906 may be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 906 may be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and other long-range wireless communication. In some embodiments, the communication chip 906 may include one or more non-planar semiconductor devices having one or more of source contacts and drain contacts and gate electrodes (which comprise a crystalline alloy containing a transition metal) as described herein in various ways.

[0065] The processor 904 of the computing system 900 includes an integrated circuit die packaged within the processor 904. In some embodiments, the processor's integrated circuit die includes onboard circuitry implemented having one or more integrated circuit structures or devices described herein in various ways. The term "processor" can refer to any device or part of a device that processes, for example, electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0066] The communication chip 906 may also include an integrated circuit die packaged within the communication chip 906. According to some exemplary embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices described herein in various ways. Given this disclosure, it should be appreciated that multi-standard wireless capabilities can be directly integrated into the processor 904 (e.g., where the functionality of any chip 906 is integrated into the processor 904, rather than having a separate communication chip). Furthermore, it should be noted that the processor 904 can be a chipset with such wireless capabilities. In short, any number of processors 904 and / or communication chips 906 can be employed. Similarly, any chip or chipset can have multiple functions integrated therein.

[0067] In various embodiments, the computing system 900 may be a laptop, netbook, notebook, smartphone, tablet computer, personal digital assistant (PDA), super mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the techniques disclosed herein as described in various ways.

[0068] Other exemplary embodiments

[0069] The examples below relate to other embodiments, through which many substitutions and constructions will become apparent.

[0070] Example 1 is a nonplanar semiconductor device comprising: a three-dimensional channel region; a gate electrode at least above the three-dimensional channel region, the gate electrode comprising a first crystalline alloy containing a transition metal; and a gate dielectric between the gate electrode and the three-dimensional channel region.

[0071] Example 2 includes the subject matter of Example 1, and also includes a source region adjacent to the channel region; a source contact portion on the source region; a drain region adjacent to the channel region; and a drain contact portion on the drain region.

[0072] Example 3 includes the subject of Example 1 or Example 2, wherein the three-dimensional channel region comprises one of silicon (Si) or a group III-V semiconductor material.

[0073] Example 4 includes the subject of any of Examples 1 through 3, wherein the work function of the first crystalline alloy is aligned with the work function of the three-dimensional channel region, such that the threshold voltage of the non-planar semiconductor device is in the range between 0.2V and 0.7V.

[0074] Example 5 includes the subject matter of any of Examples 1 through 4, wherein the first crystalline alloy includes cobalt-iron-aluminum-silicon alloys (Co2FeSi, Co2FeAl). x Si 1-x (0≤x≤l), cobalt-manganese-silicon alloy (Co2MnSi), cobalt-iron-silicon-germanium alloy (Co2FeSiGe), cobalt-chromium-iron-aluminum alloy (Co2CrFeAl, Co2Cr) 0.5 Fe 0.5 Al), cobalt-iron-germanium-gallium alloy (Co2FeGeGa), manganese-gallium alloy (Mn3Ga), manganese-germanium alloy (Mn3Ge), manganese-germanium-gallium alloy (Mn3GeGa), or iron-manganese-silicon alloy (Fe). 3-x Mn x Si, 0≤x≤1.5) is at least one of them.

[0075] Example 6 includes the subject matter of any of Examples 1 through 4, wherein the first crystalline alloy includes at least one of M-manganese-germanium alloy (M2MnGe), M-manganese-gallium alloy (M2MnGa), M-manganese-aluminum alloy (M2MnAl), M-manganese-antimony alloy (MMnSb), or M-manganese-indium alloy (M2MnIn), wherein M is one of cobalt (Co), nickel (Ni), copper (Cu), rhodium (Rh), palladium (Pd), or platinum (Pt).

[0076] Example 7 includes the subject matter of any of Examples 1 through 6, and further includes a first layer directly between the gate dielectric and the gate electrode, the first layer comprising at least one of magnesium oxide (MgO), magnesium aluminum oxide (MgAlO), strontium titanate (SrTiO3), aluminum oxide (Al2O3), dysprosium scandium oxide (DyScO3), niobium scandium oxide (NbScO3), or niobium strontium titanate (NbSrTiO3).

[0077] Example 8 includes the subject of Example 7, wherein the first layer matches the first crystalline alloy lattice.

[0078] Example 9 includes the subject of Example 7 or Example 8, wherein the first layer has a first lattice parameter and the first crystalline alloy has a second lattice parameter within + / -2% of the first lattice parameter.

[0079] Example 10 includes the subject of any of Examples 7 through 9, wherein the first layer has a first lattice parameter and the first crystalline alloy has a second lattice parameter within the tolerance of the first lattice parameter, such that there is lattice continuity across the entire interface between the first layer and the first crystalline alloy.

[0080] Example 11 is a method for forming a transistor, the method comprising: forming a three-dimensional channel region; forming a gate electrode at least over the three-dimensional channel region, the gate electrode comprising a first crystalline alloy containing a transition metal; and forming a gate dielectric between the gate electrode and the three-dimensional channel region.

[0081] Example 12 includes the subject matter of Example 11, and further includes forming a source region adjacent to the channel region; forming a source contact on the source region; forming a drain region adjacent to the channel region; and forming a drain contact on the drain region.

[0082] Example 13 includes the subject matter of Example 11 or Example 12, and further includes aligning the work function of the first crystalline alloy with the work function of the three-dimensional channel region such that the threshold voltage of the non-planar semiconductor device is in the range between 0.2V and 0.7V.

[0083] Example 14 is a nonplanar semiconductor device comprising: a three-dimensional channel region; a source region adjacent to the channel region; and a source contact portion on the source region, the source contact portion comprising a first crystalline alloy containing a transition metal.

[0084] Example 15 includes the subject matter of Example 14, and further includes a gate electrode at least above the three-dimensional channel region; and a gate dielectric between the gate electrode and the three-dimensional channel region.

[0085] Example 16 includes the subject matter of Example 14 or Example 15, and further includes a drain region adjacent to the channel region and a drain contact portion on the drain region, the drain contact portion comprising a second crystalline alloy containing a transition metal.

[0086] Example 17 includes the subject of any of Examples 14 to 16, wherein the three-dimensional channel region includes MX2, where M is molybdenum (Mo), tungsten (W), or titanium (Ti), and X is sulfur (S) or selenium (Se).

[0087] Example 18 includes the subject of any of Examples 14 through 17, wherein the first crystalline alloy is matched with the source pole lattice.

[0088] Example 19 includes the subject of any of Examples 14 to 18, wherein the first crystalline alloy has a first lattice parameter and the source region has a second lattice parameter within + / -2% of the first lattice parameter.

[0089] Example 20 includes the subject of any of Examples 14 to 19, wherein the first crystalline alloy has a first lattice parameter and the source region has a second lattice parameter within the tolerance of the first lattice parameter, such that there is lattice continuity across the entire interface between the first crystalline alloy and the source region.

[0090] Example 21 includes the subject of any of Examples 14 through 20, wherein the work function of the first crystalline alloy is aligned with the work function of the source region such that the Schottky barrier height associated with the interface between the first crystalline alloy and the source region is in the range of less than or equal to 0.3 eV.

[0091] Example 22 includes the subject matter of any of Examples 14 through 21, wherein the first crystalline alloy comprises a cobalt-iron-aluminum-silicon alloy (Co2FeSi, Co2FeAl). x Si 1-x (0≤x≤l), cobalt-manganese-silicon alloy (Co2MnSi), cobalt-iron-silicon-germanium alloy (Co2FeSiGe), cobalt-chromium-iron-aluminum alloy (Co2CrFeAl, Co2Cr) 0.5 Fe 0.5 Al), cobalt-iron-germanium-gallium alloy (Co2FeGeGa), manganese-gallium alloy (Mn3Ga), manganese-germanium alloy (Mn3Ge), manganese-germanium-gallium alloy (Mn3GeGa), or iron-manganese-silicon alloy (Fe). 3-x Mn x Si, 0≤x≤1.5) is at least one of them.

[0092] Example 23 includes the subject matter of any of Examples 14 to 21, wherein the first crystalline alloy includes at least one of M-manganese-germanium alloy (M2MnGe), M-manganese-gallium alloy (M2MnGa), M-manganese-aluminum alloy (M2MnAl), M-manganese-antimony alloy (MMnSb), or M-manganese-indium alloy (M2MnIn), wherein M is one of Co, Ni, Cu, Rh, Pd, or Pt.

[0093] Example 24 includes the subject of any of Examples 16 through 23, wherein the second crystalline alloy is matched with the drain region lattice.

[0094] Example 25 includes the subject of any of Examples 16 to 24, wherein the second crystalline alloy has a third lattice parameter and the drain region has a fourth lattice parameter within + / -2% of the third lattice parameter.

[0095] Example 26 includes the subject of any of Examples 16 to 25, wherein the second crystalline alloy has a third lattice parameter and the drain region has a fourth lattice parameter within the tolerance of the third lattice parameter, such that there is lattice continuity across the entire interface between the second crystalline alloy and the drain region.

[0096] Example 27 includes the subject of any of Examples 16 to 26, wherein the work function of the second crystalline alloy is aligned with the work function of the drain region such that the Schottky barrier height associated with the interface between the second crystalline alloy and the drain region is in the range of less than or equal to 0.3 eV.

[0097] Example 28 includes the subject matter of any of Examples 16 to 27, wherein the second crystalline alloy comprises a cobalt-iron-aluminum-silicon alloy (Co2FeSi, Co2FeAl). x Si 1-x (0≤x≤l), cobalt-manganese-silicon alloy (Co2MnSi), cobalt-iron-silicon-germanium alloy (Co2FeSiGe), cobalt-chromium-iron-aluminum alloy (Co2CrFeAl, Co2Cr) 0.5 Fe 0.5 Al), cobalt-iron-germanium-gallium alloy (Co2FeGeGa), manganese-gallium alloy (Mn3Ga), manganese-germanium alloy (Mn3Ge), manganese-germanium-gallium alloy (Mn3GeGa), or iron-manganese-silicon alloy (Fe). 3-x Mn x Si, 0≤x≤1.5) is at least one of them.

[0098] Example 29 includes the subject matter of any of Examples 16 to 27, wherein the second crystalline alloy includes at least one of M-manganese-germanium alloy (M2MnGe), M-manganese-gallium alloy (M2MnGa), M-manganese-aluminum alloy (M2MnAl), M-manganese-antimony alloy (MMnSb), or M-manganese-indium alloy (M2MnIn), wherein M is one of Co, Ni, Cu, Rh, Pd, or Pt.

[0099] Example 30 is a method for forming a nonplanar semiconductor device, the method comprising: forming a three-dimensional channel region; forming a source region adjacent to the channel region; and forming a source contact portion on the source region, the source contact portion comprising a first crystalline alloy containing a transition metal.

[0100] Example 31 includes the subject matter of Example 30, and further includes forming a gate electrode at least over the three-dimensional channel region; and forming a gate dielectric between the gate electrode and the three-dimensional channel region.

[0101] Example 32 includes the subject matter of Example 30 or Example 31, and further includes forming a drain region adjacent to the channel region; and forming a drain contact portion on the drain region, the drain contact portion comprising a second crystalline alloy containing a transition metal.

[0102] Example 33 includes the subject matter of any of Examples 30 to 32, and also includes aligning the work function of the first crystalline alloy with the work function of the source region such that the Schottky barrier height associated with the interface between the first crystalline alloy and the source region is in the range of less than or equal to 0.3 eV.

[0103] Example 34 includes the subject of Example 32 or Example 33, and further includes aligning the work function of the second crystalline alloy with the work function of the drain region such that the Schottky barrier height associated with the interface between the second crystalline alloy and the drain region is in the range of less than or equal to 0.3 eV.

[0104] Example 35 is a computing device or system that includes the subject matter of any of Examples 1 to 10 or Examples 14 to 29.

[0105] The foregoing description of exemplary embodiments has been presented for purposes of illustration and explanation. It is not intended to be exhaustive or to limit this disclosure to the exact forms disclosed. Many modifications and variations are possible in light of this disclosure. The scope of this disclosure is not intended to be limited by this specific embodiment, but rather is defined by the appended claims. Future applications claiming priority to this application may assert the disclosed subject matter in different ways and may generally include any set of one or more limitations as disclosed herein or otherwise shown.

Claims

1. A non-planar semiconductor device, comprising: Three-dimensional channel region; A gate electrode, the gate electrode being at least above the three-dimensional channel region, the gate electrode comprising a first crystalline alloy containing a transition metal; A gate dielectric, wherein the gate dielectric is located between the gate electrode and the three-dimensional channel region; and A first layer is located directly between the gate dielectric and the gate electrode, and the first layer is matched with the lattice of the first crystalline alloy.

2. The non-planar semiconductor device according to claim 1 further includes a source region adjacent to the channel region, a source contact portion on the source region, a drain region adjacent to the channel region, and a drain contact portion on the drain region.

3. The non-planar semiconductor device according to claim 1, wherein, The three-dimensional channel region includes either silicon (Si) or a III-V group semiconductor material.

4. The non-planar semiconductor device according to claim 1, wherein, The work function of the first crystalline alloy is aligned with the work function of the three-dimensional channel region, such that the threshold voltage of the non-planar semiconductor device is in the range between 0.2V and 0.7V.

5. The non-planar semiconductor device according to claim 1, wherein, The first crystalline alloy includes cobalt-iron-aluminum-silicon alloys (Co2FeSi, Co2FeAl) x Si 1-x (0≤x≤l), cobalt-manganese-silicon alloy (Co2MnSi), cobalt-iron-silicon-germanium alloy (Co2FeSiGe), cobalt-chromium-iron-aluminum alloy (Co2CrFeAl, Co2Cr) 0.5 Fe 0.5 Al), cobalt-iron-germanium-gallium alloy (Co2FeGeGa), manganese-gallium alloy (Mn3Ga), manganese-germanium alloy (Mn3Ge), manganese-germanium-gallium alloy (Mn3GeGa), or iron-manganese-silicon alloy (Fe). 3-x Mn x Si, 0≤x≤1.5) is at least one of them.

6. The non-planar semiconductor device according to claim 1, wherein, The first crystalline alloy includes at least one of M-manganese-germanium alloy (M2MnGe), M-manganese-gallium alloy (M2MnGa), M-manganese-aluminum alloy (M2MnAl), M-manganese-antimony alloy (MMnSb), or M-manganese-indium alloy (M2MnIn), wherein, M is one of cobalt (Co), nickel (Ni), copper (Cu), rhodium (Rh), palladium (Pd), or platinum (Pt).

7. The nonplanar semiconductor device according to any one of claims 1-6, wherein, The first layer comprises at least one of magnesium oxide (MgO), magnesium aluminum oxide (MgAlO), strontium titanate (SrTiO3), aluminum oxide (Al2O3), dysprosium scandium oxide (DyScO3), niobium scandium oxide (NbScO3), or niobium strontium titanate (NbSrTiO3).

8. The non-planar semiconductor device according to claim 1, wherein, The first layer has a first lattice parameter, and the first crystalline alloy has a second lattice parameter within + / -2% of the first lattice parameter.

9. The non-planar semiconductor device according to claim 1, wherein, The first layer has a first lattice parameter, and the first crystalline alloy has a second lattice parameter within the tolerance of the first lattice parameter, such that there is lattice continuity across the entire interface between the first layer and the first crystalline alloy.

10. A method for forming a non-planar semiconductor device, the method comprising: Forming a three-dimensional channel region; A gate electrode is formed at least above the three-dimensional channel region, the gate electrode comprising a first crystalline alloy containing a transition metal; A gate dielectric is formed between the gate electrode and the three-dimensional channel region; as well as A first layer is formed directly between the gate dielectric and the gate electrode, the first layer being matched with the lattice of the first crystalline alloy.

11. The method of claim 10, further comprising forming a source region adjacent to the channel region, forming a source contact portion on the source region, forming a drain region adjacent to the channel region, and forming a drain contact portion on the drain region.

12. The method according to claim 10 or 11, further comprising aligning the work function of the first crystalline alloy with the work function of the three-dimensional channel region, such that the threshold voltage of the non-planar semiconductor device is in the range between 0.2V and 0.7V.

13. A non-planar semiconductor device, comprising: Three-dimensional channel region; The source region is adjacent to the channel region; as well as A source contact portion, located on the source region, comprising a first crystalline alloy containing a transition metal. The first crystalline alloy is lattice-matched with the source pole region.

14. The nonplanar semiconductor device of claim 13, further comprising a gate electrode at least above the three-dimensional channel region, and a gate dielectric between the gate electrode and the three-dimensional channel region.

15. The nonplanar semiconductor device of claim 14, further comprising a drain region adjacent to the channel region and a drain contact portion on the drain region, the drain contact portion comprising a second crystalline alloy containing a transition metal.

16. The non-planar semiconductor device according to claim 13, wherein, The three-dimensional channel region includes MX2, where M is molybdenum (Mo), tungsten (W), or titanium (Ti), and X is sulfur (S) or selenium (Se).

17. The non-planar semiconductor device according to claim 13, wherein, The first crystalline alloy has a first lattice parameter, and the source region has a second lattice parameter within + / -2% of the first lattice parameter.

18. The non-planar semiconductor device according to claim 13, wherein, The first crystalline alloy has a first lattice parameter, and the source region has a second lattice parameter within the tolerance of the first lattice parameter, such that there is lattice continuity across the entire interface between the first crystalline alloy and the source region.

19. The non-planar semiconductor device according to claim 13, wherein, The work function of the first crystalline alloy is aligned with the work function of the source region, such that the Schottky barrier height associated with the interface between the first crystalline alloy and the source region is in the range of less than or equal to 0.3 eV.

20. The non-planar semiconductor device according to claim 15, wherein, The second crystalline alloy is lattice-matched with the drain region.

21. The non-planar semiconductor device according to claim 20, wherein, The second crystalline alloy has a third lattice parameter, and the drain region has a fourth lattice parameter within + / -2% of the third lattice parameter.

22. The non-planar semiconductor device according to claim 20, wherein, The second crystalline alloy has a third lattice parameter, and the drain region has a fourth lattice parameter within the tolerance of the third lattice parameter, such that there is lattice continuity across the entire interface between the second crystalline alloy and the drain region.

23. The non-planar semiconductor device according to claim 15, wherein, The work function of the second crystalline alloy is aligned with the work function of the drain region, such that the Schottky barrier height associated with the interface between the second crystalline alloy and the drain region is in the range of less than or equal to 0.3 eV.

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