Method for manufacturing ohmic contacts for HEMT devices

Abstract

A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of forming a photoresist layer on a semiconductor body comprising a heterostructure; forming an opening in the photoresist layer through which a surface region of the semiconductor body is exposed at the heterostructure; etching the surface region of the semiconductor body using the photoresist layer as an etch mask to form a trench in the heterostructure; depositing one or more metal layers in the trench and on the photoresist layer; and performing a process to strip the photoresist layer.

Description

Technical Field

[0001] This disclosure relates to a method for fabricating ohmic contacts for field-effect transistors, which have high electron mobility and are referred to as HEMTs (High Electron Mobility Transistors). In particular, this disclosure discusses a self-alignment process for gold-free ohmic contacts, which can be applied to, for example, the source and drain contacts of HEMT devices. Background Technology

[0002] As is well known, HEMT devices contain heterostructures, which have an interface between two semiconductors of different materials, such as aluminum gallium nitride (AlGaN) and gallium nitride (GaN). When the HEMT device is properly biased, a two-dimensional electron gas (2DEG) layer is induced at this interface.

[0003] The 2DEG layer represents an electron cloud with high charge density and high charge mobility. These characteristics make HEMT devices attractive for both radio frequency (RF) applications and power electronics.

[0004] Typically, HEMT devices include ohmic contacts for the source and drain terminals, which are made of gold to achieve low contact and access resistance (cf. Ferdinando Iucolano, Giuseppe Greco and Fabrizio Roccaforte - Applied Physics Letters 103, 201604 (2013); doi:10.1063 / 1.4828839).

[0005] Methods for fabricating gold ohmic contacts typically involve depositing a sequence of stacked metal layers on a semiconductor substrate, the stack comprising a substrate, a GaN layer, and an AlGaN layer. The GaN and AlGaN layers form a heterostructure.

[0006] The aforementioned sequence of metal layers is obtained using known processes (such as photolithography and lift-off steps) and includes a titanium (Ti) layer in contact with the semiconductor body surface, an aluminum (Al) layer on the titanium layer, a nickel (Ni) layer on the aluminum layer, and gold (Au) deposited on the nickel layer. The first three layers mentioned above are tuned in a known manner to facilitate adhesion between the gold (which functions as the central body of the ohmic contact) and the semiconductor body.

[0007] The method for fabricating gold ohmic contacts requires a thermal annealing process at high temperatures (e.g., above 800°C). Under such temperature conditions, Ti reacts with N2 available in GaN to form titanium nitride. Charge transport is guided by the metallogenic behavior of TiN due to the metal intrusion into the 2DEG region. Because gold causes metal contamination, the formation of gold contacts is not easily achieved on CMOS lines under any circumstances, requiring dedicated equipment and isolated production areas.

[0008] A commonly used alternative is to use gold-free ohmic contacts, in which the central body of the ohmic contact is made of titanium and aluminum.

[0009] The default presence of gold in ohmic contacts allows for a reduction in annealing temperatures to 600°C and enables the use of techniques such as rapid thermal annealing (RTA). In particular, RTA reduces the mechanical stress on the semiconductor body with ohmic contacts and prevents the formation of charge trap states, thus improving the efficiency and productivity of the manufacturing process and the HEMT devices themselves.

[0010] Various metal-free ohmic contact physical structures are known in the prior art. In particular, the two components in these structures... Figure 1A and 1B The middle section is shown in the side cross-section diagram.

[0011] Figure 1A An ohmic contact structure 4 in a known type of HEMT device is shown, which has a non-embedded semiconductor body 2 ("An Au-free GaN High Electron Mobility Transistor with Ti / Al / WOhmic Metal Structure" by Jing-Neng Yao et al., IEEE, 2015). A passivation layer 3, such as SiN, extends over the semiconductor body 2, and particularly over the ohmic contact 4, to protect the ohmic contact.

[0012] Figure 1BAn ohmic contact structure 6 in a known type of HEMT device is shown, which has an embedded semiconductor body 7 ("AlxGa1xN / GaN MISHEMTs with a common gold-free metal-stack for source / drain / gate" by WHTham et al., IEEE Electronic Devices Letters, Vol. 36, No. 12, December 2015). A dielectric layer 8, such as SiN, extends over the semiconductor body 7. The ohmic contact 6 extends through the dielectric layer 8.

[0013] The process of manufacturing the ohmic contact 6 embedded in the semiconductor body 7 ( Figure 1B The proof is that obtaining a non-embedded ohmic contact structure is more efficient than obtaining a non-embedded ohmic contact Figure 1A The process is more complex. However, through Figure 1B The electrical performance of the HEMT device of the type shown is proven to be higher than that obtained by... Figure 1A The HEMT devices achieve the same electrical performance as the HEMT devices, and further exhibit better reproducibility and reliability.

[0014] Furthermore, the use of passivating material (here, SiN) to protect ohmic contacts 4 and 6 results in a more dispersed value of their contact resistance. Summary of the Invention

[0015] The purpose of this disclosure is to provide a method for manufacturing ohmic contacts for HEMT devices that overcomes the limitations of the prior art.

[0016] According to this disclosure, a method for manufacturing an ohmic contact for HEMT devices is provided. Attached Figure Description

[0017] To better understand this disclosure, preferred embodiments will now be described by way of non-limiting example with reference to the accompanying drawings, in which:

[0018] Figure 1A and 1B According to known embodiments, corresponding HEMT devices with non-embedded ohmic contacts and ohmic contacts embedded in the semiconductor body are shown in side cross-sectional views respectively;

[0019] Figure 2-6 According to embodiments of the present disclosure, a side cross-sectional view illustrates the manufacturing steps for obtaining an HEMT device having an ohmic contact embedded in a semiconductor body;

[0020] Figure 7-8 It shows according to Figure 2-5 The intermediate structure that can be obtained through the manufacturing process;

[0021] Figure 9A-12 According to another embodiment of this disclosure, a side cross-sectional view illustrates the manufacturing steps for obtaining an HEMT device having an ohmic contact embedded in a semiconductor body. Detailed Implementation

[0022] Figures 2-6 The manufacturing steps for obtaining the embedded type ohmic contact structure 10 are shown in a side cross-sectional view in a triaxial rectangular coordinate system X, Y, Z. The structure as a whole is Figure 6 As shown in the figure. This structure 10 constitutes part of the HEMT device.

[0023] refer to Figure 2 It provides a substrate 12 for semiconductor materials, such as silicon, silicon carbide (SiC), or sapphire (Al2O3), or some other materials.

[0024] Along the Z-axis and in a manner known per se, the following are formed on the substrate 12: a first structural layer 14, particularly an intrinsic gallium nitride (GaN) first structural layer (channel layer of the HEMT device), which is epitaxially grown on the substrate 12, for example; a second structural layer 16, particularly an intrinsic aluminum gallium nitride (AlGaN) or more generally a compound based on a ternary or quaternary alloy of gallium nitride (barrier layer of the HEMT device), such as AlxGa1-xN, AlInGaN, InxGa1-xN, AlxIn1-xAl, which is epitaxially grown on the channel layer 14, for example; and optionally a protective layer 18, particularly a GaN protective layer with a thickness of only a few nanometers (e.g., 1-4 nm), which functions to protect the barrier layer 16 from oxidation.

[0025] The channel layer 14 and the barrier layer 16 form a heterogeneous structure 17 in a manner known per se.

[0026] One or more additional buffer layers may exist between the substrate 12 and the channel layer 14 in a manner not shown in the figure.

[0027] The channel layer 14 has a thickness, for example, between approximately 1 μm and 5 μm (along the Z-axis); the barrier layer 16 has a thickness, for example, between approximately 5 nm and 30 nm (along the Z-axis).

[0028] A 2DEG layer 15 is formed at the interface between the channel layer 14 and the barrier layer 16. Charge carriers belonging to the 2DEG layer can move freely in any direction at the 2DEG interface 15 in the plane XY (defined by the X-axis and Y-axis), while they are confined along the Z-axis.

[0029] The substrate 12, the channel layer 14, the barrier layer 16, and the protective layer 18 form the semiconductor body 5.

[0030] refer to Figure 3A A photoresist layer 28 with a thickness, for example, between 1 and 3 μm, is deposited. This photoresist layer 28 completely and uniformly covers the epitaxial layer 18.

[0031] Then, the photoresist layer 28 is exposed to light using a mask 30 (indicated by arrow 32). In the subsequent etching step, the areas of the photoresist layer 28 not covered by the mask 30 become soluble.

[0032] The mask 30 exposes region 34 of the photoresist layer 28. This region 34 defines the area in which ohmic contacts will be provided.

[0033] Then( Figure 3B The mask 30 is removed, and an etching step (e.g., wet etching) is performed to selectively remove regions 34 of the photoresist layer 28. This forms trenches 35 in the photoresist layer 28, exposing surface portions 19 of the protective layer 18 through the trenches.

[0034] The photolithography steps listed above have been described with reference to positive photoresist. In a manner obvious to those skilled in the art, different embodiments not shown envision forming trenches 35 in the photoresist layer 28 using negative photoresist by appropriately modifying the photomask used.

[0035] It can be noted that, as is generally conceived in the prior art, referring to Figure 1- Figure 3B The described process does not require the deposition of a passivation material layer (such as silicon nitride).

[0036] refer to Figure 4 Then, etching (indicated by arrow 40) is performed to selectively remove portions of the protective layer 18 exposed through the trench 35 and the underlying barrier layer 16. More specifically, the etching process includes a first step for removing the protective layer 18 and a second step for partially or completely removing the barrier layer 16. Both steps utilize Cl2-based chemicals.

[0037] The photoresist layer 28 serves as an etching mask to protect the areas of the semiconductor body 5 that are not exposed through the trench 35.

[0038] At trench 35, the semiconductor body 5 is further etched to form a contact trench 42 terminating within the barrier layer 16 itself, the contact trench extending in depth within the barrier layer 16. The contact trench 42 is defined at its bottom by the bottom surface 44 of the barrier layer 16.

[0039] Contact groove 42 is designed to accommodate ohmic contacts, as described below.

[0040] Referring to etching process 40, the first etching step is designed to remove the protective layer 18 over its entire thickness in the area exposed by trench 35, while the second etching step is designed to remove only a portion of the thickness of the barrier layer 16 along the Z-axis. Clearly, in the absence of the protective layer 18 (optionally), etching process 40 includes a single etching step for removing a selected portion of the barrier layer 16.

[0041] Furthermore, it is evident that in other embodiments, the contact trench 42 may extend through the entire thickness of the barrier layer 16, terminating at the interface with the bottom layer (here, the channel layer 14), or, depending on design requirements and parameters, continue into the bottom layer.

[0042] refer to Figure 5 Then, using known techniques such as sputtering or evaporation, one or more layers of conductive material, particularly one or more metal layers, are deposited. Specifically, a stack of metal layers suitable for forming the ohmic contact 22 is formed. Figure 5 and Figure 6 Three of them are shown in the image.

[0043] According to one embodiment, the stack forming the metal layers includes forming a first interface layer 22a and a fill layer 22b on the interface layer 22a. The interface layer 22a is made of a material selected from titanium and tantalum. The fill layer 22b is in particular made of aluminum.

[0044] According to a further embodiment, the stacking of the metal layers includes sequentially forming a first titanium or tantalum layer, an aluminum layer, and a second layer, which is also made of titanium or tantalum. The Ti layer is adapted to facilitate adhesion of the nickel or tungsten layer to the bottom surface 44 of the contact trench 42 (i.e., to the barrier layer 16) and functions as an interface layer 22a. Alternatively, the Al layer serves as a filler layer 22b or a central body for the ohmic contact 22. The final Ti or Ta layer serves as an encapsulation layer.

[0045] It is evident that, according to design specifications, other materials or different numbers of layers can be used to form the stack of ohmic contacts 22. For example, the interface layer 22a can be omitted by depositing only the fill layer 22b, in which case the fill layer 22b is made of aluminum.

[0046] One or more conductive materials for forming the ohmic contact 22 are deposited inside the trench 42 and outside the trench, on top of the photoresist layer 28, which is thus covered on top by a pseudo-metal deposition 45.

[0047] The next step is the stripping step, which is used to remove the photoresist layer 28 and the pseudo-metal material 45.

[0048] The rapid thermal annealing (RTA) step is then performed, which perfects the ohmic contact in a manner known per se. This process is carried out in a protected environment (e.g., in a nitrogen or argon atmosphere) at a temperature range of approximately 450°C to approximately 650°C.

[0049] Figure 6 The structure 10 at the end of the manufacturing step is shown, which includes an embedded gold-free ohmic contact 22.

[0050] As can be seen, the ohmic contact 22 automatically or autonomously aligns with the embedded region previously formed in the heterostructure 17.

[0051] This result is achieved by using the same photoresist layer 28 in two different steps of the manufacturing process. First, the photoresist layer 28 is used as a mask during etching 40 to form contact trenches 42 (and thus to define the embedding region in the heterostructure 17). Additionally, the photoresist layer 28 is used as another mask for forming ohmic contacts 22 by depositing a metallic material.

[0052] Figure 7 Possible arrangements are shown after depositing one or more metal layers to create ohmic contact 22 and pseudo-metallic material 45. Figure 7 The layout and Figure 5 The arrangement is similar, except that a pseudo-metallic material 45' (sometimes referred to as "dog ears") is added along the sidewalls of the photoresist layer 28. This pseudo-metallic material 45' is a possible metal deposition artifact of one or more metal layers of the ohmic contact 22, such as by sputtering or evaporation. This pseudo-metallic material 45' is undesirable because the connection between the pseudo-metallic material 45 and the ohmic contact 22 will hinder the peeling of the pseudo-metallic material 45 and / or damage the ohmic contact 22.

[0053] To avoid the formation of pseudo-metal material 45' along the sidewalls of the photoresist layer 28, a structure such as... Figure 8 The photoresist layer with sloping sidewalls 28' is shown. Typically, the deposition of an additional layer (e.g., by vapor deposition) is performed substantially vertically to form the ohmic contact 22. Therefore, the protrusion of the sloping sidewalls 28' allows the ohmic contact 22 to form within the contact trench 42 without contacting the sloping sidewalls 28' or the sidewalls of layers 16, 18, and thus prevents the formation of the pseudo-metallic material 45' along the sidewalls of any of layers 16, 18, 28. Therefore, the pseudo-metallic material 45 and the photoresist layer 28 can be stripped without damaging the ohmic contact 22.

[0054] like Figure 8 The problem with the arrangement shown is that it is difficult to control the process of forming the sloping sidewall 28', and this control needs to be very precise.

[0055] Figures 9A-12 The manufacturing steps for obtaining the ohmic contact structure 50 according to another embodiment of the present disclosure are shown.

[0056] refer to Figure 9A Structure 50 includes a semiconductor body 5' formed from a semiconductor substrate 12 and a heterostructure 17'. The heterostructure 17' is formed from a channel layer 14 and a barrier layer 16. (As in...) Figures 2-6 In some embodiments, the semiconductor body 5' may optionally include a protective layer, such as a protective layer 18, for protecting the barrier layer.

[0057] A double layer 51 is deposited on the semiconductor body 5', comprising a bottom layer 52 and a photoresist layer 28. The thickness of the bottom layer 52 may be slightly greater than that of the vapor-deposited metal, for example, between 0.6 μm and 1.5 μm. The bottom layer 52 may be a solution of an organic polymer, such as SF11 or SF09, spun on the semiconductor body 5', or may be any other material that can be etched by a developer to etch the photoresist layer 28.

[0058] The step following the deposition of the double layer 51 is to perform photolithography on the photoresist layer 28 using a mask 30 (indicated by arrow 32). In the subsequent etching step, the areas of the photoresist layer 28 not covered by the mask 30 thus become soluble.

[0059] exist Figure 9B In this process, mask 30 is removed, and an etching step (e.g., wet etching) is performed to selectively remove regions 34 of the photoresist layer 28 and a portion of the underlying layer 52. Consequently, a trench 54 is formed through the photoresist layer 28 and the underlying layer 52, exposing a surface portion 55 of the semiconductor body 5'. An underlying layer 52 is formed that can be etched by a developer used to remove regions 34 of the photoresist layer 28, and a wet developer is used such that a portion 28' of the photoresist layer 28 is suspended over the remainder of the underlying layer 52.

[0060] The photolithography steps listed above have been described with reference to positive photoresist. Different embodiments not shown, in a manner obvious to those skilled in the art, envision utilizing negative photoresist to form trench 54 by appropriately modifying the photomask used.

[0061] As is typically envisioned in the prior art, it can be noted that, reference Figures 9A-9B The described process does not require the deposition of a passivation material layer (such as silicon nitride).

[0062] refer to Figure 10 Then, etching (indicated by arrow 40) is performed to selectively remove a portion of the barrier layer 16 through the trench 54, exposing the barrier layer 16. Figures 2-6The same method can be used to partially or completely etch through the barrier layer 16. The etching is preferably dry etching, thereby protecting the portion of the semiconductor body 5' covered by the protrusion 28' of the photoresist layer 28 from etching.

[0063] Etching of the semiconductor body 5' at trench 54 forms a contact trench 56, which extends in depth within the barrier layer 16 and terminates within the barrier layer 16 itself. The contact trench 56 is defined at its bottom by the surface 57 of the barrier layer 16.

[0064] Furthermore, it is evident that in other embodiments, the contact trench 56 may extend throughout the entire thickness of the barrier layer 16, terminating at the interface with the bottom layer (here, the channel layer 14), or continuing into the bottom layer.

[0065] refer to Figure 11 Then, using known techniques such as sputtering or evaporation, one or more layers of conductive material, particularly one or more metal layers, are deposited. In particular, an ohmic contact 22 is formed by deposition, which may include layers 22a and 22b as described above.

[0066] One or more conductive materials for forming the ohmic contact 22 are deposited inside the trench 56 and outside the trench, above the photoresist layer 28, which is thus covered on top by a pseudo-metal deposition 45. Due to the presence of protrusions 28' of the photoresist layer 28, which act as a mask, the ohmic contact 22 is formed on the surface 57 of the barrier layer 16 and spaced apart from the sidewalls of the underlying layer 52. Furthermore, with... Figure 7 In contrast to the pseudo-metal material 45' shown, no pseudo-metal material is formed on those sidewalls due to the presence of the underlying layer 52 and the vertical orientation of the photoresist layer 28 sidewalls.

[0067] After the formation of the ohmic contact 22, a stripping step is performed to remove the substrate 52, the photoresist layer 28, and the pseudo-metal material 45. Figure 12 A structure 20 is shown at the end of the manufacturing step, which includes an embedded gold-free ohmic contact 22.

[0068] It can be seen that the ohmic contact 22 automatically or autonomously aligns with the embedded region previously formed in the heterostructure 17.

[0069] This result is achieved by using the same photoresist layer 28 in two different steps of the manufacturing process. First, the photoresist layer 28 is used as a mask during etching 40 to form contact trenches 56 (and thus to define the embedding region in the heterostructure 17). Additionally, the photoresist layer 28 is used as another mask for forming ohmic contacts 22 by depositing a metallic material.

[0070] The advantages provided by this disclosure are obvious from the study of the features provided herein.

[0071] In particular, it is possible to obtain gold-free ohmic contacts with lower contact and connection resistance, and their electrical performance is highly reproducible.

[0072] By using a photoresist layer as a mask during both the etching step and the metal deposition of the ohmic contact, the manufacturing process is simplified. Consequently, the ohmic contact automatically aligns with the embedded AlGaN region. This enables better electrical performance and reduces associated production costs for HEMT devices, while ensuring the structural quality of the ohmic contact.

[0073] The low contact resistance enables higher maximum current to pass through the HEMT device, and thus higher output power.

[0074] Furthermore, low contact resistance is fundamental to improving the frequency response of HEMT devices in RF applications.

[0075] According to this disclosure, a passivation layer is not necessary for forming metal contacts. The default use of passivation materials in the process of manufacturing ohmic contacts allows for a lower spread of contact resistance values, thereby improving the electrical performance of HEMT devices.

[0076] Therefore, the disclosure described herein reduces the cost of manufacturing ohmic contacts, thus making the manufacturing process compatible with CMOS technology.

[0077] Finally, it is obvious that modifications and changes can be made to the disclosure described and illustrated herein without departing from the scope of this disclosure.

[0078] The various embodiments described above can be combined to provide further embodiments. Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the claims and specification, but should be interpreted to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. A method for manufacturing an ohmic contact for a high electron mobility transistor (HEMT) device, comprising: A protective layer is formed on a semiconductor body containing a heterostructure; A photoresist layer is formed on the protective layer; An opening is formed through the photoresist layer and the protective layer, and a surface region of the semiconductor body is exposed through the opening at the location of the heterostructure; The photoresist layer is used as an etching mask to wet-etch the surface area of ​​the semiconductor body to form trenches in the heterostructure; One or more metal layers are deposited in the trench and on the photoresist layer to form an ohmic contact located in the trench; as well as A stripping process is performed on the protective layer and the photoresist layer. The formation of the opening in the protective layer and the photoresist layer includes forming a protruding portion of the photoresist layer, the protruding portion extending beyond the sidewall of the protective layer into the opening and spaced apart from the ohmic contact.

2. The method according to claim 1, wherein, Depositing the one or more metal layers includes using the photoresist layer as a deposition mask.

3. The method according to claim 1, wherein, Depositing the one or more metal layers includes forming a stack, the stack including a metal interface layer in contact with the heterostructure and a metal fill layer on the metal interface layer.

4. The method according to claim 3, wherein, Forming the metal interface layer includes depositing a material selected from titanium and tantalum; and forming the metal filler layer includes depositing an aluminum layer.

5. The method of claim 1, further comprising: A rapid thermal annealing process is performed on the one or more metal layers.

6. The method according to claim 5, wherein the rapid thermal annealing process is performed in a temperature range between 450°C and 650°C.

7. The method according to claim 1, wherein, The semiconductor body includes a substrate, a trench layer on the substrate, and a barrier layer on the trench layer, wherein the trench is formed to pass through a portion of the barrier layer or through the thickness of the barrier layer.

8. The method according to claim 1, wherein, Performing the stripping process involves performing the stripping process on portions of the one or more metal layers on the photoresist layer.

9. A method comprising: A protective layer is formed on the semiconductor body; A photoresist layer is formed on the protective layer; An opening is formed through the photoresist layer and the protective layer, and a surface region of the semiconductor body is exposed through the opening; The photoresist layer is used as an etching mask to wet-etch the surface area of ​​the semiconductor body to form trenches in the semiconductor body; One or more metal layers are deposited in the trench and on the photoresist layer to form an ohmic contact located in the trench; as well as A stripping process is performed on the protective layer and the photoresist layer. The formation of the opening in the protective layer and the photoresist layer includes forming a protruding portion of the photoresist layer, the protruding portion extending beyond the sidewall of the protective layer into the opening and spaced apart from the ohmic contact.

10. The method according to claim 9, wherein, Depositing the one or more metal layers includes using the photoresist layer as a deposition mask.

11. The method according to claim 9, wherein, Depositing the one or more metal layers includes forming a stack, the stack including a metal interface layer in contact with a heterostructure in the semiconductor body and a metal fill layer on the metal interface layer.

12. The method according to claim 9, wherein, Performing the stripping process includes performing the stripping process on portions of the one or more metal layers on the photoresist layer.

13. An intermediate structure for fabricating a high electron mobility transistor (HEMT) device, comprising: Semiconductor bodies containing heterostructures; The bottom layer on the heterogeneous structure; The photoresist layer on the underlying layer; The opening extends completely through the photoresist layer and the underlying layer and into the heterostructure, the opening including trenches in the heterostructure, and the opening extends laterally in the underlying layer than in the photoresist layer, such that the photoresist layer includes a protrusion extending beyond the underlying layer; as well as The ohmic contact formed in the trench, The protruding portion extends into the opening and is spaced apart from the ohmic contact.

14. The intermediate structure according to claim 13, wherein, The ohmic contact includes sidewalls that are aligned with the sidewalls of the protruding portion of the photoresist layer.

15. The intermediate structure according to claim 13, wherein, One or more metal layers are deposited in the trench and on the photoresist layer, the one or more metal layers comprising a stack, the stack comprising a metal interface layer in contact with the heterostructure and a metal fill layer on the metal interface layer.

16. The intermediate structure according to claim 15, wherein, The metal interface layer includes a material selected from titanium and tantalum; and the metal filler layer includes an aluminum layer.

17. The intermediate structure according to claim 13, wherein, The semiconductor body includes a substrate, a trench layer on the substrate, and a barrier layer on the trench layer, the trench extending through a portion of the barrier layer or through the thickness of the barrier layer.

18. The intermediate structure according to claim 13, wherein, The ohmic contact is spaced apart from the sidewall of the bottom layer.

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