Circuit, corresponding frequency multiplier device, system, vehicle, and method

Abstract

Embodiments of the present disclosure relate to circuits, corresponding frequency multiplier devices, systems, vehicles, and methods. A circuit includes an input port that receives an input signal having a first frequency. A phase shifter network is coupled to the input port, receives the input signal, and generates therefrom a first signal and a second signal that are orthogonal to each other. A frequency multiplier circuit system has a common node and includes a first rectifier and a second rectifier. The first rectifier rectifies the first signal to generate a first rectified signal having a second frequency that is twice the first frequency and is applied to the common node. The second rectifier rectifies the second signal to generate a second rectified signal having the second frequency and is applied to the common node. A combination of the first rectified signal and the second rectified signal is available at the common node, and the combination includes a harmonic component having a frequency that is four times the first frequency.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Italian Patent Application No. 102018000020371, filed on Dec. 20, 2018, the entire content of which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] This specification relates to the generation of high-frequency signals. One or more embodiments may relate to frequency multipliers using solid-state components, such as broadband frequency multipliers in millimeter wave, abbreviated as mmW. One or more embodiments may relate to crosswalk detection systems and / or integrated circuits, such as millimeter wave transceivers in automotive and / or consumer applications. Background Art

[0004] Frequency multipliers are commonly used to generate high-frequency signals. A frequency doubler, called a "doubler", is a common type of frequency multiplier that produces an output signal at twice the frequency of the input signal. Frequency multiplication architectures are beneficial for generating high-frequency signals and can be used in quadruple-frequency architecture designs, which provide an output signal having a frequency four times that of the input frequency, for example, for RF and millimeter wave applications. Conventionally, quadrupling can be performed by cascading frequency doubling stages, as Figure 1 shown.

[0005] As Figure 1 shown, a conventional quadruple-frequency system 100 may include:

[0006] - An input node fi, configured to receive a signal from an oscillator at a given frequency;

[0007] - A series of amplification stages 110a, 110b, 110c;

[0008] - A cascade of frequency doubling stages 120a, 120b, configured to provide a frequency-doubled signal fd;

[0009] - A high-frequency filter 130, e.g., a millimeter wave filter;

[0010] An output node fq, configured to provide a signal having the power of the input signal and having a frequency four times that of the input signal frequency.

[0011] Hereinafter, for simplicity, the same reference numerals may be used to refer to nodes and / or signals at the above nodes.

[0012] This solution can generate a large number of spurious and unwanted harmonic components, resulting in a degradation of the overall performance of the frequency doubling system 100. Additionally, several amplifiers 110a, 110b, 110c are provided to restore the power level of the signal, and a high-frequency filter 130 is provided to eliminate (or reduce) the spurious harmonics from the output of the first multiplier 120a.

[0013] Generally, extending the frequency doubling stage to work with high-frequency signals can be challenging because it may involve complex circuitry for filtering out unwanted harmonic components, e.g., signals having a frequency twice as high as the input frequency.

[0014] Thus, Figure 1 the conventional high-order frequency doubling system 100 shown in

[0015] can include a cascaded chain of multipliers 120a, 120b having intermediate "matching" stages 130 for matching the impedance of the previous stage, because unwanted reflections at these intermediate stages 130 can adversely affect the performance of multiplier 120a in driving other multipliers 120b, thereby reducing efficiency and bandwidth.

[0016] Examples of such research in the art can be:

[0017] -Y. Wang et al., "A 9% Power Efficiency 121-to-137 GHz Phase-Controlled Push-Push Frequency Quadrupler in 0.13 μm SiGe BiCMOS," presented at the IEEE International Solid-State Circuits Conference (San Francisco, CA) in 2012 (pages 262 - 264, DOI: 10.1109 / ISSCC.2012.6177008) (incorporated by reference), which discusses an enhanced frequency quadrupler core using phase-controlled push-push (PCPP) technology to directly synthesize the 4th harmonic. The article discusses a 121 - to 137 GHz frequency quadrupler based on a 0.13 μm SiGe BiCMOS process. The DC power consumption of the discussed frequency quadrupler core and the DC power consumption of the input buffer are 6.4 mW and 28.8 mW, respectively;

[0018] - U.S. Patent Application Publication No. 2017 / 0288607A1 (incorporated by reference), which discusses a quadrupler that includes the integration of a balanced frequency doubler pair with in-phase - quadrature drive, and can effectively form a "single - sided" multiplier that matches the input drive source without considering the impedance of the multiplier stage. This document discusses an architecture that uses quasi - vertical GaAs varactors fabricated on a thin silicon support membrane to implement an integrated quadrupler with an output frequency of 160 GHz. The quadrupler discussed in this document has a balanced circuit architecture and a unique quasi - vertical diode process. The balanced circuit architecture addresses degradation problems typically caused by impedance mismatches between multiplier stages, and the unique quasi - vertical diode process results in an integrated embedded chip module that integrates 18 varactors, a matching network, and beam leads for mounting a custom chip suitable for the multiplier waveguide housing, thereby achieving high reproducibility and consistency in manufacturing and performance.

[0019] As described above, the known technical solutions may have one or more of the following defects:

[0020] High architecture complexity;

[0021] For example, the adoption of high - complexity components for class - C and class - AB drive;

[0022] Sufficient, for example, a high level of supply voltage; and

[0023] The generation of spurious harmonics. SUMMARY OF THE INVENTION

[0024] An object of one or more embodiments is to contribute to providing improvements and enhancements to the above - mentioned conventional technologies.

[0025] A frequency multiplication method can be an example of such a method.

[0026] One or more embodiments can relate to corresponding circuits (e.g., integrated circuits for implementing the method according to the embodiment).

[0027] One or more embodiments can relate to corresponding circuits (e.g., radar sensors).

[0028] One or more embodiments can relate to corresponding vehicles (e.g., an automobile equipped with a circuit according to the embodiment).

[0029] The claims are an integral part of the technical teachings provided herein with reference to the embodiments.

[0030] One or more embodiments can be developed by focusing on the possible uses of millimeter - wave wavelength signals, abbreviated as mmW signals.

[0031] However, one or more embodiments can actually be applied to any possible range of operating frequencies.

[0032] One or more embodiments can be developed by looking at the possible uses of a frequency multiplier that provides a multiplication factor four times that of the input signal.

[0033] However, one or more embodiments can actually be applied to any possible multiplication factor.

[0034] One or more embodiments can use a pair of double-balanced frequency multipliers driven orthogonally, for example, splitting the same input signal into two by a 90° phase shifter.

[0035] One or more embodiments can employ a single-balanced multiplier.

[0036] One or more embodiments can advantageously:

[0037] - involve a low supply voltage;

[0038] - provide a signal with wideband characteristics, for example, due to a single-balanced multiplier;

[0039] - provide a compact architecture that is conducive to suppressing unwanted fundamental and harmonic components in the output and only providing the desired quadruple-frequency signal;

[0040] - generate a sinusoidal signal;

[0041] - avoid a cascaded multiplier that generates more spurious harmonics in the system, which in turn can use a dedicated filter to suppress these spurious harmonics.

[0042] One or more embodiments can advantageously provide a compact device.

[0043] One or more embodiments can be beneficial for improving the performance of radio frequency components, for example, for broadband applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] One or more embodiments will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0045] Figure 1 is a block diagram of a conventional quadrupling process;

[0046] Figure 2 is an example diagram of one or more embodiments of a circuit according to the present disclosure;

[0047] Figure 2A is Figure 2 an example diagram of one or more embodiments of a signal in a part of the circuit of

[0048] Figure 3 Is Figure 2 An exemplary diagram of one or more embodiments that are part of a circuit;

[0049] Figure 3A And Figure 4 Is Figure 2 And Figure 3 An exemplary diagram of signals in a circuit;

[0050] Figure 5 Is an example diagram of a method according to the present disclosure;

[0051] Figure 6 Is an exemplary diagram of a frequency configuration according to the present disclosure; and

[0052] Figure 7 Is an exemplary diagram of a vehicle according to the present disclosure. Detailed Description

[0053] The following description shows one or more specific details, aiming to provide an in - depth understanding of the example embodiments of this specification. Embodiments can be obtained in the absence of one or more specific details, or by using other methods, components, materials. In other cases, structures, materials, or operations are not shown or described in detail, so certain aspects of the embodiments will not be obscured.

[0054] In the context of this specification, referring to "an embodiment" or "one embodiment" is intended to illustrate a specific configuration, structure, or characteristic described in the relevant embodiments included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" can appear in one or more places in this specification, not necessarily referring to the same embodiment.

[0055] In addition, in one or more embodiments, specific configurations, structures, or characteristics can be combined in any appropriate manner.

[0056] The references used herein are for convenience only, and thus do not limit the scope of protection or the scope of application of the embodiments.

[0057] Throughout this specification, ordinal numbers (e.g., first, second, third, …) will be used for the purpose of facilitating the identification of components. It will also be understood that such ordinal numbers are only for the above - mentioned purpose and should not be construed in a sense that limits or indirectly limits the embodiments.

[0058] First, reference can be made to Figure 2 To describe the exemplary embodiments in detail.

[0059] For the sake of brevity, the same reference numerals may refer to ports, nodes, and signals at those ports and nodes in the following text.

[0060] It should be noted that, for simplicity, the following discussion of a circuit arrangement for providing an output signal with a multiplication factor N = 4 (an output signal having a frequency four times that of the input signal) relates to a basic exemplary embodiment in principle. Additionally, it should be understood that such figure numbers are purely exemplary and should not be construed restrictively.

[0061] In one or more embodiments, a frequency multiplier 200, as shown in Figure 2 , may include:

[0062] - An oscillator 180 configured to generate a periodic input signal S f0 ;

[0063] - An input port S f0 configured to receive an input signal S having a known frequency and phase f0 . For example, such an input signal S f0 may be a sinusoidal signal having an input frequency value f0 and an input phase value , and it can be expressed as, for example,

[0064] - A phase shifter network 210, for example, a three-port network, coupled to the input port S f0 and configured to receive the input signal S f0 , and configured to provide a set of signals at respective output ports The signals of different phases have the same frequency f0 (e.g., the input signal frequency) and phases that differ by 90° or π / 2 radians (e.g., φ1 = φ0 + π / 2);

[0065] - A set of frequency multiplier groups 220a, 220b, coupled to respective output ports of the phase shifter network 210, the set of frequency multiplier groups 220a, 220b may be configured to receive and rectify a set of signals of different phases and configured to provide a set of rectified signals

[0066] - A common node S, for example, a superposition node S, the common node S is configured to receive and combine a set of rectified signals to provide a combined signal S, the combined signal S having harmonic components S at a frequency that is the multiplication factor N times the input signal frequency f4 , for example, N = 4, for example, as a result of the combination S, for example, is the sum or superposition of rectified signals ; and

[0067] - The processing circuit 240, e.g., a capacitive DC - decoupling circuit, is coupled to the common node S and is configured to remove the DC component from the combined signal S, e.g., center its average value at 0.

[0068] It can be found that this architecture 200 is suitable for generating millimeter - wave signals, e.g., facilitating the improvement of the production margin of an oscillator (e.g., a voltage - controlled oscillator, abbreviated as VCO).

[0069] In one or more embodiments, a set of signals with different phases provided by the phase - shifter network 210 can include:

[0070] - A first signal substantially a copy of the input signal which can be expressed as: and

[0071] - A second signal having a second phase different from the first phase of This second signal can be orthogonal to the input signal S f0 , e.g., differing in phase from the input signal by 90° and / or from the first signal by which can be expressed as:

[0072] In one or more embodiments, the phase - shifter network 210 can be configured to receive the input signal S provided via a transmission line f0 , and is configured to provide signals with different phases to the multiplier stages 220a, 220b via transmission lines coupled at respective network output ports (e.g., in a three - port network 210).

[0073] For example, the phase - shifter network 210 can include passive components, e.g., an RC of resistors and capacitors, or transmission lines dedicated for high frequencies.

[0074] Figure 2A An exemplary timing diagram of a set of signals with different phases is shown where the set of signals with different phases has a period T0 = 1 / F0 and are orthogonal to each other, e.g., the second signal is orthogonal to the first signal .

[0075] In one or more embodiments, the frequency multiplier groups 220a, 220b in the circuit arrangement 200 can include:

[0076] - A first multiplier 220A, configured to receive a first signal and configured to provide a first rectified signal in a group of rectified signals as an output, and

[0077] - A second multiplier 220b, configured to receive a second signal and configured to provide a second rectified signal in a group of rectified signals as an output.

[0078] In one or more embodiments, the first multiplier 220a and the second multiplier 220b may include a similar frequency multiplier architecture 220, as discussed above with reference to Figure 3 what has been discussed.

[0079] In one or more embodiments, the frequency multiplier group 220a, 220b may include a double-balanced frequency multiplier architecture 200, for example, based on a first balanced multiplier as discussed below.

[0080] Figure 3 Is an example diagram of an embodiment of a frequency multiplier device 220, which can be applied to a group of multipliers 220a, 220b in a circuit 200.

[0081] In one or more embodiments, the frequency multiplier device 220 may be used to double the input signal frequency value f0.

[0082] In Figure 2 and Figure 3 shown in one or more embodiments, the frequency multiplier device 220 may include:

[0083] - A first input node B1, configured to receive a first waveform signal For example, the first waveform signal can be expressed as:[[]] and

[0084] - A second input node B2, configured to receive a second waveform signal non that is inverted with respect to the first waveform signal For example, the second waveform signal non can be expressed as non

[0085] - An output node L, configured to provide a rectified frequency-doubled signal as an output, and

[0086] - A ground node GND and a voltage supply node V.

[0087] In one or more embodiments, a first waveform signal and a second waveform signal may be received from corresponding parallel lines in a transmission line that couples the phase shifter network 210 to the multiplier groups 220a, 220b.

[0088] In one or more embodiments, the multiplier device 220 may include an inverter (not shown) coupled at a second input node and configured to generate a second waveform signal that is inverted with respect to the first waveform signal

[0089] In one or more embodiments, the phase shifter network 210 includes a differential network configured to provide a first signal and a second signal to corresponding first and second multipliers 220a, 220b as a pair of signal copies that are inverted with respect to each other

[0090] In one or more embodiments, the first input node B1 and the second input node B2 may be coupled to corresponding control terminals of a balanced pair of transistors Q1, Q2 in a frequency multiplier device 220 of a set of frequency multipliers 220a, 220b.

[0091] In one or more embodiments, the balanced pair of transistors Q1, Q2 may include bipolar transistors or MOSFET transistors.

[0092] For example, the balanced pair of transistors Q1, Q2 may include:

[0093] - a first transistor Q 1 , having a first input node B1 (e.g., a base terminal), coupled to the input node of the multiplier device 220, and

[0094] - a second transistor Q 2 , having a second input node B2 (e.g., a base terminal), coupled to the input node of the multiplier device 220.

[0095] In one or more embodiments, the first transistor Q 1 and the second transistor Q 2 may have a first common terminal C coupled to a voltage supply node V, e.g., a common collector, and a second common terminal that forms a current path in the respective transistors Q1, Q2, e.g., a common emitter.

[0096] In one or more embodiments, a load RFL, e.g., an impedance load, may be coupled between the second common node E and the ground terminal GND.

[0097] ​In one or more embodiments, the output node L of the multiplier device 220 may be configured to sense a rectified signal on the load RFL, e.g., between the second common control terminal E and the terminal of the load RFL.

[0098] In one or more embodiments, the multiplier device 220 may provide a rectified signal at the output node L The output node L is coupled to the common node S of the corresponding first multiplier and second multipliers 220a, 220b; when receiving a first input signal that is inverted with respect to each other and a second input signal NOT and / or the above-mentioned first input signal that is inverted with respect to each other and a second input signal NOT are respectively applied to the control terminals of the first node B1 of the first transistor Q 1 and the second node B2 of the second transistor Q 2 , the rectified signal is, for example, full-wave rectification sensed on the load RFL, as a rectification result of the two transistors Q1 and Q2.

[0099] In an exemplary transistor rectification operation, for example:

[0100] - When the first transistor Q 1 receives the positive half-wave of the first input signal , the second transistor Q 2 receives the negative half-wave of the second input signal NOT Therefore, the first transistor conducts, provides the input signal half-wave to the load, and senses it when the second transistor is cutoff.

[0101] - When the first transistor Q 1 receives the negative half-wave of the first input signal , the second transistor Q 2 receives the positive half-wave of the second input signal NOT Therefore, the second transistor conducts, provides the positive half-wave of the input signal to the load, and senses it when the first transistor is cutoff.

[0102] For example, the full-wave rectifier 220 may convert the input waveform NOT to a full-wave rectified signal at the node L coupled to the common node S in the circuit device 200 and the signal

[0103] may have a constant polarity, e.g., positive or negative.

[0104] For example, in the case where the input signals received at the control terminals Q1, Q2 of the corresponding transistors not is a full-wave rectified signal sensed at the output node L in the example case of being a sinusoidal signal having an angular frequency Ω can have contributions from multiple harmonics, as can be seen in the Fourier series X(t), which can be expressed as:

[0105]

[0106] In one or more embodiments:

[0107] - The first multiplier 220a can provide a first full-wave rectified signal For example having a phase value equal to the phase value of the first signal and

[0108] - The second multiplier 220b can provide a second full-wave rectified signal For example having a phase value twice the phase value of the second signal For example, relative to the first full-wave rectified signal shifted by 180° or π radians.

[0109] Figure 3A is an example of a timing diagram of the first full-wave rectified signal (e.g., provided by the first multiplier 220a) and the second full-wave rectified signal Sf2φ2 having a period T2 = 1 / f2 (e.g., provided by the second multiplier 220b).

[0110] In one or more embodiments, as shown in Figure 2 the common node S can receive the first full-wave rectified signal and the second full-wave rectified signal For example, this second full-wave rectified signal is shifted (e.g., delayed or advanced) by a time of half a period T2 / 2 relative to the first full-wave rectified signal (in other words, the second full-wave rectified signal is phase-shifted by 180° relative to the first full-wave rectified signal ).

[0111] In one or more embodiments, the common node S can be configured to combine the first rectified signal and the second rectified signal in a set of rectified signals of different phases e.g., by superposition.

[0112] In one or more embodiments, a common node S may be configured to generate a combined signal S that includes a rectified harmonic component, e.g., a harmonic contribution S at a frequency value f4 in a rectified sum signal f4 where the frequency value f4 is four times the input frequency value f0 of the input signal S f0 .

[0113] For example, in the example considered, in order for the combined signal to have a harmonic component at the frequency value f4 that corresponds to a wavelength λ4 in the millimeter wavelength range (e.g., λ4 = 250 microns), the input signal S provided by oscillator 180, for example f0 may thus have a first frequency value f0 and a correspondingly designed wavelength λ0, e.g., λ0 = 1 millimeter (where wavelength and frequency are related as λ = c / f in the known formula, where c is the speed of light in the optical propagation medium).

[0114] In one or more embodiments, the harmonic components in the combined signal S may be filtered 240, e.g., the DC component may be removed by a capacitive processing circuit 240

[0115] Figure 4 is the harmonic component S as a result of signal combination S f4 for one or more embodiments, an example timing diagram of the harmonic component S f4 is proportional to the main harmonic contribution having a frequency f4 that is four times the input signal frequency f0, e.g., f4 = 4*f0. For example, the combined signal S may have a period T4 = 1 / f4

[0116] Figure 5 is an example diagram of a signal processing method, including

[0117] - providing 500 an input signal S having an input frequency value f0 f0 , e.g., provided by oscillator 180, e.g., a voltage controlled oscillator (referred to as a VCO for short);

[0118] - generating 510 a set of signals with different phases composed of signals orthogonal to each other, e.g., phase shifted by 90°, e.g., provided by a phase shift network 210

[0119] - processing 520 a set of signals with different phases and generating a set of rectified signals phase shifted from each other having a second frequency value f2 that is twice the input frequency value f0; e.g., generating the rectified signals may include using multiplier devices 220a, 220b that make up a set of multiplier devices 220

[0120] - Combine a set of rectified signals at a common node S and generate a combined signal S having a harmonic signal S at a third frequency value f4 f4 , for example, four times the input frequency value f0.

[0121] In one or more embodiments, processing a set of rectified signals of different phases may include adding these signals and, optionally, filtering out the DC component from the sum signal S, for example, by circuit 240 f4 .

[0122] In one or more embodiments, generating signal Sf4 may be performed using arithmetic circuit 240, for example, filtering out the DC offset from the harmonic signal S via a capacitive element f4 .

[0123] One or more embodiments may include a "stacked" or "cascaded" set of circuit devices 200 to provide a very high multiplication factor, for example, in a customized manner (as represented by the successive points at the bottom) Figure 5 .

[0124] In one or more embodiments, frequency multiplication may include a frequency multiplier device that includes a stack or cascade 600 of frequency multipliers 200, 200', 200", as Figure 6 shown.

[0125] For example, for a cascade 600 having multiple stages:

[0126] - An oscillator 180, for example, a voltage controlled oscillator VCO, configured to generate an oscillating input signal S f0 ,

[0127] - A first frequency multiplier 200, receiving the input signal S f0 and providing a first harmonic signal S f4 having a frequency N = 4 times that of the input signal;

[0128] - A second frequency multiplier 200', coupled to the first frequency multiplier 200 and the third frequency multiplier 200", receiving the first multiplied signal S f4 and providing a second multiplied signal S f16 having a frequency N' = 4 2 times that of the input signal S f0 ;

[0129] - A third frequency multiplier 200", coupled to the second frequency multiplier 200', receiving the second frequency multiplied signal S f16 , and providing a third frequency multiplied signal S f64 as an output having a frequency N" = 43 a frequency that is a multiple of the input signal, and so on, until

[0130] the last frequency multiplier in the stack, which receives the (m - 1)-th frequency-multiplied signal and provides the m-th frequency-multiplied signal as an output, having a frequency of N” = 4 m .

[0131] Figure 7 are example diagrams of one or more embodiments of a vehicle V, such as a car, including a driver assistance system including a circuit 200 and / or a device 600; an antenna TX, for example,; a transmission antenna of a millimeter-wave transceiver.

[0132] As Figure 7 shown, the circuit 200 or the frequency device 600 can facilitate a driver or a driver assistance system in a vehicle V to detect a pedestrian P along a road, such as at a street intersection, to improve road safety.

[0133] One or more embodiments may include a circuit (such as 200) that includes:

[0134] - an input port configured to receive an input signal having an input frequency (e.g., S f0 ), the input frequency having a first frequency value (e.g., f0);

[0135] - a phase shifter network (e.g., 210) coupled to the input port, the phase shifter network being configured to receive the input signal and generate therefrom a first signal (e.g., ) and a second signal (e.g., ), the first signal and the second signal being orthogonal to each other;

[0136] - a frequency multiplier circuit (e.g., 220a, 220b; 220) having a common node (e.g., S), the frequency multiplier circuit including:

[0137] a) a first rectifier (e.g., 220a) coupled to the phase shifter network, the first rectifier being configured to rectify the first signal from the phase shifter network and apply a first rectified signal having a second frequency value (e.g., f2), which is twice the first frequency value (e.g., ) to the common node; and

[0138] b) a second rectifier (e.g., 220b) coupled to the phase shifter network, the second rectifier being configured to rectify the second signal from the phase shifter network and apply a second rectified signal having the second frequency value, which is twice the first frequency value (e.g., S f2 ) to the common node.

[0139] Wherein, a combined signal of the first rectified signal and the second rectified signal (e.g., S) is obtainable at a common node, and the combined signal includes a harmonic component (e.g., S f4 ) at a frequency value (e.g., f4) four times the above-mentioned first frequency value.

[0140] In one or more embodiments:

[0141] - The phase shifter network may be configured to generate each of the above-mentioned first signal and the above-mentioned second signal as a pair of signal copies (e.g., non ) that are in antiphase with each other;

[0142] - The first rectifier and the second rectifier in the frequency multiplier circuit may include a first transistor (e.g., Q 1 ) and a second transistor (e.g., Q 2 ) having control terminals (e.g., B1, B2), the control terminals being configured to receive the respective one of the signal copies in the above-mentioned pair of signal copies that are in antiphase with each other, and the first transistor and the second transistor having respective current paths through the first transistor and the second transistor and arranged in parallel in a current line between a voltage supply node (e.g., V) and a load (e.g., RF L ) that is referenced to ground (e.g., GND), wherein the common node is coupled between the above-mentioned load and the parallel arrangement of the first transistor and the second transistor.

[0143] In one or more embodiments, the circuit may include a voltage controlled oscillator (e.g., 180) coupled to an input port, and the voltage controlled oscillator is configured to generate the above-mentioned input signal having the first frequency value.

[0144] In one or more embodiments, the circuit may include a voltage controlled oscillator (e.g., 180) configured to generate an input signal having a frequency four times the first frequency value in the millimeter wave range.

[0145] In one or more embodiments, the circuit may include a decoupling circuit (e.g., 240) coupled to the common node and configured to remove a DC component from the combined signal.

[0146] One or more embodiments may include a frequency multiplier device (e.g., 600) including a cascading device (e.g., 200, 200’, 200”) of a plurality of circuits according to one or more embodiments, wherein an input node (e.g., S f16 ) of a circuit (e.g., 200’) in at least one of the cascading devices (e.g., 200, 200’, 200”) is coupled to a common node (e.g., S) of another circuit (e.g., 200) in the cascading device.f4 )。

[0147] One or more embodiments may include a system that includes:

[0148] - A circuit according to one or more embodiments or a frequency multiplier device according to one or more embodiments;

[0149] - A transmitting antenna (e.g., TX) coupled to a common node of the above circuit or to a common node of another circuit in a cascaded device (e.g., S f4 、S f16 、S f64 ).

[0150] In one or more embodiments, the system may include a vehicle radar sensor system.

[0151] One or more embodiments may include a vehicle (e.g., V) equipped with a vehicle radar sensor system according to one or more embodiments.

[0152] One or more embodiments may include a method that may include:

[0153] - Receiving (e.g., 500) an input signal (e.g., S f0 ) having an input frequency with a first frequency value;

[0154] - Performing (e.g., 510) a phase shift process on the input signal and generating therefrom a first signal (e.g., ) and a second signal (e.g., ), where the first signal and the second signal (e.g., ) are orthogonal to each other.

[0155] - a) Rectifying (e.g., 520) the first signal to generate therefrom a first rectified signal (e.g., ) having a second frequency value that is twice the first frequency value;

[0156] - b) Rectifying (e.g., 520) the second signal to generate therefrom a second rectified signal (e.g., ) having a second frequency value that is twice the first frequency value.

[0157] Applying (e.g., 540) the above first rectified signal and the above second rectified signal to a common node, where at the common node, a combined signal (e.g., S) of the first rectified signal and the second rectified signal can be obtained, and the combined signal (e.g., S) includes a harmonic component at a frequency value (e.g., f4) that is four times the first frequency value.

[0158] In one or more embodiments, the method may include removing a DC component from the combined signal.

[0159] It will also be understood that the various separate implementation options illustrated throughout the specification and the specification drawings are not necessarily intended to be employed in the same combinations as illustrated in the drawings. Thus, one or more embodiments may employ these (additionally non-mandatory) implementation options independently of and / or in different combinations from those illustrated in the drawings.

[0160] Without prejudice to the basic principles of the invention, details and embodiments may vary, even significantly, without departing from the scope of the invention, with reference to what has been described only by way of example. The scope of protection of the invention is defined by the appended claims.

Claims

1. A circuit, comprising: an input port configured to receive an input signal having an input frequency with a first frequency value; a phase shifter network having an input coupled to the input port to receive the input signal and generating therefrom a first signal and a second signal, the first signal and the second signal being orthogonal to each other; and a frequency multiplier circuit having a common node, the frequency multiplier circuit comprising: a) a first rectifier having an input coupled to the first output of the phase shifter network to receive and rectify the first signal and generating a first rectified signal for application to the common node, the first rectified signal having a second frequency value that is twice the first frequency value; and b) a second rectifier having an input coupled to the second output of the phase shifter network to receive and rectify the second signal and generating a second rectified signal for application to the common node, the second rectified signal having the second frequency value; wherein the common node outputs a combined signal that is a combination of the first rectified signal and the second rectified signal, the combined signal including a harmonic component at a frequency value four times the first frequency value.

2. The circuit according to claim 1, wherein: the phase shifter network is configured to produce each of the first signal and the second signal as a pair of signal copies that are in antiphase with each other; and the first rectifier and the second rectifier in the frequency multiplier circuit include a first transistor and a second transistor having control terminals configured to receive respective signal copies of the pair of signal copies, the first transistor and the second transistor having respective current paths therethrough that are arranged in parallel in a current line between a voltage supply node and a load referenced to ground, wherein the common node is coupled between the load and the parallel arrangement of the first transistor and the second transistor.

3. The circuit according to claim 1, further comprising: a voltage controlled oscillator coupled to the input port and configured to generate the input signal having the first frequency value.

4. The circuit according to claim 1, further comprising: a voltage controlled oscillator configured to generate the input signal having the first frequency value such that the frequency value four times the first frequency value is in the millimeter wave range.

5. The circuit according to claim 1, further comprising: a decoupling circuit coupled to the common node and configured to remove a DC component from the combined signal.

6. The circuit according to claim 1, further comprising: a transmitter antenna coupled to the common node.

7. An electronic device comprising a frequency multiplier means, the device comprising: a cascading means of a plurality of circuits, each of the plurality of circuits comprising: an input port configured to receive an input signal having an input frequency with a first frequency value; A phase shifter network having an input coupled to the input port to receive the input signal and generating therefrom a first signal and a second signal, the first signal and the second signal being orthogonal to each other; and A frequency doubler circuit having a common node, the frequency doubler circuit comprising: a) A first rectifier having an input coupled to the first output of the phase shifter network to receive and rectify the first signal and generate a first rectified signal for application to the common node, the first rectified signal having a second frequency value that is twice the first frequency value; and b) A second rectifier having an input coupled to the second output of the phase shifter network to receive and rectify the second signal and generate a second rectified signal for application to the common node, the second rectified signal having the second frequency value; wherein the common node outputs a combined signal that is a combination of the first rectified signal and the second rectified signal, the combined signal including a harmonic component at a frequency value four times the first frequency value.

8. The electronic device according to claim 7, wherein: The phase shifter network is configured to produce each of the first signal and the second signal as a pair of signal copies that are inverted with respect to each other; and The first rectifier and the second rectifier in the frequency doubler circuit include a first transistor and a second transistor having control terminals configured to receive respective signal copies of the pair of signal copies, the first transistor and the second transistor having respective current paths therethrough that are arranged in parallel in a current line between a voltage supply node and a load referenced to ground, wherein the common node is coupled between the load and the parallel arrangement of the first transistor and the second transistor.

9. The electronic device according to claim 7, further comprising: A voltage controlled oscillator coupled to the input port and configured to generate the input signal having the first frequency value.

10. The electronic device according to claim 7, further comprising: A voltage controlled oscillator configured to generate the input signal having a first frequency value such that the frequency value four times the first frequency value is in the millimeter wave range.

11. The electronic device according to claim 7, further comprising: A decoupling circuit coupled to the common node and configured to remove a DC component from the combined signal.

12. The electronic device according to claim 7, further comprising: A transmitter antenna coupled to another one of the plurality of circuits in the cascade arrangement.

13. The electronic device according to claim 7, wherein the device is a component in a vehicle radar sensor system.

14. The electronic device according to claim 13, further comprising: A transmitter antenna coupled to the common node.

15. The electronic device according to claim 13, wherein the device includes a vehicle equipped with the vehicle radar sensor system.

16. A method for frequency doubling, comprising: Receive an input signal having an input frequency with a first frequency value; Apply a phase shift process to the input signal to produce therefrom a first signal and a second signal, the first signal and the second signal being orthogonal to each other; Rectify the first signal to produce therefrom a first rectified signal having a second frequency value that is twice the first frequency value; Rectify the second signal to produce therefrom a second rectified signal having the second frequency value; and Apply the first rectified signal and the second rectified signal to a common node, wherein a combined signal composed of the first rectified signal and the second rectified signal is available at the common node, the combined signal including a harmonic component at a frequency value four times the first frequency value.

17. The method according to claim 16, further comprising: Removing a DC component from the combined signal.

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