Driving controller and display device including the driving controller

Abstract

A driving controller and a display device including the driving controller are provided. The driving controller includes: an image conversion circuit configured to convert an image signal into an image data signal including valid data and blanking data; a still image determination circuit configured to output a flag signal of a valid level when the image signal is a still image; an operation mode determination circuit configured to output an operation mode signal indicating a low frequency mode when the flag signal is at a valid level, and configured to output an operation mode signal indicating an image switching mode when the flag signal changes between a valid level and an invalid level; and a blanking voltage determination circuit configured to output a blanking voltage signal corresponding to a first gray scale during the low frequency mode, and to output a blanking voltage signal corresponding to a second gray scale during the image switching mode, wherein the blanking data corresponds to the blanking voltage signal.

Description

[0001] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2018-0170974, filed on December 27, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device including a driving controller having a low power consumption scheme. Background Art

[0003] The organic light emitting display device displays images using an organic light emitting diode in which electrons and electron holes are recombined to emit light. Such an organic light emitting display device is advantageous in that it has a fast response speed and is driven with low power consumption.

[0004] The organic light emitting display device may have a plurality of pixels connected to data lines and scan lines. Each of the pixels includes an organic light emitting diode and a circuit unit for controlling the amount of current flowing through the organic light emitting diode. For example, the circuit unit may control the current flowing through the organic light emitting diode from a first driving voltage to a second driving voltage according to a data signal. Then, light of desired brightness is generated based on the amount of current flowing through the organic light emitting diode.

[0005] The transistor included in the circuit unit may have a low temperature polysilicon (LTPS) semiconductor layer. The LTPS transistor may have high mobility and stability, but when the voltage level of the second driving voltage is reduced or when the operating frequency is reduced, the LTPS transistor may generate leakage current. When leakage current is generated in the circuit unit, the amount of current flowing through the organic light emitting diode changes. This may reduce the display quality.

[0006] To reduce leakage current in the circuit unit of the pixel, the transistor may include an oxide semiconductor as a semiconductor layer. In some cases, the circuit unit of the pixel may include both an LTPS semiconductor transistor and an oxide semiconductor transistor. Summary of the invention

[0007] The present disclosure provides a driving controller capable of reducing power consumption and improving display quality, and a display device including the driving controller.

[0008] The present disclosure relates to a driving method of a display device capable of reducing power consumption and improving display quality.

[0009] An embodiment of the inventive concept provides a driving controller, which includes: an image conversion circuit, configured to convert an externally received image signal into an image data signal including valid data and blanking data; a still image determination circuit, configured to output a flag signal of a valid level when the image signal is a still image; an operation mode determination circuit, configured to output an operation mode signal indicating a low-frequency mode when the flag signal is a valid level, and configured to output an operation mode signal indicating an image switching mode when the flag signal changes between a valid level and an invalid level; and a blanking voltage determination circuit, configured to receive the operation mode signal, output a blanking voltage signal corresponding to a first grayscale during the low-frequency mode, and output a blanking voltage signal corresponding to a second grayscale during the image switching mode, the second grayscale being different from the first grayscale, wherein the blanking data corresponds to the blanking voltage signal.

[0010] In an embodiment, the image conversion circuit may output the image data signal at a driving frequency corresponding to the operation mode signal.

[0011] In an embodiment, the driving frequency in the image switching mode may be higher than the driving frequency in the low frequency mode.

[0012] In an embodiment, after the flag signal changes from a valid level to an invalid level, the operation mode determination circuit may output an operation mode signal indicating an image switching mode for a specified time, and when the flag signal is at a valid level after the specified time, the operation mode determination circuit may output an operation mode signal indicating a low frequency mode.

[0013] In an embodiment, the first grayscale may be a black grayscale, and the second grayscale may be a white grayscale.

[0014] In an embodiment, the driving controller may further include: a control signal output circuit configured to output a first start control signal and a second start control signal in response to an externally received control signal and an operation mode signal.

[0015] In an embodiment, during the low frequency mode, the frequency of the first start control signal and the frequency of the second start control signal may be different from each other, and during the image switching mode, the frequency of the first start control signal and the frequency of the second start control signal may be the same.

[0016] In an embodiment of the inventive concept, a display device includes: a display panel including a plurality of pixels connected to a plurality of data lines and a plurality of scan lines, respectively; a drive controller configured to receive an image signal and output an image data signal, a data control signal, and a scan control signal; a data drive circuit configured to drive the plurality of data lines in response to the image data signal and the data control signal; and a scan drive circuit configured to drive the plurality of scan lines in response to the scan control signal, wherein the drive controller includes: an image conversion circuit configured to convert an image signal received externally into an image data signal including valid data and blanking data; a still image determination circuit A circuit configured to output a flag signal of a valid level when the image signal is a still image; an operation mode determination circuit configured to output an operation mode signal indicating a low-frequency mode when the flag signal is a valid level, and configured to output an operation mode signal indicating an image switching mode when the flag signal changes between a valid level and an invalid level; and a blanking voltage determination circuit configured to receive the operation mode signal, output a blanking voltage signal corresponding to a first gray scale during the low-frequency mode, and output a blanking voltage signal corresponding to a second gray scale during the image switching mode, the second gray scale being different from the first gray scale, wherein the blanking data corresponds to the blanking voltage signal.

[0017] In an embodiment, the image conversion circuit may output the image data signal at a driving frequency corresponding to the operation mode signal.

[0018] In an embodiment, the driving frequency in the image switching mode may be higher than the driving frequency in the low frequency mode.

[0019] In an embodiment, after the flag signal changes from a valid level to an invalid level, the operation mode determination circuit may output an operation mode signal indicating an image switching mode for a specified time, and when the flag signal is at a valid level after the specified time, the operation mode determination circuit may output an operation mode signal indicating a low frequency mode.

[0020] In an embodiment, the first grayscale may be a black grayscale, and the second grayscale may be a white grayscale.

[0021] In an embodiment, at least one pixel among the plurality of pixels may include: a light emitting diode including an anode and a cathode; a first transistor including a first electrode configured to receive a first driving voltage, a second electrode electrically connected to the anode of the light emitting diode, and a gate electrode; a second transistor including a first electrode connected to a corresponding data line among a plurality of data lines, a second electrode connected to the first electrode of the first transistor, and a gate electrode configured to receive a first scanning signal; and a third transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the gate electrode of the first transistor, and a gate electrode configured to receive a second scanning signal.

[0022] In an embodiment, each of the first transistor and the second transistor may be a P-type transistor, and the third transistor may be an N-type transistor.

[0023] In an embodiment, the display device may further include: a control signal output circuit configured to output a first start control signal and a second start control signal in response to an externally received control signal and an operation mode signal, wherein the scan control signal includes a first start control signal and a second start control signal, the scan drive circuit outputs a first scan signal for driving the first transistor and the second transistor synchronously with the first start control signal, and the scan drive circuit outputs a second scan signal for driving the third transistor synchronously with the second start control signal.

[0024] In an embodiment, during the low frequency mode, the frequency of the first start control signal and the frequency of the second start control signal may be different from each other, and during the image switching mode, the frequency of the first start control signal and the frequency of the second start control signal may be the same.

[0025] In an embodiment, each of the first transistor and the second transistor may be a low temperature polysilicon (LTPS) semiconductor transistor, and the third transistor may be an oxide semiconductor transistor.

[0026] In an embodiment of the inventive concept, a driving method for a display device includes: determining whether an image signal is a still image; when the image signal is a still image, outputting a flag signal of a valid level; when the flag signal is a valid level, outputting an operating mode signal indicating a low-frequency mode; when the flag signal changes from a valid level to an invalid level, outputting an operating mode signal indicating an image switching mode; outputting a blanking voltage signal corresponding to the operating mode signal; and converting an externally received image signal into an image data signal including valid data and blanking data in response to the operating mode signal and the blanking voltage signal, wherein the blanking voltage signal corresponds to a first grayscale during the low-frequency mode, the blanking voltage signal corresponds to a second grayscale during the image switching mode, the second grayscale is different from the first grayscale, and the blanking data corresponds to the blanking voltage signal.

[0027] In an embodiment, in the step of outputting an operation mode signal, after the flag signal changes from a valid level to an invalid level, an operation mode signal indicating an image switching mode can be output for a specified time, and when the flag signal is at a valid level after the specified time, an operation mode signal indicating a low-frequency mode can be output.

[0028] In an embodiment, the driving frequency of the image switching mode may be higher than the driving frequency of the low frequency mode, the first grayscale may be a black grayscale, and the second grayscale may be a white grayscale. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0030] Figure 1 is a block diagram of an organic light emitting display device according to an embodiment of the inventive concept;

[0031] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept;

[0032] Figure 3 It is used to explain Figure 2 A timing diagram of the operation of a pixel of an organic light emitting display device;

[0033] Figure 4 shows a hysteresis characteristic of a transistor in a pixel of a display device according to an embodiment of the inventive concept;

[0034] Figure 5 is a block diagram of a driving controller according to an exemplary embodiment of the inventive concept;

[0035] Fig. 6A shows the operation of the display device in normal frequency mode;

[0036] Figure 6B shows the operation of the display device in a low frequency mode;

[0037] Figure 7 shows a scanning signal corresponding to a driving frequency determined by an operation mode determination circuit according to an embodiment of the inventive concept;

[0038] Figure 8 is a timing diagram for explaining an image switching mode of a display device;

[0039] Fig. 9 is a timing diagram showing an example of a scan signal supplied to a second type scan line and a data signal supplied to a data line;

[0040] Fig. 10A shows a data signal and a second start control signal provided to the data line;

[0041] Fig. 10B Shows when Fig. 10A A light quantity measurement result of the display panel when the data signal shown in is provided to the display panel;

[0042] Fig.11A shows a data signal and a second start control signal provided to a data line according to an embodiment of the inventive concept; and

[0043] Fig. 11B Shows when Fig.11A Result of measuring the amount of light of the display panel when the data signal shown in FIG. 1 is supplied to the display panel. DETAILED DESCRIPTION

[0044] Embodiments of the present disclosure relate to a display device having a drive controller, which is configured to reduce power consumption by implementing a low-frequency mode when a display panel shows a still image. In some cases, a switching mode is used during a switch between operating in a normal frequency mode and operating in a low-frequency mode. Compared to the low-frequency mode, the switching mode can be associated with a higher frequency and a different grayscale for blanking data. Using the switching mode can reduce the occurrence of image artifacts (such as afterimages) or the occurrence of image flicker that can occur during switching between modes.

[0045] The same reference numerals in the drawings represent the same elements. In addition, in the drawings, the thickness, proportion and size of the elements may be exaggerated in order to effectively describe the technical content. The term "and / or" includes any combination and all combinations of one or more of the associated items.

[0046] Various components can be described using terms such as first, second, etc., but these components should not be limited by the terms. Terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, or similarly, a second component can be referred to as a first component. Unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "said / the" are also intended to include plural forms.

[0047] Additionally, terms such as "below," "lower," "above," and "over" are used to explain the relationship of items shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. In addition, it will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0049] It will also be understood that when the terms “comprise” and / or “include” are used in this specification, it indicates the presence of stated features, integers, steps, operations, elements, components or combinations thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.

[0050] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0051] Figure 1 is a block diagram of an organic light emitting display device according to an embodiment of the inventive concept.

[0052] Reference Figure 1 The organic light emitting display device 10 includes a display panel 100 , a driving controller 200 , a scan driving circuit 300 , a data driving circuit 400 , and a clock and voltage generating circuit 500 .

[0053] According to an embodiment of the present disclosure, when the drive controller 200 receives a still image, the drive controller 200 can reduce power consumption by operating in a low frequency mode, and when image switching is detected in the low frequency mode, the drive controller 200 can prevent afterimages by operating in an image switching mode (at a higher driving frequency). During a blanking period in the image switching mode, the voltage level of the data signal can be changed to a white gray voltage level to minimize flicker.

[0054] The driving controller 200 receives the image signal RGB and the control signal CTRL, and converts the data format of the image signal RGB to match the interface specification for the data driving circuit 400, thereby generating the image data signal DATA. The driving controller 200 outputs a scan control signal, a data control signal DCS, and a gate pulse signal CPV. The scan control signal may include a first start control signal FLMp and a second start control signal FLMn. Figure 1 In the embodiment, the scan control signal includes only the first start control signal FLMp and the second start control signal FLMn, but the scan control signal may also include other signals.

[0055] The clock and voltage generation circuit 500 receives the gate pulse signal CPV from the driving controller 200, and generates a voltage signal and a clock signal for the operation of the organic light emitting display device 10. In an embodiment, the clock and voltage generation circuit 500 generates a first driving voltage ELVDD, a second driving voltage ELVSS, an initialization voltage Vint, a first gate clock signal CKVP, and a second gate clock signal CKVN, but the embodiment is not limited thereto. For example, the clock and voltage generation circuit 500 may generate a plurality of first gate clock signals and second gate clock signals having different phases from each other.

[0056] The scan driving circuit 300 receives a first start control signal FLMp and a second start control signal FLMn from the driving controller 200, and receives a first gate clock signal CKVP and a second gate clock signal CKVN from the clock and voltage generating circuit 500. The scan driving circuit 300 generates a plurality of scan signals, and sequentially outputs the plurality of scan signals to the first type scan lines SPL1 to SPLn and the second type scan lines SNL1 to SNLn (to be described in more detail later). In addition, the scan driving circuit 300 generates a plurality of emission control signals in response to the first start control signal FLMp and the second start control signal FLMn, and outputs the plurality of emission control signals to the plurality of control lines EL1 to ELn.

[0057] In an exemplary embodiment of the inventive concept, the scan driving circuit 300 can output a scan signal to be provided to the first type scan lines SPL1 to SPLn in response to the first start control signal FLMp and the first gate clock signal CKVP, and output a scan signal to be provided to the second type scan lines SNL1 to SNLn in response to the second start control signal FLMn and the second gate clock signal CKVN.

[0058] exist Figure 1 In the embodiment, a plurality of scan signals and a plurality of emission control signals are output from one scan driving circuit 300, but the embodiments of the inventive concept are not limited thereto. In another embodiment of the inventive concept, a plurality of scan driving circuits may divide and output a plurality of scan signals, and may divide and output a plurality of emission control signals. In addition, in another embodiment of the inventive concept, a driving circuit configured to generate and output a plurality of scan signals and a driving circuit configured to generate and output a plurality of emission control signals may be separated.

[0059] The data driving circuit 400 receives the data control signal DCS and the image data signal DATA from the driving controller 200. The data driving circuit 400 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0060] The display panel 100 includes first-type scan lines SPL1 to SPLn, second-type scan lines SNL1 to SNLn, control lines EL1 to ELn, data lines DL1 to DLm, and a plurality of pixels PX. The first-type scan lines SPL1 to SPLn and the second-type scan lines SNL1 to SNLn extend in a first direction DR1 and are arranged separately in a second direction DR2. The data lines DL1 to DLm extend in the second direction DR2 and are arranged separately in the first direction DR1.

[0061] Each of the plurality of control lines EL1 to ELn may be arranged in parallel with a corresponding scan line among the second type scan lines SNL1 to SNLn.

[0062] Each of the plurality of pixels PX is connected to a corresponding first type scan line among the first type scan lines SPL1 to SPLn, a corresponding second type scan line among the second type scan lines SNL1 to SNLn, a corresponding control line among the control lines EL1 to ELn, and a corresponding data line among the data lines DL1 to DLm.

[0063] Each of the plurality of pixels PX receives a first driving voltage ELVDD and a second driving voltage ELVSS having a level lower than that of the first driving voltage ELVDD. Each of the plurality of pixels PX is connected to a first driving voltage line VL1 to which the first driving voltage ELVDD is applied. Each of the pixels PX is connected to an initialization voltage line RL configured to receive an initialization voltage Vint.

[0064] Each of the plurality of pixels PX may be electrically connected to four scan lines. Figure 1 As shown in , the pixels PX in the second pixel row may be connected to the scan lines SNL1 , SPL2 , SNL3 , and SPL3 .

[0065] Each of the plurality of pixels PX includes an organic light emitting diode (not shown) and a pixel circuit unit (not shown) configured to control emission of the organic light emitting diode. The pixel circuit unit may include a capacitor and a plurality of transistors. At least any one of the scan driving circuit 300 and the data driving circuit 400 may include a transistor provided by the same process as that of the pixel circuit unit.

[0066] The first type scan lines SPL1 to SPLn, the second type scan lines SNL1 to SNLn, the control lines EL1 to ELn, the data lines DL1 to DLm, the first driving voltage line VL1, the initialization voltage line RL, the pixel PX, the scan driving circuit 300, and the data driving circuit 400 may be arranged on the base substrate (not shown) by multiple photolithography processes. A plurality of insulating layers may be arranged on the base substrate (not shown) by multiple deposition processes or coating processes. Each of the plurality of insulating layers may be a thin film configured to completely cover the display panel 100, or may include at least one insulating pattern stacked only on a specific component of the display panel 100. The plurality of insulating layers may include an organic layer and / or an inorganic layer. In addition, an encapsulation layer (not shown) configured to protect the pixel PX may also be arranged on the base substrate.

[0067] The display panel 100 receives a first driving voltage ELVDD and a second driving voltage ELVSS. The first driving voltage ELVDD may be provided to a plurality of pixels PX through a first driving voltage line VL1. The second driving voltage ELVSS may be provided to a plurality of pixels PX through an electrode (not shown) or a power line (not shown) provided in the display panel 100.

[0068] The display panel 100 receives an initialization voltage Vint. The initialization voltage Vint may be provided to a plurality of pixels PX through an initialization voltage line RL.

[0069] The display panel 100 is divided into a display area DPA and a non-display area NDA. A plurality of pixels PX are arranged in the display area DPA. In the present embodiment, the scan driving circuit 300 is arranged in the non-display area NDA which is one side of the display area DPA.

[0070] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept. Figure 3 It is used to explain Figure 2 A timing diagram of the operation of a pixel of an organic light emitting display device.

[0071] Figure 2 shows an equivalent circuit diagram of a pixel PXij, where the pixel PXij is connected to Figure 1 The figure shows the i-th data line DLi among the multiple data lines DL1 to DLm, the j-th first type scan line SPLj and the (j+1)-th first type scan line SPLj+1 among the multiple first type scan lines SPL1 to SPLn, the j-th second type scan line SNLj and the (j-1)-th second type scan line SNLj-1 among the multiple second type scan lines SNL1 to SNLn, and the j-th control line ELj among the multiple control lines EL1 to ELn. Figure 1 Each of the plurality of pixels PX shown in FIG. Figure 2 The circuit configuration of the equivalent circuit diagram of the pixel PXij shown in FIG. 1 is the same as the circuit configuration of the equivalent circuit diagram of the pixel PXij shown in FIG. 1 . In the present embodiment, the circuit unit of the pixel PXij includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. In addition, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 is a P-type transistor having an LTPS semiconductor layer, and each of the third transistor T3 and the fourth transistor T4 is an N-type transistor having an oxide semiconductor as a semiconductor layer. However, the embodiments of the inventive concept are not limited thereto, and at least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor, and the rest may be P-type transistors. In addition, the circuit configuration of the pixel according to the embodiments of the inventive concept is not limited to Figure 2 . Figure 2The pixel circuit unit shown in FIG. 1 is merely an example, and the configuration of the pixel circuit unit may be modified for practice.

[0072] Reference Figure 2 , a pixel PXij of the display device according to the embodiment includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor Cst and at least one light emitting diode ED. In this embodiment, an example in which one pixel PXij includes one light emitting diode ED will be described.

[0073] For ease of explanation, the jth first type scan line SPLj, the jth second type scan line SNLj, the (j-1)th second type scan line SNLj-1 and the (j+1)th first type scan line SPLj+1 are respectively referred to as the first scan line SPLj, the second scan line SNLj, the third scan line SNLj-1 and the fourth scan line SPLj+1.

[0074] The first scan line SPLj, the second scan line SNLj, the third scan line SNLj-1, and the fourth scan line SPLj+1 may transmit scan signals SPj, SNj, SNj-1, and SPj+1, respectively. The first scan signals SPj and SPj+1 may turn on or off the second transistor T2 and the seventh transistor T7, which are P-type transistors. The second scan signals SNj and SNj-1 may turn on or off the third transistor T3 and the fourth transistor T4 (i.e., N-type transistors).

[0075] The control line ELj may transmit an emission control signal EMj capable of controlling the emission of the light emitting diode ED included in the pixel PXij. The emission control signal EMj transmitted through the control line ELj may have a waveform different from the waveforms of the scan signals SPj, SNj, SNj-1, and SPj+1 transmitted through the first scan line SPLj, the second scan line SNLj, the third scan line SNLj-1, and the fourth scan line SPLj+1, respectively. The data line DLi may transmit a data signal Di, and the first drive voltage line VL1 may transmit a first drive voltage ELVDD. The data signal Di may have different voltage levels according to an image signal to be input to the display device, and the first drive voltage ELVDD may have a substantially constant level.

[0076] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 receives a data signal Di transmitted through the data line DLi according to a switching operation of the second transistor T2, and provides a driving current Id to the light emitting diode ED. The first transistor T1 may be referred to as a driving transistor.

[0077] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the first scan line SPLj. The second transistor T2 may be turned on according to a scan signal SPj received through the first scan line SPLj, and may transmit a data signal Di received from the data line DLi to a source electrode of the first transistor T1 (i.e., the first electrode of the first transistor T1).

[0078] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the second scan line SNLj. The third transistor T3 may be turned on according to a scan signal SNj received through the second scan line SNLj, and may connect the gate electrode and the second electrode of the first transistor T1 to each other to make the first transistor T1 diode-connected.

[0079] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the initialization voltage line RL through which the initialization voltage Vint is transmitted, and a gate electrode connected to the third scan line SNLj-1. The fourth transistor T4 may be turned on according to the scan signal SNj-1 received through the third scan line SNLj-1, and transmit the initialization voltage Vint to the gate electrode of the first transistor T1 to perform an initialization operation for initializing the voltage of the gate electrode of the first transistor T1.

[0080] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the j-th control line ELj.

[0081] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting diode ED, and a gate electrode connected to the j-th control line ELj.

[0082] The fifth transistor T5 and the sixth transistor T6 are substantially simultaneously turned on according to the emission control signal EMj received through the jth control line ELj, and through this process, the first driving voltage ELVDD may be compensated through the diode-connected first transistor T1 to be transmitted to the light emitting diode ED.

[0083] The seventh transistor T7 includes a first electrode connected to the second electrode of the fourth transistor T4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the fourth scan line SPLj+1.

[0084] As described above, one end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the light emitting diode ED may be connected to a terminal through which the second driving voltage ELVSS is transmitted. The structure of the pixel PXij according to the embodiment is not limited to Figure 2 The structure shown in FIG. 1 is a structure shown in FIG. 1 ; the number of transistors and the number of capacitors included in one pixel and the connection relationship of the transistors and the capacitors are modifiable in various ways.

[0085] Reference Figure 3 As well as the above Figure 2 , the operation of the display device according to the embodiment will be described.

[0086] Reference Figure 2 and Figure 3 During the initialization period in one frame, a high-level scan signal SNj-1 is supplied through the third scan line SNLj-1. In response to the high-level scan signal SNj-1, the fourth transistor T4 is turned on, and the initialization voltage Vint is transmitted to the gate electrode of the first transistor T1 through the fourth transistor T4, so that the first transistor T1 is initialized.

[0087] Then, when the first scan signal SPj of a low level is supplied through the first scan line SPLj during the data programming and compensation period, the second transistor T2 is turned on, and substantially simultaneously, when the second scan signal SNj of a high level is supplied through the second scan line SNLj, the third transistor T3 is turned on. Here, the first transistor T1 is diode-connected and forward-biased through the turned-on third transistor T3. Then, a compensation voltage Di-Vth obtained by subtracting a threshold voltage Vth of the first transistor T1 from a data signal Di supplied from the data line DLi is applied to the gate electrode of the first transistor T1. In other words, the gate voltage applied to the gate electrode of the first transistor T1 may be the compensation voltage Di-Vth.

[0088] The first driving voltage ELVDD and the compensation voltage Di-Vth may be applied to both ends of the capacitor Cst, and charges corresponding to a voltage difference between the both ends may be stored in the capacitor Cst.

[0089] During the bypass period, the seventh transistor T7 receives the scan signal SPj+1 of a low level through the fourth scan line SPLj+1 to be turned on. A portion of the driving current Id may be a bypass current Ibp to be flowed out through the seventh transistor T7.

[0090] Even when the minimum current of the first transistor T1 for displaying a black image flows as a driving current, a black image is not properly displayed when the light emitting diode ED emits light. Therefore, the seventh transistor T7 of the organic light emitting display device according to an embodiment of the inventive concept can disperse a portion of the minimum current of the first transistor T1 as a bypass current Ibp to other current paths except the current path of the light emitting diode ED. The minimum current of the first transistor T1 represents the current under the condition that the gate-source voltage Vgs of the first transistor T1 is less than the threshold voltage Vth to turn off the first transistor T1. Under the condition that the first transistor T1 is turned off, the minimum driving current (for example, a current of 10pA or less) is transmitted to the light emitting diode ED, and a black brightness image is displayed.

[0091] When the minimum driving current for displaying a black image flows, the influence of the bypass current Ibp is large. However, when a large driving current for displaying an image such as a typical image or a white image flows, the influence from the bypass current Ibp is small. Therefore, when the driving current for displaying a black image flows, the emission current Ied of the light emitting diode ED, which is the amount of current of the bypass current Ibp flowing out through the seventh transistor T7 from the driving current Id, has the minimum amount of current through which a black image can be reliably displayed. Therefore, the contrast can be improved by using the seventh transistor T7 to realize an accurate black brightness image. In the present embodiment, the bypass signal is the scanning signal SPj+1, but is not limited thereto.

[0092] Then, during the emission period, the emission control signal EMj supplied from the j-th control line ELj changes from a high level to a low level. During the emission period, the fifth transistor T5 and the sixth transistor T6 are turned on by the emission control signal EMj. Then, the driving current Id is generated according to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD, the driving current Id is supplied to the light emitting diode ED through the sixth transistor T6 and the emission current Ied flows to the light emitting diode ED. During the emission period, the gate-source voltage Vgs of the first transistor T1 is maintained as "ELVDD-(Di-Vth)" by the capacitor Cst. According to the current-voltage relationship of the first transistor T1, the driving current Id can be connected to "(ELVDD-Di) 2 "Proportional," (ELVDD-Di) 2" is the square of a value obtained by subtracting the threshold voltage Vth (Vgs-Vth=ELVDD-(Di-Vth)-Vth) from the gate-source voltage Vgs of the first transistor T1. Therefore, the driving current Id can be determined regardless of the threshold voltage Vth of the first transistor T1.

[0093] Figure 4 The hysteresis characteristics of a transistor in a pixel of a display device according to an embodiment of the inventive concept are shown.

[0094] Reference Figure 4 ,when Figure 2 When the light emitting diode ED in the pixel PXij shown in the figure continuously emits light, the first transistor T1 of the pixel PXij may have a first voltage-current characteristic 120. When the pixel PXij discontinuously emits light, the first transistor T1 may have a second voltage-current characteristic 110. That is, the voltage-current characteristic of the pixel may depend on the voltage applied to the pixel in the previous frame. This may result in an afterimage effect in which the brightness of the pixel is affected by the previous image. Embodiments of the present disclosure describe systems and methods for reducing the afterimage effect.

[0095] The voltage-current characteristic of the pixel PXij varies according to the data signal Di transmitted through the data line DLi. Figure 1 ), a shadow effect may occur when the brightness of a first pixel including a first transistor T1 having a first voltage-current characteristic 120 among a plurality of pixels PX in a display device 10 is different from the brightness of a second pixel including a first transistor T1 having a second voltage-current characteristic 110. In addition, when a first region including a plurality of first pixels having the first voltage-current characteristic 120 is adjacent to a second region including a plurality of second pixels having the second voltage-current characteristic 110, and all of the plurality of first pixels and the plurality of second pixels are changed to an emission state, an afterimage may be generated at the moment when a boundary between the first region and the second region is visually recognized.

[0096] When the brightness of the pixel PXij changes from a high grayscale (e.g., a white grayscale) to an intermediate grayscale, the absolute value |Vg| of the gate voltage Vg of the first transistor T1 changes from a large value to a small value. Because the gate voltage Vg having a relatively high absolute value at a high grayscale is first input to the gate electrode of the driving transistor T1, when the gate voltage Vg corresponding to the intermediate grayscale is applied to the gate electrode of the driving transistor T1 while the absolute value |Vth| of the threshold voltage Vth of the driving transistor T1 increases, the driving current Id of the driving transistor T1 may be equal to the current at point "A".

[0097] When the brightness of the pixel PXij changes from a low grayscale (e.g., a black grayscale) to an intermediate grayscale, the absolute value |Vg| of the gate voltage Vg of the first transistor T1 changes from a small value to a large value. Here, because the gate voltage Vg having a relatively small absolute value at a low grayscale is first input to the gate electrode of the first transistor T1, when the gate voltage Vg corresponding to the intermediate grayscale is applied to the gate electrode of the first transistor T1 in a state where the absolute value |Vth| of the threshold voltage Vth of the first transistor T1 is reduced by ΔVth, the driving current Id of the first transistor T1 may be equal to the current at point "B".

[0098] Due to the hysteresis characteristic of the first transistor T1, even when the same gate voltage Vg is applied to the gate electrode of the first transistor T1 in order to express the brightness of the intermediate gray scale, different currents flow to the light emitting diode ED according to the gray scale in the previous frame. In other words, when the same gate voltage Vg is applied to the two gate electrodes of the two pixels in order to display the brightness of the intermediate gray scale, a current difference ΔI occurs between the pixel to which the gate voltage Vg of the low gray scale is applied in the previous frame and the pixel to which the gate voltage Vg of the high gray scale is applied in the previous frame. The current difference ΔI causes an afterimage to appear on the display.

[0099] Figure 5 is a block diagram of a driving controller according to an exemplary embodiment of the inventive concept.

[0100] Reference Figure 5 , the driving controller 200 includes an image conversion circuit 210 , a still image determination circuit 220 , a blanking voltage determination circuit 230 , an operation mode determination circuit 240 , and a control signal output circuit 250 .

[0101] The image conversion circuit 210 receives the image signal RGB, and the output is corrected to be suitable for ( Figure 1 The image data signal DATA of the display panel 100 shown in FIG. 1 may be configured to convert the image data signal DATA into an image data signal DATA having characteristics of the display panel 100. For example, the image conversion circuit 210 may perform adaptive color correction (ACC) or dynamic capacitance compensation (DCC) of the image signal RGB.

[0102] The externally provided image signal RGB may include a red image signal, a green image signal, and a blue image signal. In an exemplary embodiment of the inventive concept, when set in ( Figure 1 When the pixel PX in the display panel 100 (shown in FIG. 1 ) includes red pixels, green pixels, blue pixels and white pixels, the image conversion circuit 210 can convert the image signal RGB into the following image data signal DATA: an image data signal DATA including a red data signal, a green data signal, a blue data signal and a white data signal corresponding to the red pixels, green pixels, blue pixels and white pixels respectively set in the display panel 100.

[0103] In another embodiment, when set in ( Figure 1 When the pixel PX in the display panel 100 (shown in FIG. 1 ) includes a red pixel, a first green pixel, a blue pixel and a second green pixel, the image conversion circuit 210 can convert the image signal RGB into the following image data signal DATA: an image data signal DATA including a red data signal, a first green data signal, a blue data signal and a second green data signal corresponding to the red pixel, the first green pixel, the blue pixel and the second green pixel respectively set in the display panel 100.

[0104] The still image determination circuit 220 can determine whether the image signal RGB of a frame corresponds to a still image or a moving image. For example, when the image signal RGB of the previous frame is the same or substantially similar to the image signal RGB of the current frame, the still image determination circuit 220 can determine that the image signal RGB of the current frame is a still image.

[0105] In an exemplary embodiment of the inventive concept, the still image determination circuit 220 can use a linear feedback shift register (LFSR) to extract a representative value of the image signal RGB of a frame, and can compare the representative value of the previous frame with the representative value of the current frame to determine whether the image signal RGB of the current frame is a still image. In some embodiments, using the LFSR to identify a still image does not require a memory, so the manufacturing cost of the still image determination circuit 220 can be reduced.

[0106] When the image signal RGB of the current frame is determined to be a still image (for example, when the image signal RGB of the previous frame is the same as the image signal RGB of the current frame), the still image determination circuit 220 outputs a still image flag signal S_F indicating a valid level (for example, a high level). When the image signal RGB of the current frame is not determined to be a still image (for example, when the image signal RGB of the previous frame is not the same as the image signal RGB of the current frame), the still image determination circuit 220 outputs a still image flag signal S_F indicating an invalid level (for example, a low level).

[0107] By determining whether the image signal RGB is a still image, the still image determination circuit 220 enables the drive controller 200 to control the display panel 100 in a manner that reduces power usage and improves display quality. For example, the drive controller 200 can adjust the operating frequency and grayscale value for blanking data.

[0108] The operation mode determination circuit 240 outputs an (operation) mode signal MD in response to the still image flag signal S_F. The mode signal MD may indicate a normal frequency mode NFM, a low frequency mode LFM, or an image switching mode TM. The mode signal MD may include a plurality of bits representing a plurality of operation modes.

[0109] When the still image flag signal S_F indicates an invalid level (e.g., a low level) (in other words, the image signal RGB is not a still image), the operation mode determination circuit 240 outputs a mode signal MD indicating a normal frequency mode NFM. The mode signal MD is provided to the image conversion circuit 210, the blanking voltage determination circuit 230, and the control signal output circuit 250.

[0110] When the still image flag signal S_F indicates a valid level (e.g., a high level) (in other words, the image signal RGB is a still image), the operation mode determination circuit 240 outputs a mode signal MD indicating a low frequency mode LFM. The driving frequency (e.g., a first frequency) in the normal frequency mode NFM is not lower than the driving frequency (e.g., a second frequency) in the low frequency mode LFM. By using a low frequency when a still image is detected, power consumption can be reduced without negatively affecting the user viewing experience of the display panel 100.

[0111] When the still image flag signal S_F changes from the effective level to the ineffective level, the operation mode determination circuit 240 outputs a mode signal MD indicating the image switching mode TM. The driving frequency of the image switching mode TM may be higher than the driving frequency of the low frequency mode LFM. For example, the driving frequency of the image switching mode TM may be the same as the driving frequency (i.e., the first frequency) of the normal frequency mode NFM. As an example, the first frequency may be 60 Hz, 120 Hz, or 240 Hz, and the second frequency may be 1 Hz, 15 Hz, or 30 Hz.

[0112] After the still image flag signal S_F changes from the active level to the inactive level, the operation mode determination circuit 240 outputs the mode signal MD indicating the image switching mode TM for a prescribed time (e.g., 30 frames), and when the still image flag signal S_F indicates the active level after the prescribed time has passed, the operation mode determination circuit 240 outputs the mode signal MD indicating the low frequency mode LFM. Using the image switching mode TM during switching from the normal frequency mode NFM to the low frequency mode LFM can enable the drive controller 200 to reduce the possibility of afterimages.

[0113] The blanking voltage determination circuit 230 outputs a blanking voltage signal BV in response to the mode signal MD. When the mode signal MD indicates the low frequency mode LFM (in other words, the image signal RGB is a still image), the blanking voltage determination circuit 230 provides the blanking voltage signal BV corresponding to the first grayscale to the image conversion circuit 210. For example, the first grayscale may be a black grayscale.

[0114] When the mode signal MD indicates the image switching mode TM, the blanking voltage determination circuit 230 outputs a blanking voltage signal BV corresponding to the second grayscale. For example, the second grayscale may be a white grayscale. When the mode signal MD changes from the image switching mode TM to the low frequency mode LFM, the blanking voltage determination circuit 230 again outputs a blanking voltage signal BV corresponding to the first grayscale. In the following, it is assumed that the first grayscale is a black grayscale and the second grayscale is a white grayscale, but the inventive concept is not limited thereto.

[0115] The control signal output circuit 250 outputs a data control signal DCS, a first start control signal FLMp, a second start control signal FLMn, and a gate pulse signal CPV in response to an externally provided control signal CTRL and a mode signal MD from the operation mode determination circuit 240 .

[0116] By determining the characteristics of the input RGB data, embodiments of the inventive concept can allow lower power usage by switching display modes. The image conversion circuit 210 and the control signal output circuit 250 can drive the display panel 100 in these different modes by outputting signals that determine the refresh rate of the display and the type of blanking voltage to be applied when appropriate. In addition, in the case where the mode signal MD indicates the image switching mode TM, the display can automatically revert to the low frequency mode LFM after a predetermined amount of time allocated to change the image, which can further reduce power usage.

[0117] Fig. 6A The operation of the display device in normal frequency mode is shown. Figure 6B The operation of the display device in the low frequency mode is shown.

[0118] In normal frequency mode NFM, Figure 1 The driving frequency of the display device 10 shown in is the first frequency. As an example, the first frequency may be any one of 60 Hz, 120 Hz, and 240 Hz. When the externally provided image signal RGB is not a still image, the display device 10 may operate in the normal frequency mode NFM. For example, when the driving frequency of the display device 10 is 60 Hz in the normal frequency mode NFM, 60 frames of images FRm may be displayed on the display device 10 in one second. When a moving image is displayed on the display device 10 in the normal frequency mode NFM, the user may watch a natural moving image, and the image may switch seamlessly.

[0119] In low frequency mode LFM, Figure 1 The driving frequency of the display device 10 shown in FIG. 1 is a second frequency (ie, less than the first frequency). As an example, the second frequency may be any one of 1 Hz, 15 Hz, and 30 Hz.

[0120] When the externally provided image signal RGB is a still image in which a prescribed number of frames are the same (i.e., the current frame is the same as or similar to one or more previous frames), the display device 10 operates in the low frequency mode LFM instead of repeatedly outputting the same image. For example, when the driving frequency of the display device 10 is 1 Hz in the low frequency mode LFM, an image of 1 frame FRs can be displayed on the display device 10 in one second. For the remaining 59 frames in one second, ( Figure 1 ) data driving circuit 400 and ( Figure 1 The scan driving circuit 300 (shown in FIG. 1 ) may not operate, and thus the power consumption of the display device 10 may be reduced.

[0121] Figure 7 A scan signal corresponding to a driving frequency determined by an operation mode determination circuit according to an embodiment of the inventive concept is illustrated.

[0122] Reference Figure 1 , Figure 5 and Figure 7 The control signal output circuit 250 outputs the first start control signal FLMp and the second start control signal FLMn in response to the externally provided control signal CTRL and the mode signal MD from the operation mode determination circuit 240 .

[0123] The scan driving circuit 300 outputs first scan signals SP1 to SPn to first type scan lines SPL1 to SPLn and second scan signals SN1 to SNn to second type scan lines SNL1 to SNLn in response to the first start control signal FLMp, the second start control signal FLMn, the first gate clock signal CKVP and the second gate clock signal CKVN.

[0124] During the normal frequency mode NFM, the control signal output circuit 250 may output a first start control signal FLMp and a second start control signal FLMn of a first frequency (e.g., 60 Hz). During the normal frequency mode NFM, the frequency of the first start control signal FLMp may be the same as the frequency of the second start control signal FLMn. During one frame of the normal frequency mode NFM, the first scan signals SP1 to SPn are sequentially activated at a low level, and the second scan signals SN1 to SNn are sequentially activated at a high level.

[0125] During the low frequency mode LFM, the control signal output circuit 250 may output the first start control signal FLMp at a first frequency (e.g., 60 Hz) and may output the second start control signal FLMn at a frequency of 1 Hz. During the low frequency mode LFM, the scan driving circuit 300 outputs the first scan signals SP1 to SPn at a first frequency (e.g., 60 Hz) in synchronization with the first start control signal FLMp at a first frequency (e.g., 60 Hz), and outputs the second scan signals SN1 to SNn at a second frequency (e.g., 1 Hz) in synchronization with the second start control signal FLMn at a second frequency (e.g., 1 Hz).

[0126] One frame includes active periods (e.g., active periods AP1 and AP2) in which the second scan signals SN1 to SNn are sequentially activated (i.e., set to a high level) and blanking periods (e.g., blanking periods BP1 and BP2) in which the second scan signals SN1 to SNn are all maintained at a low level.

[0127] For the second scan signals SN1 to SNn, the active period AP1 in the normal frequency mode NFM is the same as the active period AP2 in the low frequency mode LFM, but the blanking period BP1 in the normal frequency mode NFM is not longer than the blanking period BP2 in the low frequency mode LFM.

[0128] For example, when the driving frequency corresponds to 1 Hz, 15 Hz or 30 Hz, the length of the effective period in one frame is the same, and the length of the blanking period of the second scanning signals SN1 to SNn may be different in the low frequency mode LFM. For example, as the driving frequency becomes lower, the length of the blanking period becomes longer.

[0129] In an exemplary embodiment of the inventive concept, during the low frequency mode LFM, the frequency of the second scan signals SN1 to SNn supplied to the second type scan lines SNL1 to SNLn is reduced, but the frequency of the first scan signals SP1 to SPn supplied to the first type scan lines SPL1 to SPLn and the emission control signals EM1 to EMn supplied to the control lines EL1 to ELn is maintained at a normal level (e.g., 60 Hz). However, the embodiments of the inventive concept are not limited thereto, but may be modified in various ways. In another embodiment, the frequency of the first scan signals SP1 to SPn supplied to the first type scan lines SPL1 to SPLn and the emission control signals EM1 to EMn supplied to the control lines EL1 to ELn may be changed to a low frequency in the same manner as the second scan signals SN1 to SNn supplied to the second type scan lines SNL1 to SNLn. In this optional embodiment, the power consumption of the display device 10 may be further reduced.

[0130] Refer again Figure 2, when the first transistor T1 to the seventh transistor T7 are all driven with a signal of a low driving frequency in the low frequency mode LFM, a flicker phenomenon occurs because the amount of current flowing through the light emitting diode ED is changed by leakage current of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, which may be PMOS transistors.

[0131] According to an embodiment of the inventive concept, in the low frequency mode LFM, the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 are driven at 60 Hz, and the third transistor T3 and the fourth transistor T4 are driven at 1 Hz.

[0132] In some cases, when image switching occurs in which the image signal RGB of the current frame is different from the image signal RGB of the previous frame, the display device 10 may not directly change from the low frequency mode LFM to the normal frequency mode NFM, but may operate in the image switching mode TM. Figure 6B When the number of clocks in the frame FRs shown in FIG. 1 is changed, it is more appropriate for the display device 10 to operate in the image switching mode TM rather than the normal frequency mode NFM.

[0133] Figure 8 is a timing chart for explaining the image switching mode of the display device.

[0134] Reference Figure 5 and Figure 8 When the still image flag signal S_F indicates a valid level (e.g., a high level), the operation mode determination circuit 240 outputs the mode signal MD of the low frequency mode LFM. The control signal output circuit 250 outputs the second start control signal FLMn of the second frequency (e.g., 1 Hz) and the first start control signal FLMp of the first frequency (e.g., 60 Hz) during the low frequency mode LFM.

[0135] The blanking voltage determination circuit 230 provides a blanking voltage signal BV corresponding to the first gray scale to the image conversion circuit 210 during the low frequency mode LFM. The image conversion circuit 210 generates blanking data BD corresponding to the blanking voltage signal BV.

[0136] The image conversion circuit 210 outputs the image data signal DATA including the effective data AD and the blanking data BD to the ( Figure 1 ) data driving circuit 400 shown in FIG.

[0137] ( Figure 1The data driving circuit 400 shown in FIG. 4 may supply data signals corresponding to effective data AD to the data lines DL1 to DLm during an effective period and then supply blanking data BD corresponding to a first grayscale to the data lines DL1 to DLm during a blanking period.

[0138] On the other hand, when the image signal RGB of the current frame is different from the image signal RGB of the previous frame, the still image determination circuit 220 changes the still image flag signal S_F to an inactive level (eg, a low level).

[0139] After the still image flag signal S_F changes from the valid level to the invalid level, the operation mode determination circuit 240 outputs the mode signal MD indicating the image switching mode TM for a specified time (e.g., 30 frames). During the image switching mode TM, from the first frame F1 to the 30th frame F30, the frequency of the first start control signal FLMp and the second start control signal FLMn is a first frequency (e.g., 60 Hz). In the present embodiment, the operation mode determination circuit 240 maintains the image switching mode TM for 30 frames, but the embodiments of the inventive concept are not limited thereto. For example, the holding time of the image switching mode TM can be changed in various ways. In addition, during the image switching mode TM, the frequency of the first start control signal FLMp and the second start control signal FLMn can be set to another frequency (e.g., 30 Hz) higher than the frequency of the low frequency mode LFM.

[0140] The blanking voltage determination circuit 230 provides a blanking voltage signal BV corresponding to the second grayscale (eg, white grayscale) to the image conversion circuit 210 during the image switching mode TM. The image conversion circuit 210 generates blanking data BD corresponding to the blanking voltage signal BV.

[0141] When the still image flag signal S_F indicates a valid level at the last frame of the image switching mode TM (i.e., when the operation of the 30th frame F30 is completed), the operation mode determination circuit 240 outputs the mode signal MD indicating the low frequency mode LFM. When the mode signal MD indicates the low frequency mode LFM again, the blanking voltage determination circuit 230 outputs the blanking voltage signal BV corresponding to the first grayscale.

[0142] When the still image flag signal S_F indicates an inactive level at the last frame of the image switching mode TM (ie, when the operation of the 30th frame F30 is completed), the operation mode determination circuit 240 outputs the mode signal MD indicating the normal frequency mode NFM.

[0143] Fig. 9 is a timing diagram showing an example of a scan signal supplied to a second type scan line and a data signal supplied to a data line.

[0144] For ease of explanation, Fig. 9 Shows the provided Figure 1 The scanning signal SN1 of the second type scanning line SNL1 shown in FIG. Figure 1 , but embodiments of the inventive concept are not limited thereto.

[0145] Reference Fig. 9 , in the effective period APa of the low frequency mode LFM, the data signal D1 supplied to the data line DL1 has a 35 grayscale 35G, and in the blanking period BPa, the data signal D1 supplied to the data line DL1 has a black grayscale BG.

[0146] The data signal D1 to be supplied to the data line DL1 in the active period APb of the image switching mode TM has a 250 grayscale 250G, and the data signal D1 to be supplied to the data line DL1 in the blank period BPb has a white grayscale WG.

[0147] After changing from the image switching mode TM to the low frequency mode LFM, the data signal D1 supplied to the data line DL1 in the active period APc has 250 gray 250G, and the data signal D1 supplied to the data line DL1 in the blank period BPc has black gray BG.

[0148] When image switching occurs in the low frequency mode LFM, the pixel should display an image with a changed grayscale, but due to the above reference Figure 4 The described hysteresis characteristic of the first transistor T1 may result in an afterimage.

[0149] For example, when only one frame of image is changed (such as a change in clock digits), and a still image is received again, the still image flag signal S_F output from the still image determination circuit 220 may be changed to an effective level, to an ineffective level, and then to an effective level in units of one frame. In this case, if there is no image switching mode TM, the afterimage caused by the image of the previous frame may be recognized by the user. In addition, when a low-grayscale image is displayed in the low-frequency mode LFM and then the image is switched to a high-grayscale image, the flicker caused by the brightness difference is more easily recognized.

[0150] Therefore, according to the inventive concept, when the still image flag signal S_F changes from the active level to the inactive level, an operation is performed in the image switching mode TM for a prescribed time (eg, 30 frames) to minimize the afterimage.

[0151] Fig. 10A The data signal and the second start control signal provided to the data line are shown. Fig. 10B Shows when Fig. 10A The result of measuring the amount of light of the display panel when the data signal is supplied to the display panel is shown.

[0152] Reference Fig. 10A and Fig. 10B , ( Figure 1 The data driving circuit 400 shown in FIG. 4 can connect the ( Figure 8 The data signal corresponding to the valid data AD shown in ( Figure 1 ) data lines DL1 to DLm, and then during the blanking period ( Figure 8 The blanking data BD (shown in FIG. 1 ) is supplied to the data lines DL1 to DLm.

[0153] When the blanking data BD corresponds to black gray in the low frequency mode LFM, the data signal D1 supplied to the data line DL1 may have about 7.9V. Also, when the blanking data BD corresponds to black gray in the image switching mode TM, the data signal D1 supplied to the data line DL1 may have about 7.9V.

[0154] In other words, when the blanking data BD corresponds to the black grayscale in both the low frequency mode LFM and the image switching mode TM, the flicker FLK1 caused by the brightness difference occurs after changing from the image switching mode TM to the low frequency mode LFM.

[0155] Fig.11A shows a data signal and a second start control signal provided to a data line according to an embodiment of the inventive concept, Fig. 11B Shows when Fig.11A Result of measuring the amount of light of the display panel when the data signal shown in FIG. 1 is supplied to the display panel.

[0156] Reference Fig.11A and Fig. 11B , when the blanking data BD corresponds to the black gray in the low frequency mode LFM, the data signal D1 to be supplied to the data line DL1 may have about 7.9V. In addition, when the blanking data BD corresponds to the white gray in the image switching mode TM, the data signal D1 to be supplied to the data line DL1 may have about 3.9V.

[0157] It can be understood that after the image switching mode TM is changed to the low frequency mode LFM, Fig. 10B In other words, by implementing white grayscale for blanking data BD during image switching mode TM, the brightness difference when switching from image switching mode TM to low frequency mode LFM is reduced, thereby reducing flicker.

[0158] Therefore, when a still image is input, the drive controller having the above-mentioned configuration can reduce power consumption by operating in a low-frequency mode in which the driving frequency is reduced. When image switching is sensed in the low-frequency mode, the drive controller can prevent afterimages from appearing on the displayed image by operating in an image switching mode in which the driving frequency is increased. Finally, during the blanking period of the image switching mode, the voltage level of the data signal supplied to the data line is changed to a white gray voltage level to minimize the flicker phenomenon.

[0159] Although the exemplary embodiments of the present disclosure have been described, it is understood that the present disclosure should not be limited to these exemplary embodiments, and a person of ordinary skill in the art can make various changes and modifications within the spirit and scope of the present disclosure as claimed. In addition, the embodiments disclosed in the inventive concept are not intended to limit the technical spirit of the inventive concept, and the protection scope of the present disclosure should be interpreted based on the attached claims, and it should be understood that all technical spirits included in the scope equivalent thereto are included in the protection scope of the present disclosure.

Claims

1. A drive controller, comprising: An image conversion circuit configured to convert an externally received image signal into an image data signal including effective data and blanking data; a still image determination circuit configured to output a flag signal of a valid level when the image signal is a still image; an operation mode determination circuit configured to output an operation mode signal indicating a low frequency mode when the flag signal is at the active level, and configured to output an operation mode signal indicating an image switching mode when the flag signal changes between the active level and an inactive level; as well as a blanking voltage determination circuit configured to receive the operation mode signal and output a blanking voltage signal to the image conversion circuit, wherein the blanking voltage signal corresponds to a black grayscale during the low frequency mode, and the blanking voltage signal corresponds to a white grayscale during the image switching mode, and Wherein, the blanking data corresponds to the blanking voltage signal.

2. The drive controller according to claim 1, wherein: The image conversion circuit outputs the image data signal at a driving frequency corresponding to the operation mode signal.

3. The drive controller according to claim 2, wherein: The driving frequency in the image switching mode is higher than the driving frequency in the low frequency mode.

4. The drive controller according to claim 1, wherein: The operation mode determination circuit outputs the operation mode signal indicating the image switching mode for a prescribed time after the flag signal changes from the effective level to the ineffective level, and when the flag signal is at the effective level after the prescribed time has passed, the operation mode determination circuit outputs the operation mode signal indicating the low frequency mode.

5. The drive controller according to claim 1, further comprising: The control signal output circuit is configured to output a first start control signal and a second start control signal in response to an externally received control signal and the operation mode signal.

6. The drive controller according to claim 5, wherein: During the low frequency mode, the frequency of the first start control signal and the frequency of the second start control signal are different from each other, and During the image switching mode, the frequency of the first start control signal and the frequency of the second start control signal are the same.

7. A display device, comprising: A display panel including a plurality of pixels connected to a plurality of data lines and a plurality of scan lines respectively; A driving controller configured to receive an image signal and output an image data signal, a data control signal and a scanning control signal; a data driving circuit configured to drive the plurality of data lines in response to the image data signal and the data control signal; as well as a scan driving circuit configured to drive the plurality of scan lines in response to the scan control signal, Wherein, the drive controller comprises: An image conversion circuit configured to convert an externally received image signal into an image data signal including effective data and blanking data; a still image determination circuit configured to output a flag signal of a valid level when the image signal is a still image; an operation mode determination circuit configured to output an operation mode signal indicating a low frequency mode when the flag signal is at the active level, and configured to output an operation mode signal indicating an image switching mode when the flag signal changes between the active level and an inactive level; and a blanking voltage determination circuit configured to receive the operation mode signal and output a blanking voltage signal to the image conversion circuit, wherein the blanking voltage signal corresponds to a black grayscale during the low frequency mode, and the blanking voltage signal corresponds to a white grayscale during the image switching mode, and Wherein, the blanking data corresponds to the blanking voltage signal.

8. The display device according to claim 7, wherein: The operation mode determination circuit outputs the operation mode signal indicating the image switching mode for a prescribed time after the flag signal changes from the effective level to the ineffective level, and when the flag signal is at the effective level after the prescribed time has passed, the operation mode determination circuit outputs the operation mode signal indicating the low frequency mode.

9. The display device according to claim 7, wherein: At least one pixel of the plurality of pixels comprises: A light emitting diode, comprising an anode and a cathode; a first transistor including a first electrode configured to receive a first driving voltage, a second electrode electrically connected to the anode of the light emitting diode, and a gate electrode; a second transistor including a first electrode connected to a corresponding data line among the plurality of data lines, a second electrode connected to the first electrode of the first transistor, and a gate electrode configured to receive a first scan signal; and The third transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the gate electrode of the first transistor, and a gate electrode configured to receive a second scan signal.

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