Accelerate memory device trim initialization

Abstract

This document describes apparatus and techniques for accelerating the initialization of trim in a memory device. Initialization of a memory device may be initiated by the memory device. An accelerated trim command may be received from a controller at the memory device. In response to receiving the accelerated trim command, the memory device may inhibit setting trim. It is contemplated that the trim is set by the controller. The memory device may then complete initialization after the controller sets the trim.

Description

Technical Field

[0001] The present application relates to memory devices. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems.There are many different types of memory, including volatile memory and non-volatile memory.

[0003] Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and the like.

[0004] Non-volatile memory can retain stored data when power is not supplied, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM) or magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and the like.

[0005] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of single-transistor, floating-gate, or charge-trapping memory cells, which achieve high memory density, high reliability, and low power consumption.

[0006] Two common types of flash memory array architectures include NAND and NOR architectures, named for the logical form in which the basic memory cells of each architecture are arranged. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together in series, source-to-drain, between a source line and a bit line.

[0007] Both NOR and NAND architecture semiconductor memory arrays are accessed through a decoder that activates a particular memory cell by selecting the word line coupled to the gate of the particular memory cell. In a NOR architecture semiconductor memory array, once activated, the selected memory cell places its data value on the bit line, causing different currents to flow depending on the programming state of the particular cell. In a NAND architecture semiconductor memory array, a high bias voltage is applied to the drain-side select gate (SGD) line. The word line coupled to the gates of the unselected memory cells of each group is driven with a specified pass voltage (e.g., Vpass) to cause the unselected memory cells of each group to act as pass transistors (e.g., conduct current in a manner that is not limited by the data value stored in them). Current then flows from the source line to the bit line through each series-coupled group, limited only by the selected memory cell of each group, placing the currently encoded data value of the selected memory cell on the bit line.

[0008] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively into one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), representing one data bit.

[0009] However, flash memory cells can also represent one of more than two programmed states, allowing higher density memories to be made without increasing the number of memory cells because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-bit cells, or multi-level cells (MLCs). In some examples, an MLC may refer to a memory cell that can store two bits of data per cell (e.g., one of four programmed states), a triple-level cell (TLC) may refer to a memory cell that can store three bits of data per cell (e.g., one of eight programmed states), and a quad-level cell (QLC) may store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).

[0010] Conventional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor substrate. To increase the memory capacity of a given area and reduce costs, the size of individual memory cells has been reduced. However, there are technical limitations to reducing the size of individual memory cells and, therefore, the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures (such as 3D NAND architecture semiconductor memory devices) are being developed to further increase memory density and reduce memory costs.

[0011] Such 3D NAND devices typically include a string of memory cells coupled in series (e.g., drain to source) between one or more source-side select gates (SGS) near the source and one or more drain-side select gates (SGD) near the bit line. In one example, the SGS or SGD may include one or more field effect transistors (FETs) or metal oxide semiconductor (MOS) structure devices, etc. In some examples, the string will extend vertically through multiple vertical spacer layers containing corresponding word lines. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent to the string of memory cells to form a channel for the memory cells of the string. In the example of a vertical string, the polysilicon structure may be in the form of a vertically extending column. In some examples, the string may be "folded" so as to be arranged relative to a U-shaped column. In other examples, multiple vertical structures may be stacked on each other to form a stacked array of memory cell strings.

[0012] Memory arrays or devices can be combined together to form storage volumes of a memory system, such as a solid-state drive (SSD), universal flash storage (UFS), or a flash drive. TM ) devices, Multimedia Card (MMC) solid-state storage devices, embedded MMC devices (eMMC TM ) and the like. SSDs can be used, among other things, as primary storage devices for computers, and have advantages over traditional hard disk drives with moving parts in terms of, for example, performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, SSDs can reduce seek times, wait times, or other delays associated with magnetic disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells (such as flash memory cells) to eliminate the need for internal battery power, thus allowing the drives to be more versatile and compact.

[0013] An SSD may include multiple memory devices comprising multiple dies or logical units (e.g., logical unit numbers or LUNs), and may include one or more processors or other controllers that perform the logic functions required to operate the memory devices or interface with external systems. Such an SSD may include one or more flash memory dies on which multiple memory arrays and peripheral circuitry are included. The flash memory array may include multiple blocks of memory cells organized into multiple physical pages. In many examples, the SSD will also include DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands associated with memory operations from a host, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory devices and the host, or erase operations to erase data from the memory devices. Summary of the Invention

[0014] One aspect of the present disclosure provides a memory device for accelerating the initialization of trim of a memory device, wherein the memory device includes: an interface for receiving an accelerated trim command from a controller; and a processing circuit system for: starting the initialization of the memory device; prohibiting setting trim in response to receiving the accelerated trim command, the trim being set by the controller; and completing the initialization of the memory device after the controller sets the trim.

[0015] Another aspect of the present disclosure provides a method for accelerating the initialization of trimming of a memory device, wherein the method includes: starting the initialization of the memory device at a memory device; receiving an accelerated trim command from a controller at the memory device; prohibiting, by the memory device, setting trim in response to receiving the accelerated trim command, the trim being set by the controller; and completing the initialization of the memory device by the memory device after the controller sets the trim.

[0016] Another aspect of the present disclosure provides a machine-readable medium, wherein the machine-readable medium includes instructions that, when executed by a circuit system, cause the circuit system to perform a method for accelerating the initialization of trimming of a memory device, wherein the method includes: starting the initialization of the memory device at a memory device; receiving an accelerated trim command from a controller at the memory device; prohibiting, by the memory device, setting trim in response to receiving the accelerated trim command, the trim being set by the controller; and completing the initialization of the memory device by the memory device after the controller sets the trim.

[0017] Another aspect of the present disclosure provides a system, wherein the system includes a device that performs a method for accelerating the initialization of trim of a memory device, wherein the method includes: starting the initialization of the memory device at a memory device; receiving an accelerated trim command from a controller at the memory device; prohibiting, by the memory device, setting trim in response to receiving the accelerated trim command, the trim being set by the controller; and completing the initialization of the memory device by the memory device after the controller sets the trim. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the accompanying drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different examples of similar components. By way of example, the accompanying drawings generally illustrate, in a non-limiting manner, various embodiments discussed in this document.

[0019] Figure 1 An example of an environment including a memory device is shown.

[0020] Figure 2 An example of a system implementing accelerated memory device trim initialization is shown.

[0021] Figure 3 An example of a control flow for a NAND device is shown, where the controller signals the responsible load trim.

[0022] Figure 4 An example of a control flow for a NAND device is shown, where the controller signals the part responsible for load trimming.

[0023] Figure 5 A flow chart of a method for accelerating memory device trim initialization is shown.

[0024] Figure 6 is a block diagram illustrating an example of a machine upon which one or more embodiments may be implemented. DETAILED DESCRIPTION

[0025] Some memory devices, such as NAND devices, have variations in the operation of the storage cells. These variations may occur during manufacturing or over the lifetime of the device. Because the tolerances of read and write technologies (e.g., voltages in NAND devices) leave little margin for error, variations in device operation are accounted for by small adjustments called trimming to achieve reliable, accurate, and consistent data storage. Trimming is a hardware or firmware process used to change the value or parameter of electronic functionality (such as speed, power, durability, reliability, etc.). Modern NAND devices can include thousands of trims to adjust the underlying NAND array. Although trimming can be used for different types of memory devices—such as storage-class memory (e.g., using phase change devices, memristors, ferroelectric RAM, etc.) or holographic RAM (HRAM)—the following examples use NAND devices for clarity. The following techniques can generally be applied to any memory device that relies on trimming for correct or higher-performance operation.

[0026] Typically, when a NAND array is powered on, controller circuitry within the array (e.g., an array controller) loads a prune set (e.g., from an internal ROM or from the NAND array) into volatile memory elements (e.g., latches) to ensure proper array reads and writes. Even when the array controller and the memory controller for the memory device are packaged together, the array controller can be distinct from the memory controller (e.g., as is the case with managed NAND devices). The array controller typically includes few processing or volatile memory resources and is designed to implement (e.g., orchestrate) directed reads and writes to the NAND array. Due to these limited resources, the time it takes for the array controller to load the prune set for the NAND array increases with increasing complexity and size of the NAND array, and the corresponding increase in prune set size. This problem can be exacerbated when the prune set is stored within the array itself. Fluctuations in NAND cell operation (such as wear, reading and writing across temperature, read disturb conditions, or simply a higher raw bit error rate (RBER) than other media) can require error correction operations to correct the stored data before it can be used. In these cases, the limited processing power of most array controllers can further increase initialization latency. As a further complication, in some multi-die (e.g., multi-array) devices, limited power budgets may require staggered initialization of the NAND arrays to avoid higher current peaks or averages during startup, again increasing startup latency.

[0027] Different types of devices have different sensitivities to the startup time of their memory devices. Several classes of power-constrained devices may be particularly sensitive to startup latency, as they often attempt to frequently power down components to conserve limited energy. Such devices may include battery-powered sensors or actuators (e.g., as often seen in the Internet of Things (IoT)) or mobile devices such as phones and tablets. For mobile devices, extended startup latency of memory devices may impact the user experience and limit how aggressively the mobile device can manage its power consumption. Consequently, initialization (including initial trim loading) of memory devices for mobile devices has long been an industry concern.

[0028] To address these issues, a hybrid array controller and memory controller trim loading technique is described below. Typically, memory controllers have greater computational resources to process raw trim set data into usable trims, for example, via more precise or faster error correction. Additionally, memory controllers typically include fast static memory resources (e.g., SRAM) to retain some parameters. These fast static memory resources are typically much larger than those found in some array controllers. These features enable a more efficient trim loading process, where some of the trims are loaded by the memory controller rather than the array controller. The memory controller trim loading technique can be embodied in one or more accelerated trim (e.g., turbo init) commands that communicate deviations from the traditional trim loading process to the array controller.

[0029] The overall greater processing power of the memory controller can significantly increase the amount of trimmed data that can be read by leveraging the memory controller's more accurate error correction. Furthermore, the memory controller's partial trim storage between sleep and wake cycles can further reduce startup latency. Furthermore, some device interfaces support direct access to NAND latches, further reducing the time it takes the memory controller to set trim, freeing it from the responsibility of the array controller. These features work together to enable success in energy-constrained devices such as mobile phones.

[0030] Additional details and examples are provided below. Figure 1 An overview of a managed NAND memory device is shown that includes a memory controller and an array controller in the same package. However, such an arrangement is not required, with possible arrangements including the memory controller being communicatively coupled to the array controller as part of a host when the memory controller and array controller are in separate packages. Figure 2 This separate arrangement is shown, and further details of the array controller and memory controller are discussed to implement memory device trim initialization in the context of NAND flash memory.

[0031] Figure 1 An example of an environment 100 is shown, which includes a host device 105 and a memory device 110 configured to communicate via a communication interface. The host device 105 or the memory device 110 may be included in various products 150, such as Internet of Things (IoT) devices (e.g., refrigerators or other household appliances, sensors, motors or actuators, mobile communication devices, cars, drones, etc.) to support processing, communication, or control of the product 150. Figure 2 Provides more details specific to tunable NAND write performance using pSLC encoding.

[0032] Memory device 110 includes a memory controller 115 and a memory array 120, which includes, for example, a plurality of individual memory dies (e.g., a stack of three-dimensional (3D) NAND dies). In 3D architecture semiconductor memory technology, vertical structures are stacked, thereby increasing the number of layers, physical pages, and, therefore, the density of the memory device (e.g., storage device). In one example, memory device 110 can be a discrete memory or storage device component of host device 105. In other examples, memory device 110 can be part of an integrated circuit (e.g., a system on a chip (SOC)), stacked or otherwise included in one or more other components of host device 105. In these examples, memory device 110 communicates with components of host device 105 via an interconnect link 111, such as a bus. Therefore, as described herein, even if memory device 110 is integrated into host device 105, the operation of the host or host device 105 may differ from the operation of memory device 110.

[0033] One or more communication interfaces (e.g., interconnect link 111) may be used to transfer data between the memory device 110 and one or more other components of the host device 105, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC interface, or a similar interface. TM interface or one or more other connectors or interfaces. Host device 105 may include a host system, an electronic device, a processor, a memory reader, or one or more other electronic devices external to memory device 110. In some examples, host 105 may be a Figure 6 The components of machine 600 discussed herein may be some or all of the machine.

[0034] The memory controller 115 can receive instructions from the host 105 and can communicate with the memory array 120, such as to transfer data to (e.g., write to or erase from) or transfer data from (e.g., read from) one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array 120. The memory controller 115 may include, among other things, circuitry or firmware comprising one or more components or integrated circuits. For example, the memory controller 115 may include one or more memory control units, circuits, or components configured to control access across the memory array 120 and provide a translation layer between the host 105 and the memory device 110. Although the memory controller 115 is shown here as part of the memory device 110 package, other configurations are possible, such as the memory controller 115 being a component of the host 105 (e.g., as a discrete package on a system-on-chip of the host 105, separate from the memory device 110) or even being implemented via the central processing unit (CPU) of the host 105.

[0035] The memory manager 125 may include, among other things, circuitry or firmware, such as several components or integrated circuits associated with various memory management functions. For purposes of this specification, exemplary memory operations and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operations or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or recycling), error detection or correction, block retirement, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with the operation of a memory array, etc.), or generate device commands for the array controller 135 or one or more other components of the memory device 110 (e.g., to perform various memory management functions).

[0036] The memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of the memory device 110 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller 115). For example, the management tables 130 may include information about block lifetimes, block erase counts, error histories, or one or more error counts (e.g., write error counts, read bit error counts, read error counts, erase error counts, etc.) for one or more blocks of memory cells coupled to the memory controller 115. In some examples, if the number of errors detected for one or more error counts is above a threshold, the bit error may be referred to as an uncorrectable bit error. The management tables 130 may, in particular, maintain counts of correctable or uncorrectable bit errors. In one example, the management tables 103 may include a translation table or a logical-to-physical (L2P) mapping.

[0037] The array controller 135 may include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory operations may be based on, for example, host commands received from the host 105 or generated internally by the memory manager 125 (e.g., associated with wear leveling, error detection or correction, etc.).

[0038] Array controller 135 may include an error correction code (ECC) component 140, which may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of memory device 110 coupled to memory controller 115. Memory controller 115 may be configured to proactively detect and recover from errors associated with various operations or data storage (e.g., bit errors, operational errors, etc.) based on ECC data maintained by array controller 135. This enables memory controller 115 to maintain the integrity of data transmitted between host 105 and memory device 110 or to maintain the integrity of stored data. Part of this integrity maintenance may include deleting (e.g., retiring) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors. RAIN is another technique that memory device 110 may use to maintain data integrity. Array controller 135 may be configured to implement RAIN parity data generation and storage in array 120. Memory controller 115 may be involved in using parity data to reconstruct damaged data.

[0039] The memory array 120 may include several memory cells arranged in, for example, multiple devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may contain 18,592 bytes (B) of data (16,384 + 2208 bytes) per page, 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device (storing two bits of data per cell (i.e., 4 programmable states)) may contain 18,592 bytes (B) of data (16,384 + 2208 bytes) per page, 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the required write time and double the program / erase (P / E) cycles compared to a corresponding TLC memory device. Other examples may include other numbers or arrangements. In some examples, a memory device, or a portion thereof, can be selectively operated in an SLC mode or a desired MLC mode (such as TLC, QLC, etc.).

[0040] In operation, data is typically written to or read from the NAND memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells as needed. The data transfer size of the NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0041] Although a data page can contain multiple bytes of user data (e.g., a data payload containing multiple data sectors) and corresponding metadata, the page size generally refers only to the number of bytes used to store the user data. As an example, a page of data with a page size of 4KB can contain 4KB of user data (e.g., 8 sectors with a sector size of 512B) and multiple bytes (e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0042] Different types of memory cells or memory arrays 120 may provide different page sizes or may require different amounts of metadata associated therewith. For example, different memory device types may have different bit error rates, which may result in different amounts of metadata required to ensure data page integrity (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data than a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash memory device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash memory device. Therefore, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0043] Figure 2 An example of a system implementing accelerated NAND trim initialization is shown. For illustration purposes, the memory controller 210 is shown as separate from the NAND die 215 including the array controller 220 and the NAND array 225 elements. However, the above description of Figure 1 Either the configuration described or this configuration can be used to accelerate trim initialization. In either case, the host 205 typically communicates with the memory controller 210 to complete a read or write operation to the array 225.

[0044] The following example is in the context of the host 205 waking up the NAND die 215 to perform a read or write. As mentioned above, in a mobile device, this sequence may occur frequently to manage the device's energy consumption.

[0045] At power-up, the NAND die 215 begins its initialization process. In a conventional initialization process, the array controller 220 is configured to obtain trims and load them into the controller structures (eg, latches) of the array 225 to adjust (eg, slightly adjust) the read or write voltages.

[0046] The memory controller 210 is configured to send an accelerated trim command to the array controller 220, which is configured to recognize the accelerated trim command. Through the accelerated trim command, the array controller 220 is made aware that the conventional initialization process will be altered. In one example, the accelerated trim command is one of two types of accelerated trim commands, a first type being a partial type and a second type being a complete type. These two types will be described in more detail below; however, it is sufficient to understand that the partial type means that the array controller 220 will be responsible for loading some but not all trims, with the remaining trims being handled by the memory controller 210, while the complete type means that the memory controller 210 will handle and load all trims to be set.

[0047] In response to receiving the accelerated trim command, array controller 220 is configured to refrain from setting at least one trim. This trim will be set by memory controller 210. This sequence deviates from a conventional memory device initialization process. In one example, when the accelerated trim command is of the complete type, array controller 220 refrains from initializing all trims. Again, in this case, memory controller 210 signals array controller 220 that memory controller 210 will set all trims, and thus array controller 220 does not process any trims at all.

[0048] In one example, when the accelerated trim command is of the partial type, the array controller 220 prohibits initializing a subset of all trims. Thus, here, the array controller 220 initializes some trims but not others. In one example, the subset of all trims is trims that are not specific to the NAND die 215. In one example, the array controller loads NAND die-specific trims. Such trims may include those determined for the NAND die 215 at manufacturing time and encoded in ROM or other reliable storage media of the NAND die 215. Here, non-NAND die-specific trims may include those caused by NAND cell wear in the array 225, cross-temperature conditions (e.g., trim adjustments based on the ambient temperature of the NAND die 215), or other variable trims that may change over time. This shared responsibility can benefit the overall trim loading process by enabling the array controller 220 to load only the trims that are unique to the array and enabling the memory controller 210 to transfer other common trims in parallel to multiple NAND dies 215 in the system, or by enabling the controller 220 to load only the trims needed to read the rest and transfer them to the memory controller 210 for error correction.

[0049] Once trimming is set by memory controller 210, array controller 220 completes initialization of the NAND die. In one example, memory controller 210 is configured to send an enable trim command to array controller 220 to signal that memory controller 210 has completed setting the trimming it is responsible for. Therefore, to facilitate completion of initialization, array controller 220 is arranged to wait until it receives the enable trim command.

[0050] There are situations where the memory controller 210 is unable to load the trims for which it was originally responsible. Therefore, in one example, upon failing to load the trims, the memory controller 210 is arranged to provide an error-type accelerated trim command. The command details that a previous trim load operation failed. In one example, the command includes an indication of which trims were not loaded as part of the failure. The array controller 220, upon receiving the error-type accelerated trim command, is configured to set the trims that the memory controller 210 failed to load. Therefore, if the memory controller 210 fails to load the trims, a graceful fallback to the traditional trim loading process is performed. In this context, the memory controller 210 or the host 205 can be configured to verify the loaded trims via a parity check or by reading back the loaded trims and comparing them to expected values.

[0051] Several options are available regarding trim storage. As described above, the memory controller 210 can be configured to store trims within itself, effectively in static storage media. This option is useful between sleep and wake cycles of a device (such as a mobile phone). In one example, the array controller 220 can be configured to store trims in the array 225 and provide them to the memory controller 210 upon request. This arrangement is useful, for example, when the device is shutting down and clearing the memory controller's fast static media. This can also be useful when the memory controller 210 uses its fast static storage media for other purposes to clear trim data.

[0052] Thus, in one example, memory controller 210 is configured to issue a trim read command for raw trim data (e.g., before error correction has been applied) to array controller 220, and array controller 220 is configured to provide the raw trim data in response. In one example, the trim read command does not specify an address. Typically, memory controller 210 does not need to specify a trim location within array 225 because array controller 220 already knows where the trim data will be executed, such as by performing a trim load itself. Thus, omitting the trim data location reduces overhead in the trim read command. In one example, the issuer of the trim read command cannot address the location in array 225 where the trim data is stored. This arrangement reduces the likelihood of inadvertent or malicious tampering with the trim data.

[0053] When using the accelerated pruning loading techniques described herein, several things happen. Examples of these benefits include improved system performance by reducing latency, thereby improving system responsiveness. This benefit is even more pronounced in energy-constrained systems, which can now take a more aggressive power management stance while maintaining the same level of user experience. Additionally, pruning accuracy (e.g., reliability) is improved by using more precise error correction techniques. These benefits result in better overall device performance for devices that include accelerated pruning initialization.

[0054] The following is an example of a set of accelerated trim commands that the memory controller 210 may issue to the array controller. The set of commands may include F1h (skip load), F2h (first partial trim load), F3h (second partial trim load), 0F-30h (alternate and compact trim load), and F0h (enable trim).

[0055] F1h: Skip Load. This command signals the array controller 220 to not perform the traditional "trim load procedure on first call." This is an example of a full-type accelerated trim load command. Figure 3 An example of F1h is shown.

[0056] F2h: First Partial Trim Load. Similar to F1h, F2h interrupts the array controller's traditional trim load process. However, F2h specifies that the array controller 220 will load a basic trim set to allow for optimized execution of alternative trim loads. Examples of these basic trim sets may include analog, column and row redundancy, Zq, and Open NAND Flash Interface (ONFI) trim. These trims can be considered NAND die-specific trims. F2h is an example of a partial type of accelerated NAND trim command. Figure 4 An example of F2h is shown.

[0057] F3h: Second Partial Trim Load. F3h acts as the complement of F2h to FDh (e.g., the legacy array controller 220 trim loader) to signal the array controller 220 to quickly complete trim initialization if F2h fails. Therefore, F3h is an example of an error type accelerated trim initialization command.

[0058] 0F-30h: Alternative and compact trim load. This command is a trim read command issued by the memory controller 210. Depending on the implementation, 0F-30h may specify different read characteristics for the array controller 220 to use when reading the array to provide different levels of read reliability (e.g., faster and potentially requiring more error correction, or slower and potentially requiring less error correction) or storage locations (e.g., accessing special blocks, such as additional pages on a ROM block or blocks marked "half good").

[0059] F0h: Enable trim. F0h is issued by the memory controller 210 to trigger the reg_romfuse_en signal in the array controller 220, after which the array controller 220 completes the initialization operation.

[0060] Figure 3 An example of a control flow 300 for a NAND device is shown, in which the controller signals the controller responsible for loading trim. Assume that the NAND device is exiting a hibernation state. In this power state, for example, as defined in the Universal Flash Storage (UFS) specification, the power management integrated circuit (PMIC) can disconnect Vcc (e.g., the NAND core power supply) and keep Vccq enabled (e.g., the UFS controller is still booted). To speed up NAND device reinitialization upon resume, the memory controller can store the NAND trim in a reserved SRAM of the memory controller (e.g., a few kilobytes of memory) and reload the trim using a turbo init command.

[0061] For example, the memory controller may issue an F1h command to cause the array controller to stop loading trim (operation 305). If the F1h command is unsuccessful (e.g., the array controller does not understand the command or some other error occurs), the array controller proceeds to the traditional trim loading sequence (operation 320). If the F1h command is successful, the memory controller loads and verifies all trim (operation 310). If the trim loading is successful, the memory controller issues an F0h (enable trim) command to the array controller, which completes the initialization (operation 315). Otherwise, the array controller completes the traditional trim loading procedure (operation 320). The FDh command (operation 320) may perform trim verification, which may result in a good status (e.g., passed) or a bad status (e.g., failed). For example, in a passed status, the NAND device is ready for use by the host.

[0062] In one example, if the ONFI configuration is lost when Vcc is disabled, F1h may include loading the ONFI configuration. In one example, the MLBi phase may be divided into two parts, where the first part is trim write and verify, and the second part enables ONFI after the first part is completed.

[0063] Figure 4 An example of a control flow 400 for a NAND device is shown, where the controller signals the responsible for partial load pruning. Figure 4An example of F2h partial trim loading is shown in FIG. A NAND array (e.g., die) can be divided into different sections (e.g., pages, planes, blocks, etc.). In one example, each section has its own set of trims. However, for NAND devices, all NAND arrays have some common trims, and some trims are specific to the NAND array. In one example, during F2h operation, the array controller loads these die-specific trims. Such die-specific trims can be smaller than other trims, resulting in faster trim completion by the array controller.

[0064] Thus, control flow 400 begins with the memory controller issuing an F2h command to the array controller (operation 405), signaling to the array controller that the array controller is responsible for some trimming (e.g., die-specific trimming) and that the memory controller is responsible for other trimming. As in control flow 300 above, if the F2h command fails, the array controller uses a conventional trim load process (operation 430).

[0065] If the array controller accepts the F2h command, the memory controller issues a trim read command (operation 410). If the trim read command fails, the memory controller uses an F3h command (operation 425) to signal the array controller that the trim load should be completed from the point where the memory controller interrupted. If this fails, the array controller falls back to the traditional trim load procedure (operation 430). If the memory controller fails to address (operation 410), read (operation 415), or write (operation 420) any trim during the F2h operation, then F3h is the fail path. If the read (operation 415) succeeds, the memory controller can use the trim data and modify it based on certain conditions, and then write (operation 420) the trim data to the array controller to modify the trim used by the memory.

[0066] Figure 5 A flow chart of a method 500 for accelerating memory device trim initialization is shown. The operations of the method are implemented in computer hardware, such as the hardware described above (eg, array controller, etc.) or the hardware described below (eg, processing circuitry).

[0067] In operation 505 , the memory device starts its initialization.

[0068] In operation 510, the memory device receives an accelerated trim command from a controller. In one example, the accelerated trim command is one of two types of accelerated trim commands, wherein a first type is a partial type and a second type is a complete type.

[0069] In operation 515, the memory device prohibits setting trim in response to receiving the accelerated trim command. Here, the trim will be set by the controller. In one example, when the accelerated trim command is a complete type, the array prohibits initializing all trims.

[0070] In one example, when the accelerated trim command is of a partial type, the array refrains from initializing a subset of all trims. In an example, the subset of all trims is trims that are not memory device specific. In one example, method 500 is extended to include the memory device loading memory device specific trims.

[0071] In operation 520, the memory device may complete initialization after the controller sets trim. In one example, to facilitate completion of initialization, the memory device receives an enable trim command from the controller to signal the controller that trim has been set.

[0072] In one example, the operations of method 500 can be expanded to include fallback operations in the event that a previous attempt by the controller to load trim does not work. These operations may include: initiating a second initialization of the memory device; receiving a second accelerated trim command (which is a partial type) from the controller; and prohibiting setting the second trim in response to receiving the second accelerated trim command. Now, the memory device receives a third accelerated trim command in response to the controller failing to set the second trim. The memory device then sets the second trim in response to receiving the third accelerated trim command, and upon setting the second trim, the second initialization of the memory device is complete.

[0073] In one example, method 500 can be expanded to include additional operations that enable the memory device to store raw trim data and provide it to the controller. For example, the memory device can receive a trim read command and provide the trim data stored on the memory device in response to receiving the trim read command. In one example, the trim read command does not specify an address. In one example, the issuer of the trim read command cannot address the location in the memory device where the trim data is stored.

[0074] Figure 6A block diagram of an exemplary machine 600 is shown, on which any one or more of the techniques (e.g., methods) discussed herein can be performed. In alternative embodiments, the machine 600 can act as a standalone device or can be connected (e.g., networked) to other machines. In a network deployment, the machine 600 can operate in the capacity of a server machine, a client machine, or both in a server-client network environment. In one example, the machine 600 can act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 600 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network device, an IoT device, an automotive system, or any machine capable of executing instructions (in sequence or otherwise) specifying actions to be taken by the machine. In addition, although only a single machine is shown, the term "machine" should also be considered to include any collection of machines that execute an instruction set (or multiple instruction sets) to perform any one or more of the methods discussed herein, such as cloud computing, software as a service (SaaS), or other computer cluster configurations, either individually or in combination.

[0075] As described herein, examples may include logic, components, devices, packages, or mechanisms, or may be operated by them. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity including hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system can flexibly change over time and due to the variability of the underlying hardware. A circuit system includes members that can perform specific tasks individually or in combination when in operation. In one example, the hardware of the circuit system can be designed to perform specific operations (e.g., hardwired). In one example, the hardware of the circuit system can include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), which include computer-readable media that encode instructions for specific operations through physical modifications (e.g., magnetic, electrical, removably placed particles of constant mass, etc.). When the physical components are connected, the basic electrical properties of the hardware components change, such as from an insulator to a conductor, or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to create members of the circuit system in hardware via variable connections to perform part of a specific task when in operation. Thus, when the device is in operation, the computer-readable medium is communicatively coupled to other components of the circuit system. In one example, any physical component can be used in more than one member of more than one circuit system. For example, during operation, an execution unit can be used in a first circuit in a first circuit system at one point in time and can be reused by a second circuit in the first circuit system or a third circuit in the second circuit system at another time.

[0076] The machine (e.g., computer system) 600 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof (such as memory controller 115), a main memory 604, and a static memory 606, some or all of which may communicate with each other via an interconnection link (e.g., a bus) 608. The machine 600 may also include a display unit 610, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In one example, the display unit 610, the input device 612, and the UI navigation device 614 may be a touch screen display. The machine 600 may also include a storage device (e.g., a drive unit) 608, a signal generating device 618 (e.g., a speaker), a network interface device 620, and one or more sensors 616, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 600 may include an output controller 628, such as a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC)), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0077] The storage device 608 may include a machine-readable medium 622 on which is stored one or more sets of data structures or instructions 624 (e.g., software) that embody or are used by any one or more of the techniques or functionality described herein. During execution of the instructions 624 by the machine 600, the instructions may also reside, completely or at least partially, within the main memory 604, within the static storage 606, or within the hardware processor 602. In one example, one or any combination of the hardware processor 602, the main memory 604, the static storage 606, or the storage device 608 may constitute the machine-readable medium 622.

[0078] Although the machine-readable medium 622 is shown as a single medium, the term “machine-readable medium” may also include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 624.

[0079] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions that are executed by the machine 600 and cause the machine 600 to perform any one or more of the techniques of the present disclosure, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In one example, a massed machine-readable medium includes a machine-readable medium with a plurality of particles having a constant (e.g., stationary) mass. Thus, a massed machine-readable medium is not a transient propagating signal. Specific examples of massed machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM) or electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0080] Instructions 624 (e.g., software, programs, operating system (OS), etc.) or other data are stored on storage device 621 and can be accessed by memory 604 for use by processor 602. Memory 604 (e.g., DRAM) is typically fast but volatile, and therefore a different type of storage device from storage device 621 (e.g., SSD) in that it is suitable for long-term storage, including when in a "powered-off" state. Instructions 624 or data being used by a user or machine 600 are typically loaded into memory 604 for use by processor 602. When memory 604 is full, virtual space from storage device 621 can be allocated to supplement memory 604. However, because storage device 621 is typically slower than memory 604, with write speeds typically at least twice as slow as read speeds, the use of virtual memory can significantly reduce the user experience due to storage device latency (compared to memory 604, e.g., DRAM). Furthermore, using storage device 621 for virtual memory can significantly shorten the lifespan of storage device 621.

[0081] In contrast to virtual memory, virtual memory compression (e.g. A kernel feature ("ZRAM") uses a portion of memory as compressed block storage to avoid paging to storage 621. Paging occurs in compressed blocks until it is necessary to write such data to storage 621. Virtual memory compression increases the available size of memory 604 while reducing wear on storage 621.

[0082] Storage devices optimized for mobile electronic devices or mobile storage devices have traditionally included MMC solid-state memory devices (e.g., micro Secure Digital (microSD)TM ) card, etc.). MMC devices include many parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are usually removable and separate components from the host device. In contrast, eMMC TM The device is attached to the circuit board and is considered part of the host device, with read speeds comparable to Serial ATA based SSD devices. TM Serial AT (Advanced Technology) Attachment, or SATA, is comparable to SATA. However, the demand for performance in mobile devices continues to increase, such as to fully enable virtual or augmented reality devices and take advantage of ever-increasing network speeds. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including controllers and firmware) use a low-voltage differential signaling (LVDS) serial interface with dedicated read / write paths to communicate with host devices, further improving read / write speeds.

[0083] The instructions 624 may also be transmitted or received over the communication network 626 using a transmission medium via the network interface device 620 using any of a variety of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Exemplary communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network) such as defined by the Third Generation Partnership Project (3GPP) series of standards (e.g., 3G, 4G, 5G, Long Term Evolution (LTE), etc.), a plain old telephone (POTS) network, and a wireless data network (e.g., a wireless data network known as The invention also provides a method for transmitting data to the network 626. The method further includes the use of a plurality of communication channels, such as a communication channel, a communication channel, and a communication channel 627. The method further includes the use of a plurality of communication channels, such as a communication channel, a communication channel, and a communication channel 628. The method further includes the use of a plurality of communication channels, such as a communication channel, a communication channel, and a communication channel 629. The method further includes the use of a plurality of communication channels, such as a communication channel, a communication channel, and a communication channel 629. The method further includes the use of a plurality of communication channels, such as a communication channel, a communication channel, and a communication channel 629. The method further includes the use of a plurality of communication channels, such as a communication channel, a communication channel, and a communication channel 629. The method further includes the use of a plurality of communication channels, such as a communication channel, a communication channel, and a communication channel 629. The method further includes the use of a plurality of communication channels, such as a communication channel, a communication channel, and a communication channel 629.

[0084] Additional Examples:

[0085] Embodiment 1 is a memory device for accelerating the initialization of trimming of a memory device, the memory device comprising: an interface for receiving an accelerated trim command from a controller; and a processing circuit system for: starting the initialization of the memory device; prohibiting setting trimming in response to receiving the accelerated trimming command, the trimming being set by the controller; and completing the initialization of the memory device after the controller sets the trimming.

[0086] In embodiment 2, according to the subject matter of embodiment 1, the accelerated trim command is one of two types of accelerated trim commands, a first type being a partial type and a second type being a complete type.

[0087] In embodiment 3, the subject matter of embodiment 2 is according to which the accelerated trim command is of type complete, and wherein to inhibit setting trims, the processing circuitry is configured to inhibit setting all trims.

[0088] In embodiment 4, the subject matter of any one of embodiments 2 to 3, wherein the accelerated trim command is of a partial type, and wherein to inhibit setting trims, the processing circuitry is configured to inhibit setting a subset of all trims.

[0089] In embodiment 5, the subject matter of embodiment 4 wherein the subset of all prunes are prunes that are not specific to the memory device.

[0090] In embodiment 6, the subject matter of embodiment 5 wherein the processing circuitry is configured to load trim specific to the memory device.

[0091] In Example 7, according to the subject matter of any one of Examples 4 to 6, the interface is configured to: receive a second accelerated trim command from the controller, the second accelerated trim command being a partial type; and receive a third accelerated trim command in response to the controller failing to set the second trim; and wherein the processing circuit system is configured to: start a second initialization of the memory device; prohibit setting the second trim in response to receiving the second accelerated trim command; set the second trim in response to receiving the third accelerated trim command; and complete the second initialization of the memory device after setting the second trim.

[0092] In embodiment 8, the subject matter of any one of embodiments 1 to 7, wherein the interface is configured to receive an enable trim command from the controller to signal the controller that the trim has been set, and wherein the processing circuitry is configured to complete the initialization of the memory device after receiving the enable trim command.

[0093] In embodiment 9, the subject matter of any one of embodiments 1 to 8, wherein the interface is configured to receive a trimmed read command, and wherein the processing circuitry is configured to provide trimmed data stored on the memory device in response to receiving the trimmed read command.

[0094] In embodiment 10, the subject matter of embodiment 9 wherein the trim read command does not specify an address.

[0095] In embodiment 11, the subject matter of any one of embodiments 9-10, wherein an issuer of the trim read command is not able to address a location in the memory device where the trim data is stored.

[0096] Embodiment 12 is a method for accelerating the initialization of trimming of a memory device, the method comprising: starting the initialization of the memory device in a memory device; receiving an accelerated trim command from a controller in the memory device; prohibiting the setting of trim by the memory device in response to receiving the accelerated trim command, the trim being set by the controller; and completing the initialization of the memory device by the memory device after the controller sets the trim.

[0097] In embodiment 13, according to the subject matter of embodiment 12, the accelerated trim command is one of two types of accelerated trim commands, a first type being a partial type and a second type being a complete type.

[0098] In embodiment 14, the subject matter of embodiment 13, wherein the accelerated trim command is of type complete, and wherein prohibiting setting trims includes prohibiting setting all trims.

[0099] In embodiment 15, the subject matter of any one of embodiments 13 to 14, wherein the accelerated trim command is of a partial type, and wherein prohibiting setting trims comprises prohibiting setting a subset of all trims.

[0100] In embodiment 16, the subject matter of embodiment 15, wherein the subset of all prunes are prunes that are not specific to the memory device.

[0101] In embodiment 17, the subject matter of embodiment 16 includes loading, by the memory device, trims specific to the memory device.

[0102] In Example 18, according to the subject matter of any one of Examples 15 to 17, it includes: starting a second initialization of the memory device in the memory device; receiving a second accelerated trim command from the controller in the memory device, the second accelerated trim command being a partial type; prohibiting setting the second trim by the memory device in response to receiving the second accelerated trim command; receiving a third accelerated trim command by the memory device in response to the controller failing to set the second trim; setting the second trim by the memory device in response to receiving the third accelerated trim command; and completing the second initialization of the memory device by the memory device after setting the second trim.

[0103] In Example 19, the subject matter of any one of Examples 12 to 18, wherein completing the initialization of the memory device by the memory device after the controller sets the trim comprises receiving an enable trim command from the controller to signal the controller that the trim has been set.

[0104] In embodiment 20, the subject matter of any one of embodiments 12 to 19 includes: receiving, by the memory device, a trim read command; and providing trim data stored on the memory device in response to receiving the trim read command.

[0105] In embodiment 21, the subject matter of embodiment 20, wherein the trim read command does not specify an address.

[0106] In embodiment 22, the subject matter of any one of embodiments 20-21, wherein an issuer of the trim read command is not able to address a location in the memory device where the trim data is stored.

[0107] Embodiment 23 is a machine-readable medium comprising instructions for accelerating the initialization of trimming of a memory device, wherein the instructions, when executed by a processing circuit system, cause the processing circuit system to perform operations including: starting initialization of the memory device in a memory device; receiving an accelerated trim command from a controller in the memory device; prohibiting, by the memory device, setting trim in response to receiving the accelerated trim command, the trim being set by the controller; and completing the initialization of the memory device by the memory device after the controller sets the trim.

[0108] In embodiment 24, the subject matter according to embodiment 23, wherein the accelerated trim command is one of two types of accelerated trim commands, a first type being a partial type and a second type being a complete type.

[0109] In embodiment 25, the subject matter of embodiment 24, wherein the accelerated trim command is of type complete, and wherein prohibiting setting trims includes prohibiting setting all trims.

[0110] In embodiment 26, the subject matter of any one of embodiments 24-25, wherein the accelerated trim command is of a partial type, and wherein prohibiting setting trims comprises prohibiting setting a subset of all trims.

[0111] In embodiment 27, the subject matter of embodiment 26, wherein the subset of all prunes are prunes that are not specific to the memory device.

[0112] In embodiment 28, the subject matter of embodiment 27, wherein the operation comprises loading, by the memory device, trims specific to the memory device.

[0113] In Example 29, the subject matter according to any one of Examples 26 to 28 includes: starting a second initialization of the memory device in the memory device; receiving a second accelerated trim command from the controller in the memory device, the second accelerated trim command being a partial type; prohibiting setting the second trim by the memory device in response to receiving the second accelerated trim command; receiving a third accelerated trim command by the memory device in response to the controller failing to set the second trim; setting the second trim by the memory device in response to receiving the third accelerated trim command; and completing the second initialization of the memory device by the memory device after setting the second trim.

[0114] In embodiment 30, the subject matter of any one of embodiments 23 to 29, wherein completing the initialization of the memory device by the memory device after the controller sets the trim comprises receiving an enable trim command from the controller to signal the controller that the trim has been set.

[0115] In embodiment 31, the subject matter of any one of embodiments 23 to 30, wherein the operations include: receiving, by the memory device, a trim read command; and providing trim data stored on the memory device in response to receiving the trim read command.

[0116] In embodiment 32, the subject matter of embodiment 31, wherein the trim read command does not specify an address.

[0117] In embodiment 33, the subject matter of any one of embodiments 31-32, wherein an issuer of the trim read command is not able to address a location in the memory device where the trim data is stored.

[0118] Embodiment 34 is a system for accelerating the initialization of trimming of a memory device, the system comprising: a device for starting the initialization of the memory device in a memory device; a device for receiving an accelerated trim command from a controller in the memory device; a device for prohibiting the setting of trim by the memory device in response to receiving the accelerated trim command, the trim being set by the controller; and a device for completing the initialization of the memory device by the memory device after the controller sets the trim.

[0119] In embodiment 35, the subject matter according to embodiment 34, wherein the accelerated trim command is one of two types of accelerated trim commands, a first type being a partial type and a second type being a complete type.

[0120] In Example 36, the subject matter of Example 35 wherein the accelerated trim command is of type complete, and wherein the means for inhibiting setting trims comprises means for inhibiting setting all trims.

[0121] In Example 37, the subject matter of any one of Examples 35 to 36, wherein the accelerated trim command is of a partial type, and wherein the means for inhibiting setting a trim comprises means for inhibiting setting a subset of all trims.

[0122] In embodiment 38, the subject matter of embodiment 37, wherein the subset of all prunes are prunes that are not specific to the memory device.

[0123] In embodiment 39, the subject matter of embodiment 38 includes loading, by the memory device, trims specific to the memory device.

[0124] In Example 40, according to the subject matter of any one of Examples 37 to 39, it includes: a device for starting a second initialization of the memory device in the memory device; a device for receiving a second accelerated trim command from the controller in the memory device, the second accelerated trim command being a partial type; a device for prohibiting the memory device from setting the second trim in response to receiving the second accelerated trim command; a device for the memory device to receive a third accelerated trim command in response to the controller failing to set the second trim; a device for the memory device to set the second trim in response to receiving the third accelerated trim command; and a device for the memory device to complete the second initialization of the memory device after setting the second trim.

[0125] In Example 41, the subject matter of any one of Examples 34 to 40, wherein the means for completing the initialization of the memory device by the memory device after the controller sets the trim includes means for receiving an enable trim command from the controller to signal the controller that the trim has been set.

[0126] In embodiment 42, the subject matter of any one of embodiments 34 to 41 includes: means for receiving a trim read command by the memory device; and means for providing trim data stored on the memory device in response to receiving the trim read command.

[0127] In embodiment 43, the subject matter of embodiment 42, wherein the trim read command does not specify an address.

[0128] In embodiment 44, the subject matter of any one of embodiments 42 to 43, wherein an issuer of the trim read command is not able to address a location in the memory device where the trim data is stored.

[0129] Embodiment 45 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any one of embodiments 1-44.

[0130] Embodiment 46 is an apparatus comprising means for performing any one of embodiments 1-44.

[0131] Embodiment 47 is a system for implementing any one of embodiments 1 to 44.

[0132] Example 48 is a method for implementing any one of Examples 1 to 44.

[0133] The above detailed description includes reference to the accompanying drawings that form a part of the detailed description. The accompanying drawings show specific embodiments in which the present invention can be put into practice by way of illustration. These embodiments are also referred to as "embodiments" herein. Such embodiments may also include elements other than those shown or described. However, the present inventors have also contemplated embodiments that only provide those elements shown or described. In addition, the present inventors have also contemplated examples of any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0134] In this document, as is common in patent documents, the terms "a" or "an" are used to include one or more than one, independent of any other examples or usages of "at least one" or "one or more." In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "A or B" may include "A but not B," "B but not A," and "A and B." In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Moreover, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include elements other than those listed after such terms in the claim are still deemed to fall within the scope of the claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0135] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" refers to any type of computing circuitry, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuitry, including a group of processors or a multi-core device.

[0136] The terms "wafer" and "substrate" are generally used herein to refer to any structure on which an integrated circuit is formed, and also to refer to such structures during the various stages of integrated circuit fabrication. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

[0137] Various embodiments according to the present disclosure and described herein include memories utilizing a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, directional adjectives will be employed relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure will be considered to extend away from the substrate surface, a bottom end of the vertical structure will be considered to be the end closest to the substrate surface, and a top end of the vertical structure will be considered to be the end farthest from the substrate surface).

[0138] As used herein, operating a memory cell includes reading, writing, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming" and can include writing to a memory cell or erasing from a memory cell (e.g., a memory cell can be programmed to an erased state).

[0139] According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, controller, firmware, etc.) located inside or outside a memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adjust, derive, define, utilize, modify, apply, etc.) the number of wear cycles or the wear state (e.g., record wear cycles, count operations occurring in the memory device, track operations initiated by the memory device, evaluate memory device characteristics corresponding to the wear state, etc.).

[0140] According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to a memory device during each memory operation. Memory device control circuitry (e.g., control logic) may be programmed to compensate for memory device performance variations corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0141] The method examples described herein may be implemented at least in part with a machine or computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions, which are operable to configure an electronic device to perform the method as described in the above examples. The implementation scheme of such methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for executing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical disks and digital video disks), tapes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSDs), universal flash memory (UFS) devices, embedded MMC (eMMC) devices, etc.

[0142] The above description is intended to be illustrative and not restrictive. For example, the above embodiments (or one or more aspects thereof) can be used in combination with each other. Other embodiments may be used by those of ordinary skill in the art when viewing the above description. It should be understood at the time of submission that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above specific embodiments, various features can be combined together to simplify the present disclosure. This should not be interpreted as intending that the disclosed functions that are not claimed for protection are essential to any claim. On the contrary, the subject matter of the invention may lie in less than all the features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated into the specific embodiments, wherein each claim is independently a separate embodiment, and it is expected that such embodiments can be combined with each other in various combinations or arrangements. Therefore, the scope of the present invention should be determined with reference to the full scope of the appended claims and the equivalents of such claims.

Claims

1. A memory device for accelerating memory device trim initialization, the memory device comprising: an interface for receiving an accelerated trim command from a memory controller; and Processing circuitry for: initiating initialization of the memory device, the initialization of the memory device comprising an initial trim load of the memory device; disabling, in response to receiving the accelerated trim command, setting of a first trim by an array controller, the first trim being set by the memory controller, wherein the memory device would have set the first trim as part of the initial trim load had the accelerated trim command not been received; receiving an enable trim command from the memory controller after the memory controller sets the first trim; as well as After receiving the enable trim command, completing the initialization of the memory device, the initialization including setting, by the array controller, a second trim, the second trim being set as part of completing the initial trim load to complete the initialization of the memory device. 2 . The memory device of claim 1 , wherein the accelerated trim command is a partial type accelerated trim command rather than a full type trim command. 3 . The memory device of claim 2 , wherein to disable setting of trims, the processing circuitry is configured to disable setting of a subset of all trims.

4. The memory device of claim 3, wherein the subset of all prunes are prunes that are not specific to the memory device, and wherein the prunes that are not specific to the memory device comprise variable prunes that can change over time.

5. The memory device of claim 4, wherein the processing circuitry is configured to load trim specific to the memory device, and wherein the trim specific to the memory device comprises a trim determined for the memory device at manufacturing time.

6. The memory device of claim 3 , wherein the interface is configured to: receiving a second accelerated trim command from the memory controller, the second accelerated trim command being of a partial type; and receiving a third accelerated trim command in response to the memory controller failing to set a third trim; and wherein the processing circuitry is configured to: Initiating a second initialization of the memory device; inhibiting setting the second trim in response to receiving the second accelerated trim command; setting the third trim in response to receiving the third accelerated trim command; and The second initialization of the memory device is completed after setting the third trim. 7 . The memory device of claim 1 , wherein the interface is configured to receive a trimmed read command, and wherein the processing circuitry is configured to provide trimmed data stored on the memory device in response to receiving the trimmed read command.

8. The memory device of claim 7, wherein the trim read command does not specify an address.

9. The memory device of claim 7, wherein an issuer of the trim read command is not able to address a location in the memory device where the trim data is stored.

10. A method for accelerating memory device trim initialization, the method comprising: initiating, at a memory device, initialization of the memory device, the initialization of the memory device comprising an initial trim load of the memory device; receiving, at the memory device, an accelerated trim command from a memory memory controller; disabling, by the memory device in response to receiving the accelerated trim command, setting of a first trim by an array controller, the first trim being set by the memory controller, wherein the memory device would have set the first trim as part of the initial trim load if the accelerated trim command had not been received; receiving an enable trim command from the memory controller after the memory controller sets the first trim; as well as After receiving the enable trim command, the memory device completes the initialization of the memory device, the initialization including setting, by the array controller, a second trim, the second trim being set as part of completing the initial trim load, to complete the initialization of the memory device. The method of claim 10 , wherein the accelerated trim command is a partial type accelerated trim command rather than a full type trim command. The method of claim 11 , wherein disabling setting of prunes comprises disabling setting of a subset of all prunes.

13. The method of claim 12, wherein the subset of all prunes are prunes that are not specific to the memory device, and wherein the prunes that are not specific to the memory device comprise variable prunes that can change over time.

14. The method of claim 13, comprising loading, by the memory device, trimming specific to the memory device, wherein the trimming specific to the memory device comprises trimming determined for the memory device at a time of manufacture.

15. The method according to claim 12, comprising: initiating, at the memory device, a second initialization of the memory device, the initialization of the memory device comprising an initial trim load of the memory device; receiving, at the memory device, a second accelerated trim command from the memory controller, the second accelerated trim command being of a partial type, wherein the memory device would set the first trim as a partial of the initial trim load if the accelerated trim command had not been received; inhibiting, by the memory device, setting a second trim in response to receiving the second accelerated trim command; receiving, by the memory device, a third accelerated trim command in response to the memory controller failing to set the second trim; setting, by the memory device, the second trim in response to receiving the third accelerated trim command; as well as The second initialization of the memory device is completed by the memory device after setting the second trim, which is set as part of completing the initial trim load to complete the initialization of the memory device.

16. The method according to claim 10, comprising: receiving, by the memory device, a trim read command; and Trim data stored on the memory device is provided in response to receiving the trim read command. The method of claim 16 , wherein the trim read command does not specify an address.

18. The method of claim 16, wherein an issuer of the trim read command is not able to address a location in the memory device where the trim data is stored.

19. A machine-readable medium comprising instructions which, when executed by circuitry, cause the circuitry to perform the method of any one of claims 10 to 18.

20. A system comprising means for performing the method according to any one of claims 10 to 18.

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