Display device and method for manufacturing the same

Abstract

According to an exemplary embodiment of the present invention, there is provided a display device and a method of manufacturing the display device. The display device includes: a substrate; a display element layer provided with a plurality of light-emitting elements; a packaging layer covering the plurality of light-emitting elements; a first conductive layer disposed on the packaging layer and including a plurality of first conductive patterns; a first insulating layer disposed on the packaging layer to cover the plurality of first conductive patterns; a second conductive layer disposed on the first insulating layer and including a plurality of first sensing patterns, a plurality of second conductive patterns electrically connecting the plurality of first sensing patterns, and a plurality of second sensing patterns electrically connected through the plurality of first conductive patterns; a second insulating layer disposed on the first insulating layer and the second conductive layer without overlapping the plurality of light-emitting elements to cover the second conductive layer; and a light-shielding layer covering the second insulating layer. The light-shielding layer and the second insulating layer are in contact with the first insulating layer.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2019-0008688, filed on Jan. 23, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a display device, and more particularly, to a display device and a method of manufacturing the same. Background Art

[0003] Various display devices have been developed for use in multimedia devices such as televisions, mobile phones, tablet computers, navigation units, and game consoles.

[0004] A display device includes a display panel for displaying an image and an input sensing unit for sensing an external input. The display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the plurality of scan lines and the plurality of data lines. In addition, the display device includes a display area for displaying an image and a non-display area disposed adjacent to the display area. In addition, the input sensing unit includes a plurality of detection sensors and a plurality of sensing signal lines connected to the detection sensors. Summary of the Invention

[0005] The present disclosure provides a display device including an input sensing unit having improved sensing reliability and a method of manufacturing the display device.

[0006] According to an exemplary embodiment of the present invention, a display device includes: a substrate base on which a display area and a non-display area are defined, the display area including a plurality of pixel areas and a light-shielding area disposed adjacent to the plurality of pixel areas, the non-display area being disposed adjacent to the display area; a display element layer disposed on the substrate base and including a pixel defining layer and a plurality of light-emitting elements, the pixel defining layer having a plurality of light-emitting openings respectively overlapping the plurality of pixel areas, the plurality of light-emitting elements respectively overlapping the plurality of light-emitting openings; a packaging layer covering the plurality of light-emitting elements; a first conductive layer disposed on the packaging layer and including a plurality of first conductive patterns; a first insulating layer disposed on the packaging layer to cover the plurality of first conductive patterns; a second conductive layer disposed on the first insulating layer and including a plurality of first sensing patterns, a plurality of second conductive patterns electrically connecting the plurality of first sensing patterns, and a plurality of second sensing patterns electrically connected through the plurality of first conductive patterns; a second insulating layer disposed on the first insulating layer and the second conductive layer without overlapping the plurality of light-emitting elements to cover the second conductive layer; and a light-shielding layer disposed on the same layer as the second insulating layer to cover the second insulating layer and overlapping the light-shielding area.

[0007] According to an exemplary embodiment of the present invention, a display device includes: a substrate base including a display area and a non-display area disposed adjacent to the display area; a display element layer disposed on the substrate base, and a plurality of pixel areas overlapping with the display area are defined in the display element layer, wherein the display element layer includes a plurality of display elements respectively overlapping with the plurality of pixel areas; a packaging layer disposed on the display element layer; a plurality of first conductive patterns disposed on the packaging layer; a first insulating layer covering the plurality of first conductive patterns; a plurality of second conductive patterns disposed on the first insulating layer; a second insulating layer covering the plurality of second conductive patterns; and a light-shielding layer covering the second insulating layer. Each of the second insulating layer and the light-shielding layer is in contact with the first insulating layer. The light-shielding layer includes a plurality of openings, and each opening overlaps with a corresponding one of the plurality of display elements. The second insulating layer covers the plurality of second conductive patterns without overlapping with the plurality of openings.

[0008] According to an exemplary embodiment of the present invention, a method of manufacturing a display device includes: providing a display panel including a substrate base, a display element layer disposed on the substrate base, and a packaging layer disposed on the display element layer, the display element layer having display elements; forming a plurality of first conductive patterns on the packaging layer; forming a first insulating layer on the plurality of first conductive patterns; forming a plurality of second conductive patterns on the first insulating layer; forming a second insulating layer to cover the plurality of second conductive patterns without overlapping with the display elements; and forming a light-shielding layer to cover the second insulating layer without overlapping with the display elements. Each of the second insulating layer and the light-shielding layer is in contact with the first insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other features of the inventive concept will become more apparent by referring to the exemplary embodiments of the inventive concept described in detail with reference to the drawings, in which:

[0010] Figure 1 is a perspective view showing a display device according to an embodiment of the inventive concept;

[0011] Figure 2 is a cross-sectional view showing a display module according to an embodiment of the inventive concept;

[0012] Figure 3A is a plan view showing a display panel according to an embodiment of the inventive concept;

[0013] Figure 3B is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept;

[0014] Figure 3C is a cross-sectional view showing a part of a display panel according to an embodiment of the inventive concept;

[0015] Figure 4is a cross-sectional view showing an input sensing unit according to an embodiment of the inventive concept;

[0016] Figure 5 is a plan view showing an input sensing unit according to an embodiment of the inventive concept;

[0017] Figures 6A to 6D is a plan view showing an input sensing unit according to an embodiment of the inventive concept;

[0018] Figure 7A shows Figure 6C an enlarged view of region AA in;

[0019] Figure 7B shows Figure 7A an enlarged view of region BB in;

[0020] Figure 8 is a cross-sectional view taken along line I-I' in according to an embodiment of the inventive concept; Figure 7A in;

[0021] Figure 9A is a cross-sectional view taken along line II-II' in according to an embodiment of the inventive concept; Figure 7A in;

[0022] Figure 9B is a partial cross-sectional view showing a display panel according to an embodiment of the inventive concept; and

[0023] Figure 10 is a cross-sectional view showing a display device according to another embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] In this specification, it will also be understood that when a component (or region, layer, part) is referred to as being "on" another component, "connected to" or "coupled to" another component, the one component may be directly disposed on the other component, directly connected to / coupled to the other component, or there may also be an intervening third component.

[0025] Like reference numerals always denote like elements. Also, in the figures, for clarity of illustration, the thickness, ratios, and dimensions of components are exaggerated.

[0026] The term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0027] It will be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one component from other components. For example, an element referred to as the first element in one embodiment may be referred to as the second element in another embodiment without departing from the scope of the claims. Terms in the singular form may include the plural form unless there is a contrary indication.

[0028] In addition, terms such as "under", "below", "above", "on", etc. are used to explain the association relationship of components shown in the drawings. The terms may be relative concepts and are described based on the directions shown in the drawings.

[0029] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. Terms defined in a general dictionary should be interpreted as having the same meaning as in the context of the relevant technology, and unless clearly defined in the description, the terms are not ideally or overly interpreted as having a formal meaning.

[0030] The meaning of "comprising" or "including" describes the nature, fixed quantity, steps, operations, elements, components, or combinations thereof, but does not exclude other natures, fixed quantities, steps, operations, elements, components, or combinations thereof.

[0031] Hereinafter, embodiments of the inventive concept will be described with reference to the drawings.

[0032] Figure 1 is a perspective view showing a display device according to an embodiment of the inventive concept. Figure 2 is a cross-sectional view showing a display module according to an embodiment of the inventive concept.

[0033] Referring to Figure 1 , the display device DD may display an image IM through a display surface DD-IS. As an example of the image IM, a clock display window and application icons are shown. The display surface DD-IS includes a display area DD-DA for displaying the image IM and a non-display area DD-NDA disposed adjacent to the display area DD-DA. The non-display area DD-NDA is an area where no image is displayed.

[0034] For example, the non-display area DD-NDA may surround the display area DD-DA. However, embodiments of the inventive concept are not limited thereto. For example, according to an embodiment, the non-display area DD-NDA may be disposed adjacent to only a part of the display area DD-DA or may be omitted.

[0035] The display surface DD-IS may have a shape extending in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The normal direction of the display surface DD-IS (i.e., the thickness direction of the display device DD) may represent a third direction DR3. In this specification, expressions such as "when viewed from a plane", "on a plane", or "area (region) on a plane" may represent the situation when viewed from the third direction DR3. Hereinafter, the front surface (or top surface) and the rear surface (or bottom surface) of each of the plurality of layers or the plurality of units may be distinguished from each other in the third direction DR3. However, the directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and may be marked differently as shown in Figure 1 and Figure 2 .

[0036] According to an embodiment of the inventive concept, although the display device DD has a display surface DD-IS in a rectangular shape, the embodiment of the inventive concept is not limited thereto. For example, the display device DD may include a three-dimensional display surface or a display surface having a curved shape in part on a plane. The three-dimensional display surface may include a plurality of display regions indicating different directions from each other. For example, the three-dimensional display surface may include a polygonal columnar display surface.

[0037] According to an embodiment of the inventive concept, the display device DD may be a flexible display device. However, the embodiment of the inventive concept is not limited thereto. For example, the display device DD according to an embodiment of the inventive concept may be a rigid display device. In an embodiment, a display device DD applicable to a mobile terminal is exemplarily shown. Although not shown, an electronic module, a camera module, and a power module mounted on a main board may be provided together with the display device DD on a bracket / case to constitute a mobile phone terminal. The display device DD according to an embodiment of the inventive concept can be used in large-sized electronic devices such as televisions and monitors, and medium- and small-sized electronic devices such as tablet computers, vehicle navigation units, game consoles, and smart watches.

[0038] Referring to Figure 2 , the display device DD may include a display module DM that displays an image and detects an external input. The display module DM may include a display panel DP and an input sensing unit ISU.

[0039] According to an embodiment of the inventive concept, the display panel DP may include an organic light-emitting display panel, a liquid crystal display panel, or a quantum dot light-emitting display panel. However, the embodiment of the inventive concept is not limited thereto. The organic light-emitting display panel includes organic light-emitting elements. The liquid crystal display panel includes liquid crystal molecules. The quantum dot light-emitting display panel includes quantum dots or quantum rods.

[0040] Hereinafter, a display panel DP according to an embodiment of the inventive concept will be described as an organic light-emitting display panel. However, the inventive concept is not limited thereto. For example, according to an embodiment, the inventive concept of the present invention can be applied to various display panels.

[0041] The display panel DP includes a substrate base SUB, a circuit element layer DP-CL, a display element layer DP-OLED, and an insulating layer ECL. The display panel DP includes a display area DP-DA and a non-display area DP-NDA. The display area DP-DA and the non-display area DP-NDA of the display panel DP may be respectively superimposed on Figure 1 the display area DP-DA and the non-display area DP-NDA of the display device DD described in. The non-display area DP-NDA may be provided at one side of the display area DP-DA or may be omitted.

[0042] The substrate base SUB may support all components of the display panel DP and the input sensing unit ISU, and may include a flexible material. For example, the substrate base SUB may include a plastic substrate, a glass substrate, or an organic / inorganic composite substrate. In addition, the substrate base SUB may be a stacked structure including a plurality of insulating layers. The plastic substrate may include at least one selected from the group consisting of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, silicone resins, polyimide resins, polyamide resins, and perylene resins.

[0043] The circuit element layer DP-CL may include a semiconductor layer, a plurality of insulating layers, and a plurality of conductive layers. The plurality of conductive layers of the circuit element layer DP-CL may constitute a control circuit or signal lines of a pixel.

[0044] The display element layer DP-OLED is disposed on the substrate base SUB while being superimposed on the display area DP-DA. The display element layer DP-OLED may include display elements, for example, organic light-emitting diodes. However, embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, the display element layer DP-OLED may include inorganic light-emitting diodes or organic-inorganic hybrid light-emitting diodes according to the type of the display panel DP.

[0045] The insulating layer ECL may seal the display element layer DP-OLED. For example, the insulating layer ECL may be superimposed on each of the display area DP-DA and the non-display area DP-NDA, or may be superimposed on the display area DP-DA without being superimposed on the non-display area DP-NDA.

[0046] According to an embodiment, the insulating layer ECL may be provided as a thin film encapsulation layer and may include at least one insulating layer. The insulating layer ECL may also be referred to as an encapsulation layer. The insulating layer ECL according to an embodiment of the inventive concept may include at least one organic encapsulation layer and at least one inorganic encapsulation layer.

[0047] The inorganic encapsulation layer of the insulating layer ECL may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation layer of the insulating layer ECL may be used to protect the display element layer DP-OLED from foreign substances such as dust particles. Although the inorganic encapsulation layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, the organic encapsulation layer may include an acrylic organic layer. However, embodiments of the inventive concept are not limited thereto.

[0048] Although not shown, according to an embodiment, the insulating layer ECL may be an encapsulation substrate. The insulating layer ECL may be used to protect the display element layer DP-OLED from foreign substances such as moisture, oxygen, and dust particles. The insulating layer ECL may be bonded to the substrate base SUB through a sealant.

[0049] The input sensing unit ISU may detect an input applied from the outside. The input applied from the outside may be provided in various types. For example, the external input may include various types of external inputs generated by a part of the user's body, a stylus, light, heat, or pressure. In addition, in addition to the input generated by contact with a part of the human body such as the user's hand, spatial touch (e.g., hovering) generated by proximity or nearness may be a type of input.

[0050] According to an embodiment of the inventive concept, the input sensing unit ISU may be directly provided on the display panel DP. In this specification, the expression "component A is directly provided on component B" means that there is no intermediate layer such as an adhesive layer between component A and component B, such that component A and component B touch or contact each other. The input sensing unit ISU may be manufactured together with the display panel DP through a continuous process. That is, the input sensing unit ISU may be directly formed on the insulating layer ECL through a continuous process. In an exemplary embodiment, the input sensing unit ISU may be in contact with the display panel DP.

[0051] Figure 3A is a plan view of a display panel according to an embodiment of the inventive concept. Figure 3B is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept. Figure 3C is a cross-sectional view showing a part of a display panel according to an embodiment of the inventive concept.

[0052] Refer to Figure 3A, the display panel DP includes a scan driving circuit GDV, a plurality of signal lines SGL, a plurality of pixels PX, and a plurality of driving pads (pads, or also known as "bonding pads") PD. The area where a plurality of pixels PX are provided is defined as a display area DP-DA.

[0053] The scan driving circuit GDV can generate a plurality of scan signals and can sequentially output the plurality of scan signals to a plurality of scan lines. The scan driving circuit GDV can also output other control signals to the driving circuit of each pixel PX.

[0054] The plurality of signal lines SGL include scan lines SL, data lines DL, power lines PL, and control signal lines CSL.

[0055] The scan lines SL are respectively connected to the corresponding pixels PX among the plurality of pixels PX, and the data lines DL are respectively connected to the corresponding pixels PX among the plurality of pixels PX. The power lines PL are connected to the plurality of pixels PX. In addition, the scan driving circuit GDV connected to the scan lines SL can be provided in a non-display area DP-NDA. The control signal line CSL can provide a control signal to the scan driving circuit GDV.

[0056] A part of the scan lines SL, data lines DL, power lines PL, and control signal lines CSL can be provided on the same layer, while another part can be provided on different layers. When the signal lines provided on the first layer among the scan lines SL, data lines DL, power lines PL, and control signal lines CSL are defined as first signal lines, the signal lines provided on the second layer can be defined as second signal lines. The signal lines provided on the third layer can be defined as third signal lines. The first layer, the second layer, and the third layer can be different layers.

[0057] The display panel DP includes a plurality of driving pads PD electrically connected to the data lines DL, power lines PL, and control signal lines CSL. The driving pads PD overlap with the non-display area DP-NDA.

[0058] Refer to Figure 3B , an exemplary pixel PX connected to one scan line SL, one data line DL, and a power line PL is shown. However, the embodiments of the inventive concept are not limited to this configuration of the pixel PX. For example, the pixel PX can have various configurations.

[0059] The pixel PX includes a pixel circuit PXC and an organic light-emitting element ED including a first electrode AE and a second electrode CE. The pixel PX includes the organic light-emitting element ED as a display element.

[0060] The organic light-emitting element ED can be included in Figure 2 the display element layer DP-OLED of. The organic light-emitting element ED can be a front-emitting diode or a back-emitting diode.

[0061] The pixel circuit PXC, which is a circuit section for driving the organic light-emitting element ED, includes a first transistor T1 (or switching transistor), a second transistor T2 (or driving transistor), and a capacitor Cap. The pixel circuit PXC may be included in Figure 2 the circuit element layer DP-CL in

[0062] The organic light-emitting element ED can generate light by the electrical signals provided from the first transistor T1 and the second transistor T2.

[0063] The first transistor T1 can output the data signal applied to the data line DL in response to a scan signal applied to the scan line SL. The capacitor Cap can be charged with a voltage corresponding to the data signal received from the first transistor T1. The first power supply voltage ELVDD is provided to the first electrode AE through the second transistor T2, and the second power supply voltage ELVSS is provided to the second electrode CE. The second power supply voltage ELVSS can be less than the first power supply voltage ELVDD.

[0064] The second transistor T2 is electrically connected to the first electrode AE of the organic light-emitting element ED. The second transistor T2 can control the driving current ID flowing through the organic light-emitting element ED corresponding to the amount of electric charge stored in the capacitor Cap. The organic light-emitting element ED can emit light during the on-period of the second transistor T2.

[0065] Referring to Figure 3C , a partial cross-section corresponding to the equivalent circuit in Figure 3B of the display panel DP is shown. The circuit element layer DP-CL, the display element layer DP-OLED, and the insulating layer ECL are sequentially provided on the substrate base SUB.

[0066] The circuit element layer DP-CL may include at least one insulating layer and at least one circuit element. The circuit element may include signal lines and a driving circuit of the pixel PX. The circuit element layer DP-CL can be formed by processes of forming insulating layers, semiconductor layers, and conductive layers by coating, deposition, etc., and processes of patterning the insulating layers, semiconductor layers, and conductive layers by photolithography processes.

[0067] The circuit element layer DP-CL includes a buffer layer BFL as an inorganic layer, a first intermediate inorganic layer 10, a second intermediate inorganic layer 20, and an intermediate organic layer 30 as an organic layer. The buffer layer BFL may include a plurality of stacked inorganic layers. Figure 3CExemplarily, the layout relationship among a first semiconductor pattern OSP1, a second semiconductor pattern OSP2, a first control electrode GE1, a second control electrode GE2, a first input electrode DE1, a first output electrode SE1, a second input electrode DE2, and a second output electrode SE2 is shown. The first semiconductor pattern OSP1, the first control electrode GE1, the first input electrode DE1, and the first output electrode SE1 constitute a switching transistor T1. The second semiconductor pattern OSP2, the second control electrode GE2, the second input electrode DE2, and the second output electrode SE2 constitute a driving transistor T2. Also exemplarily shown are a first via hole CH1, a second via hole CH2, a third via hole CH3, and a fourth via hole CH4.

[0068] The display element layer DP-OLED includes an organic light-emitting diode OLED and a pixel defining layer PDL. The organic light-emitting diode OLED corresponds to Figure 3B the organic light-emitting element ED in

[0069] The first electrode AE is disposed on an intermediate organic layer 30 (hereinafter referred to as a "planarization layer"). The first electrode AE is connected to the second output electrode SE2 through a fifth contact hole CH5 passing through the planarization layer.

[0070] According to an embodiment of the inventive concept, a light-emitting opening OM is defined in the pixel defining layer PDL. The light-emitting opening OM of the pixel defining layer PDL exposes at least a part of the first electrode AE.

[0071] Although not shown separately, a spacer overlapping with a part of the pixel defining layer PDL may be disposed on the top surface of the pixel defining layer PDL. The spacer may be integral with the pixel defining layer PDL or may be an insulating structure provided by an additional process.

[0072] The display area DP-DA of the display panel DP may include a plurality of light-emitting areas OPA and non-light-emitting areas NPA disposed adjacent to the light-emitting areas OPA. The display element layer DP-OLED overlapping with the display area DP-DA may include light-emitting areas OPA and non-light-emitting areas NPA disposed adjacent to the light-emitting areas OPA. For example, the non-light-emitting areas NPA may surround the light-emitting areas OPA. In an embodiment, each light-emitting area OPA may be formed in a region corresponding to a partial region of the first electrode AE, and the partial region is exposed by the light-emitting opening OM.

[0073] The hole control layer HCL may be disposed in both the light-emitting region OPA and the non-light-emitting region NPA. The hole control layer HCL may include a hole transport layer and a hole injection layer. The light-emitting layer EML is disposed on the hole control layer HCL. The light-emitting layer EML is disposed in a region corresponding to the light-emitting opening OM. That is, the light-emitting layer EML may be divided and disposed in each pixel PX. The light-emitting layer EML may include an organic material and / or an inorganic material. The light-emitting layer EML may generate colored light having a predetermined color.

[0074] The electron control layer TCL is disposed on the light-emitting layer EML. The electron control layer TCL may include an electron transport layer and an electron injection layer. The hole control layer HCL and the electron control layer TCL may be provided for a plurality of pixels PX by using an opening mask. In an exemplary embodiment, each of the hole control layer HCL and the electron control layer TCL may be formed continuously such that portions of the formation of the hole control layer HCL in the plurality of pixels PX may be connected to each other, and portions of the formation of the electron control layer TCL in the plurality of pixels PX may be connected to each other. The second electrode CE is disposed on the electron control layer TCL. The second electrode CE is disposed on the electron control layer TCL included in each of the plurality of pixels PX and has an integral shape.

[0075] The insulating layer ECL is disposed on the second electrode CE. The insulating layer ECL may be provided as a single encapsulation layer or a plurality of thin films. Hereinafter, the insulating layer ECL will be described as an encapsulation layer.

[0076] Figure 4 is a cross-sectional view showing an input sensing unit ISU according to an embodiment of the inventive concept.

[0077] Referring to Figure 4 , the input sensing unit ISU includes a first conductive layer IS-CL1, a first insulating layer IS-IL1, a second conductive layer IS-CL2, and a second insulating layer IS-IL2 disposed on the insulating layer ECL. The first conductive layer IS-CL1 is directly disposed on the insulating layer ECL.

[0078] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a single-layer structure or a multi-layer structure, and the multi-layer structure includes a plurality of layers stacked in a third direction DR3. The multi-layer structure may include at least two of a plurality of transparent conductive layers and a plurality of metal layers. The metal layers may include different metals from each other. The transparent conductive layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT:PSS (poly(3,4-ethylenedioxythiophene):polystyrene sulfonate), metal nanowires, and graphene. The metal layer may include at least one of molybdenum, silver, titanium, copper, aluminum, and their alloys. In an exemplary embodiment, each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a three-layer metal layer structure, for example, a three-layer structure of titanium / aluminum / titanium.

[0079] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may include a plurality of conductive patterns. Hereinafter, it is assumed that the first conductive layer IS-CL1 includes a first conductive pattern and the second conductive layer IS-CL2 includes a second conductive pattern. According to an embodiment of the inventive concept, the conductive patterns disposed on the same layer may be formed by the same process, may include the same material, and may have the same stacked structure.

[0080] Each of the first conductive pattern and the second conductive pattern may include a sensing pattern and a sensing signal line connected to the sensing pattern. The sensing pattern may have a grid shape that overlaps with the non-light-emitting area NPA in Figure 3C and does not overlap with the light-emitting area OPA in Figure 3C . Additionally, the sensing pattern may be transparent and may overlap with the light-emitting area OPA and the non-light-emitting area NPA.

[0081] Each of the first insulating layer IS-IL1 and the second insulating layer IS-IL2 may include an inorganic material or an organic material. According to an embodiment of the inventive concept, each of the first insulating layer IS-IL1 and the second insulating layer IS-IL2 may be an organic layer including an organic material. The organic layer may include at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, silicone resins, polyimide resins, polyamide resins, and perylene resins.

[0082] However, the embodiments of the inventive concept are not limited thereto. For example, each of the first insulating layer IS-IL1 and the second insulating layer IS-IL2 may be an inorganic layer including an inorganic material. In this case, the inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, oxynitride, zirconium oxide, and hafnium oxide.

[0083] According to an embodiment of the inventive concept, the input sensing unit ISU may detect an external input by a capacitive method. For example, the input sensing unit ISU may calculate coordinate information of the external input based on a change in capacitance between second conductive patterns included in the second conductive layer IS-CL2.

[0084] Here, a parasitic capacitance may be generated between the first conductive pattern and the second conductive pattern in the third direction DR3. In addition, a parasitic capacitance may be generated between the second conductive layer IS-CL2 and the second electrode CE of the display element layer DP-OLED (refer to 3C).

[0085] The parasitic capacitance affects the capacitance between the second conductive patterns, and thus reduces the overall reliability of the input sensing unit ISU. For example, as the distance between the first conductive pattern and the second conductive pattern or the distance between the second conductive layer IS-CL2 and the display element layer DP-OLED decreases, the magnitude of the parasitic capacitance increases.

[0086] According to an embodiment of the inventive concept, compared to a typical invention, the input sensing unit ISU may have an increased distance between the first conductive layer IS-CL1 and the second conductive layer IS-CL2 in the third direction DR3. Accordingly, the parasitic capacitance between the first conductive layer IS-CL1 and the second conductive layer IS-CL2 or the parasitic capacitance between the second conductive layer IS-CL2 and the display element layer DP-OLED may be reduced in magnitude.

[0087] In an exemplary embodiment, in the third direction DR3, the thickness of the first insulating layer IS-IL1 may be greater than the thickness of the second insulating layer IS-IL2. As the thickness of the first insulating layer IS-IL1 increases, the distance between the first conductive pattern and the second conductive pattern in the third direction DR3 increases, thereby reducing the magnitude of the parasitic capacitance.

[0088] In an exemplary embodiment, the thickness of the first insulating layer IS-IL1 increases, but the overall thickness of the display device DD may not be changed, or the overall thickness of the display device DD may have a thickness increase smaller than the thickness increase of the first insulating layer IS-IL1. This will be described in more detail with reference to 8 later.

[0089] Figure 5 is a plan view showing an input sensing unit ISU according to an embodiment of the inventive concept. Figures 6A to 6D is a plan view showing an input sensing unit according to an embodiment of the inventive concept.

[0090] Refer to Figure 5, the input sensing unit ISU includes a plurality of first sensor parts, a plurality of second sensor parts, a plurality of sensing signal lines, a first pad part PD1, and a second pad part PD2.

[0091] The input sensing unit ISU includes an active area AR and a non-active area NAR disposed adjacent to the active area AR. The active area AR may correspond to Figure 3A the display area DP-DA in Figure 3A and the non-active area NAR may correspond to

[0092] the non-display area DP-NDA in

[0093] Each of the first sensor parts may have a shape arranged along a first direction DR1 and extending along a second direction DR2. Each of the first sensor parts may include a plurality of first sensing patterns SP1 and a plurality of first connection patterns CP1 connecting the first sensing patterns SP1.

[0094] Each of the first sensing pattern SP1 and the first connection pattern CP1 may have a mesh shape in which a plurality of mesh openings are defined. The first sensing pattern SP1 and the first connection pattern CP1 are arranged along the second direction DR2. Each of the first connection patterns CP1 connects two adjacent first sensing patterns SP1 among the first sensing patterns SP1.

[0095] Each of the second sensor parts may have a shape extending along the first direction DR1 and arranged along the second direction DR2. Each of the second sensor parts may include a plurality of second sensing patterns SP2 and a plurality of second connection patterns CP2 connecting the second sensing patterns SP2.

[0096] Each of the second sensing pattern SP2 and the second connection pattern CP2 may have a mesh shape in which a plurality of mesh openings are defined. The second sensing pattern SP2 and the second connection pattern CP2 are arranged along the first direction DR1. Each of the second connection patterns CP2 connects two adjacent second sensing patterns SP2 among the second sensing patterns SP2.

[0097] The first sensing pattern SP1 included in the first sensor part and the second sensing pattern SP2 included in the second sensor part may be capacitively coupled. When a sensing signal is applied to the first sensing pattern SP1, a capacitor is formed between the first sensing pattern SP1 and the second sensing pattern SP2.

[0098] According to an embodiment of the inventive concept, the second connection pattern CP2 may be included in the first conductive layer IS-CL1 and may correspond to the first conductive pattern described with reference to Figure 4 The first sensing pattern SP1, the second sensing pattern SP2, and the second connection pattern CP2 may be included in the second conductive layer IS-CL2 and may correspond to the second conductive pattern described with reference to Figure 4 However, embodiments of the inventive concept are not limited thereto. For example, the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may change positions with each other.

[0099] The plurality of sensing signal lines include first sensing signal lines SPL1a to SPL1d and second sensing signal lines SPL2a to SPL2e. Each of the first sensing signal lines SPL1a to SPL1d has one end connected to the first sensing pattern SP1 and the other end connected to a pad included in the first pad portion PD1. The first sensing signal lines SPL1a to SPL1d may transmit a sensing signal output from the first pad portion PD1 to the first sensing pattern SP1.

[0100] The second sensing signal lines SPL2a to SPL2e have one ends respectively connected to the second sensing pattern SP2. The second sensing signal lines SPL2a to SPL2e have the other ends respectively connected to pads included in the second pad portion PD2. The second sensing signal lines SPL2a to SPL2e may transmit an electrical signal output from the second pad portion PD2 to the second sensing pattern SP2.

[0101] Although not shown, each of the first sensing signal lines SPL1a to SPL1d and the second sensing signal lines SPL2a to SPL2e may have a mesh shape.

[0102] Hereinafter, the arrangement structure among the first conductive layer IS-CL1, the first insulating layer IS-IL1, and the second insulating layer IS-IL2 will be described in detail through Figures 6A to 6D Referring to

[0103] Referring to Figure 6A the second connection pattern CP2 may overlap with the active region AR and may be directly disposed on the insulating layer ECL of the display panel DP. In the present specification, the second connection pattern CP2 may correspond to the first conductive pattern included in the first conductive layer IS-CL1.

[0104] Referring to Figure 6B the first insulating layer IS-IL1 may be disposed on the insulating layer ECL while covering the second connection pattern CP2. In an exemplary embodiment, the first insulating layer IS-IL1 may be disposed on the insulating layer ECL while completely covering the active region AR and the non-active region NAR.

[0105] In addition, the first insulating layer IS-IL1 may include contact holes CH that partially expose the second connection pattern CP2. In an exemplary embodiment, the contact holes CH may be formed in the first insulating layer IS-IL1 through a photolithography process.

[0106] According to an embodiment of the inventive concept, the first insulating layer IS-IL1 may have a thickness greater than that of the second insulating layer IS-IL2. The first insulating layer IS-IL1 may be provided as an organic layer.

[0107] Referring to Figure 6C , the first sensing pattern SP1, the second sensing pattern SP2, and the first connection pattern CP1 may overlap with the active region AR and may be disposed on the first insulating layer IS-IL1.

[0108] The first sensing pattern SP1 may be insulated from the second sensing pattern SP2 by being separated from the second sensing pattern SP2. The first sensing patterns SP1 may be connected to each other through the first connection pattern CP1. In an exemplary embodiment, the first sensing pattern SP1 and the first connection pattern CP1 may be located at the same height with respect to the insulating layer ECL. The second sensing pattern SP2 may be connected to the second connection pattern CP2 through the contact holes CH formed in the first insulating layer IS-IL1. In an exemplary embodiment, the second connection pattern CP2 may be located at a height lower than the height of the second sensing pattern SP2 with respect to the insulating layer ECL.

[0109] In addition, the first sensing signal lines SPL1a to SPL1d and the second sensing signal lines SPL2a to SPL2e may be disposed on the first insulating layer IS-IL1 while overlapping with the non-active region NAR. The first sensing signal lines SPL1a to SPL1d and the second sensing signal lines SPL2a to SPL2e may be electrically connected to the first sensing pattern SP1 and the second sensing pattern SP2, respectively.

[0110] However, embodiments of the inventive concept are not limited to this structure of the sensing signal lines. For example, the sensing signal lines may have various structures. For example, the sensing signal lines may further include third sensing signal lines connected to the first sensing pattern SP1. In this case, the first sensing signal lines SPL1a to SPL1d may be respectively connected to one end of the first sensor unit, while the third sensing signal lines may be respectively connected to the other end of the first sensor unit.

[0111] Referring to Figure 6D , the second insulating layer IS-IL2 may be disposed on the first insulating layer IS-IL1 while covering the first sensing pattern SP1, the second sensing pattern SP2, the first connection pattern CP1, and the first sensing signal lines SPL1a to SPL1d and the second sensing signal lines SPL2a to SPL2e.

[0112] According to an embodiment of the inventive concept, the second insulating layer IS-IL2 may partially overlap with the active region AR and the non-active region NAR, rather than completely overlapping with the active region AR and the non-active region NAR. For example, the second insulating layer IS-IL2 may completely overlap with the first sensing pattern SP1, the second sensing pattern SP2, and the first connection pattern CP1, and may not overlap with at least one region of the grid openings defined in each of the first sensing pattern SP1, the second sensing pattern SP2, and the first connection pattern CP1. Additionally, the second insulating layer IS-IL2 may not overlap with the portions between the first sensing pattern SP1 and the second sensing pattern SP2. In addition to referring to Figure 6D In addition to referring to Figure 7A and Figure 8 the non-overlap of the second insulating layer IS-IL2 with at least one region of the grid openings, the portions between the first sensing pattern SP1, and the portions between the second sensing pattern SP2 will be described.

[0113] Additionally, the second insulating layer IS-IL2 may completely overlap with the first sensing signal lines SPL1a to SPL1d and the second sensing signal lines SPL2a to SPL2e. In an exemplary embodiment, the second insulating layer IS-IL2 may not overlap with the portions of the first insulating layer IS-IL1 where the first sensing signal lines SPL1a to SPL1d and the second sensing signal lines SPL2a to SPL2e are not provided.

[0114] According to an embodiment of the inventive concept, since the second insulating layer IS-IL2 partially overlaps with the active region AR and the non-active region NAR, when observed in a plan view, the first insulating layer IS-IL1 may have an area larger than that of the second insulating layer IS-IL2.

[0115] Figure 7A is an enlarged view showing Figure 6C the region AA in Figure 7B is an enlarged view showing Figure 7A the region BB in

[0116] Referring to Figure 7A the display area DP-DA includes a plurality of pixel areas PXA-R, PXA-G, and PXA-B, and a light-shielding area NPXA disposed adjacent to the pixel areas PXA-R, PXA-G, and PXA-B. For example, the light-shielding area NPXA may surround the pixel areas PXA-R, PXA-G, and PXA-B. Additionally, the pixel areas PXA-R, PXA-G, and PXA-B may respectively overlap with Figure 3C the plurality of light-emitting areas OPA described in In this specification, a pixel area refers to an area where light passes throughFigure 1 The display surface DD-IS described in Figure 1 basically emits to the outside.

[0117] The first sensing pattern SP1 includes first grid lines SPt1 that define grid openings. Although the first grid lines SPt1 are described as defining grid openings, at least a portion of the first grid lines SPt1 may not define a grid opening. For example, a portion E1 of the first grid lines SPt1 adjacent to the edge of the first sensing pattern SP1 may not define a grid opening.

[0118] The second sensing pattern SP2 includes second grid lines SPt2 that define grid openings. Similarly, although the second grid lines SPt2 are described as defining grid openings, at least a portion of the second grid lines SPt2 may not define a grid opening. For example, a portion E2 of the second grid lines SPt2 adjacent to the edge of the second sensing pattern SP2 may not define a grid opening.

[0119] In addition, each of the first grid lines SPt1 and the second grid lines SPt2 overlaps with the light-shielding region NPXA. Each of the first grid lines SPt1 includes two first extensions SPt1-A and two second extensions SPt1-B. The two first extensions SPt1-A extend in a fifth direction DR5 that intersects the first direction DR1 and the second direction DR2. The two second extensions SPt1-B extend in a fourth direction DR4 that intersects the fifth direction DR5. The first extensions SPt1-A may be connected to the second extensions SPt1-B while facing each other. The second extensions SPt1-B may be connected to the first extensions SPt1-A while facing each other. The grid lines may have a line width of, for example, several micrometers.

[0120] Each of the second grid lines SPt2 includes two third extensions SPt2-A and two fourth extensions SPt2-B. The two third extensions SPt2-A extend in the fourth direction DR4 that intersects the first direction DR1 and the second direction DR2. The two fourth extensions SPt2-B extend in the fifth direction DR5 that intersects the fourth direction DR4. The third extensions SPt2-A may be connected to the fourth extensions SPt2-B while facing each other. The fourth extensions SPt2-B may be connected to the third extensions SPt2-A while facing each other. The grid lines may have a line width of, for example, several micrometers.

[0121] According to an embodiment of the inventive concept, the grid openings may have an area larger than the area of each of the pixel regions PXA-R, PXA-G, and PXA-B. Figure 6DThe second insulating layer IS-IL2 that overlaps with the active region AR in [[ ]] can cover the first grid line SPt1 and the second grid line SPt2 without overlapping with the pixel regions PXA-R, PXA-G, and PXA-B.

[0122] As shown in [[ ]] Figure 7B The second insulating layer IS-IL2 can be disposed on the first insulating layer IS-IL1 while covering the second grid line SPt2 of the second sensing pattern SP2. Specifically, the second insulating layer IS-IL2 can have a structure that does not overlap with the pixel region PXA. The second insulating layer IS-IL2 can not overlap with a region of a grid opening that overlaps with the pixel region PXA, and can overlap with the remaining region that overlaps with the light-shielding region NPXA. That is, when observed in a plan view, the second insulating layer IS-IL2 according to an embodiment of the inventive concept can have an opening pattern that overlaps with the pixel region PXA. In [[ ]] Figure 7B The region defined by the outermost dotted line and the innermost dotted line can correspond to the second insulating layer IS-IL2; the region defined by two dotted lines adjacent to the outermost dotted line and the innermost dotted line, respectively, can correspond to the second grid line SPt2 of the second sensing pattern SP2.

[0123] In addition, although not shown in [[ ]] Figure 7B the light-shielding region NPXA can completely overlap with the second insulating layer IS-IL2. That is, a light-shielding layer BY (refer to [[ ]] Figure 8 ) that completely covers the second insulating layer IS-IL2 can be disposed on the first insulating layer IS-IL1.

[0124] According to an embodiment of the inventive concept, each of the grid openings corresponds to one of the pixel regions PXA-R, PXA-G, and PXA-B. However, the embodiments of the inventive concept are not limited thereto. One grid opening can overlap with two or more pixel regions. The grid openings can include a first grid opening IS-OP1 and a second grid opening IS-OP2, the first grid opening IS-OP1 having a first area and the second grid opening IS-OP2 having a second area different from the first area.

[0125] In an exemplary embodiment, each of the pixel regions PXA-R, PXA-G, and PXA-B can have various sizes. For example, the pixel region PXA-R that emits the first light, the pixel region PXA-G that emits the second light, and the pixel region PXA-B that emits the third light can have different sizes from each other. Here, the first light to the third light can be lights of the same color or lights of different colors from each other.

[0126] However, embodiments of the inventive concept are not limited thereto. For example, the pixel regions PXA-R, PXA-G, and PXA-B may have the same size, and the grid openings may also have the same size.

[0127] Figure 8 is a cross-sectional view taken along the Figure 7A I-I' line according to an embodiment of the inventive concept. Figure 9A is a cross-sectional view taken along the Figure 7A II-II' line according to an embodiment of the inventive concept. Figure 9B is a partial cross-sectional view showing a display panel according to an embodiment of the inventive concept. Figure 10 is a cross-sectional view showing a display device according to another embodiment of the inventive concept.

[0128] Referring to Figure 8 , in addition to the aforementioned display module DM, the display device DD may further include a window WM, a color filter layer CFY, a planarization layer OCY, and a light-shielding layer BY.

[0129] According to an embodiment of the inventive concept, the first insulating layer IS-IL1 is directly disposed on the insulating layer ECL of the display panel DP. In addition, the first insulating layer IS-IL1 may have a first thickness D1 greater than a second thickness D2 of the second insulating layer IS-IL2. For example, the first insulating layer IS-IL1 may have a thickness of about 2.3 μm.

[0130] As described above, the first thickness D1 of the first insulating layer IS-IL1 and the second thickness D2 of the second insulating layer IS-IL2 may be different from each other. Specifically, although the first thickness D1 of the first insulating layer IS-IL1 is greater than the second thickness D2 of the second insulating layer IS-IL2, the distance LD between the pixel defining layer PDL and the light-shielding layer BY may not increase compared to the previous distance.

[0131] As a result, the distance between the first conductive pattern disposed on the insulating layer ECL and the second conductive pattern disposed on the first insulating layer IS-IL1 may increase. As the distance between the first conductive pattern and the second conductive pattern increases, the amount of parasitic capacitance between the first conductive pattern and the second conductive pattern may be reduced.

[0132] In addition, as the distance LD between the pixel defining layer PDL and the light-shielding layer BY increases, the luminance characteristics and viewing angle characteristics of the light emitted through the pixel region PXA may deteriorate. However, according to an embodiment of the inventive concept, the distance LD between the pixel defining layer PDL and the light-shielding layer BY may be maintained such that the viewing angle characteristics and luminance characteristics do not deteriorate, and the distance between the first conductive pattern and the second conductive pattern may increase to reduce the amount of parasitic capacitance between the first conductive pattern and the second conductive pattern.

[0133] Specifically, the second sensing pattern SP2 may be disposed on the first insulating layer IS-IL1. The second sensing pattern SP2 may correspond to the second conductive pattern.

[0134] The second insulating layer IS-IL2 may be disposed on the first insulating layer IS-IL1 while covering the second sensing pattern SP2. According to an embodiment of the inventive concept, the second insulating layer IS-IL2 may be disposed on the same layer as the first sensing pattern SP1, the second sensing pattern SP2, and the first connection pattern CP1. In this specification, the expression "component A and component B are disposed on the same layer" means that all components of component A and component B are directly disposed on or in contact with a component C corresponding to the same layer. In other words, the expression may mean that both component A and component B are in contact with component C.

[0135] The light-shielding layer BY and the second insulating layer IS-IL2 may be disposed on the same layer. In other words, the light-shielding layer BY and the second insulating layer IS-IL2 may be in contact with the first insulating layer IS-IL1 corresponding to the same layer. The light-shielding layer BY may completely cover the second insulating layer IS-IL2. The light-shielding layer BY may be disposed over the entire first insulating layer IS-IL1 that overlaps with the non-effective region NAR as shown in Figure 6D and may be disposed over the entire first insulating layer IS-IL1 that overlaps with the light-shielding region NPXA of the effective region AR.

[0136] According to an embodiment of the inventive concept, the light-shielding layer BY may have a thickness that is different for each of its parts, rather than being completely the same. For example, the light-shielding layer BY may have a first part and a second part, the first part not overlapping with the second insulating layer IS-IL2, and the second part overlapping with the second insulating layer IS-IL2 and the second sensing pattern SP2. The first part may have a thickness greater than the thickness of the second part. The light-shielding layer BY may have a bottom surface that is recessed in the third direction DR3 to accommodate the second sensing pattern SP2 and the second insulating layer IS-IL2, thereby offsetting an increase in the thickness of the first insulating layer IS-IL1. In an exemplary embodiment, the bottom surface of the light-shielding layer BY may include a first bottom surface BY_BS1 and a second bottom surface BY_BS2. The first bottom surface BY_BS1 may be in contact with the first insulating layer IS-IL1, and the second bottom surface BY_BS2 may be recessed in the third direction DR3 to be spaced apart from the first insulating layer IS-IL1.

[0137] Here, although the thickness of the first insulating layer IS-IL1 increases, since the second insulating layer IS-IL2 according to an embodiment of the inventive concept is disposed on the same layer as the light-shielding layer BY and is disposed in the inner space of the light-shielding layer BY, the thickness of the display device DD may not increase substantially. In an exemplary embodiment, the inner space of the light-shielding layer BY may be defined by a second bottom surface BY_BS2, sidewalls BY_SW connecting the first bottom surface BY_BS1 and the second bottom surface BY_BS2, and a top surface of the first insulating layer IS-IL1. According to the above description, when viewed in a plan view, the light-shielding layer BY may have an area larger than that of the second insulating layer IS-IL2.

[0138] In addition, the light-shielding layer BY may include an opening overlapping with the pixel region PXA. For example, the pixel region PXA may be defined in the opening included in the light-shielding layer BY.

[0139] The color filter layer CFY may be disposed on the light-shielding layer BY and the first insulating layer IS-IL1. In an exemplary embodiment, the color filter layer CFY may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 may be configured to transmit light having a first color, the second color filter CF2 may be configured to transmit light having a second color, and the third color filter CF3 may be configured to transmit light having a third color. For example, the first color is red, the second color is green, and the third color is blue.

[0140] According to an embodiment of the inventive concept, each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a first portion and a second portion, the first portion being directly disposed on the first insulating layer IS-IL1, and the second portion being disposed on the light-shielding layer BY. A first boundary between the first color filter CF1 and the second color filter CF2 may be formed on the light-shielding layer BY. A second boundary between the third color filter CF3 and the second color filter CF2 may be formed on the light-shielding layer BY.

[0141] The planarization layer OCY may be disposed on the color filter layer CFY, and the planarization layer OCY may be disposed as an organic layer.

[0142] The window WM may be disposed on the planarization layer OCY while corresponding to Figure 1 the display surface DD-IS of the display device DD in

[0143] Refer to Figure 9A, as the thickness of the first insulating layer IS-IL1 according to an embodiment of the inventive concept increases, the distance in the third direction DR3 between each of the second connection patterns CP2 and the corresponding second sensing pattern SP2 among the second sensing patterns SP2 may increase. As a result, the amount of parasitic capacitance generated between the second connection pattern CP2 and the second sensing pattern SP2 may decrease.

[0144] In addition, as the thickness of the first insulating layer IS-IL1 according to an embodiment of the inventive concept increases, the distance in the third direction DR3 between the second sensing pattern SP2 and the second electrode CE of the display panel DP or the distance in the third direction DR3 between the second sensing pattern SP2 and the first electrode AE of the display panel DP may increase. As a result, the amount of parasitic capacitance generated between the second sensing pattern SP2 and the second electrode CE or between the second sensing pattern SP2 and the first electrode AE may decrease.

[0145] In addition, referring to Figure 9B , as the distance in the third direction DR3 between the first sensing pattern SP1 and the second electrode CE of the display panel DP or the distance in the third direction DR3 between the first sensing pattern SP1 and the first electrode AE of the display panel DP increases, the amount of parasitic capacitance generated between the first sensing pattern SP1 and the second electrode CE or between the first sensing pattern SP1 and the first electrode AE may decrease.

[0146] Referring to Figure 10 , a color filter layer CFY according to another embodiment of the inventive concept may be disposed between the input sensing unit ISU and the display panel DP. For example, the color filter layer CFY may be directly disposed on the insulating layer ECL. According to an embodiment of the inventive concept, each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a first portion and a second portion, the first portion being directly disposed on the insulating layer ECL and the second portion being disposed on the auxiliary light-shielding layer BMz. A first boundary between the first color filter CF1 and the second color filter CF2 may be formed on the auxiliary light-shielding layer BMz. A second boundary between the third color filter CF3 and the second color filter CF2 may be formed on the auxiliary light-shielding layer BMz.

[0147] The first conductive pattern included in the first conductive layer IS-CL1 may be directly disposed on the color filter layer CFY. However, the embodiments of the inventive concept are not limited thereto. For example, an organic layer may be disposed between the first conductive layer IS-CL1 and the color filter layer CFY, and the first conductive layer IS-CL1 may be disposed on the organic layer.

[0148] According to an embodiment of the inventive concept, a display device can be provided that has a reduced parasitic capacitance between a conductive layer of an input sensing unit and a display element layer of a display panel. Additionally, an input sensing unit can be provided that has a reduced parasitic capacitance between two conductive patterns disposed on different layers from each other. As a result, a display device having improved overall driving reliability can be provided.

[0149] Although the present invention has been shown and described with reference to exemplary embodiments of the present invention, it is understood that the present invention should not be limited to these exemplary embodiments, but rather various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present invention as claimed.

Claims

1. A display device, the display device comprising: a substrate base, a display area and a non-display area being defined on the substrate base, the display area including a plurality of pixel areas and a light-shielding area disposed adjacent to the plurality of pixel areas, the non-display area being disposed adjacent to the display area; a display element layer, disposed on the substrate base and including a pixel defining layer and a plurality of light-emitting elements, the pixel defining layer having a plurality of light-emitting openings, the plurality of light-emitting openings respectively overlapping with the plurality of pixel areas, the plurality of light-emitting elements respectively overlapping with the plurality of light-emitting openings; a packaging layer, covering the plurality of light-emitting elements; a first conductive layer, disposed on the packaging layer and including a plurality of first conductive patterns; a first insulating layer, disposed on the packaging layer to cover the plurality of first conductive patterns; a second conductive layer, disposed on the first insulating layer and including a plurality of first sensing patterns, a plurality of second conductive patterns electrically connecting the plurality of first sensing patterns, and a plurality of second sensing patterns electrically connected through the plurality of first conductive patterns; a second insulating layer, disposed on the first insulating layer and the second conductive layer without overlapping with the plurality of light-emitting elements to cover the plurality of first sensing patterns, the plurality of second sensing patterns and the plurality of second conductive patterns; and a light-shielding layer, disposed on the second insulating layer to cover the upper surface and side walls of the second insulating layer.

2. The display device according to claim 1, Among them, the light-shielding layer includes a first bottom surface, a second bottom surface and side walls, the first bottom surface is in contact with the first insulating layer, the second bottom surface is separated from the first insulating layer, the side walls connect the first bottom surface and the second bottom surface, and the second bottom surface, the side walls and the first insulating layer define an internal space of the light-shielding layer.

3. The display device according to claim 2, Among them, the second insulating layer is disposed in the internal space of the light-shielding layer.

4. The display device according to claim 1, Among them, in the thickness direction of the substrate base, the first insulating layer has a thickness greater than that of the second insulating layer.

5. The display device according to claim 1, Among them, when observed in a plan view, the first insulating layer has an area larger than that of the second insulating layer.

6. The display device according to claim 5, Among them, when observed in a plan view, the light-shielding layer has an area larger than that of the second insulating layer.

7. The display device according to claim 1, Among them, the light-shielding layer defines the light-shielding area of the display device, and the second insulating layer partially overlaps with the light-shielding layer without overlapping with the plurality of light-emitting elements.

8. The display device according to claim 1, Among them, the first conductive layer is directly disposed on the packaging layer.

9. The display device according to claim 1, Among them, the pixel defining layer has a black color.

10. The display device according to claim 7, Among them, the second conductive layer further includes a plurality of sensing signal lines connected to the plurality of first sensing patterns and the plurality of second sensing patterns.

11. The display device according to claim 10, Among them, The second insulating layer is disposed on the first insulating layer to cover the plurality of sensing signal lines.

12. The display device according to claim 7, Among them, The light-shielding layer includes a first portion and a second portion. The first portion is disposed not to overlap with the second insulating layer when observed in a plan view, and the second portion overlaps with the second insulating layer when observed in a plan view. The thickness of the first portion is greater than the thickness of the second portion.

13. The display device according to claim 1, Among them, The first insulating layer includes a plurality of contact holes, and the plurality of second sensing patterns and the plurality of first conductive patterns are electrically connected to each other through the plurality of contact holes.

14. The display device according to claim 1, the display device further comprising: A color filter layer including a first color filter, a second color filter, and a third color filter that transmit lights of different colors from each other, wherein each of the first color filter, the second color filter, and the third color filter includes a first portion disposed directly on the first insulating layer and a second portion disposed on the light-shielding layer.

15. The display device according to claim 1, the display device further comprising: A color filter layer including a plurality of color filters disposed between the encapsulation layer and the first conductive layer and transmitting lights of different colors from each other.

16. The display device according to claim 15, Among them, The first conductive layer is in contact with the color filter layer.

17. A display device, the display device comprising: A substrate substrate including a display area and a non-display area disposed adjacent to the display area; A display element layer disposed on the substrate substrate, and a plurality of pixel areas overlapping with the display area are defined in the display element layer. Wherein, the display element layer includes a plurality of display elements respectively overlapping with the plurality of pixel areas; An encapsulation layer disposed on the display element layer; A plurality of first conductive patterns disposed on the encapsulation layer; A first insulating layer covering the plurality of first conductive patterns; A plurality of second conductive patterns disposed on the first insulating layer; A second insulating layer covering the plurality of second conductive patterns; and A light-shielding layer covering the upper surface and sidewalls of the second insulating layer, wherein each of the second insulating layer and the light-shielding layer is in contact with the first insulating layer, wherein the light-shielding layer includes a plurality of openings, each of the plurality of openings overlapping with a corresponding display element among the plurality of display elements, and wherein the second insulating layer covers the plurality of second conductive patterns without overlapping with the plurality of openings.

18. The display device according to claim 17, Among them, When observed in a plan view, each of the first insulating layer and the light-shielding layer has an area larger than the area of the second insulating layer.

19. A method of manufacturing a display device, the method comprising: Providing a display panel including a substrate substrate, a display element layer disposed on the substrate substrate, and an encapsulation layer disposed on the display element layer. Wherein, the display element layer includes display elements; Forming a plurality of first conductive patterns on the encapsulation layer; Form a first insulating layer on the plurality of first conductive patterns; Form a plurality of second conductive patterns on the first insulating layer; Form a second insulating layer to cover the plurality of second conductive patterns without overlapping with the display element; and Form a light-shielding layer to cover the upper surface and sidewalls of the second insulating layer without overlapping with the display element, wherein each of the second insulating layer and the light-shielding layer contacts the first insulating layer.

20. The method according to claim 19, Among them, the light-shielding layer includes a first portion and a second portion, the first portion is arranged not to overlap with the second insulating layer when observed in a plan view, the second portion overlaps with the second insulating layer when observed in a plan view, and wherein the thickness of the first portion is greater than the thickness of the second portion.

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