Gate driver, method for transmitting information bits and integrated circuit

Abstract

Disclosed is a gate driver, a method and an integrated circuit for transmitting information bits across a termination region between a high-side region and a low-side region of the gate driver. The gate driver includes: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a termination region between the high-side region and the low-side region, the termination region being configured to isolate the first voltage domain from the second voltage domain; a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor; a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor; and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, wherein each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.

Description

Technical Field

[0001] The present disclosure relates generally to bit routing in gate drivers, and more particularly, to low power cycle-to-cycle bit transfer in high voltage gate drivers and methods of operating the same. Background Art

[0002] In a monolithic high voltage (HV) gate driver, the gate driver may include a low voltage (LV) gate driver for driving a low-side transistor switch and an HV gate driver for driving a high-side transistor switch. In such a configuration, it may be useful to transmit asynchronous digital data between the LV gate driver and the HV gate driver. Level shifter transistors can perform such transmissions, but require a wide silicon area and consume power.

[0003] Therefore, an improved system capable of transferring data between a LV gate driver and a HV gate driver that requires less silicon area and has lower power dissipation may be desired. Summary of the invention

[0004] An embodiment provides a gate driver, which includes: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain that is lower than the first voltage domain; a termination region between the high-side region and the low-side region, the termination region being configured to isolate the first voltage domain from the second voltage domain; a high-side gate driver disposed in the high-side region, the high-side gate driver being configured to drive a high-side power transistor; a low-side gate driver disposed in the low-side region, the low-side gate driver being configured to drive a low-side power transistor; and a plurality of termination diodes disposed in the termination region, the plurality of termination diodes being configured to transmit information bits between the high-side region and the low-side region, wherein each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.

[0005] Embodiments also provide a method for transmitting an information bit across a termination region between a high-side region and a low-side region of a gate driver. The method includes: operating the high-side region in a first voltage domain; operating the low-side region in a second voltage domain lower than the first voltage domain; and transmitting the information bit between the high-side region and the low-side region through a plurality of termination diodes disposed in the termination region, wherein each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments are described herein with reference to the accompanying drawings.

[0007] Figure 1Ais a schematic block diagram showing a motor control actuator of a power semiconductor device according to one or more embodiments;

[0008] Figure 1B is a schematic diagram illustrating a power inverter utilizing single shunt current sensing according to one or more embodiments;

[0009] Figure 2 is a schematic block diagram of an inverter control unit according to one or more embodiments;

[0010] Figure 3A and Figure 3B A schematic block diagram showing a transmission interface circuit between a high-side region and a low-side region according to one or more embodiments;

[0011] Figure 4A shows a schematic block diagram of a high-side receiver circuit according to one or more embodiments;

[0012] Figure 4B Shown with Figure 4A The truth table for the high-side receiver circuit shown in ;

[0013] Figure 4C Shows Figure 4A Schematic block diagram of the high-side receiver circuit shown, where Bitx is 1;

[0014] Figure 4D Shows Figure 4A Schematic block diagram of the high-side receiver circuit shown, where Bitx is 0;

[0015] Figure 5A A schematic block diagram of a low-side receiver circuit is shown according to one or more embodiments when a differential input signal is equal to 1;

[0016] Figure 5B A schematic block diagram of a low-side receiver circuit is shown according to one or more embodiments when a differential input signal is equal to 0;

[0017] Fig. 6A shows a schematic circuit diagram of a high-side event sensor according to one or more embodiments;

[0018] Figure 6B A schematic circuit diagram showing a low-side event sensor according to one or more embodiments; and

[0019] Figure 6C A graph plotting voltage Vs versus time during which different voltage events or phases occur is shown in accordance with one or more embodiments. DETAILED DESCRIPTION

[0020] In the following, details are set forth to provide a more comprehensive explanation of the example embodiments. However, it will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In other cases, in order to avoid obscuring the embodiments, known structures and devices are shown in block diagram form or in schematic diagrams rather than in detail. In addition, unless otherwise specifically noted, the features of the different embodiments described below may be combined with each other.

[0021] In addition, equivalent or similar reference numerals are used in the following description to represent equivalent or similar elements or elements having equivalent or similar functions. Since the same or functionally equivalent elements are given the same reference numerals in the drawings, repeated descriptions of the elements having the same reference numerals may be omitted. Therefore, the descriptions provided for the elements having the same or similar reference numerals are interchangeable.

[0022] In this regard, directional terms such as "top," "bottom," "below," "front," "back," "rear," "front," "rear," "under," "above," and the like may be used with reference to the orientation of the figures being described. Because components of the embodiments may be positioned in a number of different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be utilized or structural or logical changes may be made without departing from the scope defined by the claims. Accordingly, the following detailed description should not be taken in a limiting sense.

[0023] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

[0024] In the embodiments described herein or shown in the accompanying drawings, any direct electrical connection or coupling, i.e., any connection or coupling without additional intermediate elements, may also be achieved by an indirect connection or coupling, i.e., a connection or coupling with one or more additional intermediate elements, and vice versa, as long as the general purpose of the connection or coupling is basically maintained, such as for sending a certain signal or sending certain information. Features from different embodiments may be combined to form additional embodiments. For example, unless otherwise stated, variations or modifications described with respect to one of the embodiments may also apply to other embodiments.

[0025] The term "substantially" may be used herein to account for small manufacturing tolerances (eg, within 5%) that are considered acceptable in the industry without departing from aspects of the embodiments described herein.

[0026] A sensor may refer to a component that converts a physical quantity to be measured into an electrical signal such as a current signal or a voltage signal. The physical quantity may be, for example, a current or a voltage at a shunt resistor in a single shunt resistor system.

[0027] Signal processing circuits and / or signal conditioning circuits may receive one or more signals from one or more components and perform signal conditioning or processing on one or more signals. As used herein, signal conditioning refers to manipulating a signal so that the signal meets the requirements of the next stage for further processing. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0028] Thus, the signal processing circuit may include an analog-to-digital converter (ADC) that converts an analog signal from one or more sensor elements into a digital signal. The signal processing circuit may also include a digital signal processor (DSP) that performs some processing on the digital signal.

[0029] Modern devices rely on power semiconductor devices for many functions in motor vehicles, consumer and industrial applications, such as converting electrical energy and driving electric motors or electric machines. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0030] A power semiconductor device generally comprises a semiconductor structure configured to conduct a load current along a load current path between two load terminal structures of the device. In addition, the load current path can be controlled by means of a control electrode, sometimes referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to one of a conducting state and a blocking state. The control signal can be a voltage signal or a current signal having a controlled value.

[0031] A power transistor is a power semiconductor device that can be used to drive a load current. For example, an IGBT is turned "on" or "off" by activating and deactivating its gate terminal. Applying a positive input voltage signal across the gate and emitter will keep the device in its "on" state, while making the input gate signal zero or slightly negative will turn it "off". There are turn-on and turn-off processes for turning the power transistor on and off. During the turn-on process, a gate driver integrated circuit (IC) can be used to provide (source) a gate current (i.e., a turn-on current) to the gate of the power transistor to charge the gate to a sufficient voltage to turn on the device. In contrast, during the turn-off process, the gate driver IC is used to draw (absorb) a gate current (i.e., a turn-off current) from the gate of the power transistor, thereby fully discharging the gate to turn off the device. Current pulses can be output from the gate driver IC as control signals according to a pulse width modulation (PWM) scheme. Therefore, during a PWM cycle for controlling a power transistor, a control signal can be switched between an on current level and an off current level. This in turn charges and discharges the gate voltage to switch the power transistor on and off, respectively.

[0032] In particular, the gate of the power transistor is a capacitive load, and the on-current (i.e., gate source current) and the off-current (i.e., gate absorption current) are specified as initial currents when a switching event is initiated. During the off-event, after a small amount of time (less than the PWM cycle), the gate current decreases and reaches a zero value when the gate reaches 0V. During the on-event, after a small amount of time (less than the PWM cycle), the gate current decreases and reaches a zero value when the gate reaches 15V. According to the embodiments provided herein, the current values ​​of the on-current and the off-current can be programmed for both the HV gate driver and the LV gate driver. For example, a 3-bit configuration signal can be used to select the values ​​of the on-current and the off-current, which are selected from eight possible configurations under a 3-bit scheme. More or fewer configurations can be achieved by changing the number of bits used for the configuration signal.

[0033] The transistor may include an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET) (e.g., a silicon MOSFET or a silicon carbide MOSFET). Although the IGBT may be used as an example in the following embodiments, it should be understood that the IGBT may be replaced by a MOSFET, and vice versa. In this case, when the IGBT is replaced by a MOSFET, the collector of the IGBT may be replaced by the drain of the MOSFET, the emitter of the IGBT may be replaced by the source of the MOSFET, and the drain-source voltage V of the MOSFET may be replaced by the drain-source voltage V DS Substituting the collector-emitter voltage V of the IGBT in any of the examples described hereinCE Therefore, any IGBT module can be replaced by a MOSFET module, and vice versa, any MOSFET module can be replaced by an IGBT module.

[0034] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Therefore, in an embodiment, the power semiconductor device can be configured to carry a load current to be provided to a load and / or a load current provided by a power supply, respectively. For example, the semiconductor device may include one or more power semiconductor units, such as a monolithically integrated diode unit and / or a monolithically integrated transistor unit. Such a diode unit and / or such a transistor unit can be integrated in a power semiconductor module.

[0035] Power semiconductor devices comprising transistors suitably connected to form a half-bridge are commonly used in the field of power electronics. For example, a half-bridge may be used to drive a motor or a switched-mode power supply.

[0036] For example, a multiphase inverter is configured to provide multiphase power by providing a multiphase load (e.g., a three-phase motor). For example, three-phase power includes three symmetrical sine waves that are 120 electrical degrees out of phase with each other. In a symmetrical three-phase power system, each of the three conductors carries an alternating current (AC) with the same frequency and voltage amplitude relative to a common reference but with a phase difference of one-third of a cycle. Due to the phase difference, the voltage on any conductor reaches its peak value one-third of a cycle after one of the other conductors and one-third of a cycle before the remaining conductors. This phase delay provides constant power transmission for balanced linear loads. It also makes it possible to generate a rotating magnetic field in the motor.

[0037] In a three-phase system feeding a balanced and linear load, the sum of the instantaneous currents in the three conductors is zero. In other words, the current in each conductor is equal in magnitude to the sum of the currents in the other two conductors, but opposite in sign. The return path for the current in any phase conductor is through the other two phase conductors. The instantaneous currents produce a current space vector.

[0038] The three-phase inverter includes three inverter branches, one for each of the three phases, and each inverter branch is connected to a direct current (DC) voltage source in parallel with each other. Each inverter branch includes, for example, a pair of transistors arranged in a half-bridge configuration for converting DC to AC. In other words, each inverter branch includes two complementary transistors (i.e., a high-side transistor and a low-side transistor) connected in series, which are turned on and off to drive the phase load in a complementary manner. However, a multiphase inverter is not limited to three phases, and may include two or more phases, wherein an inverter branch is provided for each phase.

[0039] Figure 1A1 is a schematic block diagram of a motor control actuator 100 of a power semiconductor device according to one or more embodiments. In particular, the motor control actuator 100 includes a power inverter 1 and an inverter control unit 2. The inverter control unit 2 is embodied as a motor control unit and can therefore also be referred to as a motor controller or a motor control IC. The motor control unit can be a single chip IC or can be divided into a microcontroller and a gate driver on two or more ICs.

[0040] The motor control actuator 100 is further coupled to a three-phase motor M including three phases U, V and W. The power inverter 1 is a three-phase current generator configured to provide three-phase power by providing three-phase current to drive the motor M. It should also be understood that the power inverter 1 and the inverter control unit 2 can be placed on the same circuit board or on separate circuit boards.

[0041] Deviations in both amplitude and phase may result in loss of power and torque in the motor M. Therefore, the motor control actuator 100 may be configured to monitor and control the amplitude and phase of the current provided to the motor M in real time based on a feedback control loop to ensure that proper current balance is maintained. Open-loop motor control units also exist and may be implemented.

[0042] The power inverter 1 includes a switch array of six transistor modules 3u+, 3u-, 3v+, 3v-, 3w+ and 3w- (collectively referred to as transistor modules 3) arranged in complementary pairs. Each complementary pair constitutes an inverter branch that provides phase current to the three-phase motor M. Therefore, each inverter branch includes an upper (high-side) transistor module 3 and a lower (low-side) transistor module 3. Each transistor module may include a transistor and may also include a diode (not shown). Therefore, each inverter branch includes an upper transistor and a lower transistor. Load current paths U, V and W extend from the output of each inverter branch (i.e., the output of each half bridge) located between the complementary transistors and are configured to be coupled to a load, such as a motor M. The power inverter 1 is coupled to a DC power supply 4 (e.g., a battery or a diode bridge rectifier) ​​and is coupled to an inverter control unit 2.

[0043] In this example, the inverter control unit 2 includes a motor control circuit and a gate driver circuit for controlling the switch array. In some examples, the inverter control unit 2 can be monolithic, wherein the motor control circuit and the gate driver circuit are integrated onto a single die. In other examples, the motor control circuit and the gate driver circuit can be separated into separate ICs. A "monolithic" gate driver is a gate driver on a single silicon chip and can also be made using specific HV technology. In addition, the gate driver IC can be integrated on the power inverter 1.

[0044] The motor controller IC performs in real time the motor control functions of the motor control actuator 100. The motor control functions may include controlling a permanent magnet motor or an induction motor, and may be configured for sensorless control that does not require rotor position sensing, for sensor-based control with Hall sensors and / or encoder devices, or for a combination of both sensor-based control (e.g., for use at lower rotor speeds) and sensorless control (e.g., for use at higher rotor speeds).

[0045] For example, the inverter control unit 2 includes a controller and driver unit 5 including a microcontroller unit (MCU) as a motor controller IC and a gate driver IC for generating a driver signal for controlling the transistor of each transistor module 3. Therefore, the load current paths U, V, and W can be controlled by the controller and driver unit 5 by means of a control electrode (i.e., gate electrode) of the control transistor 3. For example, upon receiving a control signal from the microcontroller, the gate driver IC can set the corresponding transistor to one of a conducting state (i.e., an on state) or a blocking state (i.e., an off state).

[0046] The gate driver IC may be configured to receive instructions including power transistor control signals from the microcontroller, and to turn on or off the corresponding transistor 3 according to the received instructions and control signals. For example, during the turn-on process of the corresponding transistor 3, the gate driver IC may be used to provide (source) a gate current to the gate of the corresponding transistor 3 to charge the gate. Conversely, during the turn-off process, the gate driver IC may be used to draw (absorb) a gate current from the gate of the transistor 3 to discharge the gate.

[0047] The inverter control unit 2 or the controller and driver unit 5 itself may include a PWM controller, an ADC, a DSP and / or a clock source (i.e. a timer or counter) for implementing a PWM scheme to control the state of each transistor and ultimately control each phase current provided on the corresponding load current paths U, V and W.

[0048] In particular, the microcontroller of the controller and driver unit 5 can use a motor control algorithm, such as a field oriented control (FOC) algorithm, to provide current control in real time for each phase current output to a multi-phase load, such as a multi-phase motor. The motor speed can be further controlled by adding a speed control loop in addition to the FOC control. Therefore, the FOC can be considered as an inner control loop, and the speed control loop can be considered as an outer control loop. In some cases, a third control loop (e.g., a position control loop) outside the speed control loop can be used to control the motor position.

[0049] For example, during FOC, the motor phase current should be measured so that the accurate rotor position can be determined in real time. To implement the determination of the motor phase current, the MCU 5 can employ an algorithm using single shunt current sensing (e.g., space vector modulation (SVM), also known as space vector pulse width modulation (SVPWM)).

[0050] In addition, the switches 3 (i.e. transistors) of the power inverter 1 are controlled so that two switches in the same inverter branch are not turned on at the same time at any time, otherwise the DC power supply will be short-circuited. According to the motor control algorithm, this requirement can be met by performing complementary operations on the switches 3 in the inverter branch.

[0051] Figure 1B is a schematic diagram showing a power inverter 1 utilizing single shunt current sensing according to one or more embodiments. In particular, the power inverter 1 includes a shunt resistor Rs placed on the negative DC link of the power inverter 1. The transistor 3 u+ , 3 u- , 3 v+ , 3 v- , 3 w+ and 3 w- Represented as switches and the motor M is shown having a winding for each of its phases. Figure 1A The MCU 5 in can receive samples of the current obtained from the shunt resistor Rs, and then use an algorithm (ie, software) to reconstruct the three-phase current in real time.

[0052] For example, SVPWM is a vector control-based algorithm that requires sensing of three motor phase currents. By using a single shunt resistor Rs, the DC link current pulses are sampled at precise time intervals. The voltage drop across the shunt resistor Rs can be amplified by an operational amplifier within the inverter control unit 2 and changed upward by, for example, 1.65V. The resulting voltage can be converted by an ADC within the inverter control unit 2. Based on the actual combination of switches, the three-phase current of the motor M is reconstructed using the SVPWM algorithm. The ADC can measure the DC link current during the active vector of the PWM cycle. In each sector, two-phase current measurements are available. Since the sum of the three winding currents is zero, the third phase current value can be calculated.

[0053] SVPWM itself is an algorithm for controlling PWM in real time. The algorithm is used to generate an AC waveform and can be used to drive a three-phase AC powered motor at a variable speed from a DC source using multiple switching transistors. Although the examples herein are described in the context of a three-phase motor, the examples are not limited thereto and can be applied to any load scenario.

[0054] Furthermore, it should be appreciated that other implementations besides a single shunt resistor may be used for current sensing, and other motor control algorithms may be used to control the load, and the embodiments described herein are not limited thereto.

[0055] Figure 2 is a schematic block diagram of an inverter control unit 200 according to one or more embodiments. The inverter control unit 200 is configured to control the conduction state of power transistors arranged in one or more inverter branches, wherein an exemplary inverter branch 1a is shown. The power transistors of the inverter branch 1a include a high-side transistor 3H and a low-side transistor 3L, and correspond to a complementary pair of transistors. Therefore, the high-side transistor 3H and the low-side transistor 3L can represent Figure 1A and Figure 1B One of a complementary pair of transistors shown.

[0056] The inverter control unit 200 includes a gate driver 5a and a microcontroller 5b, wherein the microcontroller 5b is electrically coupled to the gate driver 5a to transmit information and control signals between the microcontroller 5b and the gate driver 5a, and the gate driver 5a is electrically coupled to the inverter branch 1a to transmit information and control signals between the gate driver 5a and the inverter branch 1a.

[0057] Specifically, the gate driver 5a is a monolithic gate driver that includes three regions: a high-side region 10, which includes a HV gate driver 11; a low-side region 20, which includes a LV gate driver 21; and a termination region 30, which includes a bit transfer diode 31. The three regions 10, 20 and 30 are monolithically constructed in a single integrated circuit. The technology used to manufacture the gate driver 5a is capable of building all three regions on a single silicon die and building a single IC gate driver. In other words, the gate driver 5a is a single chip that includes both the high side 10 and the low side 20. Between the high side 10 and the low side 20 is the termination region 30, the main purpose of which is to electrically isolate the region 10 from the region 20. The termination region 30 in this particular technology (and other high voltage technologies) includes a large diode that is usually used as a bootstrap diode 9 to charge the bootstrap capacitor 7.

[0058] The inverter control unit 200 also includes: a high-side supply voltage Vb (i.e., the supply of the high-side region 10); a high-side ground voltage Vs (i.e., the grounding of the high-side region 10); a low-side supply voltage Vcc (i.e., the supply of the low-side region 20); a low-side ground voltage Vss (i.e., the grounding of the low-side region 20); a bootstrap capacitor 7; and a bootstrap diode 9 located in the termination region 30. Typically, Vb is equal to Vs+Vcc, where Vcc is equal to 15V (i.e., Vb–Vs=15V) in this example. In other words, due to the bootstrap capacitor 7 supplied to the high side, Vb is 15V higher than Vs during normal operation. The positive power supply rail DC+ is typically in the range of 200V to 1200V, but is not limited thereto. In addition, when the low-side switch 3L is turned on (and 3H is turned off), Vs is equal to DC- (e.g., Vss or 0V). DC- is a negative power supply rail and may be short-circuited to Vss as shown, but not necessarily so. In this case, Vb is close to 15V and the bootstrap capacitor 7 is charged by Vcc through the bootstrap diode 9. Otherwise, when the high-side switch 3H is turned on (and 3L is turned off), Vs is equal to DC+, in which case Vb is 15V higher than DC+, and since the bootstrap diode 9 is turned off, the bootstrap capacitor 7 is slowly discharging.

[0059] The above voltages are set so that the high-side region 10 operates in a higher voltage or power domain than the low-side region 20. For example, the low-side (external) supply voltage Vcc can be set to 15V, and when DC+ is 1200V, the high-side supply voltage Vb can operate at a maximum voltage of 1215V. In addition, the voltage Vdd refers to the nominal (drain) supply voltage, which is an internally generated and regulated voltage (e.g., 5.5V). The voltage Vdd can be used as a reference voltage for all logic gates.

[0060] The high-side region 10 includes a HV gate driver 11 configured to drive the power transistor 3H. In addition, the high-side region 10 includes: a high-side receiver 12 configured to receive information bits from the low-side region 20 along the uplink transmission direction; a high-side transmitter 13 configured to transmit information bits to the low-side region 20 along the downlink transmission direction; a high-side logic 14 configured to receive a control signal from the microcontroller 5b (e.g., via a pulse generator 27 and an nMOS level converter 28) and send the control signal to the HV gate driver 11; a diagnostic logic block 15 configured to sense abnormal events at the high-side region 10 (e.g., short circuit events, overcurrent events, high-side power supply (Vb-Vs) overvoltage events, and high-side power supply (Vb-Vs) undervoltage events) and generate an error flag in response thereto; and an output buffer 16. The output buffer 16 can be used to amplify the output of the HV gate driver 11 and provide the amplified signal as a control signal to the power transistor 3H.

[0061] The nMOS level converter 28 is used to convert (i.e., level shift) the control signal and thus transfer the control information from the low voltage / power domain to the high voltage / power domain. The terminating diode 31 is used to transfer the information bit between the two voltage domains. The level converter is a "real-time" transmitter (i.e., low latency compared to the PWM cycle). On the other hand, the terminating diode has a larger delay, but consumes less power and occupies a smaller area.

[0062] The low-side region 20 includes a LV gate driver 21 configured to drive the power transistor 3L. In addition, the low-side region 20 includes: a low-side transmitter 22 configured to transmit information bits to the high-side region 10 along the uplink transmission direction; a low-side receiver 23 configured to receive information bits from the high-side region 10 along the downlink transmission direction; a low-side logic 14 configured to receive a control signal from the microcontroller 5b and transmit the control signal to the LV gate driver 21; an output buffer 26 configured to output a control signal to the power transistor 3L; a pulse generator 27; and an nMOS level converter 28.

[0063] Since the microcontroller 5b is in the voltage domain (i.e., power domain) identical with the low-side region 20, it is electrically coupled to the low-side region 20 of the gate driver 5a. The microcontroller 5b is configured to generate a control signal for controlling transistors 3L and 3H and sends the control signal to the gate driver 5a at the low-side region 20. For example, the gate driver 5a is configured to receive instructions from the microcontroller 5b to drive the motor phase (i.e., inverter branch) connected to the voltage Vs using a PWM control signal. These PWM control signals are received by the gate driver 5a at the low-side region 20 and are transferred to the corresponding HV gate driver 11 and LV gate driver 21 via appropriate logic (e.g., low-side logic 24, or a combination of a pulse generator 27, an nMOS level converter 28, and a high-side logic 14). In order for the control signal to arrive at the HV gate driver 11, a control signal is sent from the low-side region 20 via the termination region 30. The HV gate driver 11 and the LV gate driver 21 are configured to receive control signals and output the control signals to the corresponding power transistors 3L and 3H via output terminals of the gate driver 5 a .

[0064] The microcontroller 5b is also configured to send information bits to the high-side region 10 via the low-side region 20 and receive information bits from the high-side region 10 via the low-side region 20. The transmission toward the high-side region 10 of the gate driver 5a enables the microcontroller 5b to program one or more parameters of the HV gate driver 11, such as the output current of the current pulse (control signal) and other synchronous rectification programming, thereby making the HV gate driver 11 flexible and suitable for different application environments. Here, the high level and low level of the output current of the PWM current pulse can be configured according to the information received from the microcontroller 5b.

[0065] The microcontroller 5 b is also configured to program one or more parameters of the LV gate driver 21, such as the output current of the current pulse (control signal), and other synchronous rectification programming. Since the microcontroller 5 b and the LV gate driver 21 are in the same voltage domain, the configuration information bits can be sent to the LV gate driver 21 through the low-side logic 24.

[0066] In addition, the diagnostic block 15 in the high-side region 10 can be configured to sense abnormal events and issue flags when these abnormal events occur. For example, the diagnostic block 15 can be configured to detect overcurrents indicating short-circuit events in the inverter branch 1a and generate error flags in response to such detection. The transmission to the low-side region 20 enables the diagnostic block 15 to send diagnostic information including error flags to the microcontroller 5b. The microcontroller 5b can then analyze the received diagnostic information and take countermeasures and quickly restore safe working conditions. For example, the microcontroller 5b can adjust the control signals sent to the HV and LV gate drivers based on the received diagnostic information.

[0067] The high side region 10 and the low side region 20 can transmit information bits between the two regions via a bit transmitting diode 31 (i.e., a termination diode 31) located in the termination region 30. The low side region 20 is located in a low voltage domain in which the microcontroller 5b also resides, while the high side region 10 is located in a high voltage domain. Therefore, the gate driver 5a includes two different voltage domains. The termination region 30 isolates the high voltage domain from the low voltage domain and can be referred to as an isolation termination region. Therefore, the termination region 30 provides a high voltage isolation barrier, wherein the bit transmitting diode 31 is used to isolate the two voltage domains while enabling communication between the two voltage domains.

[0068] In this example, a multi-bit communication protocol is used to transmit information bits between the high-side region 10 and the low-side region 20. In other words, there are multiple communication lines along the downlink direction (high side to low side), each of which has a termination diode 31, and there are multiple communication lines along the uplink direction (low side to high side), each of which has a termination diode 31. Since these termination diodes 31 are used to transmit information bits between the high-side region 10 and the low-side region 20, they can be called transmission diodes. Each termination diode 31 has an anode coupled to the LV side region 20 (e.g., a low-side transmitter or receiver) and a cathode coupled to the HV side region 10 (e.g., a high-side transmitter or receiver). Some termination diodes 31 can be configured to transmit information bits from the high-side region 10 to the low-side region 20, while other termination diodes can be configured to transmit information bits from the low-side region 20 to the high-side region 10. It should be appreciated that the number of bits transmitted is fully configurable, with one or more bits being transmitted in each direction.

[0069] Figure 3A and Figure 3B 1 shows a schematic block diagram of a transmission interface circuit between a high-side region and a low-side region according to one or more embodiments. In particular, Figure 3A shows an uplink transmission from the low side transmitter 22 to the high side receiver 12 via the terminating diode 31 and Figure 3B A downlink transmission from a high-side transmitter 13 to a low-side receiver 23 via a terminating diode 31 is shown. A receiver node is defined herein as an input node of a receive path on the receiver side (i.e., a node of a high-side receiver coupled to the cathode of a terminating diode and a node of a low-side receiver coupled to the anode of a terminating diode). The receiver nodes are identified as N1 and N2 in all figures.

[0070] If real-time transmission is not required (for example, if it is sufficient to transmit several bits at a time during a PWM cycle), a possible solution for transmitting information bits to and from the high-side region 10 is to use a termination diode 31 arranged across the isolation termination region 30. Compared with the bootstrap diode 9, the termination diode 31 is smaller in width. For example, the bootstrap diode 9 usually has a low resistivity to quickly charge the bootstrap capacitor 7. Therefore, the bootstrap diode 9 is almost as wide as the termination region 30 (millimeter range) to achieve the lowest possible resistivity. In contrast, the transmission diode 31 should occupy the smallest possible area to leave most of the termination area for the bootstrap diode 9. Therefore, the termination diode 31 can be manufactured using the smallest available technology (for example, with a width of 12μm or less). For this reason, the termination diode 31 can be called a minimum width diode. Therefore, the termination diode 31 can have a minimum width defined by the smallest technology node of the technology that implements the gate driver, and is configured to transmit information bits when the floating HV well is low (i.e., when the lower power switch 3L is turned on). In one example, the termination diode 31 may have a minimum width having a width of 12 μm or less.

[0071] When the floating HV well is low (i.e., when the low-side power switch 3L is turned on), Vs is equal to or substantially equal to Vss (i.e., Vs = ~Vss) and Vcc is equal to or substantially equal to Vb (i.e., Vcc = ~Vb), differential transmission can be performed through the transmission interface circuit. In this case, during the PWM cycle, when the low-side power switch 3L is turned on, it can be said that the voltage domains are aligned. When the voltage domains are aligned, the two minimum width termination diodes 31 can be forward biased and the bit can propagate across the junction. Uplink transmission or downlink transmission can only occur when the voltage domains are aligned, and any transmission will be interrupted when the high-side power switch is turned on, because the termination diode 31 is reverse biased in this case.

[0072] The voltage Vs changes synchronously with the pulse width modulation applied by the microcontroller 5b. For example, when the power transistor 3H is turned on and the power transistor 3L is turned off, Vs is equal to or substantially equal to DC+, which is generally in the range of 200V to 1200V, but is not limited thereto. Vb is 15V higher than Vs during normal operation. In addition, when the power transistor 3L is turned on and the power transistor 3H is turned off, Vs is equal to or substantially equal to DC- (e.g., Vss or 0V). Therefore, Vs alternates between DC+ and DC- according to the PWM command. The PWM applied by the microcontroller 5b indicates the on / off cycle of each power transistor 3H and 3L. Therefore, PWM also indicates the duty cycle of the voltage Vs and when the voltage domain is aligned (i.e., when the power transistor 3L is turned on and Vs=~Vss). The inductive load connected to the Vs node of the inverter branch 1a is driven using the PWM voltage.

[0073] The operating region of the termination diode 31 depends on two voltages: the transmitter output level and the Vs level. The transmitter output level is controlled by the input bit intended to be transmitted, while the Vs level is controlled by the high-side driver 11 acting on the power switch 3H, which in turn is controlled by the microcontroller 5b (by means of the pulse generator 27 and the nMOS level converter 28) to apply PWM to Vs.

[0074] As will be described, an error correction transmission protocol is introduced to distinguish correct transmission from erroneous transmission, where erroneous transmission occurs across the termination diode 31 during dV / dt (diode capacitor coupling) and negative Vs (-Vs or Neg Vs) events. Negative Vs events occur when the high-side potential Vs goes deep underground. Therefore, dV / dt and Neg Vs sensing circuits are also included.

[0075] Figure 4A A schematic block diagram of a high-side receiver circuit is shown in accordance with one or more embodiments. Figure 4B Shown with Figure 4A The corresponding truth table of the high-side receiver circuit is shown in Figure 1. In particular, the high-side receiver circuit Figure 2 The high-side receiver 12 shown in FIG. 1 is implemented in FIG. 1 and receives a differential transmission including a differential signal pair corresponding to an input signal Bitx (ie, information bit) from a low-side transmitter 22 via a terminating diode 31 .

[0076] The high-side receiver circuit includes a Schmitt trigger 41a, a Schmitt trigger 41b, a pull-down resistor Ra-down, a pull-down resistor Rb-down, an event sensor 42 (i.e., a dV / dt and Neg Vs event sensor), an XOR gate 43, a three-port AND gate 44, a three-port AND gate 45, a 0 to 1 delay gate 46, a 0 to 1 delay gate 47, and a set-reset (SR) trigger 48.

[0077] On the low side, differential signaling is used to send each information bit by the termination area 30. In particular, the low side transmitter circuit of the low side transmitter 22 includes two buffers 22a and 22b, which are configured to output differential signals to, as complementary bits Bitx and Bitx! of input signals. Buffer 22b can be a converter that converts the bit Bitx to its complementary bit Bitx!. In other words, the low side transmitter circuit is configured to receive input signal Bitx from a microcontroller 5b or from (inside or outside of the gate driver 5a) memory and convert the input signal Bitx to two complementary signals. Complementary signals are differential signals for transmitting a transmission bit to. Two buffers 22a and 22b can also be used as amplifiers.

[0078] The topology and logic of the high-side receiver circuit 12 are designed to distinguish between correct transmission and incorrect transmission. The sudden switching action of the voltage Vs between the high voltage domain and the low voltage domain makes the gate driver a harsh environment and cannot perform reliable bit transmission. The data may be damaged due to parasitic currents and voltage drops. As long as the high-side voltage domain is aligned with the low-side voltage domain (i.e., when the low-power switch 3L is turned on) and there is no interference affecting the transmission, the bit to be transmitted can be written into the SR flip-flop.

[0079] During each PWM cycle, Vs is high for a portion of the PWM cycle and switches to low for the rest of the PWM cycle. Since transmission occurs only when Vs=DC- (e.g., Vs=Vss), the time when Vs is low (Vs=Vss) should be greater than the "0 to 1 delay" (see, e.g., elements 46 and 47) plus some other transmission delays (e.g., diode conduction delay, delays at the receiver input nodes N1 and N2 due to parasitic resistance and capacitance, and Schmitt trigger and logic gate propagation delays) to successfully transmit information via the terminating diodes. The "0 to 1 delay" provided by elements 46 and 47 is introduced to eliminate eventual false glitches that may appear at the output of the three-input AND gate described below. The "0 to 1 delay" time can be selected so that this delay time plus the transmission delay meets the above requirements to allow transmission and at the same time filter out NegVs events and ring in the first part of the low phase. However, there is a trade-off between transmission and false transmission rejection in each PWM cycle.

[0080] The input signal Bitx represents the information bit to be written into the output buffer of the high-side receiver 12. The low-side transmitter 22 sends two complementary (ie, differential) bits Bitx and Bitx! as differential transmission. The two bits must be complementary values ​​to each other and are used to help distinguish correct transmission from erroneous transmission. For example, if the two bits are the same, the receiver circuit 12 can determine that the transmission is an erroneous transmission and does not update its output buffer. Therefore, two terminal diodes 31a and 31b are used to send a single information bit (ie, two terminal diodes 31 are used for each information bit), and the other terminal diode 31s is used by the event sensor 42 to detect negative dV / dt events and / or Neg Vs events.

[0081] Figure 4A The receiver circuit 12 shown shows a configuration for sending a single transmission bit (e.g., Bitx) using a differential receiver branch including signal paths A and B. According to this arrangement, if three information bits (e.g., Bitx, Bity, and Bitz) are being sent by the low side, additional differential receiver branches will be added, each of which has its own SR trigger. Each differential receiver branch can be shared in a similar manner and therefore coupled to the output of the event sensor 42. Here, the event sensor signal path S can be coupled to each AND gate of each differential receiver branch. Therefore, seven termination diodes 31 will be used for three-bit transmission, including three pairs of termination diodes for sending information bits and one termination diode for the event sensor 42.

[0082] As described above, the two bits Bitx and Bitx! must be complementary values ​​to each other for valid transmission. The receiver circuit 12 reads the differential digital voltage signal and stores one bit as Bithox in the high-side output buffer. In addition, when the SR flip-flop 48 is allowed to be written, the output of the event sensor 42 is high (ie, S=1). In other words, writing is allowed when there is no negative dV / dt or Neg Vs event. The output of the event sensor 42 can be referred to as an event signal S, which indicates whether there is a write (valid) event (writing is enabled during the event) or an invalid event (writing is disabled during the event). Negative dV / dt events and Neg Vs events are called invalid events.

[0083] Figure 4B The truth table shown shows a column for each variable at each stage of the receiver circuit, where valid bits at Bithox are indicated as 0 or 1, and invalid bits are indicated as "*". Invalid bits may be the result of voltage domain misalignment (e.g., when the high-side switch 3H is turned on) or due to errors detected by the event sensor 42. When an invalid bit occurs, the SR flip-flop 48 is not written and the output buffer is not updated or refreshed.

[0084] An input voltage at the Schmitt trigger exceeding the upper threshold causes the Schmitt trigger to change its output to a logic 1, while an input voltage below the lower threshold causes the Schmitt trigger to change its output to a logic 0.

[0085] Returning to the function of the pull-down resistors Ra-down and Rb-down, each resistor connects the receiver input at the receiver node to Vs on the high side when the terminating diode 31a or 31b is off. For example, when the high side switch 3H is on, the receiver input can be connected to 1200V.

[0086] When the voltage domains are aligned, the low-side switch 3L is turned on and Vs is substantially equal to Vss (i.e., 0V). In this case, Vb is also approximately equal to Vcc. Only in this case can the termination diodes be intentionally selectively turned on: diode 31a is turned on and diode 31b is turned off, and vice versa, diode 31b is turned on and diode 31a is turned off. In all other cases, the diodes are always all turned on or all turned off at the same time.

[0087] Both dV / dt and negVs are "common mode events". While they should not generate an erroneous differential transmission, the diodes and receivers are not identical and may be mismatched. Due to the mismatch, in certain critical cases, both dV / dt and neg Vs can force current sufficient to turn on the receiver in only one of the diodes (e.g., a differential pair) and generate an erroneous transmission. The sensors used to blank the transmission are similar to the receiver (i.e., resistor Ra-down and Schmitt trigger 41a), but are intentionally more sensitive to overcome any possible mismatch.

[0088] Returning to the case of voltage domain alignment, when the diode turns on, the voltage at the receiver node rises above the upper threshold of the Schmitt trigger. This happens only when Vs=Vss=0V and the transmitter 22 in the low side is sending a logic 1 (Vforward=(Vcc-Vs)>Von=1V). In other words, the termination diode can be forward biased only when the output of buffer 22a or 22b is 1. When the output of buffer 22a or 22b is 0, the termination diode remains reverse biased and turns off.

[0089] Since Vcc is equal to 15V and Vs is equal to 0V when the low-side switch 3L is turned on, the termination diode can transmit when its input is a logic 1. Therefore, when Vs is equal to 0V, the termination diode can transmit when the input bit Bitx is 1 and the termination diode 31b can transmit when the input bit Bitx is 0 (i.e., when Bitx! is 1).

[0090] During the low-side to high-side transmission, current flows from the low side to the high side through the termination diode 31a or 31b. This current sinks the current from the low side through the termination diode and through the pull-down resistor to Vs. The voltage drop (ΔV) applied across the pull-down resistor by the absorbed current keeps the voltage at the receiver node greater than the upper Schmitt trigger threshold. For example, when the termination diode is turned on, the voltage at the receiver node can be configured to exceed the upper Schmitt trigger threshold. When the voltage exceeds its upper threshold, the Schmitt trigger can output a logic 1.

[0091] When the terminating diode is turned off (i.e., when the high-side power transistor 3H is turned on), the voltage at the receiver node is equal to Vs (e.g., 1200 V), which is greater than the voltage at the anode regardless of the input bit Bitx. For example, when the output of the buffer 22a or 22b is 1, the voltage at the anode is at most 15 V. Therefore, there is a strong reverse bias across the terminating diode and the communication channel through the terminating diode is completely interrupted in these cases.

[0092] Since bits Bitx and Bitx! are complementary, one of the terminating diodes 31a and 31b will be forward biased and the other will be reverse biased. It should be noted that the diode series resistance (e.g., about 10 kilo-ohms) limits the minimum value of the pull-down resistor (and the pull-up resistor in other embodiments). This may limit the minimum transmission time due to the delay in turning on and off the terminating diodes.

[0093] In contrast, when the voltage domains are not aligned, the high-side switch 3H is turned on, Vs remains high, and thus both terminating diodes 31a and 31b are reverse biased. In this case, the transmission of the information bit is blocked.

[0094] Figure 4C Shows Figure 4A Schematic block diagram of the high-side receiver circuit shown in FIG. 1 , where Bitx = 1. In contrast, Figure 4D Shows Figure 4A Schematic block diagram of a high-side receiver circuit shown in , where Bitx=0. It can be seen that when Bitx=1, the terminating diode 31a is forward biased (ie, turned on) and the terminating diode 31b is reverse biased (ie, turned off).

[0095] Schmitt triggers 41a and 41b are configured to forward their input bits to their output terminals. Thus, a logic high "1" bit received at their input terminals is output as a logic high "1" bit, and a logic low "0" bit received at their input terminals is output as a logic low "0" bit.

[0096] XOR gate 43 is configured to ensure that the bits output from Schmitt triggers 41a and 41b are complementary. This is to ensure that voltage Vs is low, indicating that the voltage domains are aligned and there is no interference or other errors that may produce erroneous transmission. For example, when voltage Vs is high, the outputs of both Schmitt triggers 41a and 41b are logic 0, indicating that the voltage domains are not aligned. Writing to SR flip-flop 48 is enabled only when the output of XOR gate 43 is logic 1. Therefore, when voltage Vs is high, writing to SR flip-flop 48 is prevented by XOR gate 43.

[0097] AND gates 44 and 45 are each configured to receive three inputs: one from event sensor 42, one from XOR gate 43, and one from its corresponding Schmitt trigger 41a or 41b. The output of event sensor 42 is high except when a negative dV / dt event or a Neg Vs event occurs. Therefore, when writing to SR flip-flop 48 is enabled, the output of event sensor 42 is high (i.e., S=1), and when writing to SR flip-flop 48 is disabled, the output of event sensor 42 is low (i.e., S=0). In addition, as described above, writing to SR flip-flop 48 is enabled only when the output of XOR gate 43 is logic 1.

[0098] In the case where both the outputs of event sensor 42 and XOR gate 43 are high, SR flip-flop 48 will be set or reset according to the bit value of Bitx. When Bitx=1, AND gate 44 will output logic 1 and AND gate 45 will output logic 0. In this case, the set input of SR flip-flop 48 will be high (enabled) after the delay gate is delayed from 0 to 1. Therefore, the output of SR flip-flop 48 will be set or refreshed to logic 1 (i.e., Bithox=1). In this case, the reset input of SR flip-flop 48 will be low and have no effect on writing to the output buffer.

[0099] Delay gate 46 introduces a "0 to 1 delay" to eliminate eventual false glitches that may appear at the output of three-input AND gate 44. For example, when the inputs of XOR gate 43 switch simultaneously (e.g., from 11 to 00), a positive glitch may occur due to the topology of XOR gate 43, causing XOR gate 43 to output 1 instead of 0 for a short period of time during the input transition. The duration of the "0 to 1 delay" is set longer than the time required for the output of XOR gate 43 to stabilize. In this way, any change in the output of three-input AND gate 44 that is less than the "0 to 1 delay" will be ignored and filtered out, and can therefore be used to filter out false glitches that may occur during the input transition at XOR gate 43. Without filtering these false glitches, these glitches may propagate to SR flip-flop 48 and cause incorrect bits to be stored at Bithox.

[0100] Conversely, when Bitx=0, AND gate 44 will output a logic 0 and AND gate 45 will output a logic 1. In this case, the reset input of SR flip-flop 48 will be high (enabled) after delay gate 47 delays 0 to 1. Therefore, the output of SR flip-flop 48 will be set or refreshed to logic 0 (i.e., Bitx=0). In this case, the set input of SR flip-flop 48 will be low and have no effect on writing to the output buffer.

[0101] In a manner similar to delay gate 46, delay gate 47 introduces a "0 to 1 delay" to eliminate eventual false glitches that may appear at the output of three-input AND gate 45. For example, when the inputs of XOR gate 43 switch simultaneously (e.g., from 11 to 00), due to the topology of the XOR gate, a positive glitch may occur, causing XOR gate 43 to output 1 instead of 0 for a short period of time during the input transition. The duration of the "0 to 1 delay" is set longer than the time required for the output of XOR gate 43 to stabilize. In this way, any changes in the output of three-input AND gate 45 that are less than the "0 to 1 delay" will be ignored and filtered out, and can therefore be used to filter out false glitches that may occur during the input transition at XOR gate 43. Without filtering these false glitches, these glitches may propagate to SR flip-flop 48 and cause incorrect bits to be stored at Bithox.

[0102] The enable signal output by the AND gates 44 and 45 to enable the set input or the reset input of the SR flip-flop 48 may also be referred to as a strobe signal.

[0103] In view of the above, the high-side receiving circuit 12 has the following features.

[0104] The high-side receiving circuit 12 reads the differential digital voltage signal (square wave pulse) and stores one bit.

[0105] Errors may occur due to disturbance events such as significant parasitic currents due to stray capacitance of the junction and sudden changes in the high-side voltage level (I=C*dV / dt). Disturbance events include negative dV / dt events and Neg Vs events. During negative dV / dt events, parasitic currents are induced by charging and discharging the diode capacitance of the termination diode 31 during the falling Vs transition. These "common mode" disturbance events can be detected to prevent erroneous writes to the SR flip-flop 48.

[0106] The pull-up / pull-down loads and inverter thresholds should be carefully sized so that transmission can proceed despite the distribution effect of the parasitic resistance of the terminating diodes.

[0107] High dVs / dt currents and negative Vs can create spikes (voltage protection diodes of transistors connected to anode or cathode) and glitches on the receiver side.Differential transmission and symmetrical paths minimize the possibility of errors due to common mode interference.

[0108] Dedicated sensors for detecting dVs / dt and Neg Vs events compensate for offsets introduced by mismatches in the differential branches (pull-up / pull-down resistors, termination diodes, temperature, etc.) that can generate erroneous transmissions in the presence of small disturbances. The sensors suppress transmissions in the presence of dV / dt and negVs.

[0109] In the presence of noisy input, the Schmitt trigger gives a clean output.

[0110] A sensor node is defined herein as an input node of an event sensor on the receiver side. A receiver node is defined herein as an input node of a receiving path on the receiver side (i.e., a node of a high-side receiver coupled to the cathode of a terminating diode and a node of a low-side receiver coupled to the anode of a terminating diode). The sensing node is more sensitive than the receiver node due to having a higher impedance to allow interruption of erroneous transmission. In the event of erroneous transmission, the output state of the SR trigger 48 remains unchanged, and the last valid data at the output buffer is maintained. In particular, when both the set and reset inputs of the SR trigger 48 are set to logic 0, the output state of the SR trigger 48 remains the same as the last valid data stored in the output buffer.

[0111] Strong differential signals (desired bits) can cause transitions, while common mode signals such as dV / dt current or Vs oscillations do not cause erroneous transmissions for large or small interferences. Any burrs that last less than the "0 to 1 delay" filtering time will be eliminated by the "0 to 1 delay" in the strobe signal. Therefore, whenever the high-side voltage domain is aligned with the low-side voltage domain and there is no common-mode interference affecting the transmission, the transmitted bit Bitx can be stored in the SR trigger 48 until the next PWM cycle. According to this technology, the bit can be refreshed or changed safely within the PWM cycle where the shutdown duration is greater than the "0 to 1 delay". In addition, when the voltage Vs is high, since both receiver nodes (i.e., the input nodes of Schmitt triggers 41a and 41b) are pulled down, the XOR gate 43 prevents writing. In this case, when the voltage Vs is high, the last valid bit at the output buffer will remain until the next alignment of the voltage domain.

[0112] Figure 5A 1 shows a schematic block diagram of a low-side receiver circuit in the case where the differential input signal is equal to 1 according to one or more embodiments. Figure 5BFIG. 1 is a schematic block diagram of a low-side receiver circuit according to one or more embodiments when a differential input signal is equal to 0. In particular, the low-side receiver circuit Figure 2 The low-side receiver 23 is shown implemented in the figure and receives a differential transmission including a differential signal pair corresponding to an input signal Bitx (ie, information bits) from the high-side transmitter 13 via a terminating diode 31 .

[0113] The low-side receiver circuit includes a 3-level low-side receiver core 51a, a 3-level low-side receiver core 51b, a pull-up resistor Ra-up, a pull-up resistor Rb-up, an event sensor 52 (i.e., a dV / dt and Neg Vs event sensor), an XOR gate 53, a three-port AND gate 54, a three-port AND gate 55, a 0-to-1 delay gate 56, a 0-to-1 delay gate 57, and an SR trigger 58. The operation of the 3-level low-side receiver core 51a is similar to a Schmitt trigger because the 3-level low-side receiver core 51a is configured with an upper threshold and a lower threshold, and generates a logic high output or a logic low output based on the voltage at the receiver node compared to the threshold level.

[0114] On the high side, differential signaling is used to send each information bit through the termination area 30. In particular, the high-side transmitter circuit of the high-side transmitter 13 includes two buffers 13a and 13b, which are configured to output a differential version of the input signal (Bitx) as Bitx itself and its complementary bit Bitx! . Buffer 13b can be a converter that transforms the bit Bitx into its complementary bit Bitx! . In other words, the high-side transmitter circuit is configured to receive the input signal Bitx from the diagnostic block 15 and convert the input signal Bitx into two complementary bits. This encoding (conversion into differential bits) allows error transmission detection and rejection. The two buffers 22a and 22b can also be used as amplifiers.

[0115] Similar to Figure 4A The topology and logic of the high-side receiver circuit 23 are designed to distinguish between correct transmission and erroneous transmission. The sudden switching action of the voltage Vs between the high voltage domain and the low voltage domain makes the gate driver a harsh environment and cannot perform reliable bit transmission. The data may be damaged due to parasitic current and voltage drop. As long as the high-side voltage domain is aligned with the low-side voltage domain (i.e., when the low power switch 3L is turned on) and there is no interference affecting the transmission, the transmitted bit can be written into the SR trigger.

[0116] The operations of the XOR gate 53, the three-port AND gate 54, the three-port AND gate 55, the 0-to-1 delay gate 56, the 0-to-1 delay gate 57, and the SR flip-flop 58 are basically similar to those of the combination FIG. 4A to FIG. 4D Their equivalent components are described in Figure 5A and 5BIn the case of , as long as writing is enabled, the SR flip-flop 58 outputs the output bit Bitlox to the low-side output buffer according to the input bit Bitx.

[0117] Although the termination diode 31s is reverse biased during the negative dV / dt event, current can flow into the termination diode 31s in any way due to the voltage change across its parasitic capacitance. In addition, the neg Vs event is caused by the high forward bias current with the same direction as the negative dv / dt current. Therefore, when the write SR flip-flop 58 is enabled, the output of the event sensor 52 is high (i.e., S=1), and when the write SR flip-flop 58 is disabled, the output of the event sensor 52 is low (i.e., S=0). In addition, the write SR flip-flop 58 is enabled only when the output of the XOR gate 53 is logic 1, which indicates that the voltage domains are aligned.

[0118] An input voltage at the 3-level low-side receiver core that exceeds the upper threshold causes the 3-level low-side receiver core to change its output to a logic one, while an input voltage that is below the lower threshold causes the 3-level low-side receiver core to change its output to a logic zero.

[0119] During a positive dV / dt event, the parasitic current in the termination diode 31 flows in the opposite direction compared to the transmission direction when the diode is conducting, so writing is disabled because the receivers all give a 0 output (ie, the inputs to the XOR gate are all 0).

[0120] Returning to the function of the pull-up resistors Ra-up and Rb-up, each resistor connects the receiver input at the receiver node to Vdd in the low side when the terminating diode 31a or 31b is off. For example, Vdd can be an internally generated regulated voltage of 5.5V, and when the high side switch 3H is on, the receiver input can be connected to 5.5V.

[0121] When the voltage domains are aligned, the low-side switch 3L is turned on and Vs is substantially equal to Vss (i.e., 0V). When the diode is turned on, the voltage at the receiver node drops below the lower threshold of the 3-stage low-side receiver core. This only happens when Vs=Vss=0V and the transmitter 13 in the high side is sending a logic 0 (Vforward=(Vdd-Vs)>Von=1V). In other words, the termination diode can be forward biased only when the output of the buffer 13a or 13b is 0. Therefore, when Vs is equal to 0V, the termination diode 31a can transmit when the input bit Bitx is 0, and the termination diode 31b can transmit when the input bit Bitx is 1 (i.e., when Bitx! is 0). When the output of the buffer 13a or 13b is 1, the termination diode remains reverse biased and turns off.

[0122] During the transmission from the high side to the low side, the current flows from the low side to the high side through the termination diode 31a or 31b. This current absorbs the current from the low side, from Vdd through the pull-up resistor, and through the termination diode to the high side. Due to the voltage drop (ΔV) applied across the pull-up resistor by the absorption current, the voltage at the receiver node is greater than 0V but less than the lower threshold voltage of the 3-level low-side receiver core. For example, the lower threshold voltage can be 3V, which can be a half-scale voltage. When the termination diode is turned off, the voltage at the receiver node is equal to Vdd.

[0123] The supply voltages to the high-side amplifier / buffers 13a and 13b are Vb and Vs. Therefore, the logic high output (i.e., logic 1) from the amplifier / buffer is equal to Vb (i.e., Vs plus Vcc), while the logic low output (i.e., logic 0) from the amplifier / buffer is equal to Vs.

[0124] When the voltage domain is not aligned, Vs equals the maximum high side voltage (e.g., 1200V), and the output of the high side amplifier / buffer equals Vb (e.g., 1215V, where Vcc equals 15V) or equals Vs (e.g., 1200V) when outputting logic 1. In either case, since local power supplies such as Vcc or Vdd are only equal to, for example, 5.5V and the termination diode is turned off, there is a strong reverse bias at both ends of the termination diode. The communication channel through the termination diode is completely interrupted in these cases. In addition, since the receiver node is connected to Vdd (e.g., 5.5V) by a pull-up resistor when the diode is turned off, the voltage at the receiver node is sensed as a logical high level by the 3-level low side receiver core. The 3-level low side receiver core then outputs a logical high value.

[0125] On the other hand, when the voltage domains are aligned, Vs is equal to Vss (i.e., 0V). In this case, since Vb is equal to Vs plus 15V (i.e., 0V+15V), the output of the high-side amplifier / buffer is equal to Vb (e.g., 15V) when outputting a logic 1 or equal to Vs (e.g., 0V) when outputting a logic 0. In the case where the buffer 13a or 13b outputs a logic 0 (i.e., 0V, when Vs is equal to 0V), the corresponding termination diode 31a or 31b is forward biased due to the presence of a higher voltage (i.e., Vdd-ΔV) at the receiver node (i.e., at the anode of the termination diode). Turning on the termination diode causes the voltage at the receiver node to drop below the lower threshold of the 3-stage low-side receiver core, and the 3-stage low-side receiver core outputs a logic 0.

[0126] Fig. 6A 1 shows a schematic circuit diagram of a high-side event sensor according to one or more embodiments. In particular, the high-side event sensor is Figure 4AAn example of an event sensor 42 is shown in FIG. 1 , wherein its input is coupled to the cathode of the terminating diode 31s and its output is coupled to AND gates 44 and 46. The event sensor 42 is configured to generate a signal S for distinguishing correct transmission from erroneous transmission, wherein S=1 indicates that the write SR trigger is enabled and S=0 indicates that the write SR trigger is not allowed or disabled.

[0127] Figure 6B 1 shows a schematic circuit diagram of a low-side event sensor according to one or more embodiments. In particular, the high-side event sensor is Figure 5A An example of an event sensor 52 is shown in FIG. 1 , wherein its input is coupled to the anode of the terminating diode 31s and its output is coupled to AND gates 54 and 56. The event sensor 52 is configured to generate an event signal S for distinguishing correct transmission from erroneous transmission, wherein S=1 indicates that the write SR trigger is enabled and S=0 indicates that the write SR trigger is not allowed or disabled.

[0128] Figure 6C A graph plotting voltage versus time (i.e., within a PWM cycle) during which different voltage events or phases occur according to one or more embodiments is shown. In particular, the graph shows the occurrence of the following events: a negative dV / dt event during which writes are disabled by event sensors 42 and 52; a Neg Vs event during which writes are disabled by event sensors 42 and 52; a low Vs event during which the voltage domains are aligned and writes are enabled by the high-side receiver circuit and the low-side receiver circuit; a positive dV / dt event during which writes are disabled by the XOR gates 43 and 53 due to the equal inputs to the XOR gates 43 and 53; and a high VS event during which the voltage domains are not aligned and writes are disabled by the XOR gates 43 and 53 due to the equal inputs to the XOR gates 43 and 53. Therefore, the only time period during which writes are enabled by the low-side receiver circuit and the high-side receiver circuit is during the low Vs event.

[0129] Back to Fig. 6A Although the terminating diode 31s is reverse biased during the negative dV / dt event, current may flow into the terminating diode 31s anyway due to the voltage change across its parasitic capacitance. Furthermore, the neg Vs event is caused by the high forward bias current having the same direction as the negative dv / dt current. The event sensor 42 is configured to detect this current flow and change its output to a logic 0 in response to detecting this current flow.

[0130] The Vs falling phase (i.e., negative dV / dt event) and the Neg Vs event cause the Zener diode and diode device 61 of the event sensor 42 to turn on, which causes the output of the inverter 62 of the event sensor to switch from logic 1 to logic 0. A single diode 63 protects the inverter 62 from the positive dV / dt current. The inverter 62 is a CMOS inverter designed to have a strong output pull-down (i.e., wide / short nmos) and a weak pull-up (narrow / long pmos) to increase the sensitivity range and pre-filter the Vs oscillation in its low phase. In this way, the inverter 62 quickly forces its output S low to suppress transmission, and slowly pulls S high to allow transmission. For example, the inverter 62 can be designed to make its zero threshold lower than the zero threshold of the Schmitt trigger of the receiving node. The result is enhanced sensitivity and pre-filtering. Resistor 64 pulls down the sense node (ie, the input of inverter 62), thereby confirming the steady-state condition (ie, whether Vs is high or low).

[0131] The positive dV / dt, Vs rising phase is not critical for event detection by the event sensor 42 because the receiver circuit topology substantially avoids false transmissions and the gate driver has been designed for the desired current capability in the previous phase (i.e., in the low Vs phase). Here, the common mode current is forced through the pull-down resistors Ra-down and Rb-down, pulling both receiver nodes at the high-side receiver 12 below Vs. Since both nodes N1 and N2 are moved below the local ground away from the Schmitt trigger threshold, the Schmitt trigger rejects such a signal before the XOR gate, and the SR flip-flop 48 cannot be rewritten. In other words, both Schmitt triggers will output 0 because their inputs are both off the positive threshold of the Schmitt trigger. Then, of course, the output of the XOR gate will be 0 and the flip-flop will not be rewritten.

[0132] Steering Figure 6B During the neg dV / dt period, the diode 31s is reverse biased, but due to the discharge of the parasitic capacitance of the terminating diode, current can flow in the diode 31s, except that the negdV / dt current originates from the discharge of the parasitic capacitance and the Neg Vs current originates from the forward biased diode, as in the neg V S The event sensor is triggered as in the case of a Neg Vs event. At positive dV / dt, diode 31s pulls the input node of inverter 66 above Vcc (clamped by protection diode 67) and nothing happens at the event sensor output. Therefore, no current flows through the termination diode unless it is a dV / dt current or a large direct bias current peak typically associated with a Neg Vs event.

[0133] The Vs falling phase (i.e., negative dV / dt event) and the Neg Vs event cause the Zener diode and diode device 65 of the event sensor 52 to turn on, which causes the output of the inverter 66 of the event sensor 52 to switch from logic 0 to logic 1. Another inverter 69 is used to invert the output of the inverter 66 to convert the event signal S into an error flag (S=0), so that the rest of the logic of the receiver circuit 23 (e.g., AND gates 54 and 55) can recognize and properly handle the error flag. A single diode 67 protects the inverter 66 from the positive dV / dt current. The inverter 66 is a CMOS inverter that is designed to have a strong output pull-up (i.e., wide / short pmos) and a weak pull-down (narrow / long nmos) to increase the sensitivity range and pre-filter the Vs oscillation in its low phase. In this way, the inverter 66 quickly forces its output S low to inhibit transmission, and slowly pulls S high to allow transmission. For example, inverter 66 can be designed so that its zero threshold is lower than the zero threshold of the Schmitt trigger of the receiving node. The result is enhanced sensitivity and pre-filtering. Resistor 68 pulls up the sense node (i.e., the input of inverter 66) to confirm the steady-state condition (i.e., whether Vs is high or low).

[0134] The positive dV / dt, Vs rising phase is not critical for event detection by the event sensor 52 because the receiver circuit topology substantially avoids false transmissions and the gate driver has already been set to the desired current capability in the previous phase (i.e., in the low Vs phase). Here, the common mode current is forced through the pull-up resistors Ra-up and Rb-up, thereby pulling both receiver nodes at the low-side receiver 23 above Vcc (i.e., clamped one diode drop above Vcc by the protection diode 67). Since the inputs to the XOR gate are the same, such a signal is rejected by the XOR gate and therefore cannot rewrite the SR flip-flop 58.

[0135] For example, during a positive dV / dt event, both receiver nodes of the low-side receiver 23 are pulled above Vcc, but the 3-stage receiver core is only sensitive when the input nodes N1 and N2 are pulled down compared to Vcc. Therefore, the output of the XOR gate 53 is a logic 0, causing the outputs of both AND gates 54 and 55 to be logic 0, and thereby preventing the SR flip-flop 58 from being written or refreshed.

[0136] Due to the mismatch, false transmissions may occur in some small intervals of dVs / dt values.Being sensitive to current, the event sensors 42 and 52 are configured to interrupt any transmission as a false transmission.

[0137] In view of the above, when the voltage domains are aligned (Vs = ~Vss and Vb = ~Vcc), bits can be transmitted bidirectionally between the high-side region 10 and the low-side region 20 using small HV termination isolation diodes as a whole, where each diode is responsible for transmitting in a specific uplink or downlink direction. Compared with existing bit transmission solutions, this solution reduces silicon area and power dissipation at the expense of small delays. Such an arrangement also has the advantage of being implemented in the internal circuits of the gate driver inside the power module.

[0138] High voltage gate drivers are usually designed with a single output current level for driving an external power switch. Selecting the right output current level is not simple, which forces multiple iterations in gate driver design development. The possibility to dynamically change and reconfigure the current level of the current pulses (control signals) in a single gate driver design leads to a one system fits all approach with greater flexibility and resulting in a shorter time to market.

[0139] For example, if the gate current is too low, the delay and power dissipation into the power switch increases, both with negative consequences. On the other hand, too much current can speed up the power switch and introduce electromagnetic interference that interferes with nearby electronic circuits and prevents them from meeting certain standards. Therefore, using the concepts described herein, a multi-bit configuration message (e.g., a 3-bit message) can be sent from the low side to the high side to configure the output current of the high side driver itself as determined by the microcontroller 5b.

[0140] Since this is a case of parallel transmission, all the bits constituting the multi-bit configuration message are sent simultaneously. After converting each of them into its differential version, each of them is fed to a dedicated pair of termination diodes and a dedicated differential receiver (the input bit Bitx is converted into a bit pair consisting of Bitx itself and its complementary bit Bitx!). The SR flip-flop 48 ( Figure 4A ) stores a single bit version equal to Bitx.

[0141] Furthermore, the same bits are also used to configure the output current of the low side driver, but this is straightforward since the microcontroller 5b interfaces directly with the low side and no HV communication is required.

[0142] In the same gate driver IC 5a, communication in the opposite direction from the high side to the low side can also be used for desaturation diagnostics and detection of other abnormal events. Desaturation is a very high intensity overcurrent in the power switch, such as when a low ohmic short circuit occurs and the current reaches ten times the maximum load current (as an example). If a desaturation event occurs on the high side, a single warning bit can be sent from the high side to the low side, and then ultimately sent to the microcontroller 5b.

[0143] Although various embodiments have been described, it will be apparent to one of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the present disclosure. For example, although embodiments are described in the context of a monolithic gate driver IC having two voltage domains, the concepts are also applicable to a monolithic integrated circuit having two voltage domains (HV and LV) isolated by a termination region, where information communication between the domains is beneficial. Therefore, the present invention is not limited except in accordance with the appended claims and their equivalents. With respect to the various functions performed by the components or structures (components, devices, circuits, systems, etc.) described above, unless otherwise indicated, the terms used to describe such components (including references to "devices") are intended to correspond to (i.e., functionally equivalent to) any component or structure that performs the specified function of the described component, even if the disclosed structure is not structurally equivalent to the functions in the exemplary embodiments of the invention shown herein.

[0144] In addition, the attached claims are hereby incorporated into the detailed description, wherein each claim can be independently presented as a separate example embodiment. Although each claim can be independently presented as a separate example embodiment, it should be noted that although a dependent claim can refer to a specific combination with one or more other claims in a claim, other example embodiments can also include a combination of a dependent claim with the subject matter of each other independent claim or dependent claim. Unless it is stated that a specific combination is not intended, such a combination is proposed herein. In addition, even if the claim does not directly refer to an independent claim, it is intended that the features of a claim are included in any other independent claim.

[0145] It should also be noted that the methods disclosed in the specification or claims can be implemented by a device having means for performing each of the corresponding actions of these methods.

[0146] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in the specification or claims may not be interpreted as being in a specific order. Therefore, unless these actions or functions are not interchangeable for technical reasons, the disclosure of multiple actions or functions does not limit these actions or functions to a specific order. In addition, in some embodiments, a single action may include multiple sub-actions or may be divided into multiple sub-actions. Unless explicitly excluded, such sub-actions may be included and such a single action may be part of the disclosure.

[0147] According to certain implementation requirements, the embodiments provided herein can be implemented in hardware or software. The implementation can be performed using a digital storage medium (e.g., a floppy disk, DVD, Blu-ray, CD, RAM, ROM, PROM, EPROM, EEPROM, or FLASH memory) on which an electrically readable control signal is stored, and the electrically readable control signal cooperates (or can cooperate) with a programmable computer system to perform the corresponding method. Therefore, the digital storage medium can be computer readable.

[0148] Instructions may be executed by one or more processors, such as one or more central processing units (CPUs), digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuit systems. Thus, the term "processor" as used herein refers to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules. Likewise, the techniques may be fully implemented in one or more circuits or logic elements.

[0149] Therefore, the techniques described in the present disclosure may be implemented at least in part in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented in one or more processors, including one or more microprocessors, DSPs, ASICs, or any other equivalent integrated or discrete logic circuits, and any combination of such components.

[0150] The control unit including the hardware may also perform one or more of the techniques described in the present disclosure. Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in the present disclosure. The software may be stored on a non-transitory computer-readable medium such that the non-transitory computer-readable medium includes a program code or program algorithm stored thereon that causes a computer program to perform the steps of a method when the program code or program algorithm is executed.

[0151] Although various exemplary embodiments have been disclosed, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention, which will achieve some of the advantages of the concepts disclosed herein. It will be apparent to those skilled in the art that other components performing the same functions may be appropriately replaced. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be noted that the features explained with reference to a particular figure may be combined with the features of other figures, even in those cases where not explicitly mentioned. Such modifications to the general inventive concept are intended to be covered by the appended claims and their legal equivalents.

Claims

1. A half-bridge gate driver, comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a termination region between the high-side region and the low-side region, the termination region being configured to isolate the first voltage domain from the second voltage domain; a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor; a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, the low-side power transistor and the high-side power transistor forming a half-bridge; as well as a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, wherein each of the plurality of termination diodes comprises an anode coupled to the low-side gate driver and a cathode coupled to the high-side gate driver, The first voltage domain and the second voltage domain are aligned when a high-side ground voltage is substantially equal to a low-side ground voltage and a high-side supply voltage is substantially equal to a low-side supply voltage.

2. The half-bridge gate driver according to claim 1, wherein: the plurality of termination diodes being configured to transmit the information bits between the high-side region and the low-side region when the first voltage domain is aligned with the second voltage domain; And the plurality of termination diodes are configured to interrupt transmission of the information bit between the high-side region and the low-side region if the first voltage domain is not aligned with the second voltage domain.

3. The half-bridge gate driver according to claim 2, wherein: When the low-side power transistor is turned on, the first voltage domain is aligned with the second voltage domain; as well as When the high-side power transistor is turned on, the first voltage domain is misaligned with the second voltage domain.

4. The half-bridge gate driver according to claim 1, wherein: A first pair of termination diodes among the plurality of termination diodes is configured to transmit a first information bit from the low-side region to the high-side region via differential signaling; and A second pair of termination diodes among the plurality of termination diodes is configured to transmit a second information bit from the high-side region to the low-side region through the differential signaling.

5. The half-bridge gate driver according to claim 4, wherein: The first information bit includes current pulse information, and the high-side gate driver is configured to receive the first information bit and set a current level of a current pulse for driving the high-side power transistor based on the current pulse information.

6. The half-bridge gate driver according to claim 4, wherein: The second information bit includes diagnostic information corresponding to an inverter branch to which the high-side power transistor and the low-side power transistor are coupled.

7. The half-bridge gate driver according to claim 6, wherein: The diagnostic information indicates an overcurrent condition at the inverter branch.

8. The half-bridge gate driver according to claim 4, wherein: The low-side region is coupled to a microcontroller, and the low-side region is configured to receive the first information bit from the microcontroller and to send the second information bit to the microcontroller.

9. The half-bridge gate driver according to claim 8, wherein: The low-side region is configured to receive at least one control signal from the microcontroller in response to sending the second information bit to the microcontroller, the at least one control signal being used to control the high-side gate driver and the low-side gate driver.

10. The half-bridge gate driver according to claim 1, further comprising: a first disturbance detection diode disposed in the termination region and configured to enable a first event detection current to flow from the low-side region to the high-side region during at least one disturbance event and to prevent the first event detection current from flowing from the low-side region to the high-side region in the absence of the at least one disturbance event; a first event sensor disposed in the high-side region and configured to detect the first event detection current and interrupt transmission to the high-side region through at least one of the plurality of termination diodes in response to detecting the first event detection current; a second disturbance detection diode disposed in the termination region and configured to enable a second event detection current to flow from the low-side region to the high-side region during the at least one disturbance event and to prevent the second event detection current from flowing from the low-side region to the high-side region in the absence of the at least one disturbance event; as well as A second event sensor is disposed in the low-side region and is configured to detect the second event detection current and interrupt transmission to the low-side region through at least another one of the plurality of termination diodes in response to detecting the second event detection current.

11. The half-bridge gate driver according to claim 10, wherein: The at least one disturbance event includes at least one of a negative Vs event and a falling dVs / dt event, wherein Vs is a high-side ground voltage.

12. The half-bridge gate driver according to claim 1, further comprising: a low-side transmitter disposed in the low-side region and configured to transmit at least one uplink information bit; a high-side receiver disposed in the high-side region and configured to receive the at least one uplink information bit from the low-side transmitter; a high-side transmitter disposed in the high-side region and configured to transmit at least one downlink information bit; as well as A low-side receiver is disposed in the low-side region and is configured to receive the at least one downlink information bit from the high-side transmitter.

13. The half-bridge gate driver of claim 12, wherein: The high-side receiver includes a first set-reset flip-flop configured to store one of the at least one uplink information bit; as well as The low-side receiver includes a second set-reset flip-flop configured to store one of the at least one downlink information bit.

14. The half-bridge gate driver of claim 13, wherein: The high-side receiver is configured to: receive the uplink information bit through differential signaling including two uplink signals, and store the uplink information bit at the first set-reset flip-flop if the two uplink signals are complementary values ​​of each other and ignore the uplink information bit if the two uplink signals are not complementary values ​​of each other; as well as The low-side receiver is configured to receive the downlink information bit by differential signaling including two downlink signals, store the downlink information bit at the second set-reset flip-flop when the two downlink signals are complementary values ​​of each other, and ignore the downlink information bit when the two downlink signals are not complementary values ​​of each other.

15. The half-bridge gate driver of claim 13, wherein: The high-side receiver includes a first event sensor configured to detect at least one interference event and interrupt storing the uplink information bit at the first set-reset flip-flop in response to detecting the at least one interference event; as well as The low-side receiver includes a second event sensor configured to detect the at least one interference event and to interrupt storing the downlink information bit at the second set-reset flip-flop in response to detecting the at least one interference event.

16. The half-bridge gate driver of claim 12, wherein: The high-side receiver includes a first event sensor configured to detect at least one interference event and interrupt transmission to the high-side region through at least one of the plurality of termination diodes in response to detecting the at least one interference event; as well as The low-side receiver includes a second event sensor configured to detect the at least one interference event and to interrupt transmission to the low-side region through at least another of the plurality of termination diodes in response to detecting the at least one interference event.

17. A method of transmitting information bits across a termination region between a high-side region and a low-side region of a half-bridge gate driver, the half-bridge gate driver comprising a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor, and a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, the low-side power transistor and the high-side power transistor forming a half-bridge, the method comprising: operating the high-side region in a first voltage domain; operating the low-side region in a second voltage domain lower than the first voltage domain; as well as information bits are transmitted between the high-side region and the low-side region via a plurality of termination diodes disposed in the termination region, wherein each of the plurality of termination diodes comprises an anode coupled to the low-side gate driver and a cathode coupled to the high-side gate driver, and The first voltage domain and the second voltage domain are aligned when a high-side ground voltage is substantially equal to a low-side ground voltage and a high-side supply voltage is substantially equal to a low-side supply voltage.

18. The method according to claim 17, further comprising: transmitting the information bits between the high-side region and the low-side region through the plurality of termination diodes with the first voltage domain aligned with the second voltage domain; as well as In the event that the first voltage domain is not aligned with the second voltage domain, the transfer of the information bit between the high-side region and the low-side region is interrupted.

19. The method according to claim 17, further comprising: using a first pair of termination diodes among the plurality of termination diodes, transmitting a first information bit from the low-side region to the high-side region via differential signaling; as well as A second information bit is transmitted from the high-side region to the low-side region through the differential signaling using a second pair of termination diodes among the plurality of termination diodes.

20. The method of claim 17, further comprising: detecting at least one interference event; as well as Transmission of the information bits between the high-side region and the low-side region is interrupted in response to detecting the at least one interference event.

21. An integrated circuit comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a termination region between the high-side region and the low-side region, the termination region being configured to isolate the first voltage domain from the second voltage domain; a high-side circuit disposed in the high-side region, the high-side circuit comprising a high-side power transistor and a high-side gate driver; A low-side circuit is arranged in the low-side region, the low-side circuit comprises a low-side power transistor and a low-side gate driver, the low-side power transistor and the high-side power transistor forming a half bridge; as well as a plurality of termination diodes disposed in the termination region, the plurality of termination diodes being configured to transmit information bits between the high-side region and the low-side region, wherein each of the plurality of termination diodes comprises an anode coupled to the low-side gate driver and a cathode coupled to the high-side gate driver, and The first voltage domain and the second voltage domain are aligned when a high-side ground voltage is substantially equal to a low-side ground voltage and a high-side supply voltage is substantially equal to a low-side supply voltage.

22. The integrated circuit of claim 21, wherein: the plurality of termination diodes being configured to transmit information bits between the high-side region and the low-side region when the first voltage domain is aligned with the second voltage domain; as well as The plurality of termination diodes are configured to interrupt transmission of the information bit between the high-side region and the low-side region if the first voltage domain is misaligned with the second voltage domain.

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