Organic Light Emitting Diode Display

Abstract

An organic light emitting diode display is provided, the organic light emitting diode display comprising: data wiring including a main data line arranged in a display area and a first data line arranged in a peripheral area; a driving voltage wiring including a main driving voltage line arranged in the display area and a first driving voltage line connected to the main driving voltage line and arranged in the peripheral area while extending in a first direction; and a driving low voltage wiring including a cathode extending to the peripheral area while overlapping the display area and a plurality of first driving low voltage connection portions connected to the cathode and arranged in the peripheral area, wherein each of the plurality of first driving low voltage connection portions includes a wiring portion extending in the first direction and a pad portion electrically connected to the wiring portion.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0002679 filed on January 9, 2019, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present invention relates to an organic light emitting diode display, and more particularly, to a peripheral area surrounding a display area of ​​the organic light emitting diode display. Background Art

[0003] A display device is a device for displaying an image, and an organic light emitting diode display is one example of the display device.

[0004] Since the organic light emitting diode display has a self-emitting characteristic, it does not require a separate light source. Therefore, the organic light emitting diode display can be made with reduced thickness and weight. In addition, the organic light emitting diode display has high quality characteristics such as low power consumption, high brightness and high response speed.

[0005] Organic light emitting diode displays have a complex pixel structure and a large number of wirings connected to the pixels. Therefore, the wiring structure of the peripheral area surrounding the display area is relatively complex. Summary of the invention

[0006] Exemplary embodiments are directed to preventing a short circuit between a driving voltage line and a driving low voltage line disposed adjacent to each other in a peripheral region.

[0007] An organic light emitting diode display according to an exemplary embodiment of the present invention includes: data wiring including a main data line disposed in a display area and a first data line disposed in a peripheral area; a driving voltage wiring including a main driving voltage line disposed in the display area and a first driving voltage line connected to the main driving voltage line and disposed in the peripheral area while extending in a first direction; and a driving low voltage wiring including a cathode extending to the peripheral area while overlapping the display area and a plurality of first driving low voltage connection portions connected to the cathode and disposed in the peripheral area, wherein each of the plurality of first driving low voltage connection portions includes a wiring portion extending in the first direction and a pad portion electrically connected to the wiring portion.

[0008] The driving low voltage wiring may further include a second driving low voltage connection portion electrically connecting the cathode and the first driving low voltage connection portion.

[0009] The second driving low voltage connection portion may include a wiring portion extending in the first direction and a connection portion electrically connected to the wiring portion.

[0010] The first driving voltage line may include a wiring portion extending in the first direction and a pad portion electrically connected to the wiring portion.

[0011] In a plan view, the second driving low voltage connection portion and the first driving voltage line may overlap each other.

[0012] A width at which the wiring portion of the second driving low voltage connection portion overlaps the wiring portion of the first driving voltage line may be half or less than half the width of the wiring portion of the first driving voltage line.

[0013] The wiring portion of the second driving low voltage connection portion may overlap the pad portion of the first driving voltage line.

[0014] The first driving voltage line may extend to a region adjacent to the display region, and may include only a plurality of pads separated from each other.

[0015] The first driving voltage line and the first driving low voltage connection portion may be disposed in different layers.

[0016] The driving voltage wiring may further include a second driving voltage line disposed in the display area and electrically connected to the main driving voltage line, wherein the driving voltage wiring may have a grid shape in the display area.

[0017] The driving low voltage wiring may further include a first driving low voltage line and a second driving low voltage line disposed in the display area, and may have a mesh shape.

[0018] An organic light emitting diode display according to an exemplary embodiment of the present invention includes: data wiring including a main data line disposed in a display area and a first data line disposed in a peripheral area; a driving voltage wiring including a main driving voltage line disposed in the display area, a first driving voltage line connected to the main driving voltage line and disposed in the peripheral area, and a plurality of driving voltage pads for receiving a driving voltage, wherein the first driving voltage line extends in a first direction; and a driving low voltage wiring including a cathode extending to the peripheral area and overlapping the display area, a peripheral driving low voltage line disposed in the peripheral area and connected to the cathode, and a plurality of driving low voltage pads for receiving a driving low voltage, wherein the driving voltage pad is formed in a layer different from that of the first driving voltage line, and the driving low voltage pad is formed in a layer different from that of the peripheral driving low voltage line.

[0019] The first driving voltage line and the peripheral driving low voltage line may be formed in the data conductive layer, and the driving voltage pad and the driving low voltage pad may be formed in the gate conductive layer.

[0020] The cathode electrode may cover at least a portion of the first driving voltage line.

[0021] The cathode electrode may not overlap the first driving voltage line.

[0022] The driving voltage wiring may further include a first driving voltage connecting portion electrically connecting a driving voltage pad of the driving voltage wiring and the second driving voltage line.

[0023] The first driving voltage connection portion may be provided in the metal layer.

[0024] The first driving voltage connection portion may be provided in the anode layer.

[0025] The driving voltage wiring may further include a second driving voltage line disposed in the display area and electrically connected to the main driving voltage line, wherein the driving voltage wiring may have a mesh structure.

[0026] The driving low voltage wiring may further include a first driving low voltage line and a second driving low voltage line disposed in the display area, and may have a mesh structure.

[0027] An organic light emitting diode display according to an exemplary embodiment of the present invention includes: data wiring; driving voltage wiring including a main driving voltage line and a first driving voltage line disposed in a peripheral area and connected to the main driving voltage line; and driving low voltage wiring including a cathode and a plurality of first driving low voltage connection portions, wherein at least one of the first driving low voltage connection portions is disposed in the peripheral area and includes a wiring portion and a pad portion.

[0028] According to an exemplary embodiment, the area where the pixel electrode layer electrically connected to the driving low voltage line overlaps the driving voltage line is reduced, thereby preventing a short circuit between the driving low voltage line and the driving voltage line. Since the portion to which the driving low voltage is applied is arranged as far as possible from the portion to which the driving voltage is applied, a short circuit between the two portions can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a layout diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0030] Figure 2 is based on Figure 1 An enlarged view of a peripheral area at one side of an organic light emitting diode display of an exemplary embodiment.

[0031] Figure 3 yes Figure 2 A cross-sectional view taken along line III-III.

[0032] Figure 4 , Figure 6 and Figure 8is an enlarged view of a peripheral area at one side of an organic light emitting diode display according to another exemplary embodiment of the present invention.

[0033] Figure 5 yes Figure 4 A cross-sectional view taken along line VV.

[0034] Figure 7 yes Figure 6 A cross-sectional view taken along line VII-VII.

[0035] Fig. 9 yes Figure 8 A cross-sectional view taken along line IX-IX.

[0036] Fig.10 is an enlarged view of a peripheral area at the other side of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0037] Fig.11 and Fig.12 yes Fig.10 A cross-sectional view taken along line XI-XI.

[0038] Fig.13 and Fig.15 is an enlarged view of a peripheral area at another side of an organic light emitting diode display according to another exemplary embodiment of the present invention.

[0039] Fig.14 yes Fig.13 A cross-sectional view taken along line XIV-XIV.

[0040] Fig.16 and Fig.17 yes Fig.15 A cross-sectional view taken along line XVI-XVI.

[0041] Fig.18 is a cross-sectional view of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0042] Fig.19 is a schematic diagram of a display area of ​​an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0043] Fig. 20 is a circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0044] Fig.21 and Fig. 22 is a cross-sectional view of a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0045] Hereinafter, exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways and should not be limited to the embodiments set forth herein.

[0046] Like reference numerals may denote like elements throughout the specification.

[0047] In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity.

[0048] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0049] Furthermore, in this specification, the phrase “on a plane” may mean viewing a target portion from the top, and the phrase “on a cross section” may mean viewing a cross section formed by vertically cutting the target portion from the side.

[0050] In the following, reference will be made to Figure 1 The structure of an organic light emitting diode (OLED) display is described.

[0051] Figure 1 is a layout diagram of an organic light emitting diode (OLED) display according to an exemplary embodiment of the present invention.

[0052] The OLED display according to the present exemplary embodiment includes a display panel 100 in which pixels PX are formed, a printed circuit board 300 in which voltage applying parts 310 and 320 are formed, and a flexible printed circuit board 200 connecting the display panel 100 and the printed circuit board 300 and in which a driving chip 250 is formed.

[0053] The display panel 100 includes a display area 110 in which pixels PX are formed and thus an image is displayed, and a peripheral area 120 including a fan-out area while surrounding the display area 110 .

[0054] The data line 171 to which the data voltage is applied, the driving voltage line 181 to which the driving voltage ELVDD is applied, and the driving low voltage line 182 to which the driving low voltage ELVSS is applied are connected to the pixel PX formed in the display area 110. Here, the driving low voltage line 182 may be a cathode 410 having an integral structure that completely covers the display area 110. In addition, the pixel PX is connected to the detection signal lines 173 and 173' to which the initialization voltage is applied, and the detection signal lines 173 and 173' detect the voltage of a specific node in the pixel PX when the initialization voltage is not applied.

[0055] In addition to the detection signal lines 173 and 173', more various lines may be connected to the pixel PX. Fig.12 and Fig.14 The pixel PX according to the present exemplary embodiment is shown in detail in FIG.

[0056] exist Figure 1 In the embodiment, with respect to the pixel PX, the data line (hereinafter, also referred to as the main data line) 171 is arranged at the left side, and the driving voltage line (hereinafter, also referred to as the main driving voltage line) 181 is arranged at the right side, and the driving low voltage line 182 passes over the pixel PX, but this is not restrictive. In addition, the detection signal lines 173 and 173' may not be formed in each array of the pixel PX. However, in Figure 1 In the exemplary embodiment, a vertical detection signal line 173 is formed in each array of a plurality of pixels PX, and is connected to the plurality of pixels PX through a detection signal extension portion 173' extending from the vertical detection signal line 173 in a horizontal direction (e.g., a first direction). In the present exemplary embodiment, a vertical detection signal line 173 is formed in each array of pixels PX, and three pixels PX in a row of the array are connected to the vertical detection signal line 173 through the detection signal line extension portion 173'. In addition, according to an exemplary embodiment of the present invention, the driving voltage line 181 may not be formed in each pixel array.

[0057] In the peripheral area 120 of the display panel 100, a peripheral data line (hereinafter, also referred to as the first data line) 171-1 connected to the data line 171, a peripheral detection signal line 173-1 connected to the vertical detection signal line 173, a peripheral driving voltage line (hereinafter, also referred to as the first driving voltage line) 181-1 connected to the driving voltage line 181, and a peripheral driving low voltage connection part (hereinafter, referred to as the first driving low voltage connection part) 182-1 connected to the driving low voltage line 182 are formed.

[0058] The peripheral data line 171-1 and the peripheral detection signal line 173-1 are arranged at opposite sides in the fan-out area in the peripheral area 120. Such a structure makes it possible to receive a signal from a driver chip 250 in a predetermined area, so that the peripheral data line 171-1 and the peripheral detection signal line 173-1 point to the center of the fan-out area while being bent (bent). Therefore, the pads (pads, also known as "pads", "pads") arranged at the ends of the peripheral data line 171-1 and the peripheral detection signal line 173-1 can be arranged adjacent to each other at the driver chip 250. In addition, the peripheral data line 171-1 and the peripheral detection signal line 173-1 have different lengths respectively due to the curved structure. In order to compensate for the length difference, each of the peripheral data line 171-1 and the peripheral detection signal line 173-1 can also include a resistor part, which can make all data lines or all detection signal lines have the same resistance value. A first conductive layer (e.g., a data conductive layer in the present exemplary embodiment) in which the data line 171 and the detection signal line 173 are formed in the display area 110 and a second conductive layer (e.g., a gate conductive layer in the present exemplary embodiment) in which the peripheral data line 171-1 and the peripheral detection signal line 173-1 are formed in the peripheral area 120 may be different from each other.

[0059] The peripheral driving voltage line 181-1 extends in the horizontal direction and has a structure including a connection line connecting a plurality of driving voltage lines 181. The connection line of the peripheral driving voltage line 181-1 has a structure in which the connection line is integrally formed in the peripheral area 120 as a whole so that all driving voltage lines 181 are connected to a single connection line. However, according to an exemplary embodiment of the present invention, the connection line of the peripheral driving voltage line 181-1 may be provided in plurality, and one connection line may be connected to only some of the driving voltage lines 181.

[0060] In addition, the peripheral driving low voltage connection portion 182-1 is provided in plurality, and the peripheral driving low voltage connection portions 182-1 are separated from each other. Figure 1 , the peripheral driving low voltage connection portion 182-1 is shown as a single wiring extending in the horizontal direction, but the respective peripheral driving low voltage connection portions 182-1 separated from each other are connected through the cathode 410, and therefore, when viewed in the circuit structure, they are shown as being connected (refer to Figure 2). In other words, each separated peripheral driving low voltage connection portion 182-1 may be connected to the driving low voltage line 182, which is the cathode 410 covering the display area 110. The cathode 410 not only covers the entire display area 110, but is also formed in a portion of the peripheral area 120, and thus may be connected to the peripheral driving low voltage connection portion 182-1 in the peripheral area 120. The driving low voltage ELVSS applied to the peripheral driving low voltage connection portion 182-1 is transmitted to the cathode 410, and the portion where the driving low voltage ELVSS is applied to the cathode 410 may have a plurality of positions.

[0061] The peripheral data line 171-1 formed in the peripheral area 120 is formed in a second conductive layer different from the first conductive layer in which the peripheral drive voltage line 181-1 and the peripheral drive low voltage connection portion 182-1 are formed, and thus can be overlapped with the first conductive layer in the layout diagram. In addition, the peripheral drive voltage line 181-1 and the peripheral drive low voltage connection portion 182-1 are formed in the same conductive layer, and therefore, in the layout diagram, they can be separated from each other. The peripheral drive voltage line 181-1 and the peripheral drive low voltage connection portion 182-1 are formed in the same conductive layer as the drive voltage line 181.

[0062] The data line 171 disposed in the display area 110 and the peripheral data line 171 - 1 disposed in the peripheral area 120 may also be referred to as data wiring lines hereinafter.

[0063] The driving voltage line 181 disposed in the display area 110 and the peripheral driving voltage line 181 - 1 disposed in the peripheral area 120 may also be referred to as driving voltage wirings hereinafter.

[0064] The cathode 410 extending to the peripheral region 120 while covering the display region 110 and the peripheral driving low voltage connection portion 182-1 disposed in the peripheral region 120 may be referred to as a driving low voltage wiring. Here, the driving low voltage wiring may include a driving low voltage line (refer to Fig.19 182 and 182').

[0065] The flexible printed circuit board 200 includes a driving chip 250 that applies a data voltage to the data wirings 171 and 171-1. An input wiring 2171 that transmits a signal from the outside to the driving chip 250 and an output wiring 1171-1 that outputs a data voltage from the driving chip 250 are formed in the flexible printed circuit board 200. In addition, the detection signal lines 173 and 173-1 may be connected to the driving chip 250.

[0066] The output wiring 1171-1 is connected to the peripheral data line 171-1 provided in the peripheral area 120. The input wiring 2171 has a structure for receiving a signal from the printed circuit board 300.

[0067] The flexible printed circuit board 200 further includes a driving voltage transmission line 1181 to which a driving voltage ELVDD is applied and a driving low voltage transmission line 1182 to which a driving low voltage ELVSS is applied.

[0068] The driving voltage transmission line 1181 is connected to the peripheral driving voltage line 181 - 1 of the peripheral area 120 , and the driving low voltage transmission line 1182 is connected to the peripheral driving low voltage connection portion 182 - 1 of the peripheral area 120 .

[0069] The printed circuit board 300 includes a driving voltage applying part 310 that generates and transmits a driving voltage ELVDD and a driving low voltage applying part 320 that generates and transmits a driving low voltage ELVSS. The printed circuit board 300 includes a driving voltage output line 2181 connected to the driving voltage applying part 310. The driving voltage output line 2181 is connected to the driving voltage transmission line 1181 of the flexible printed circuit board 200. Therefore, the driving voltage ELVDD is transmitted from the driving voltage output line 2181 to the driving voltage transmission line 1181 to the display panel 100. The printed circuit board 300 also includes a driving low voltage output line 2182 connected to the driving low voltage applying part 320. The driving low voltage output line 2182 is connected to the driving low voltage transmission line 1182 of the flexible printed circuit board 200. Therefore, the driving low voltage ELVSS is transmitted from the driving low voltage output line 2182 to the driving low voltage transmission line 1182 to the display panel 100.

[0070] The printed circuit board 300 may further include a video driver that divides an externally applied video signal and transmits the divided video signal to each driving chip 250 provided in the flexible printed circuit board 200. The video driver is connected to the input wiring 2171 of the flexible printed circuit board 200 through a video signal transmission line. Therefore, the video signal can be transmitted to the driving chip 250.

[0071] Now refer to Figure 2 and Figure 3 The structure of the peripheral region 120 in the organic light emitting diode display is further described in detail.

[0072] Figure 2 is based on Figure 1 An enlarged view of a peripheral area at one side of an organic light emitting diode display of an exemplary embodiment, Figure 3 yes Figure 2 A cross-sectional view taken along line III-III.

[0073] exist Figure 2 , the peripheral area 120 provided in the lower portion of the display panel 100 is shown, and a fan-out area in which the peripheral data line 171 - 1 is arranged is mainly shown.

[0074] The data line 171 is connected to the peripheral data line 171-1 in the peripheral area 120 while extending in the vertical direction (eg, the second direction) in the display area 110, and then is concentrated to the center of the fan-out area by being bent in the fan-out area. Figure 2 and Figure 3 , the peripheral data line 171-1 is formed in a layer (e.g., gate conductive layer) in which the gate line is formed, rather than in a layer (e.g., data conductive layer) in which the data line 171 is formed. Therefore, the data line 171 is formed to extend to a portion of the peripheral area 120 while passing through the display area 110 in the data conductive layer, and is electrically connected to the peripheral data line 171-1 formed in the gate conductive layer through a contact structure. Here, the gate conductive layer is formed closer to the semiconductor layer than the data conductive layer, and is disposed away from the anode and the cathode.

[0075] The peripheral driving voltage line 181-1 and the peripheral driving low voltage connection portion 182-1 are formed in the data conductive layer of the peripheral area 120. Although the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection portion 182-1 are formed in the same layer, they are Figure 2 and Figure 3 are shown separated from each other.

[0076] The peripheral driving voltage line 181-1 disposed in the peripheral area 120 includes a wiring portion extending in a horizontal direction (e.g., a first direction) and a pad portion protruding downward from the wiring portion. The pad portion of the peripheral driving voltage line 181-1 is disposed between adjacent fan-out areas. The pad portion of the peripheral driving voltage line 181-1 is connected to the driving voltage transmission line 1181 of the flexible printed circuit board 200 and receives the driving voltage ELVDD. The driving voltage ELVDD transmitted to the peripheral driving voltage line 181-1 is transmitted to the driving voltage line 181. By increasing the number of pad portions protruding from the peripheral driving voltage line 181-1, the driving voltage ELVDD can maintain a constant voltage level in the display area 110. The driving voltage line 181 is formed in the data conductive layer, and the peripheral driving voltage line 181-1 is also formed in the data conductive layer, and therefore, the driving voltage line 181 and the peripheral driving voltage line 181-1 can have an integral structure in which they are directly connected without an additional contact structure.

[0077] The peripheral drive low voltage connection portion 182-1 provided in the peripheral area 120 has a plurality of separated structures. The pad portion is provided at opposite sides of each connection portion, and the wiring portion is provided between the pad portions to connect the two pad portions. In other words, the peripheral drive low voltage connection portion 182-1 includes a wiring portion extending in one direction and a pad portion protruding from opposite sides of the wiring portion and electrically connected thereto. The peripheral drive voltage line 181-1 has one connection structure as a whole through the connection line, but the peripheral drive low voltage connection portion 182-1 is formed by a plurality of separated connection portions.

[0078] The peripheral driving low voltage horizontal connection portion 192 (hereinafter, also referred to as a second driving low voltage connection portion) electrically connected through the opening 405 is formed on the peripheral driving low voltage connection portion 182 - 1 .

[0079] The peripheral drive low voltage horizontal connection portion 192 includes a wiring portion extending in a horizontal direction (e.g., a first direction) and a contact portion electrically connected while protruding downward from the wiring portion. The contact portion of the peripheral drive low voltage horizontal connection portion 192 overlaps the peripheral drive low voltage connection portion 182-1 and is electrically connected to the peripheral drive low voltage connection portion 182-1 through the opening 405. For example, in the opening 405, the peripheral drive low voltage horizontal connection portion 192 is in direct contact with the peripheral drive low voltage connection portion 182-1. The wiring portion of the peripheral drive low voltage horizontal connection portion 192 overlaps the peripheral drive voltage line 181-1, but the area overlapped with the peripheral drive voltage line 181-1 is kept less than a predetermined size to prevent the occurrence of a short circuit. In other words, the area where the wiring portion of the peripheral drive low voltage horizontal connection portion 192 and the wiring portion of the peripheral drive voltage line 181-1 overlap each other can be formed to be or less than half the width of the wiring portion of the peripheral drive voltage line 181-1. In addition, the peripheral driving low voltage horizontal connection portion 192 does not protrude in the pad portion of the peripheral driving voltage line 181 - 1 , and thus, an overlap area with the peripheral driving voltage line 181 - 1 may be reduced.

[0080] The cathode 410 is disposed on the peripheral driving low voltage horizontal connection portion 192, and thus, the cathode 410 and the peripheral driving low voltage horizontal connection portion 192 are electrically connected to each other through the opening 405. For example, in the opening 405, the cathode 410 and the peripheral driving low voltage horizontal connection portion 192 directly contact each other.

[0081] exist Figure 2 , an opening 405 is shown, but referring to Figure 3, the opening 405 may be formed in two insulating layers (e.g., the organic insulating layer 15 and the barrier rib 20). Therefore, the peripheral driving low voltage connection portion 182-1, the peripheral driving low voltage horizontal connection portion 192, and the cathode 410 are sequentially connected to each other. Due to this connection structure, the driving low voltage ELVSS applied to the pad portion of the peripheral driving low voltage connection portion 182-1 is transmitted to the cathode 410 through the peripheral driving low voltage horizontal connection portion 192.

[0082] Since the peripheral driving low voltage connection portion 182 - 1 is a data conductive layer in the fan-out region, the peripheral driving low voltage connection portion 182 - 1 may be easily electrically connected to the cathode 410 through the opening 405 .

[0083] The driving voltage ELVDD and the driving low voltage ELVSS should be transmitted to the pixel PX as separate voltages, respectively, but there is such a possibility that the peripheral driving voltage line 181-1 to which the driving voltage ELVDD is applied and the wiring to which the driving low voltage ELVSS is applied (e.g., the peripheral driving low voltage connection portion 182-1 and the peripheral driving low voltage horizontal connection portion 192) may be adjacent to each other or overlap each other in the peripheral area 120, thereby causing a short circuit. Therefore, the area in which the peripheral driving low voltage horizontal connection portion 192 and the peripheral driving voltage line 181-1 overlap each other is minimized in the present exemplary embodiment to prevent the occurrence of such a short circuit. In other words, the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection portion 182-1 adjacent to each other are formed in the same layer (e.g., data conductive layer) by using the same mask. Since they are formed by the same mask, they can be formed at a predetermined distance from each other. However, the opening 405 formed thereon may change in position due to the misalignment of the mask. When the opening 450 is improperly positioned, the overlapping area of ​​the peripheral driving low voltage horizontal connection portion 192 and the peripheral driving voltage line 181-1 may increase, thereby increasing the possibility that they will be connected to each other in the misaligned opening 405. However, in the present exemplary embodiment, the driving low voltage horizontal connection portion 192 overlaps the peripheral driving voltage line 181-1 with a minimum area, so that the occurrence of a short circuit can be prevented even if the opening 405 is misaligned.

[0084] The cathode 410 not only covers the entire display area 110, but is also formed in the peripheral area 120. Figure 2 , the cathode 410 covers the peripheral driving low voltage connection portion 182-1, the peripheral driving voltage line 181-1, and the peripheral driving low voltage horizontal connection portion 192. However, according to an exemplary embodiment of the present invention, the cathode 410 may overlap only a portion of the peripheral driving low voltage connection portion 182-1, the peripheral driving voltage line 181-1, or the peripheral driving low voltage horizontal connection portion 192.

[0085] exist Figure 3 In the figure, the positional relationship of each wiring will be described through a cross-sectional view.

[0086] Reference Figure 3 , a buffer layer 11 is stacked on a substrate 10. The substrate 10 may be a flexible substrate such as a glass substrate or a plastic substrate. A metal layer may be formed on the substrate 10. In addition, a semiconductor layer is formed on the buffer layer 11, and the semiconductor layer is not formed in the peripheral region 120. A gate insulating layer 12 is stacked on the buffer layer 11. A gate conductive layer is formed on the gate insulating layer 12, and a peripheral data line 171-1 is formed in the peripheral region 120. An interlayer insulating layer 14 covering the peripheral data line 171-1 and the gate insulating layer 12 is formed on the peripheral data line 171-1 and the gate insulating layer 12. According to an exemplary embodiment of the present invention, the layer for forming the pixel PX may include a second gate conductive layer. In this case, the second gate insulating layer 13 may also be disposed between the interlayer insulating layer 14 and the gate insulating layer 12. In addition, according to an exemplary embodiment of the present invention, the peripheral data line 171-1 may be formed as a second gate conductive layer.

[0087] The data conductive layer is formed on the interlayer insulating layer 14, and the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection portion 182-1 are formed in the peripheral area 120. Since the driving voltage line 181 of the display area 110 is formed in the data conductive layer, the peripheral driving voltage line 181-1 may have a directly connected structure.

[0088] The organic insulating layer 15 covering the peripheral drive voltage line 181-1 and the peripheral drive low voltage connection part 182-1 is formed on the peripheral drive voltage line 181-1 and the peripheral drive low voltage connection part 182-1. The anode can be formed on the organic insulating layer 15, and the peripheral drive low voltage horizontal connection part 192 can be formed in the peripheral area 120. The peripheral drive low voltage horizontal connection part 192 is connected to the peripheral drive low voltage connection part 182-1 through the opening 405 formed in the organic insulating layer 15. The barrier rib 20 is formed on the organic insulating layer 15 and the peripheral drive low voltage connection part 182-1 to cover the organic insulating layer 15 and the peripheral drive low voltage connection part 182-1. The cathode 410 is formed on the barrier rib 20, and the cathode 410 and the peripheral drive low voltage connection part 182-1 are electrically connected to each other through the opening 405 formed in the barrier rib 20.

[0089] Hereinabove, the structure in which the peripheral driving low voltage horizontal connection portion 192 and the peripheral driving voltage line 181 - 1 extend in the horizontal direction while reducing the overlapping area therebetween has been described.

[0090] In the following, reference is made to Figure 4 and Figure 5 , a structure in which the peripheral driving low voltage horizontal connection portion 192 is formed without overlapping the peripheral driving voltage line 181 - 1 except for the pad portion of the peripheral driving voltage line 181 - 1 will be described.

[0091] Figure 4 is an enlarged view of a peripheral area of ​​an organic light emitting diode display according to another exemplary embodiment of the present invention, Figure 5 yes Figure 4 A cross-sectional view taken along line VV.

[0092] First, refer to Figure 4 ,and Figure 2 In contrast, the peripheral driving low voltage horizontal connection portion 192 overlaps only the pad portion of the peripheral driving voltage line 181 - 1 , but does not overlap the wiring portion of the peripheral driving voltage line 181 - 1 .

[0093] As a result, the area where the peripheral driving voltage line 181-1 and the peripheral driving low voltage horizontal connection portion 192 overlap each other is minimized. For example, the opening 405 is positioned away from the pad portion of the peripheral driving voltage line 181-1 so that the peripheral driving low voltage connection portion 182-1 and the peripheral driving low voltage horizontal connection portion 192 can be electrically connected to each other. Figure 4 In the exemplary embodiment of FIG. 4 , a short circuit of the peripheral driving voltage line 181 - 1 and the peripheral driving low voltage horizontal connection portion 192 due to misalignment of the opening 405 does not occur.

[0094] Reference Figure 5 Differences can also be identified.

[0095] In other words, with Figure 3 In comparison, Figure 5 , a structure is shown in which the peripheral drive low voltage horizontal connection portion 192 provided on the peripheral drive voltage line 181-1 in the cross-sectional view is not formed in a partial area. In other words, the area of ​​the peripheral drive voltage line 181-1 does not overlap with the peripheral drive low voltage horizontal connection portion 192. Therefore, due to the area in which the peripheral drive voltage line 181-1 and the peripheral drive low voltage horizontal connection portion 192 do not overlap, the possibility of a short circuit between the two wirings (e.g., the peripheral drive voltage line 181-1 and the peripheral drive low voltage horizontal connection portion 192) is reduced.

[0096] In the following, the following will describe Figure 6 and Figure 7 An exemplary embodiment of the present invention is shown in FIG.

[0097] Figure 6is an enlarged view of a peripheral area of ​​an organic light emitting diode display according to another exemplary embodiment of the present invention, Figure 7 yes Figure 6 A cross-sectional view taken along line VII-VII.

[0098] exist Figure 6 and Figure 7 , an exemplary embodiment of the present invention is shown in which only a pad portion is expanded instead of forming a wiring portion horizontally extending from the peripheral driving voltage line 181-1 to reduce an area overlapped with the peripheral driving low voltage horizontal connection portion 192.

[0099] and Figure 2 In comparison, the structure of the peripheral driving voltage line 181-1 is Figure 6 is different.

[0100] In other words, Figure 6 The peripheral driving voltage line 181 - 1 according to an exemplary embodiment of the present invention shown in FIG. 1 has the following structure.

[0101] For example, in Figure 6 In the embodiment, the peripheral driving voltage line 181-1 disposed in the peripheral area 120 does not include a wiring portion extending in a horizontal direction (e.g., a first direction), but includes only a pad portion protruding in a downward direction (e.g., a second direction) and electrically connected thereto. The pad portion extends to an area adjacent to the display area 110 and is formed of a plurality of pad portions formed separately from each other. Although in Figure 6 is not explicitly shown, but Fig.19 As shown in FIG. 1 , the driving voltage wiring for applying the driving voltage ELVDD includes a driving voltage line 181 and a horizontal driving voltage line 181' (hereinafter, also referred to as a second driving voltage line) formed in the display area 110 in a grid shape. Therefore, although the peripheral driving voltage line 181-1 provided in the peripheral area 120 does not extend in the first direction, the entire display area 110 has a constant driving voltage ELVDD by virtue of the grid structure connection of the display area 110. Figure 6 The peripheral driving voltage line 181-1 shown in FIG. 1 may be formed in the data conductive layer and thus directly connected to the driving voltage line 181 of the display area 110 without an additional contact structure. Figure 6 In the structure of FIG. 1 , when the driving voltage ELVDD is applied through the pad portion, the driving voltage ELVDD may be applied only to a portion of the driving voltage line 181 of the display area 110. However, since the horizontal driving voltage line 181' is provided in the display area 110, the driving voltage lines 181 are connected to each other through the horizontal driving voltage line 181'. Therefore, the driving voltage ELVDD may be applied to the entire display area 110.

[0102] Will refer to Figure 7 This is described in the cross-sectional structure shown in .

[0103] and Figure 3 In comparison, Figure 7 In the embodiment, the area where the peripheral driving voltage line 181-1 and the peripheral driving low voltage horizontal connection portion 192 overlap each other is reduced. Figure 6 This reduction in overlap is also shown.

[0104] Therefore, since the area where the peripheral driving voltage line 181-1 and the peripheral driving low voltage horizontal connection portion 192 overlap each other is reduced, the peripheral driving voltage line 181-1 and the peripheral driving low voltage horizontal connection portion 192 are not electrically connected to each other even if the opening 405 is not aligned.

[0105] In the above, reference has been made to Figures 2 to 7 An exemplary embodiment of the present invention in which the peripheral driving low voltage horizontal connection portion 192 is formed is described.

[0106] In the following, reference will be made to Figure 8 and Fig. 9 An exemplary embodiment of the present invention in which the peripheral driving low voltage horizontal connection portion 192 is omitted is described.

[0107] Figure 8 is an enlarged view of a peripheral area of ​​an organic light emitting diode display according to another exemplary embodiment of the present invention, Fig. 9 yes Figure 8 A cross-sectional view taken along line IX-IX.

[0108] Reference Figure 8 ,and Figure 2 , Figure 4 and Figure 6 Unlike, the peripheral driving low voltage horizontal connection portion 192 is not formed. Therefore, in the present exemplary embodiment, when the peripheral driving low voltage connection portion 182-1 and the cathode 410 are electrically connected to each other, they are directly connected to each other, not through a layer provided in the anode.

[0109] Reference Fig. 9 In the present exemplary embodiment, the peripheral driving low voltage connection portion 182 - 1 is disposed in the data conductive layer, and the cathode 410 is formed in the cathode layer disposed on the anode. The cathode 410 and the peripheral driving low voltage connection portion 182 - 1 are directly connected to each other through the opening 405 .

[0110] exist Figure 8 and Fig. 9In the exemplary embodiment of the present invention shown in , the possibility of the wiring connection of the peripheral driving voltage line 181-1 with the transmission driving low voltage ELVSS is further reduced. When the peripheral driving low voltage horizontal connection part 192 is provided in the anode, the opening 405 formed in the organic insulating layer 15 causes a short circuit, but as Fig. 9 As shown in FIG. 1 , when two insulating layers (e.g., an organic insulating layer 15 and a barrier rib 20) are disposed between a peripheral driving voltage line 181-1 and a cathode 410 overlapping the peripheral driving voltage line 181-1, the possibility of a short circuit can be reduced as long as the opening 405 is not misaligned. In addition, as the overlapping distance increases, the parasitic capacitance between the peripheral driving voltage line 181-1 and the cathode 410 can be reduced.

[0111] In the above, the peripheral area at the lower side of the display device has been described.

[0112] Hereinafter, a peripheral area at an upper side of the organic light emitting diode display will be described.

[0113] We will now describe Figures 10 to 12 An exemplary embodiment of the present invention is shown in FIG.

[0114] Fig.10 is an enlarged view of another peripheral area of ​​an organic light emitting diode display according to an exemplary embodiment of the present invention, Fig.11 and Fig.12 yes Fig.10 A cross-sectional view taken along line XI-XI.

[0115] First, we will describe Fig.10 .

[0116] The peripheral area 120 is provided at the upper side of the display area 110 within the display panel 100. A peripheral driving voltage wiring and a peripheral driving low voltage wiring are formed in the peripheral area 120 on the upper side of the display area 110. Here, unlike the peripheral driving low voltage connection portion 182-1 of the peripheral area 120 in the lower side, the peripheral driving low voltage wiring in the upper side extends in the horizontal direction and is thus formed integrally. In addition, in the peripheral area 120 on the upper side, a driving voltage pad 181-3 for transmitting the driving voltage ELVDD and a driving low voltage pad 182-3 for transmitting the driving low voltage ELVSS are respectively included.

[0117] A peripheral driving voltage wiring that is disposed at the upper peripheral area 120 and transmits the driving voltage ELVDD will now be described.

[0118] The peripheral driving voltage wiring at the upper side includes a second peripheral driving voltage line 181-2 and a driving voltage pad 181-3. Unlike the peripheral driving voltage line 181-1 as the peripheral driving voltage wiring in the lower side, for example, the peripheral driving voltage wiring at the upper side is formed separately rather than integrally, and has only electrical connections.

[0119] Reference Fig.10 , the second peripheral driving voltage line 181-2 is formed in the data conductive layer, and thus is formed in the same layer as the driving voltage line 181 of the display area 110. Fig.10 As shown in FIG. 1 , the second peripheral driving voltage line 181-2 is formed integrally with the driving voltage line 181. Figure 2 The difference shown in Fig.10 In, because Fig.10 is an enlarged view, so the driving voltage line 181 has a predetermined width. This can be achieved by Figure 2 and Fig.10 According to an exemplary embodiment of the present invention, this size difference can also be changed.

[0120] In addition, the driving voltage pad 181-3 extends in the vertical direction and overlaps the second peripheral driving voltage line 181-2 at the end of the peripheral area 120. Fig.10 , only one driving voltage pad 181-3 is shown, but a plurality of driving voltage pads 181-3 may be included at a plurality of locations. Unlike the second peripheral driving voltage line 181-2, the driving voltage pad 181-3 is formed in a gate conductive layer disposed in a lower portion of the data conductive layer. According to an exemplary embodiment of the present invention, the gate conductive layer may be formed as two layers (e.g., a first gate conductive layer and a second gate conductive layer), but the driving voltage pad 181-3 may be formed in either of the two layers. Fig.11 In the cross-sectional view of FIG. 1 , the driving voltage pad 181 - 3 is formed in the second gate conductive layer. Fig.12 In the cross-sectional view of , the driving voltage pad 181 - 3 is formed in the first gate conductive layer.

[0121] The second peripheral driving voltage line 181 - 2 and the driving voltage pad 181 - 3 are directly connected to each other through the opening 401 , and thus the driving voltage ELVDD input to the driving voltage pad 181 - 3 is applied to the second peripheral driving voltage line 181 - 2 , and thus the driving voltage ELVDD is applied to the driving voltage line 181 of the display area 110 .

[0122] In addition, the peripheral driving low voltage wiring disposed in the upper peripheral region 120 and transmitting the driving low voltage ELVSS includes a second peripheral driving low voltage line 182-2 and a driving low voltage pad 182-3. The driving low voltage wiring disposed in the lower peripheral region 120 has a structure in which a separately formed connection portion is provided in plurality, but the second peripheral driving low voltage line 182-2 in the upper peripheral region 120 extends integrally in the horizontal direction. However, the second peripheral driving low voltage line 182-2 does not include a pad connected thereto, but includes a separately formed driving low voltage pad 182-3.

[0123] Reference Fig.10 , the second peripheral driving low voltage line 182-2 is formed in the data conductive layer and extends in the horizontal direction. Therefore, in the display panel 100, the structure in which the plurality of peripheral driving low voltage connection parts 182-1 are disposed in the lower portion is different from the structure in which one second peripheral driving low voltage line 182-2 is integrally formed.

[0124] In addition, the driving low voltage pad 182-3 extends in the vertical direction and overlaps the second peripheral driving low voltage line 182-2 at the end of the peripheral area 120. Fig.10 , only one driving low voltage pad 182-3 is shown, but a plurality of driving low voltage pads 182-3 may be included at a plurality of locations. Unlike the second peripheral driving low voltage line 182-2, the driving low voltage pad 182-3 is formed in the gate conductive layer located at the lower portion of the data conductive layer, and according to an exemplary embodiment of the present invention, the driving low voltage pad 182-3 may be disposed in the first gate conductive layer (refer to Fig.11 ) or disposed on a second gate conductive layer disposed on the first gate conductive layer (refer to Fig.12 ).

[0125] The second peripheral driving low voltage line 182 - 2 and the driving low voltage pad 182 - 3 are directly connected to each other through the opening 402 , and thus, the driving low voltage ELVSS input to the driving low voltage pad 182 - 3 is applied to the second peripheral driving low voltage line 182 - 2 .

[0126] The second peripheral driving low voltage line 182-2 includes a portion exposed by the opening 405, and is connected to the cathode 410 (at Fig.10 Indicated by hatching in the figure) for electrical connection. Fig.10 The middle opening 405 is disposed on the second peripheral driving low voltage line 182-2, but the position of the opening 405 may be any position that can expose the second peripheral driving low voltage line 182-2. Therefore, the driving low voltage ELVSS applied to the driving low voltage pad 182-3 is transmitted to the cathode 410 through the second peripheral driving low voltage line 182-2.

[0127] Fig.11 and Fig.12 The exemplary embodiment of the present invention shown in FIG. 1 shows a difference in the layers where the driving voltage pad 181-3 and the driving low voltage pad 182-3 are respectively formed. Due to this layer difference, Fig.11 Compared to the exemplary embodiment of the present invention shown in Fig.12 The exemplary embodiment of the present invention shown in FIG. 1 may have fewer short circuits. In other words, referring to FIG. Fig.10 , the driving voltage pad 181-3 overlaps a portion of the second peripheral driving low voltage line 182-2 to which the driving low voltage ELVSS is applied. In this case, when the number of insulating layers between the driving voltage pad 181-3 and the second peripheral driving low voltage line 182-2 is small, parasitic capacitance increases, and a short circuit may occur due to misalignment and dielectric breakdown. However, when Fig.12 When the number of insulating layers increases in the exemplary embodiment of the present invention shown in , parasitic capacitance is reduced and the possibility of short circuit can be reduced.

[0128] like Fig.11 and Fig.12 As shown in FIG. 1 , the cathode 410 and the second peripheral driving low voltage line 182-2 are directly connected to each other in the organic insulating layer 15 without providing a layer in the anode. Figure 8 and Fig. 9 The structure in which the connection member is not included in the anode is the same as the lower peripheral area 120 shown in FIG. 1 , and thus, the possibility of a short circuit between the driving voltage wiring and the driving low voltage wiring is eliminated.

[0129] In addition, in order to reduce the possibility of short circuit between the driving voltage wiring and the driving low voltage wiring, Fig.13 and Fig.14 An exemplary embodiment of the present invention in which the cathode 410 does not overlap the second peripheral driving voltage line 181 - 2 is shown.

[0130] Fig.13 is an enlarged view of the other side peripheral area of ​​the organic light emitting diode display according to another exemplary embodiment of the present invention, Fig.14 yes Fig.13 A cross-sectional view taken along line XIV-XIV.

[0131] and Figures 10 to 12 In contrast, the present invention Fig.13 and Fig.14The exemplary embodiment shown in has a structure in which the cathode 410 does not overlap with the second peripheral driving voltage line 181-2 in the peripheral area 120. In this case, the driving low voltage ELVSS is not applied to the cathode 410 through the upper peripheral area. In other words, the cathode 410 is provided with the driving low voltage ELVSS through the lower peripheral area, and can also receive the driving low voltage ELVSS through the left and right sides of the peripheral area 120. In addition, as Fig.19 As shown in FIG. 1 , the driving low voltage lines 182 and 182 ′ applying the driving low voltage ELVSS are arranged in a mesh structure in the display area 110 , and thus, the cathode 410 may be prevented from being applied with a different driving low voltage ELVSS at each position.

[0132] However, according to an exemplary embodiment of the present invention, the driving low voltage ELVSS may be applied to the cathode 410 in the upper peripheral region at some locations, and in this case, Figures 10 to 12 The structures shown in may be formed only in corresponding positions.

[0133] in addition, Fig.14 The exemplary embodiment of the present invention shown in FIG. Fig.11 A structure in which the driving low voltage pad 182-3 is disposed in the second gate conductive layer. However, according to an exemplary embodiment of the present invention, the driving low voltage pad 182-3 may be disposed in the first gate conductive layer.

[0134] In the following, the following will describe Fig.15 and Fig.16 An exemplary embodiment of the present invention is shown in FIG. Fig.15 and Fig.16 In the embodiment, the number of insulating layers between the driving voltage pad 181-3 and the second peripheral driving low voltage line 182-2 is increased to eliminate a short circuit that may occur in a portion where the second peripheral driving low voltage line 182-2 and the driving voltage pad 181-3 overlap each other.

[0135] Fig.15 is an enlarged view of another peripheral area of ​​an organic light emitting diode display according to another exemplary embodiment of the present invention, Fig.16 yes Fig.15 A cross-sectional view taken along line XVI-XVI.

[0136] and Figures 10 to 13 Different, in Fig.15In the embodiment, the driving voltage pad 181-3 does not extend to the second peripheral driving voltage line 181-2. A peripheral driving voltage connection portion 1181-3 (hereinafter, also referred to as a first driving voltage connection portion) is further included to connect with the second peripheral driving voltage line 181-2. The peripheral driving voltage connection portion 1181-3 is disposed under the semiconductor layer and is formed in a metal layer disposed on the substrate 10.

[0137] The peripheral driving voltage connection portion 1181-3 extends in the vertical direction and is connected between the driving voltage pad 181-3 and the second peripheral driving voltage line 181-2. Fig.16 , the driving voltage pad 181-3 and the peripheral driving voltage connection portion 1181-3 are connected to each other through the opening 403, and the second peripheral driving voltage line 181-2 and the peripheral driving voltage connection portion 1181-3 are connected to each other through the opening 401. Therefore, the driving voltage pad 181-3 and the second peripheral driving voltage line 181-2 are connected to each other. Therefore, the driving voltage ELVDD applied through the driving voltage pad 181-3 is applied to the second peripheral driving voltage line 181-2 through the peripheral driving voltage connection portion 1181-3, and then transmitted to the driving voltage line 181 of the display area 110 through the second peripheral driving voltage line 181-2.

[0138] In addition, a metal layer may be formed on the substrate 10 to have a lower resistance than that of the gate conductive layer.

[0139] In addition, according to an exemplary embodiment of the present invention, the peripheral driving voltage connection portion 1181-3 may be formed in a layer other than the metal layer. Fig.17 Describe this structure.

[0140] Fig.17 yes Fig.15 A cross-sectional view taken along line XVI-XVI.

[0141] Fig.17 A structure is shown in which the peripheral driving voltage connection portion 1181-3 is provided in the anode.

[0142] Reference Fig.17 , the driving voltage pad 181-3 and the peripheral driving voltage connection portion 1181-3 are connected to each other through the opening 403, and the second peripheral driving voltage line 181-2 and the peripheral driving voltage connection portion 1181-3 are connected to each other through the opening 401. Therefore, the driving voltage ELVDD applied through the driving voltage pad 181-3 is applied to the second peripheral driving voltage line 181-2 through the peripheral driving voltage connection portion 1181-3, and thus is transmitted to the driving voltage line 181 of the display area 110 through the second peripheral driving voltage line 181-2.

[0143] and Fig.17 Compared to the exemplary embodiment of the present invention shown in Fig.16 The exemplary embodiment of the present invention shown in has low resistance, low parasitic capacitance between the driving voltage wiring and the driving low voltage wiring, and less possibility of short circuit. However, according to the exemplary embodiment of the present invention, as Fig.17 As shown in , the peripheral driving voltage connection portion 1181-3 may be formed in the anode.

[0144] Hereinabove, the exemplary embodiment of the present invention in which the peripheral driving voltage line 181 - 1 and the peripheral driving low voltage connection portion 182 - 1 and the second peripheral driving voltage line 181 - 2 and the second peripheral driving low voltage line 182 - 2 are formed in the same layer has been described.

[0145] However, according to an exemplary embodiment of the present invention, these lines can be arranged in different layers, thereby reducing the possibility of short circuits. Fig.18 An exemplary embodiment of the present invention having the peripheral driving voltage line 181 - 1 and the peripheral driving low voltage connection portion 182 - 1 in different layers is described.

[0146] Fig.18 is a cross-sectional view of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0147] Fig.18 is with Figure 3 In a cross-sectional view corresponding to the cross-sectional view of the embodiment, the peripheral driving voltage line 181-1 and the peripheral driving low voltage connection part 182-1 are formed in different layers. In other words, the peripheral driving voltage line 181-1 is arranged on the interlayer insulating layer 14 and is thus formed as a first data conductive layer, and the peripheral driving low voltage connection part 182-1 is arranged on the second interlayer insulating layer 14-1 and is thus formed as a second data conductive layer. In this case, two masks are required, resulting in an increase in manufacturing costs; however, the possibility of a short circuit between the driving voltage wiring to which the driving voltage ELVDD is applied and the driving low voltage wiring to which the driving low voltage ELVSS is applied can be further reduced. For example, as the number of pixels of the display device gradually increases to 4K, 8K, etc., the pixels of the display device are clustered, and therefore, the gap between the driving voltage wiring and the driving low voltage wiring can be reduced. Therefore, the present invention, wherein Fig.18 The exemplary embodiment shown in FIG. 1 in which the driving voltage wiring and the driving low voltage wiring are formed in different layers may be used even if the manufacturing cost increases.

[0148] In addition, according to an exemplary embodiment of the present invention, the second peripheral driving voltage line 181 - 2 and the second peripheral driving low voltage line 182 - 2 may be formed in different layers.

[0149] In the above, the structure of the driving voltage wiring and the driving low voltage wiring in the peripheral area 120 disposed in the upper side and the lower side of the display area 110 has been described. However, the driving voltage wiring and the driving low voltage wiring may also be formed in the peripheral area 120 disposed in the left and right sides of the display area 110. In this case, the structure of the driving voltage wiring and the driving low voltage wiring may be similar to the structure in which the driving voltage wiring and the driving low voltage wiring are formed in the upper peripheral area. However, in addition to the fan-out structure, according to an exemplary embodiment of the present invention, the driving voltage wiring and the driving low voltage wiring may be formed in the lower peripheral area.

[0150] In the above, various examples of the driving voltage wiring and the driving low voltage wiring have been described. However, the present invention is not limited thereto, and additional variations are contemplated as to which layer each wiring is formed.

[0151] In the following, reference will be made to Fig.19 A structure in which a driving voltage wiring and a driving low voltage wiring are provided in the display region 110 is described.

[0152] Fig.19 is a schematic diagram of a display area of ​​an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0153] Fig.19 Driving voltage lines 181 and 181 ′ and driving low voltage lines 182 and 182 ′ disposed between pixels PX are schematically illustrated.

[0154] exist Fig.19 In the exemplary embodiment of the present invention shown in , the driving voltage lines 181 and 181' include a driving voltage line 181 (also referred to as a vertical driving voltage line) and a driving voltage line 181' (also referred to as a horizontal driving voltage line) along the vertical direction formed in a mesh or grid-like structure. The vertical driving voltage line 181 is arranged in the data conductive layer, and the horizontal driving voltage line 181' is arranged in the data conductive layer or in another layer, and thus is electrically connected through the opening.

[0155] In addition, the driving low voltage lines 182 and 182' include a driving low voltage line 182 (also referred to as a vertical driving low voltage line or a second driving low voltage line) and a driving low voltage line 182' (also referred to as a horizontal driving low voltage line or a first driving low voltage line) in a vertical direction formed with a mesh or grid-like structure. The vertical driving low voltage line 182 is arranged in the data conductive layer, and the horizontal driving low voltage line 182' is arranged in the data conductive layer or in another layer. When the vertical driving low voltage line 182 and the horizontal driving low voltage line 182' are arranged in different layers, they can be electrically connected to each other through an opening. Since the cathode 410 covers the entire display area 110, even when one of the vertical driving low voltage line 182 and the horizontal driving low voltage line 182' is omitted, the remaining lines can also be connected to the cathode 410 to form a mesh structure, so one of the vertical driving low voltage line 182 and the horizontal driving low voltage line 182' can be omitted.

[0156] In addition, Fig.19 , the vertical driving voltage line 181 is not disposed in a portion in which the vertical driving low voltage line 182 is disposed; however, according to an exemplary embodiment of the present invention, the vertical driving voltage line 181 may be disposed in a portion in which the vertical driving low voltage line 182 is disposed.

[0157] exist Fig.19 In the embodiment, the display area 110 includes driving voltage lines 181 and 181' and driving low voltage lines 182 and 182', but according to an exemplary embodiment of the present invention, only the driving voltage lines 181 and 181' may have a mesh structure, and the driving low voltage lines 182 and 182' may not have a mesh structure. However, according to an exemplary embodiment of the present invention, the driving voltage lines 181 and 181' may not have a mesh structure, and only the driving low voltage lines 182 and 182' may have a mesh structure.

[0158] In the following, reference will be made to Fig. 20 The circuit diagram of FIG. 1 describes the structure of a pixel used in the present exemplary embodiment.

[0159] Fig. 20 is a circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0160] The pixel PX according to the present exemplary embodiment includes three transistors T1, T2, and T3, an organic light emitting diode (OLED), and two capacitors C st and C oledIn addition, as signal lines, gate lines SC, previous gate lines SS, data lines 171, driving voltage lines 181, detection signal lines 173, and driving low voltage lines 182 are included. Here, the detection signal line 173 is also used as an initialization voltage line to which an initialization voltage INT is applied.

[0161] Fig. 20 The pixel PX includes a driving transistor T1, a switching transistor (e.g., a second transistor T2) connected to the gate line SC, and an initialization transistor (e.g., a third transistor T3 (hereinafter, also referred to as a detection transistor)) connected to the previous gate line SS. The third transistor T3 may be connected to a signal line that transmits a gate-on voltage at a timing different from that of the previous gate line SS.

[0162] The gate line SC is connected to the gate driver and transmits a scan signal to the second transistor T2 , and extends in a horizontal direction.

[0163] The previous gate line SS is connected to the gate driver and transmits a previous scanning signal applied to the pixel PX disposed at the previous stage to the third transistor T3. Like the gate line SC, the previous gate line SS also extends in the horizontal direction.

[0164] The data line 171 extends in a vertical direction, and is a wiring that receives a data voltage (eg, Data) from the driving chip 250 and transmits the received data voltage to the pixel PX.

[0165] The detection signal line 173 also extends in the vertical direction, and a single detection signal line 173 may be formed in each row of the plurality of pixels PX.

[0166] The driving voltage line 181 applies a driving voltage ELVDD, and the driving low voltage line 182 applies a driving low voltage ELVSS. According to an exemplary embodiment of the present invention, the driving voltage line 181 extends in a vertical direction, and may further include a portion extending in a horizontal direction and may be formed in a mesh structure.

[0167] The driving low voltage line 182 may be formed to completely cover the cathode 410 of the pixel PX of the display area 110. However, when the cathode 410 is provided with a single plate structure, a voltage difference may occur. In order to prevent the voltage difference, the driving low voltage line 182 may further include a mesh structure including a portion extending in the horizontal direction and a portion extending in the vertical direction.

[0168] Hereinafter, a plurality of transistors will be described.

[0169] First, the driving transistor T1 is a transistor that controls current output according to a data voltage applied to a gate electrode, and the output driving current is applied to the organic light emitting diode OLED to adjust the brightness of the organic light emitting diode OLED according to the data voltage. For example, the first electrode (e.g., input side electrode) of the driving transistor T1 is set to receive the driving voltage ELVDD, and the second electrode (e.g., output side electrode) is connected to the anode of the organic light emitting diode OLED. In addition, the gate electrode of the driving transistor T1 is connected to the second electrode (e.g., output side electrode) of the second transistor T2 to receive the data voltage.

[0170] In addition, the gate electrode of the driving transistor T1 is connected to the storage capacitor C st The first electrode of the storage capacitor C st The data voltage transmitted to the gate electrode of the driving transistor T1 is controlled to be maintained for one frame period. Therefore, the voltage of the gate electrode of the driving transistor T1 is stored in the storage capacitor C st The voltage in φ1 changes, and therefore, the driving current output from the driving transistor T1 is changed and constantly output for one frame period.

[0171] In addition, according to an exemplary embodiment of the present invention, the driving transistor T1 may also have a metal layer M1 below the semiconductor layer provided with the channel. Such a metal layer M1 may overlap the channel and the gate electrode of the driving transistor T1, thereby improving the characteristics of the driving transistor T1 and maintaining the voltage of the gate electrode of the driving transistor T1. The metal layer M1 may be electrically connected to the second electrode of the driving transistor T1 and to the anode of the organic light emitting diode OLED. However, according to an exemplary embodiment of the present invention, the driving voltage ELVDD may be transmitted to the metal layer M1.

[0172] The second transistor T2 (hereinafter, also referred to as a switching transistor) is a transistor that receives a data voltage in the pixel PX. The gate electrode of the second transistor T2 is connected to the gate line SC, the first electrode thereof is connected to the data line 171, and the second electrode thereof (e.g., the output side electrode) is connected to the gate electrode of the driving transistor T1. When the second transistor T2 is turned on according to the scanning signal transmitted through the gate line SC, the data voltage transmitted through the data line 171 is transmitted to the gate electrode of the driving transistor T1 and then stored in the storage capacitor C. st middle.

[0173] The third transistor T3 (hereinafter, also referred to as an initialization transistor or a sensing transistor) enables the second electrode (output side electrode) of the driving transistor T1, the storage capacitor C stThe second electrode of the third transistor T3 is connected to the anode of the organic light emitting diode OLED. The gate electrode of the third transistor T3 is connected to the previous gate line SS, and the first electrode thereof is connected to the initialization voltage line 173. The second electrode of the third transistor T3 is electrically connected to the second electrode (output side electrode) of the driving transistor T1, and therefore, the second electrode of the third transistor T3 is connected to the anode of the organic light emitting diode OLED.

[0174] The detection signal line 173 transmits an initialization voltage INT based on a period of time, or detects a voltage of an anode to which the second electrode of the third transistor T3 is connected. Therefore, the third transistor T3 is also referred to as a detection transistor T3.

[0175] Hereinafter, the operation of the third transistor T3 will be described. The voltage of the anode of the organic light emitting diode OLED when emitting light is stored in the storage capacitor C st In this case, the data voltage is stored in the storage capacitor C st In another electrode of. In this case, when the gate-on voltage is applied to the gate electrode of the third transistor T3, the detection signal line 173 operates as an initialization voltage line, so that the voltage of the anode is transmitted to the detection part. Hereinafter, this is referred to as the detection period. After the voltage of the anode is transmitted to the detection part, the detection signal line 173 applies the initialization voltage INT to the anode so that the voltage of the anode is initialized during the remaining period in which the gate-on voltage is applied to the gate electrode of the third transistor T3. Hereinafter, this is referred to as the initialization period.

[0176] When the voltage detected during the detection period is determined to be different from the voltage of the anode, the data voltage can be adjusted and then applied to the pixel PX. In other words, the characteristics of the driving transistor T1 change and detect this change to provide a suitable data voltage so that the organic light emitting diode OLED can emit light normally.

[0177] The voltage of the anode of the organic light emitting diode OLED is passed through two capacitors C st and C oled is stored and then held during one frame.

[0178] However, according to an exemplary embodiment of the present invention, other than Fig. 20 Pixels other than the pixel PX shown in .

[0179] have Fig. 20 The pixel PX of the circuit structure shown in FIG. Fig.21 and Fig. 22 Various layered structures shown in .

[0180] First, we will describe Fig.21The structure shown in .

[0181] Fig.21 is a cross-sectional view of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0182] exist Fig.21 The cross-sectional view mainly shows Fig. 20 The driving transistor T1 and the storage capacitor C st and organic light-emitting diodes OLED.

[0183] The metal layer M1 is formed on the substrate 10 , and the buffer layer 11 is stacked on the metal layer M1 and the substrate 10 .

[0184] The semiconductor layers S1, Ch, and S2 are formed on the buffer layer 11. The semiconductor layers S1, Ch, and S2 include a first region S1, a channel region Ch, and a second region S2 of the driving transistor T1. The gate insulating layer 12 is formed on the semiconductor layers S1, Ch, and S2.

[0185] The gate conductive layer is formed on the gate insulating layer 12 and Fig.21 In the circuit, the gate electrode Gate and the storage capacitor C st The first electrode cap-1 is shown as a gate conductive layer. The gate insulating layer 12 is only provided between the gate electrode Gate and the storage capacitor C st beneath the first electrode cap-1.

[0186] The second gate insulating layer 13 is disposed on the gate insulating layer 12 to cover the gate insulating layer 12 and the storage capacitor C st The second gate conductive layer is disposed on the second gate insulating layer 13 and Fig.21 , the connection electrodes S1-1, S2-1 and Gate-1 electrically connected to the electrodes of the driving transistor T1 and the storage capacitor C are shown. st The second electrode cap-2 of the storage capacitor C is connected to the output side connection electrode S2-1 connected to the second electrode of the driving transistor T1 among the connection electrodes S1-1, S2-1 and Gate-1. st The gate electrode is formed by a first electrode cap-1, a second electrode cap-2, and a second gate insulating layer 13 disposed between the first electrode cap-1 and the second electrode cap-2.

[0187] The second gate conductive layer is covered with an interlayer insulating layer 14 .

[0188] The data conductive layer is formed on the interlayer insulating layer 14 and Fig.21In the embodiment, as a data conductive layer, a driving voltage line 181 for transmitting the driving voltage ELVDD to the first electrode of the driving transistor T1, an output electrode DD of the driving transistor T1 connected to the output side connection electrode S2-1, and a peripheral driving low voltage connection portion 182-1 provided in the peripheral area 120 are formed as a data conductive layer. The output electrode DD of the driving transistor T1 is also connected to the storage capacitor C st The second electrode cap-2 is connected.

[0189] The data conductive layer is covered by the organic insulating layer 15. The anode is formed on the organic insulating layer 15, and is connected to the output electrode DD of the driving transistor T1 and receives the output of the driving transistor T1.

[0190] The barrier rib 20 is disposed on the anode, and the organic emission layer OL is disposed on a portion of the anode and is exposed through the opening of the barrier rib 20. The cathode 410 is disposed on the organic emission layer OL and the barrier rib 20.

[0191] The cathode electrode 410 is connected to the peripheral driving low voltage connection portion 182 - 1 exposed through the barrier rib 20 and the opening provided in the organic insulating layer 15 , thereby receiving the driving low voltage ELVSS.

[0192] Fig.21 The exemplary embodiment of the present invention shown in is a structure in which a metal layer, a semiconductor layer, a gate conductive layer, a second gate conductive layer, a data conductive layer, an anode layer, and a cathode layer are stacked. However, according to an exemplary embodiment of the present invention, this stacking structure may be different. Fig. 22 Another exemplary embodiment of the present invention is described.

[0193] Fig. 22 is a cross-sectional view of a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention.

[0194] The metal layer M1 is formed on the substrate 10 , and the buffer layer 11 is stacked on the metal layer M1 and the substrate 10 .

[0195] The semiconductor layers S1, Ch, and S2 are formed on the buffer layer 11. The semiconductor layers S1, Ch, and S2 include a first region S1, a channel region Ch, and a second region S2 of the driving transistor T1. The gate insulating layer 12 is formed on the semiconductor layers S1, Ch, and S2.

[0196] The gate conductive layer is formed on the gate insulating layer 12 and Fig. 22 , the gate electrode Gate and the storage capacitor C are shown st The gate insulating layer 12 is only provided between the gate electrode Gate and the storage capacitor C st beneath the first electrode cap-1.

[0197] The interlayer insulating layer 14 is provided between the gate electrode Gate and the storage capacitor C st The first electrode cap-1 is formed on the gate electrode Gate and the storage capacitor C st The first electrode cap-1.

[0198] The data conductive layer is formed on the interlayer insulating layer 14 and Fig. 22 In the embodiment, a driving voltage line 181 for transmitting a driving voltage ELVDD to a first electrode of the driving transistor T1, an output electrode DD of the driving transistor T1, a peripheral driving low voltage connection portion 182-1 disposed in the peripheral area 120, and a storage capacitor C are formed. st The output electrode DD of the driving transistor T1 is connected to the metal layer M1. Fig. 22 , but the output electrode DD of the driving transistor T1 is connected to the storage capacitor C st The second electrode cap-2 is electrically connected to the

[0199] The data conductive layer may be covered by a second interlayer insulating layer 14-1 (also referred to as a passivation layer). An opening exposing the peripheral driving low voltage connection portion 182-1 is provided in the second interlayer insulating layer 14-1, and an interlayer low voltage connection portion C-PXL electrically connected to the opened peripheral driving low voltage connection portion 182-1 is formed on the second interlayer insulating layer 14-1. The layer formed on the second interlayer insulating layer 14-1 is referred to as a second data conductive layer (also referred to as a pixel electrode layer in other embodiments).

[0200] The organic insulating layer 15 is formed on the second data conductive layer to cover the second data conductive layer. The anode is formed on the organic insulating layer 15, and the anode is connected to the output electrode DD of the driving transistor T1 and receives the output of the driving transistor T1.

[0201] The barrier ribs 20 are disposed on the anodes, and the organic emission layer OL is formed in portions exposed by the openings of the barrier ribs 20. The cathode 410 is disposed on the organic emission layer OL and the barrier ribs 20.

[0202] The cathode 410 is connected to the interlayer low voltage connection portion C-PXL exposed through the barrier rib 20 and the opening provided in the organic insulating layer 15 , and receives the driving low voltage ELVSS from the peripheral driving low voltage connection portion 182 - 1 through the interlayer low voltage connection portion C-PXL.

[0203] Fig. 22 The exemplary embodiment of the present invention shown in is a structure in which a metal layer, a semiconductor layer, a gate conductive layer, a data conductive layer, a second data conductive layer, an anode, and a cathode are stacked.

[0204] Fig.21 The exemplary embodiments of the present invention shown in Fig. 22 The exemplary embodiments of the present invention shown in are different from each other based on whether a second gate conductive layer is included and whether a second data conductive layer is included.

[0205] Since each pixel PX is formed by a stacked structure such as Fig.21 and Fig. 22 So Figures 2 to 19 The structure shown in can be formed by different layers. In other words, a layer in which each driving voltage wiring and driving low voltage wiring are formed differently by a combination of a metal layer, a gate conductive layer (including a second gate conductive layer), a data conductive layer (including a second data conductive layer) and an anode can be formed.

[0206] According to an exemplary embodiment of the present invention, one gate conductive layer may include a second gate conductive layer, and the data conductive layer may include a second data conductive layer.

[0207] Exemplary embodiments of the present invention can prevent a short circuit between a driving voltage line and a driving low voltage line disposed adjacent to each other in a peripheral region.

[0208] According to an exemplary embodiment of the present invention, the area where the pixel electrode layer electrically connected to the driving low voltage line overlaps the driving voltage line is reduced, thereby preventing a short circuit between the driving low voltage line and the driving voltage line. Since the portion to which the driving low voltage is applied and the portion to which the driving voltage is applied are arranged as far as possible, a short circuit between the two portions can be prevented.

[0209] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various modifications may be made therein without departing from the spirit and scope of the invention as defined in the claims.

Claims

1. An organic light emitting diode display, the organic light emitting diode display include: Data wiring, including a main data line arranged in the display area and a first data line arranged in the peripheral area; a driving voltage wiring including a main driving voltage line disposed in the display area and a first driving voltage line connected to the main driving voltage line and disposed in the peripheral area while extending in a first direction; as well as a driving low voltage wiring including a cathode extending to the peripheral area while overlapping the display area and a plurality of first driving low voltage connection parts connected to the cathode and disposed in the peripheral area, Wherein, each of the multiple first drive low voltage connection parts includes: a wiring part extending along the first direction; and a pad part electrically connected to the wiring part, protruding from opposite sides of the wiring part in a second direction intersecting the first direction, and constituting opposite ends of the first drive low voltage connection part.

2. The organic light emitting diode display according to claim 1, in, The driving low voltage wiring further includes a second driving low voltage connection portion electrically connecting the cathode and the plurality of first driving low voltage connection portions, and The second driving low voltage connection portion includes a wiring portion extending along the first direction and a connection portion electrically connected to the wiring portion.

3. The organic light emitting diode display according to claim 2, in, The first driving voltage line includes a wiring portion extending along the first direction and a pad portion electrically connected to the wiring portion, and Wherein, in a plan view, the second driving low voltage connection portion and the first driving voltage line overlap each other.

4. The organic light emitting diode display according to claim 3, in, The width by which the wiring portion of the second driving low voltage connection portion overlaps the wiring portion of the first driving voltage line is half or less than half of the width of the wiring portion of the first driving voltage line.

5. The organic light emitting diode display according to claim 3, in, The wiring portion of the second driving low voltage connection portion overlaps the pad portion of the first driving voltage line.

6. The organic light emitting diode display according to claim 2, in, The first driving voltage line extends to an area adjacent to the display area and includes only a plurality of pads separated from each other.

7. The organic light emitting diode display according to claim 1, in, The first driving voltage line and the plurality of first driving low voltage connection portions are disposed in different layers.

8. The organic light emitting diode display according to claim 1, in, The driving voltage wiring further includes a second driving voltage line disposed in the display area and electrically connected to the main driving voltage line. The driving voltage wiring has a grid shape in the display area.

9. The organic light emitting diode display according to claim 1, in, The driving low voltage wiring further includes a first driving low voltage line and a second driving low voltage line disposed in the display area and having a mesh shape.

10. An organic light emitting diode display, the organic light emitting diode display include: Data wiring, including a main data line arranged in the display area and a first data line arranged in the peripheral area; a driving voltage wiring including a main driving voltage line disposed in the display area, a first driving voltage line connected to the main driving voltage line and disposed in the peripheral area, and a plurality of driving voltage pads for receiving a driving voltage, wherein the first driving voltage line extends along a first direction; and a driving low voltage wiring including a cathode extending to the peripheral area and overlapping the display area, a peripheral driving low voltage line disposed in the peripheral area and connected to the cathode, and a plurality of driving low voltage pads for receiving a driving low voltage, wherein the plurality of driving voltage pads are formed in a layer different from that of the first driving voltage line, and The plurality of driving low voltage pads are formed in a layer different from that of the peripheral driving low voltage lines.

11. The organic light emitting diode display according to claim 10, in, The first driving voltage line and the peripheral driving low voltage line are formed in the data conductive layer, and The plurality of driving voltage pads and the plurality of driving low voltage pads are formed in a gate conductive layer.

12. The organic light emitting diode display according to claim 10, in, The driving voltage wiring further includes a first driving voltage connecting portion electrically connecting the plurality of driving voltage pads of the driving voltage wiring and a second driving voltage line.

13. The organic light emitting diode display according to claim 10, in, The driving voltage wiring further includes a second driving voltage line disposed in the display area and electrically connected to the main driving voltage line. Wherein, the driving voltage wiring has a grid structure in the display area.

14. The organic light emitting diode display according to claim 10, in, The driving low voltage wiring further includes a first driving low voltage line and a second driving low voltage line disposed in the display area and having a mesh structure.

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