Display device

Abstract

A display device is provided. The display device includes: a first display area including a plurality of first pixel areas; a second display area including a plurality of second pixel areas and a plurality of transmission areas; a plurality of pixels arranged in a matrix form in the first display area and the second display area; and a first signal line and a second signal line arranged to correspond to each pixel column of the plurality of pixels. In each pixel column, one of the first signal line and the second signal line may extend throughout the first display area and the second display area, and the remaining one of the first signal line and the second signal line may not be arranged in the second display area.

Description

[0001] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2019-0018527, filed on February 18, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] An exemplary embodiment of the invention relates to a display device. Background Art

[0003] The display device includes a display panel including pixels that display an image. The display device may include a sensor that senses the proximity of an object, ambient brightness, etc., and the sensor may be disposed in the periphery of the display panel. The sensor is disposed in a frame area (an area surrounding the screen) of the display device, an optical member is included in the frame area (or edge area), and the object may be recognized by the sensor.

[0004] For example, when the sensor is an optical sensor such as an infrared sensor, the sensor may emit light and receive light reflected by an object. The display device may calculate the distance between the display device and the object based on the intensity of the reflected light, and may not display an image when the distance is within a predetermined distance. When the sensor is an illuminance sensor, the sensor may measure the illuminance around the display device, and the display device may adjust the brightness of the screen based on the measured illuminance.

[0005] By reducing the size of the bezel of the display device, the screen-to-body ratio of the display device (i.e., the ratio of the screen to the display device when viewed from the front of the display device) can be increased. The screen-to-body ratio represents the technical level of the display device and is important for consumers to choose products. Summary of the invention

[0006] Since it is difficult to dispose a sensor in a bezel area as the size of a bezel of a display device decreases, it is desirable to develop a technology for disposing a sensor and for sensing.

[0007] Exemplary embodiments provide a display device which can improve transmittance and display quality of a display area corresponding to an optical member in a display device including the optical member.

[0008] An exemplary embodiment provides a display device, the display device comprising: a first display area including a plurality of first pixel areas; a second display area including a plurality of second pixel areas and a plurality of transmission areas; a plurality of pixels arranged in a matrix form in the first display area and the second display area; and a first signal line and a second signal line provided to correspond to each of the pixel columns in the plurality of pixels. In each of the pixel columns, one of the first signal line and the second signal line may extend throughout the first display area and the second display area, and the remaining one of the first signal line and the second signal line may not be provided in the second display area.

[0009] In an exemplary embodiment, the first signal line and the second signal line may be provided in each of the pixel columns in the first display area.

[0010] In an exemplary embodiment, the plurality of second pixel regions and the plurality of transmission regions may be arranged in a checkerboard pattern in the second display area.

[0011] In exemplary embodiments, the first signal line and the second signal line may be data lines transmitting data signals.

[0012] In an exemplary embodiment, each of the second pixel areas may include at least one pixel electrode, and the plurality of transmission areas may not include a pixel electrode.

[0013] In an exemplary embodiment, the second display area may include a plurality of scan lines and a voltage line disposed in the same layer as the at least one pixel electrode. The voltage line may include a portion overlapping at least one of the plurality of scan lines and extending side by side with the at least one scan line in at least one of the plurality of transmissive areas.

[0014] In an exemplary embodiment, pixels in each of pixel columns among a plurality of pixels may be alternately connected to the first signal line and the second signal line one by one.

[0015] In an exemplary embodiment, the size of the second pixel area and the size of the transmission area may be the same.

[0016] In an exemplary embodiment, a size of at least one of the plurality of transmission regions may be greater than a size of each of the second pixel regions.

[0017] In an exemplary embodiment, each of the second pixel regions may include at least one of a red pixel, a green pixel, and a blue pixel.

[0018] In an exemplary embodiment, each of the second pixel regions may include one red pixel, one blue pixel, and two green pixels.

[0019] In an exemplary embodiment, the second display area may display a single color.

[0020] In an exemplary embodiment, the display device may further include an optical member overlapping the second display area.

[0021] An exemplary embodiment provides a display device, the display device comprising: a first display area including a plurality of first pixel areas; a second display area including a plurality of second pixel areas and a plurality of transmission areas; a plurality of pixels arranged in a matrix form in the first display area and the second display area; a plurality of scan lines extending in a first direction in the first display area and the second display area; and a first signal line and a second signal line extending in a second direction crossing the first direction in the plurality of pixels and overlapping each other in each of the pixel columns. In each of the pixel columns, both the first signal line and the second signal line may be provided in the first display area, and only one of the first signal line and the second signal line may be provided in the second display area.

[0022] In an exemplary embodiment, the first signal line and the second signal line may be data lines transmitting data signals, and pixels in each of pixel columns among the plurality of pixels may be alternately connected to the first signal line and the second signal line one by one.

[0023] In an exemplary embodiment, it is possible to improve sensing sensitivity and display quality of an optical member by improving transmittance of a display area corresponding to the optical member in a display device including the optical member. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other exemplary embodiments, advantages and features of the present disclosure will become more apparent by describing exemplary embodiments of the present disclosure in further detail with reference to the attached drawings.

[0025] Figure 1 A schematic top plan view of an exemplary embodiment of a display device is shown.

[0026] Figure 2 A schematic cross-sectional view of an exemplary embodiment of a display device is shown.

[0027] Figure 3 , Figure 4 and Figure 5 A schematic plan view showing an exemplary embodiment of a first display area and a second display area of ​​a display device.

[0028] Figure 6 A plan view showing an exemplary embodiment of a second display area of ​​a display device.

[0029] Figure 7 A circuit diagram of one pixel of a display device is shown.

[0030] Figure 8 and Fig. 9 Partial plan views of exemplary embodiments of a first display area of ​​a display device are respectively shown.

[0031] Fig.10 Shown along Figure 8 A sectional view taken along line Ⅹ-Ⅹ'.

[0032] Fig.11 Shown along Figure 8 A cross-sectional view taken along line XI-XI'.

[0033] Fig.12 A plan view showing an exemplary embodiment of a pixel electrode layer of a display device is shown.

[0034] Fig.13 and Fig.14 Partial plan views of exemplary embodiments of a second display area of ​​a display device are respectively shown.

[0035] Fig.15 A circuit diagram showing an exemplary embodiment of a circuit connected to a data line of a display device.

[0036] Fig.16 A waveform diagram showing an exemplary embodiment of a driving signal of a display device is shown. DETAILED DESCRIPTION

[0037] The invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the invention.

[0038] Parts irrelevant to the description will be omitted to clearly describe the invention, and like reference numerals denote like elements throughout the specification.

[0039] In addition, in the drawings, the size and thickness of each element are arbitrarily shown for ease of description, but the invention is not limited to the size and thickness of each element shown in the drawings. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thickness of some layers and regions are exaggerated for ease of description.

[0040] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0041] In the specification, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” and “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0042] In the drawings, as symbols for indicating directions, "x" is a first direction, "y" is a second direction perpendicular to the first direction, and "z" is a third direction perpendicular to the first direction and the second direction. The first direction x, the second direction y, and the third direction z may correspond to the horizontal direction, the vertical direction, and the thickness direction of the display device, respectively.

[0043] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0044] Hereinafter, a display device (a light emitting display device as an example) according to an embodiment will be described with reference to the drawings.

[0045] First, refer to Figure 1 and Figure 2 Exemplary embodiments of a display device are described. Figure 1 shows a schematic top plan view of an exemplary embodiment of a display device 1, Figure 2 A schematic cross-sectional view of an exemplary embodiment of a display device 1 is shown.

[0046] Reference Figure 1 and Figure 2 , the display device 1 may include a display panel 10 , a flexible printed circuit film 20 connected to the display panel 10 , a driving device including an integrated circuit (“IC”) chip 30 , and an optical member 40 .

[0047] The display panel 10 may include a display area DA for displaying an image and a non-display area NA surrounding the display area DA. The display area DA may correspond to a screen, and the non-display area NA may correspond to a frame. The pixels PX are arranged in a matrix form in the display area DA. Circuits and / or signal lines for generating and / or transmitting various signals to be applied to the display area DA are provided in the non-display area NA. Scan lines, emission control lines, data lines, drive voltage lines, etc. are connected to each pixel PX, and the pixel PX may receive scan signals, emission control signals, data signals, drive voltages, etc. from these lines.

[0048] The display area DA includes a first display area DA1 and a second display area DA2. The second display area DA2 has a transmittance higher than that of the first display area DA1 so as to be able to perform another function in addition to the sole function of displaying an image. For this reason, the density of the pixels PX may be lower in the second display area DA2 than in the first display area DA1. Here, the transmittance means the transmittance of light passing through the display panel 10 in the third direction z. The light may be light having a wavelength other than that of visible light (e.g., infrared light), but may also include visible light.

[0049] The ratio of the area in which the image can be displayed in the second display area DA2 (i.e., the area occupied by the pixel area) may be smaller than the ratio of the area occupied by the pixel area in the first display area DA1. In an exemplary embodiment, for example, the second display area DA2 includes a pixel area and a transmission area, and the transmission area has a transmittance higher than the transmittance of the pixel area. The pixel PX may not be disposed in the transmission area. Here, the pixel PX is the minimum unit for forming a screen (i.e., the minimum unit for displaying an image), and each pixel PX may display a specific color (e.g., any one of red, green, and blue colors at various brightness levels) according to an input image signal.

[0050] The second display area DA2 may be disposed above the first display area DA1. As shown, both sides of the second display area DA2 may be the first display area DA1, but the second display area DA2 may be positioned in various ways. In an exemplary embodiment, for example, the second display area DA2 may completely span the upper end of the display area DA to be disposed along the first direction x. The second display area DA2 may be surrounded by the first display area DA1. The second display area DA2 may be disposed at the left or right side of the upper end of the display area DA, and may not be disposed at the central portion of the upper end of the display area DA but may be separately disposed at the left and right sides. The second display area DA2 may be substantially rectangular. In an exemplary embodiment, the second display area DA2 may have various shapes such as a trapezoid, a circle, and an ellipse.

[0051] A driving unit for generating and / or processing various signals for driving the display panel 10 may be provided in the non-display area NA of the display panel 10. The driving unit includes a data driver for applying a data signal to a data line, a scan driver for applying a scan signal to a scan line, an emission driver for applying an emission control signal to an emission control line, and a signal controller for controlling the data driver, the scan driver, and the emission driver. The scan driver and the emission driver may be integrated in the display panel 10 and may be provided at the left and right sides of the display area DA or at one side of the display area DA. The data driver and the signal controller may be provided as an IC chip (also referred to as a driver IC chip) 30, and the IC chip 30 may be provided (e.g., mounted) on the flexible printed circuit film 20 to be electrically connected to the display panel 10. The IC chip 30 may be provided (e.g., mounted) on the non-display area NA of the display panel 10.

[0052] The display panel 10 may include a substrate 110, and the pixel PX may be disposed on the substrate 110. The substrate 110 may be continuously disposed throughout the first display area DA1 and the second display area DA2. The display panel 10 may include an encapsulation layer 210 that completely covers the pixel PX. The encapsulation layer 210 may seal the first display area DA1 and the second display area DA2 to prevent moisture or oxygen from penetrating into the display panel 10. When the encapsulation layer 210 is in the form of a substrate, the substrate 110 and the encapsulation layer 210 may be combined together by a sealant. An anti-reflection layer 300 for reducing external light reflection may be disposed on the encapsulation layer 210, and the anti-reflection layer 300 may include a polarizing layer and / or a retardation layer.

[0053] The optical member 40 may be disposed on the rear surface of the display panel 10. In an exemplary embodiment, the optical member 40 may be a sensor, a camera, a flash, etc. When the optical member 40 is a sensor, the optical member 40 may be a proximity sensor or an illumination sensor. Light of a wavelength used by the optical member 40 may pass through the display panel 10 with a higher transmittance through the second display area DA2. In addition to the optical member 40, various electronic devices may be disposed on the rear surface of the display panel 10.

[0054] The optical member 40 may emit light L in a predetermined wavelength range toward an object OB disposed on the front surface of the display panel 10 or receive light L reflected from the object OB. The light L having a predetermined wavelength may be light having a wavelength that can be processed by the optical member 40, and may be light having a wavelength other than a wavelength in a visible light region, which corresponds to a region of light of an image displayed by the pixel PX. The light L of the predetermined wavelength may mainly pass through a transmission region disposed in the second display area DA2. In an exemplary embodiment, when the optical member 40 uses infrared light, the light of the predetermined wavelength may have a wavelength range of, for example, about 900 nanometers (nm) to about 1000 nm. The optical member 40 may receive light of a predetermined wavelength to be irradiated onto the front surface of the display panel 10. The light of the predetermined wavelength may include visible light. The optical member 40 may be disposed to correspond to the entire second display area DA2, or may be disposed to correspond to only a portion of the second display area DA2. A plurality of optical members 40 may be disposed in the second display area DA2.

[0055] Now refer to Figures 3 to 5 With the attachment described above Figure 1 The first display area DA1 and the second display area DA2 of the display device 1 in the exemplary embodiment will be described first.

[0056] Figure 3 , Figure 4 and Figure 5 A schematic plan view showing an exemplary embodiment of a first display area DA1 and a second display area DA2 of a display device. Figure 3 Schematic plan view showing pixel areas PA1 and PA2 and a transmissive area TA, Figure 4 Specifically, pixels that may be included in the pixel areas PA1 and PA2 are shown, and Figure 5 Some signal lines provided in the pixel areas PA1 and PA2 are shown.

[0057] Reference Figure 3 The first display area DA1 includes a first pixel area PA1, and the second display area DA2 includes a second pixel area PA2 and a transmission area TA. The size of one first pixel area PA1 and the size of one second pixel area PA2 may be the same or different.

[0058] In the first display area DA1, the first pixel area PA1 may be arranged in a matrix form in the first direction x and the second direction y as different directions. In the second display area DA2, the second pixel area PA2 and the transmission area TA may be arranged in a matrix form. The second pixel area PA2 and the transmission area TA may be arranged in a checkerboard ("checkerboard" is also called "checkers board" or "chess board") pattern so that the second pixel area PA2 and the transmission area TA may be uniformly mixed. That is, the transmission area TA is adjacent to one second pixel area PA2 in the first direction x and the second direction y, and the second pixel area PA2 may be adjacent to one transmission area TA in the first direction x and the second direction y. The size of one second pixel area PA2 and the size of one transmission area TA may be the same or different. The respective transmission areas TA may have the same size or may be different in size from each other. The arrangement and size of the second pixel area PA2 and the transmission area TA may be variously changed.

[0059] Each of the pixel areas PA1 and PA2 may include one or more pixels. Figure 4 and Figure 5 In the exemplary embodiment shown in FIG. 1 , each of the pixel areas PA1 and PA2 may include one red pixel R, two green pixels G, and one blue pixel B. Each of the transmission areas TA may have a size corresponding to four pixels.

[0060] The pixels R, G, and B included in the pixel areas PA1 and PA2 form a pixel row R in the first direction x. j , R j+1 , R j+2 , ..., R j+7 , where j is a natural number. Although Figure 4 and Figure 5 Eight pixel rows are shown, but the display area DA may include pixel rows of a number corresponding to a predetermined resolution. In each pixel row, pixels R, G, and B are substantially arranged as a line in a direction parallel to the first direction x. The pixels R, G, and B in each pixel row are repeatedly arranged in the order of blue pixels B, green pixels G, red pixels R, and green pixels G in the first direction x, or repeatedly arranged in the order of red pixels R, green pixels G, blue pixels B, and green pixels G. In each pixel row of the second display area DA2, the transmission area TA may be arranged between adjacent second pixel areas PA2. The arrangement of pixels R, G, and B included in a pixel row may be variously changed. In an exemplary embodiment, pixels R, G, and B may be, for example, repeatedly arranged in the order of red pixels R, blue pixels B, green pixels G, and blue pixels B in the first direction x.

[0061] The pixels R, G, and B included in the pixel areas PA1 and PA2 also form a pixel column C in the second direction y. i , C i+1 , C i+2 , ..., C i+7 , where i is a natural number. Although Figure 4 16 pixel columns are shown and Figure 5 8 pixel columns are shown, but the display area DA may include a number of pixel columns corresponding to the predetermined resolution. In each pixel column, pixels R, G, and B are substantially arranged in a line in a direction parallel to the second direction y. In an exemplary embodiment, for example, Figure 5 The leftmost pixel column C is shown in i The pixel columns C include blue pixels B, blue pixels B, blue pixels B, red pixels R, blue pixels B, and red pixels R. Due to the transmissive area TA in the second display area DA2, the pixel columns C i The red pixel R may not be included in the second display area DA2. In other words, in the second display area DA2, no pixel is disposed at a position where the red pixel R is to be disposed. i Adjacent pixel column C i+1 Only green pixels G are included. Pixel column C i+2 The pixel columns C include red pixels R, red pixels R, red pixels R, blue pixels B, red pixels R, and blue pixels B. Due to the transmissive area TA in the second display area DA2, the pixel columns C i+2 The blue pixel B may not be included in the second display area DA2. i+3 Only green pixels G are included. Four pixel columns C i , C i+1 , C i+2 and C i+3 Such pixel arrangement is repeated as a basic unit in the first direction x. The arrangement of pixels R, G, and B included in one pixel column may be variously changed.

[0062] The scanning lines SL1 and SL2 and the emission control line EL may be arranged along each pixel row R. j , R j+1 , R j+2 , ..., R j+7 The data lines DLa and DLb extend in the first direction x, and may extend along the respective pixel columns C. i , C i+1 , C i+2 , ..., C i+7 Extending in the second direction y.

[0063] The data lines DLa and DLb, which are signal lines for transmitting data signals, may include a first data line DLa and a second data line DLb paired with each other. In each pixel column, one data line of a pair of data lines DLa and DLb may be connected to a pixel disposed on an odd pixel row, and the other data line may be connected to a pixel disposed on an even pixel row. In an exemplary embodiment, for example, in a pair of data lines DLa and DLb, the first data line DLa may be connected to a pixel disposed on an odd pixel row, and the second data line DLb may be connected to a pixel disposed on an even pixel row. Conversely, in a pair of data lines DLa and DLb, the first data line DLa may be connected to a pixel disposed on an even pixel row, and the second data line DLb may be connected to a pixel disposed on an odd pixel row.

[0064] The data lines DLa and DLb in each pixel column are disposed in both the first display area DA1 and the second display area DA2, but one of the data lines DLa and DLb is substantially disposed only in the first display area DA1 and not in the second display area DA2. i In the example, the second data line DLb is not disposed in the second display area DA2. i+1 In the embodiment, the first data line DLa is not arranged in the second display area DA2. Thus, even if only one of the pair of data lines DLa and DLb extends to the second display area DA2, since the pixels are arranged only in even rows or odd rows for each pixel column in the second display area DA2, the pixels arranged in the second display area DA2 can receive data signals through the data line extending to the second display area DA2. In addition, since only one data line is arranged in the transmission area TA of the second display area DA2 in each pixel column, the transmittance of each transmission area TA and the transmittance of the second display area DA2 can be increased.

[0065] Figure 6 A plan view of an exemplary embodiment of a second display area DA2 of a display device is shown.

[0066] Figure 6 An example is shown, in which the first display area DA1 is arranged at the opposite side of the second display area DA2 and the transmission area TA is not the same but varies. Each second pixel area PA2 may include one pixel. In the illustrated embodiment, although each second pixel area PA2 includes a red pixel R, it may include a blue pixel B or a green pixel G, and it may display a monochrome (e.g., a red color, a blue color, or a green color). Each second pixel area PA2 may include two or more of a red pixel R, a green pixel G, and a blue pixel B.

[0067] Pixels (e.g., red pixels R) may be arranged only in even pixel rows or odd pixel rows in each pixel column. Pixels are not arranged in a pixel column (e.g., the fourth pixel column from the left, the third pixel column from the right), and only the transmission area TA may be arranged in the pixel column. The transmission area TA may have a size corresponding to one pixel, a size corresponding to two pixels, or a size corresponding to three pixels. In the illustrated embodiment, the transmission area TA having a size corresponding to three pixels occupies most of the area of ​​the pixel column. The transmission area TA may have a size corresponding to three or more pixels.

[0068] In this way, by reducing the number of pixels included in each second pixel area PA2, the ratio of the transmission area TA can be increased in the second display area DA2, thereby increasing the transmittance of the second display area DA2. However, the density of the pixels is reduced, so the resolution of the second display area DA2 is reduced. Only one of the data lines DLa and DLb described above can be extended in each pixel column in the second display area DA2 to be connected to the pixels set in the odd pixel row or the even pixel row. Therefore, the data voltage can be applied to the pixels set in the second display area DA2, and the transmittance of the transmission area TA can be increased. Both the data lines DLa and DLb can be extended in the pixel column that does not include the pixel in the second display area DA2, and the transmittance of the second display area DA2 can be further increased.

[0069] Figure 7 A circuit diagram showing an exemplary embodiment of one pixel of a display device is shown.

[0070] Reference Figure 7 , one pixel PX includes transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 connected to signal lines 151 , 152 , 153 , 154 , 161 , 171 , and 172 , a capacitor Cst, and a light emitting diode ED.

[0071] The signal lines 151 , 152 , 153 , 154 , 161 , 171 , and 172 may include scan lines 151 , 152 , and 154 , an emission control line 153 , a data line 171 , a driving voltage line 172 , and an initialization voltage line 161 .

[0072] The scan lines 151, 152, and 154 may transmit scan signals GWn, GIn, and GI(n+1), respectively. The scan signals GWn, GIn, and GI(n+1) may transmit a gate-on voltage and a gate-off voltage, which may turn on and off the transistors T2, T3, T4, and T7 included in the pixel PX.

[0073] The scan lines 151, 152, and 154 connected to one pixel PX may include a first scan line 151 capable of transmitting a scan signal GWn, a second scan line 152 capable of transmitting a scan signal GIn having a gate-on voltage at a timing different from that of the first scan line 151, and a third scan line 154 capable of transmitting a scan signal GI(n+1). The second scan line 152 may transmit a gate-on voltage at a timing earlier than that of the first scan line 151. In an exemplary embodiment, when the scan signal GWn is an nth scan signal among scan signals applied during one frame, the scan signal GIn may be a previous scan signal such as an n-1th scan signal, and the scan signal GI(n+1) may be, for example, an nth scan signal. In another exemplary embodiment, the scan signal GI(n+1) may be a scan signal different from the nth scan signal.

[0074] The emission control line 153 may transmit an emission control signal EM to control light emission of the light emitting diode ED. The emission control signal EM may include a gate-on voltage and a gate-off voltage.

[0075] The data line 171, which is one of the data lines DLa and DLb described above, may transmit a data signal Dm. The driving voltage line 172 may transmit a driving voltage ELVDD. The data signal Dm may have different voltage levels according to an image signal input to the display device, and the driving voltage ELVDD may have a substantially constant level. The initialization voltage line 161 may transmit a constant voltage such as an initialization voltage Vint.

[0076] The display device may include a driving device (eg, a scan driver, an emission driver, a data driver, a signal controller, etc.) for generating signals transmitted to the signal lines 151 , 152 , 153 , 154 , 161 , 171 , and 172 .

[0077] The transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 included in one pixel PX may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 .

[0078] The first scan line 151 may transmit a scan signal GWn to the second transistor T2 and the third transistor T3. The second scan line 152 may transmit a scan signal GIn to the fourth transistor T4. The third scan line 154 may transmit a scan signal GI(n+1) to the seventh transistor T7. The emission control line 153 may transmit an emission control signal EM to the fifth transistor T5 and the sixth transistor T6. Each transistor T1, T2, T3, T4, T5, T6 and T7 may include corresponding source electrodes S1, S2, S3, S4, S5, S6 and S7, corresponding drain electrodes D1, D2, D3, D4, D5, D6 and D7, and corresponding gate electrodes G1, G2, G3, G4, G5, G6 and G7, and may be connected as shown.

[0079] The first transistor T1 may receive the data signal Dm transmitted from the data line 171 according to a switching operation of the second transistor T2 , and may supply a driving current Id to the light emitting diode ED.

[0080] The second transistor T2 may be turned on according to the scan signal GWn transmitted through the first scan line 151 to transmit the data signal Dm transmitted from the data line 171 to the source electrode S1 of the first transistor T1 .

[0081] The third transistor T3 may be turned on according to the scan signal GWn transmitted through the first scan line 151 to connect the gate electrode G1 and the drain electrode D1 of the first transistor T1 to each other so that the first transistor T1 is diode-connected.

[0082] The fourth transistor T4 is turned on according to the scan signal GIn transmitted through the second scan line 152 to transmit the initialization voltage Vint to the gate electrode G1 of the first transistor T1 , thereby performing an initialization operation of initializing the voltage of the gate electrode G1 of the first transistor T1 .

[0083] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the emission control signal EM transmitted through the emission control line 153, so that the driving voltage ELVDD is compensated through the diode-connected first transistor T1 to be transmitted to the light emitting diode ED.

[0084] The transistors T1, T2, T3, T4, T5, T6 and T7 may be P-channel transistors such as P-type metal oxide semiconductor ("PMOS"), and at least one of the transistors T1, T2, T3, T4, T5, T6 and T7 may be an N-channel transistor.

[0085] One end of the capacitor Cst may be connected to the gate electrode G1 of the first transistor T1, and the other end of the capacitor Cst may be connected to the driving voltage line 172. The cathode of the light emitting diode ED may be connected to a common voltage (ELVSS) terminal for transmitting the common voltage ELVSS to receive the common voltage ELVSS.

[0086] The number of transistors and the number of capacitors included in one pixel PX and their connection relationship may be variously modified.

[0087] The operation of the display device in the exemplary embodiment will be briefly described as follows. When the scan signal GIn of the gate-on voltage level is supplied through the second scan line 152 during the initialization period (the scan signal GIn may be the n-1th scan signal), the fourth transistor T4 is turned on, the initialization voltage Vint is transmitted to the gate electrode G1 of the first transistor T1 through the fourth transistor T4, and the first transistor T1 is initialized by the initialization voltage Vint.

[0088] Subsequently, when a scan signal GWn (the scan signal GWn may be an nth scan signal) of a gate-on voltage level is supplied through the first scan line 151 during the data programming period and the compensation period, the second transistor T2 and the third transistor T3 are turned on. The first transistor T1 is diode-connected by the turned-on third transistor T3 and biased in the forward direction. Therefore, a compensation voltage obtained by subtracting a threshold voltage of the first transistor T1 from the data signal Dm supplied by the data line 171 is applied to the gate electrode G1 of the first transistor T1. The driving voltage ELVDD and the compensation voltage are respectively applied to opposite terminals of the capacitor Cst, and the capacitor Cst is charged with charges corresponding to the voltage difference of the opposite terminals.

[0089] Next, when the emission control signal EM supplied from the emission control line 153 changes from the gate-off voltage level to the gate-on voltage level during the light emission period, the fifth transistor T5 and the sixth transistor T6 are turned on, generating a driving current Id corresponding to the voltage difference between the gate voltage of the gate electrode G1 of the first transistor T1 and the driving voltage ELVDD, and the driving current Id is supplied to the light emitting diode ED through the sixth transistor T6, and therefore, the current Ied flows through the light emitting diode ED.

[0090] During the initialization period, the seventh transistor T7 receives the gate-on voltage level scan signal GI(n+1) through the third scan line 154 to be turned on. The scan signal GI(n+1) may be the nth scan signal. A portion of the drive current Id flows out as a bypass current Ibp through the turned-on seventh transistor T7.

[0091] In the following, reference will be made to Figures 8 to 12A detailed structure of a display device in an exemplary embodiment is described. For better understanding and ease of description, layers will be described in a stacking order in a cross-sectional view, and a planar structure thereof will be described in the description of each layer.

[0092] Figure 8 and Fig. 9 1 and 2 are partial plan views respectively showing an exemplary embodiment of a first display area DA1 of a display device, Fig.10 Shown along Figure 8 A cross-sectional view taken along line X-X', Fig.11 Shown along Figure 8 A cross-sectional view taken along line XI-XI', Fig.12 A plan view showing an exemplary embodiment of a pixel electrode layer of a display device is shown. Fig. 9 Shown separately Figure 8 A portion of the element shown in (third conductive layer).

[0093] Figure 8 The planar structure shown in is a structure for two pixels PX1 and PX2 adjacent to each other in the first direction x. One pixel PX1 or PX2 may include transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6, and T7 connected to scan lines 151 and 152, an emission control line 153, one of a pair of data lines 171a and 171b, and a driving voltage line 172, and a capacitor Cst. Figure 8 The structure shown in may be repeatedly arranged in the first direction x and the second direction y. The structures of two adjacent pixels PX1 and PX2 may be symmetrical in the first direction x. Two adjacent pixels in the second direction y may have a left-right flipped shape.

[0094] The display device includes a substrate 110 and various layers, wirings, and elements disposed on the substrate 110. In an exemplary embodiment, the substrate 110 may include an insulating material such as a polymer such as polyimide, glass, or the like.

[0095] The buffer layer 120 as an insulating layer may be disposed on the substrate 110, and the active pattern 130 may be disposed on the buffer layer 120. The active pattern 130 may be bent to have various shapes. The active pattern 130 disposed in one pixel PX1 or PX2 may form one continuous body.

[0096] The active pattern 130 may include a plurality of channel regions and a plurality of conductive regions having semiconductor properties. The channel region includes channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g forming corresponding channels of transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6, and T7. The conductive regions disposed at opposite sides of each channel region 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g may be source and drain regions of corresponding transistors T1, T2, T3_1, T3_2, T4_1, T4_2, T5, T6, and T7.

[0097] In exemplary embodiments, the active pattern 130 may include a semiconductor material such as amorphous silicon, polysilicon, or an oxide semiconductor.

[0098] The first insulating layer 140 may be disposed on the active pattern 130. A first conductive layer including scan lines 151 and 152, an emission control line 153, and a driving gate electrode 155a may be disposed on the first insulating layer 140.

[0099] The scan lines 151 and 152 and the emission control line 153 may respectively extend substantially in the first direction x. The first scan line 151 may include a gate electrode 155 c_1 protruding near a boundary between two adjacent pixels PX1 and PX2 . Figure 7 The third scan line 154 shown in FIG. 1 may be a scan line of the same type as that of the second scan line 152 , and may transmit a scan signal of a next stage after the scan signal transmitted by the second scan line 152 .

[0100] The driving gate electrode 155 a may be disposed in each of the pixels PX1 and PX2 , and may be disposed between the first scan line 151 and the emission control line 153 in a plan view.

[0101] The second insulating layer 141 may be disposed on the first conductive layer. A second conductive layer including an initialization voltage line 161, a storage line 162, and a conductive pattern 163 may be disposed on the second insulating layer 141. The storage line 162 may be included in the signal line described above. The initialization voltage line 161 and the storage line 162 may extend substantially in the first direction x.

[0102] The initialization voltage line 161 may transmit the initialization voltage Vint. The storage line 162 may overlap with most of the drive gate electrode 155a in each of the pixels PX1 and PX2, and the opening 62 may be defined in the storage line 162 to correspond to each of the pixels PX1 and PX2. Each opening 62 may overlap with the drive gate electrode 155a. The conductive pattern 163 may be disposed between the initialization voltage line 161 and the storage line 162 in a plan view, and the conductive patterns 163 respectively disposed in two adjacent pixels PX1 and PX2 may be connected to each other at the boundaries of the two pixels PX1 and PX2 to form a continuum disposed to correspond to the two pixels PX1 and PX2. The storage line 162 and the conductive pattern 163 may transmit the drive voltage ELVDD.

[0103] Each channel of the transistors T1 , T2 , T3_1 , T3_2 , T4_1 , T4_2 , T5 , T6 , and T7 may be disposed inside one active pattern 130 .

[0104] The first transistor T1 may include a channel region 131a of an active pattern 130, a source region 136a and a drain region 137a disposed at opposite sides of the channel region 131a, and a driving gate electrode 155a overlapping the channel region 131a in a plan view. The channel region 131a may be bent at least once. In an exemplary embodiment, the channel region 131a may have a meandering shape or a zigzag shape, and may have, for example, a shape such as Figure 8 The vertically inverted U shape shown in .

[0105] The second transistor T2 may include a channel region 131b, a source region 136b and a drain region 137b disposed at opposite sides of the channel region 131b, and a gate electrode 155b as a portion of the scan line 151 overlapping the channel region 131b. The drain region 137b may be connected to the source region 136a of the first transistor T1.

[0106] The third transistor T3 may be provided as two parts to prevent leakage current. That is, the third transistor T3 may include a third transistor first part T3_1 and a third transistor second part T3_2 connected to each other.

[0107] The third transistor first portion T3_1 may include a channel region 131c_1, a source region 136c_1 and a drain region 137c_1 disposed at opposite sides of the channel region 131c_1, and a gate electrode 155c_1 as a protruding portion of the scan line 151 overlapping the channel region 131c_1.

[0108] The third transistor second portion T3_2 may include a channel region 131c_2, a source region 136c_2 and a drain region 137c_2 disposed at opposite sides of the channel region 131c_2, and a gate electrode 155c_2 as a portion of the scan line 151 overlapping the channel region 131c_2. The source region 136c_2 of the third transistor second portion T3_2 may be connected to the drain region 137a of the first transistor T1, and the drain region 137c_2 of the third transistor second portion T3_2 may be connected to the source region 136c_1 of the third transistor first portion T3_1.

[0109] The fourth transistor T4 may also be provided as two parts to prevent leakage current. That is, the fourth transistor T4 may include a fourth transistor first part T4_1 and a fourth transistor second part T4_2 connected to each other.

[0110] The fourth transistor first portion T4_1 may include a channel region 131d_1, a source region 136d_1 and a drain region 137d_1 disposed at opposite sides of the channel region 131d_1, and a gate electrode 155d_1 as a portion of the scan line 152 overlapping the channel region 131d_1. The drain region 137d_1 may be connected to the drain region 137c_1 of the third transistor first portion T3_1. The conductive region of the active pattern 130 may further include an extension 137 extending from a point where the drain region 137d_1 and the drain region 137c_1 of the third transistor first portion T3_1 meet.

[0111] The fourth transistor second portion T4_2 may include a channel region 131d_2, a source region 136d_2 and a drain region 137d_2 disposed at opposite sides of the channel region 131d_2, and a gate electrode 155d_2 as a portion of the scan line 152 overlapping the channel region 131d_2. The drain region 137d_2 may be connected to the source region 136d_1 of the fourth transistor first portion T4_1.

[0112] The fifth transistor T5 may include a channel region 131e, a source region 136e and a drain region 137e disposed at opposite sides of the channel region 131e, and a gate electrode 155e as a portion of the emission control line 153 overlapping the channel region 131e. The drain region 137e may be connected to the source region 136a of the first transistor T1.

[0113] The sixth transistor T6 may include a channel region 131f, source and drain regions 136f and 137f disposed at opposite sides of the channel region 131f, and a gate electrode 155f as a portion of the emission control line 153 overlapping the channel region 131f. The source region 136f may be connected to the drain region 137a of the first transistor T1.

[0114] The seventh transistor T7 includes a channel region 131g, a source region 136g and a drain region 137g disposed at opposite sides of the channel region 131g, and a transistor as a scan line (in Figure 8 A gate electrode 155g of a portion of a scan line 152 or 154 arranged at a lower portion thereof overlapping with the channel region 131g.

[0115] The conductive region of the active pattern 130 may further include an extension 138 extending from the source region 136d_2 of the fourth transistor second portion T4_2. The extension 138 may extend substantially in the first direction x.

[0116] The driving gate electrode 155a and the storage line 162 overlapping each other may form a capacitor Cst capable of maintaining a voltage of the driving gate electrode 155a. The second insulating layer 141 disposed between the driving gate electrode 155a and the storage line 162 may serve as a dielectric of the capacitor Cst.

[0117] The third insulating layer 142 may be disposed on the second conductive layer.

[0118] Contact holes 42, 43, 45, 47, and 49 disposed on the conductive region of the active pattern 130 may be defined in the first insulating layer 140, the second insulating layer 141, and the third insulating layer 142. The second insulating layer 141 and the third insulating layer 142 may include the contact hole 41 disposed on the first conductive layer. The third insulating layer 142 may include contact holes 44, 46, and 48 disposed on the second conductive layer.

[0119] In an exemplary embodiment, the first insulating layer 140, the second insulating layer 141, and the third insulating layer 142 may include a silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiON) inorganic insulating materials and / or organic insulating materials.

[0120] A third conductive layer including a driving voltage line 172 and connection members 72 , 74 , 75 , and 78 may be disposed on the third insulating layer 142 .

[0121] The driving voltage line 172 may transmit the driving voltage ELVDD and may receive the driving voltage ELVDD through a pad (also called a "pad" or "pad") portion of the display device. The driving voltage line 172 may overlap a boundary between two adjacent pixels PX1 and PX2, and may include a portion extending substantially in the second direction y, a transverse portion 172a disposed in the corresponding pixels PX1 and PX2 and extending substantially in the first direction x, and an extension 172b connected to an end of the corresponding transverse portion 172a.

[0122] The driving voltage line 172 may be electrically connected to a portion 163b disposed at a boundary between two adjacent pixels PX1 and PX2 of the conductive pattern 163 through a contact hole 46. An extension 172b of the driving voltage line 172 may be electrically connected to a source region 136e of the fifth transistor T5 through a contact hole 47, and may be electrically connected to the storage line 162 through a contact hole 48. Therefore, the source region 136e of the fifth transistor T5 and the storage line 162 may be electrically connected to the driving voltage line 172 to receive the driving voltage ELVDD.

[0123] The connection member 72 may be electrically connected to the source region 136b of the second transistor T2 through the contact hole 42. The connection member 72 may include a portion extending in an oblique direction with respect to the first direction x and the second direction y.

[0124] The connection member 74 may extend substantially in the second direction y to cross the scan line 151. One end of the connection member 74 may be electrically connected to the drive gate electrode 155a through the contact hole 41. The contact hole 42 may be defined in the opening 62 of the storage line 162. The other end of the connection member 74 may be electrically connected to the extension 137 of the active pattern 130 through the contact hole 43, and the extension 137 is connected to the drain region 137d_1 of the fourth transistor first part T4_1 and the drain region 137c_1 of the third transistor first part T3_1. Therefore, the drain region 137d_1 of the fourth transistor first part T4_1 and the drain region 137c_1 of the third transistor first part T3_1 may be electrically connected to the drive gate electrode 155a through the connection member 74. The connection member 74 may be connected together with the drive gate electrode 155a to the active pattern 130. Figure 7 corresponds to the driving gate node GN shown in .

[0125] The connection member 75 may extend substantially in the second direction y. One end of the connection member 75 may be electrically connected to the initialization voltage line 161 through the contact hole 44, and the other end of the connection member 75 may be connected to a portion (referred to as a first conductive region) of the extension 138 of the active pattern 130 through the contact hole 45, which is connected to the drain region 137g of the seventh transistor T7. Therefore, the drain region 137g of the seventh transistor T7 may be electrically connected to the initialization voltage line 161 to receive the initialization voltage Vint.

[0126] The connection member 78 may be electrically connected to the drain region 137 f of the sixth transistor T6 through the contact hole 49 .

[0127] The fourth insulating layer 180 and the fifth insulating layer 181 may be disposed on the third conductive layer. The contact hole 87 defined on the connection member 72 and the contact hole 88 defined on the connection member 78 may be defined in the fourth insulating layer 180 and the fifth insulating layer 181 .

[0128] In an exemplary embodiment, the fourth insulating layer 180 may include an inorganic insulating material and / or an organic insulating material, and the fifth insulating layer 181 may include an organic insulating material such as polyimide, acrylic polymer, and siloxane polymer. In another exemplary embodiment, the fourth insulating layer 180 may be omitted.

[0129] A fourth conductive layer including the data lines 171 a and 171 b and the connecting member 79 may be disposed on the fifth insulating layer 181 .

[0130] The data lines 171a and 171b correspond to the pair of data lines DLa and DLb described above, and they may extend substantially in the second direction y in a plan view, and cross the scan lines 151 and 152 and the emission control line 153. Two data lines 171a and 171b may be correspondingly disposed in each of the pixels PX1 and PX2. In an exemplary embodiment, for example, a pair of data lines 171a and 171b may be disposed to correspond to one pixel PX1, and a pair of data lines 171a and 171b may be disposed to correspond to one pixel PX2. The shape of the first data line 171a at the left side and the shape of the second data line 171b at the right side may be symmetrical with respect to a boundary between two adjacent pixels PX1 and PX2, and the shape of the first data line 171a and the shape of the second data line 171b may be symmetrical to each other.

[0131] The data lines 171a and 171b may include an extension 71 overlapping the connection member 72. The extension 71 may be electrically connected to the connection member 72 through the contact hole 87. Therefore, the source region 136b of the second transistor T2 may be electrically connected to the data lines 171a and 171b through the connection member 72 to receive the data signal Dm.

[0132] The connection member 79 may be electrically connected to the connection member 78 of the third conductive layer through the contact hole 88. In a plan view, the connection member 79 may be disposed between a pair of data lines 171a and 171b corresponding to the respective pixels PX1 and PX2.

[0133] In exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may include a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), and tantalum (Ta), or a conductive material such as a metal alloy.

[0134] The sixth insulating layer 182 may be disposed on the fourth conductive layer. The contact hole 89 defined on the connection member 79 may be defined in the sixth insulating layer 182. In an exemplary embodiment, the sixth insulating layer 182 may include an organic insulating material such as polyacrylic resin, polyimide resin, or the like.

[0135] A pixel electrode layer including pixel electrodes 191a and 191b and a voltage line 192 may be disposed on the sixth insulating layer 182. The pixel electrode layer may include a reflective conductive material or a semi-transmissive conductive material.

[0136] Each of the pixel electrodes 191a and 191b may correspond to each of the pixels PX1 and PX2. Each of the pixel electrodes 191a and 191b is connected to the connection members 79 and 78 through the contact hole 89 to be electrically connected to the drain region 137f of the sixth transistor T6 to receive a voltage.

[0137] Fig.12 , the arrangement of pixel electrodes 191a, 191b, and 191c that may be arranged in the first display area DA1 is shown. The pixel electrodes 191a, 191b, and 191c may be arranged in a Pentile matrix form. The pixel electrodes 191a and 191c may be arranged alternately in a first direction x. The pixel electrodes 191a and 191b may be arranged alternately in a diagonal direction that is inclined relative to the first direction x and the second direction y. The pixel electrodes 191c and 191b may be arranged alternately in another diagonal direction. The pixel electrode 191a may be smaller than the pixel electrode 191c, and the pixel electrode 191b may be smaller than the pixel electrode 191a. The pixel electrode 191a may be a pixel electrode of a red pixel R, the pixel electrode 191b may be a pixel electrode of a green pixel G, and the pixel electrode 191c may be a pixel electrode of a blue pixel B. The arrangement and shape of the pixel electrodes 191a, 191b, and 191c may be variously changed.

[0138] Each of the voltage lines 192 may extend substantially in the first direction x and may be bent along the edges of the pixel electrodes 191a, 191b, and 191c. The voltage line 192 may cross the data lines 171a and 171b. The voltage line 192 may be connected to a wiring that may be provided in the non-display area NA and may transmit a constant voltage such as an initialization voltage Vint, a driving voltage ELVDD, and a common voltage ELVSS.

[0139] The voltage line 192 may overlap at least a portion of the channel region 131c_1 of the third transistor first portion T3_1 and at least a portion of the channel region 131d_1 of the fourth transistor first portion T4_1. Thus, external light is blocked from being incident on the channel region 131c_1 of the third transistor first portion T3_1 and the channel region 131d_1 of the fourth transistor first portion T4_1 directly connected to the drive gate electrode 155a, thereby preventing leakage current from occurring. In addition, since a voltage change at the drive gate electrode 155a due to external light can be prevented, display defects such as brightness change and color coordinate change of an image can be prevented.

[0140] The seventh insulating layer 350 may be disposed on the pixel electrode layer. An opening 355 overlapping each of the pixel electrodes 191 a , 191 b , and 191 c may be defined in the seventh insulating layer 350 .

[0141] The light emitting layer 370 may be disposed on the pixel electrodes 191a, 191b, and 191c. The light emitting layer 370 may include an organic light emitting material or an inorganic light emitting material.

[0142] The common electrode 270 may be disposed on the light emitting layer 370. The common electrode 270 is also disposed on the seventh insulating layer 350 and may extend throughout the pixels PX1 and PX2. The common electrode 270 may transmit a common voltage ELVSS.

[0143] The pixel electrodes 191a, 191b, and 191c, the light emitting layer 370, and the common electrode 270 together form a light emitting diode ED. The pixel electrodes 191a, 191b, and 191c may be anodes of the light emitting diode ED, and the common electrode 270 may be a cathode of the light emitting diode ED.

[0144] An encapsulation layer for protecting the light emitting diode ED may be disposed on the common electrode 270 , and the encapsulation layer may include at least one inorganic layer and may further include at least one organic layer.

[0145] The relationship between the connection member 75 for transmitting the initialization voltage Vint and the data lines 171a and 171b will be described below. The data lines 171a and 171b may include a bent portion 71a bent in a direction away from the connection member 75 near the connection member 75. By disposing the data lines 171a and 171b in a fourth conductive layer different from the third conductive layer in which the connection member 75 is disposed, the data lines 171a and 171b can be further separated from the connection member 75. Therefore, the parasitic capacitance between the connection member 75 and the data lines 171a and 171b can be reduced, and the coupling between the initialization voltage Vint and the data signal Dm can be prevented, thereby preventing defective display such as horizontal line spot.

[0146] The conductive pattern 163 may include a shielding portion 163a disposed between the connection member 75 and the data lines 171a and 171b. The shielding portion 163a may overlap a portion (referred to as a second conductive region) of the extension 138 of the active pattern 130 disposed between the data lines 171a and 171b and the connection member 75, which portion is electrically connected to the connection member 75 and transmits the initialization voltage Vint, and thus may shield between the data lines 171a and 171b and the extension 138 of the active pattern 130. Therefore, coupling between the data signal Dm transmitted by the data lines 171a and 171b and the initialization voltage Vint may be further prevented.

[0147] A constant voltage (e.g., a driving voltage ELVDD or a common voltage ELVSS) other than the initialization voltage Vint is applied to a voltage line 192 disposed in the pixel electrode layer, so that the coupling between the data signal Dm and the initialization voltage Vint can be further reduced by overlapping the voltage line 192 (which crosses the data lines 171a and 171b) with the data lines 171a and 171b.

[0148] Now, refer to Fig.13 and Fig.14 A detailed structure of the second display area DA2 of the display device is described focusing on differences from the above-described exemplary embodiments.

[0149] Fig.13 and Fig.14 Partial plan views of exemplary embodiments of the second display area DA2 of the display device are respectively shown. Fig.13 shows the planar structure of the second pixel area PA2, Fig.14 A planar structure of the transmission area TA is shown.

[0150] Fig.13 Two adjacent pixels PX1 and PX2 are shown in the second pixel area PA2 of the second display area DA2. Figure 8 The pixel structures shown in are substantially the same. However, only one data line 171a or 171b is correspondingly arranged in each pixel PX1 or PX2. That is, only the first data line 171a of a pair of data lines 171a and 171b is arranged in the pixel PX1, and only the second data line 171b of a pair of data lines 171a and 171b is arranged in the pixel PX2. The pixel PX1 can receive the data signal Dm from the first data line 171a, and the pixel PX2 can receive the data signal Dm from the second data line 171b.

[0151] Fig.13 The pixels PX1 and PX2 shown in FIG. 1 are, for example, Figure 5 The pixel column C shown in i and Ci+1 In an alternative exemplary embodiment, when the pixels PX1 and PX2 are pixel columns (eg, Figure 5 C i+1 and C i+2 ), only the second data line 171b may be provided in the pixels PX1 and PX2. When the pixel PX1 is a pixel column (eg, Figure 5 C i+2 ) and the pixel PX2 is a pixel column (eg, Figure 5 C i+3 ), only the second data line 171b is disposed in the pixel PX1 and only the first data line 171a is disposed in the pixel PX2.

[0152] Fig.14 1 and 2 show an area corresponding to about two pixels in the transmission area TA of the second display area DA2. Figure 8 The structure shown in FIG. 1 is substantially the same, but only one of a pair of data lines 171a and 171b is correspondingly arranged in adjacent pixel columns (eg, Figure 5 C i+2 and C i+3 ) in each pixel column. In addition, Figure 8 and Fig.12 The pixel electrodes 191a, 191b, and 191c shown in FIG. 1 may not be disposed in the transmission area TA. As such, by excluding the conductive layer that may reduce the transmittance of the transmission area TA from the transmission area TA, the transmittance of the transmission area TA may be improved.

[0153] In order to further improve the transmittance of the transmission area TA, it may be advantageous to eliminate both of the pair of data lines 171a and 171b, but in this case, the data signal Dm cannot be transmitted to the pixel disposed above the transmission area TA. When the pixel is not disposed above the transmission area TA, both of the data lines 171a and 171b may not be disposed.

[0154] Unlike the illustrated structure, when two adjacent pixels disposed below or above the transmission area TA are two pixel columns (eg, Figure 5 C i and C i+1), only the first data line 171a or the second data line 171b may be disposed in the transmission area TA of the corresponding pixel column. When two adjacent pixels disposed below or above the transmission area TA are two pixel columns (e.g., Figure 5 C i+1 and C i+2 ), only the second data line 171b may be disposed in the transmission area TA of the corresponding pixel column.

[0155] As described above, in the pixel electrode layer, the pixel electrodes 191a, 191b, and 191c may be removed from the transmission area TA. However, it is desirable that the voltage line 192 is substantially and continuously arranged in the first direction x to cross the second pixel area PA2 adjacent to the left and right sides of the transmission area TA, so that the voltage transmitted through the voltage line 192 can be applied to the pixels of the pixel column. Therefore, the voltage line 192 may also be arranged in the transmission area TA. In this case, when the voltage line 192 is not arranged as Figure 8 The zigzag shape shown in FIG. 1 and the majority of the voltage line 192 are arranged as shown in FIG. Fig.14 When the voltage line 192 is arranged to overlap with the second scan line 152 as shown in FIG. 1 , the reduction in transmittance due to the voltage line 192 can be minimized. In the region where the second scan line 152 is arranged, since light is pre-blocked by the second scan line 152, it is beneficial to improve the transmittance of the transmission area TA by forming the voltage line 192 to overlap with the conductive layer. In the transmission area TA, in addition to the second scan line 152, the voltage line 192 may be arranged to overlap with another signal line (e.g., the first scan line 151) extending substantially in the first direction x.

[0156] Finally, refer to Fig.15 and Fig.16 With the attachment described above Figure 1 Hereinafter, exemplary embodiments of a display device and a method of driving the same will be described.

[0157] Fig.15 An exemplary embodiment of a circuit diagram showing a circuit connected to a data line of a display device, Fig.16 A waveform diagram showing an exemplary embodiment of a driving signal of a display device is shown.

[0158] Reference Fig.15 , the display device in the exemplary embodiment includes a data driver 400 for applying a data signal Dm. The data driver 400 may be connected to the data lines 171a and 171b and may output the data signal Dm to the data lines 171a and 171b.

[0159] The display area DA may include pixels R, G, and B, data lines 171a and 171b, and scan lines 151_1 and 151_2. Each of the scan lines 151_1 and 151_2 may correspond to the scan line 151 described above.

[0160] Pixels R, G, and B may be connected to corresponding data lines 171a and 171b and corresponding scan lines 151_1 and 151_2, respectively. A transistor connected to the data lines 171a and 171b and the scan lines 151_1 and 151_2 in each of the pixels R, G, and B may be the second transistor T2 described above.

[0161] When the pixels R, G, and B are arranged substantially in a matrix form, a pair of data lines 171a and 171b may be provided in each of the pixel columns C1, C2, C3, ..., C8 to be connected to the pixels R, G, and B of the corresponding pixel columns C1, C2, C3, ..., C8. The pixels R, G, and B of each of the pixel columns C1, C2, C3, ..., C8 may be alternately connected to the pair of data lines 171a and 171b.

[0162] A demultiplexer circuit including transmission gate lines TG1, TG2, TG3, and TG4 and a switching element Q may be provided between the data driver 400 and the display area DA. The transmission gate lines TG1, TG2, TG3, and TG4 may transmit transmission gate signals and may cross the data lines 171a and 171b. Each of the data lines 171a and 171b is connected to the switching element Q, which is connected to at least one of the transmission gate lines TG1, TG2, TG3, and TG4, and then, when a gate-on voltage is applied to the transmission gate lines TG1, TG2, TG3, and TG4, a data signal Dm from the data driver 400 may be applied to the corresponding data lines 171a and 171b.

[0163] Reference Fig.15 and Fig.16 , when the gate-on voltage Von (here, low level) is applied to the transmission gate line TG1 during approximately half (H / 2) of the horizontal period in the first period P1, the data lines 171a and 171b connected to the switching element Q connected to the transmission gate line TG1 are charged with the voltage of the data signal Dm.

[0164] Then, when the gate-on voltage Von is applied to the transmission gate line TG2 during about half (H / 2) of the horizontal period in the second period P2, the data lines 171a and 171b connected to the switching element Q connected to the transmission gate line TG2 are charged with the voltage of the data signal Dm. Similarly, the gate-on voltage Von may be sequentially applied to the transmission gate line TG3 and the transmission gate line TG4 in the third period P3 and the fourth period P4, respectively.

[0165] Then, when the gate-on voltage Von is applied to the scan line 151_1 during approximately one horizontal period 1H in the third period P3 and the fourth period P4, the voltage charged in the corresponding data lines 171a and 171b is applied to the pixels R, G and B of the pixel groups PG1 and PG2, and the pixel groups PG1 and PG2 are connected to the data lines 171a and 171b connected through the transmission gate lines TG1 and TG2 and the switching element Q, and are connected to the scan line 151_1 at the same time.

[0166] Then, when the gate-on voltage Von is applied to the scan line 151_2 during approximately one horizontal period 1H in the fifth period P5 and the sixth period P6, the voltage charged in the corresponding data lines 171a and 171b is applied to the pixels R, G and B of the pixel groups PG3 and PG4, and the pixel groups PG3 and PG4 are connected to the data lines 171a and 171b connected through the transmission gate lines TG3 and TG4 and the switching element Q, and are connected to the scan line 151_2 at the same time.

[0167] According to the driving method described above, since there is a period in which the data voltage is first charged in one of the data lines 171a and 171b and the data voltage is charged in the other of the data lines 171a and 171b in a state of floating from the data driver 400, the ripple of the initialization voltage Vint coupled with the data signal Dm of the data lines 171a and 171b affects the data voltage of the other of the data lines 171a and 171b in a floating state, which may cause display defects such as horizontal line spots. However, the display device in the exemplary embodiment can prevent the coupling between the initialization voltage Vint and the data signal Dm to prevent the display defects as described above.

[0168] While the invention has been described in connection with what is presently considered to be practical embodiments, it will be understood that the invention is not limited to the disclosed embodiments, but on the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: A first display area, comprising a plurality of first pixel areas; A second display area, comprising a plurality of second pixel areas and a plurality of transmission areas; a plurality of pixels arranged in a matrix form in the first display area and the plurality of second pixel areas; as well as A first signal line and a second signal line are provided to correspond to each of the pixel columns in the plurality of pixels, wherein, in each of the pixel columns, one of the first signal line and the second signal line extends throughout the first display area and the second display area, and the remaining one of the first signal line and the second signal line is not disposed in the second display area, and The first signal line and the second signal line are data lines for transmitting data signals.

2. The display device according to claim 1, wherein The first signal line and the second signal line are provided in each of the pixel columns in the first display area.

3. The display device according to claim 1, wherein The plurality of second pixel regions and the plurality of transmission regions are arranged in a checkerboard pattern in the second display area.

4. The display device according to claim 1, wherein Each of the plurality of second pixel areas includes at least one pixel electrode, and the plurality of transmission areas does not include a pixel electrode.

5. The display device according to claim 4, wherein The second display area includes a plurality of scan lines and a voltage line disposed in the same layer as the at least one pixel electrode, and The voltage line includes, in at least one of the plurality of transmission regions, a portion overlapping at least one scan line among the plurality of scan lines and extending side by side with the at least one scan line.

6. The display device according to claim 1, wherein Pixels of each of the pixel columns among the plurality of pixels are connected alternately one by one to the first signal line and the second signal line.

7. The display device according to claim 1, wherein The sizes of the plurality of second pixel regions are the same as the sizes of the plurality of transmission regions.

8. The display device according to claim 1, wherein A size of at least one of the plurality of transmission regions is greater than a size of each of the plurality of second pixel regions.

9. The display device according to claim 1, wherein Each of the plurality of second pixel regions includes at least one of a red pixel, a green pixel, and a blue pixel.

Images