Display device and method for manufacturing the same

Abstract

The present invention provides a display device and a manufacturing method thereof. The display device includes: a substrate; an active layer disposed on the substrate and including a first active pattern; a first insulating layer disposed on the active layer; a first gate conductive layer disposed on the first insulating layer; a second insulating layer disposed on the first gate conductive layer; and a third gate conductive layer including a third a gate pattern disposed on the second insulating layer. The third gate conductive layer is not directly connected to the first gate conductive layer.

Description

Technical Field

[0001] The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device and a method of manufacturing the same that improve display quality. Background Art

[0002] Recently, with the development of technology, display products that are smaller, lighter, and have better performance have been produced. So far, in display devices, existing cathode ray tube (CRT) televisions have many advantages in terms of both performance and price and have been widely used. However, display devices that overcome the disadvantages of CRTs in terms of miniaturization or portability and have advantages such as miniaturization, light weight, and low power consumption, such as plasma display devices, liquid crystal display devices, or organic light emitting display devices, have gradually attracted attention.

[0003] The display device includes a gate conductive layer that forms scan wirings and the like. In the case where the display device becomes larger in size and the resolution increases and high-speed driving is required, the scan signal transmitted through the gate conductive layer is delayed, thereby reducing the display quality. Therefore, it is necessary to reduce the resistance value of the gate conductive layer while solving problems that may occur in the process. Summary of the Invention

[0004] In view of the above situation, the technical problem to be solved by the present invention is proposed. The object of the present invention is to provide a display device including a low-resistance gate conductive layer to improve display quality.

[0005] Another object of the present invention is to provide a method of manufacturing the display device.

[0006] A display device according to an embodiment for achieving the object of the present invention includes: a substrate; an active layer disposed on the substrate and including a first active pattern; a first insulating layer disposed on the active layer; a first gate conductive layer disposed on the first insulating layer; a second insulating layer disposed on the first gate conductive layer; and a third gate conductive layer including a third a gate pattern disposed on the second insulating layer. The third gate conductive layer is not directly connected to the first gate conductive layer.

[0007] In an embodiment of the present invention, the third a gate pattern may be directly connected to the first active pattern through a first contact hole, wherein the first contact hole is formed through the second insulating layer and the first insulating layer.

[0008] In an embodiment of the present invention, the display device may further include: a fourth insulating layer disposed on the third gate conductive layer; and a source-drain conductive layer disposed on the fourth insulating layer and including a first SD pattern and a second SD pattern. The first gate conductive layer includes a first a gate pattern and a first b gate pattern, the first a gate pattern overlaps with the first active pattern, and the first b gate pattern may be separated from the first a gate pattern. The first SD pattern may be directly connected to the third a gate pattern through a second contact hole, wherein the second contact hole is formed through the fourth insulating layer. The second SD pattern may be directly connected to the first b gate pattern through a third contact hole, wherein the third contact hole is formed through the fourth insulating layer and the second insulating layer.

[0009] In an embodiment of the present invention, the display device may further include: a second gate conductive layer disposed on the second insulating layer; and a third insulating layer disposed on the second gate conductive layer and below the third gate conductive layer. The third gate conductive layer may not be directly connected to the second gate conductive layer.

[0010] In an embodiment of the present invention, the active layer may include polysilicon.

[0011] In an embodiment of the present invention, the first gate conductive layer may be formed of a single layer of aluminum or an aluminum alloy.

[0012] In an embodiment of the present invention, the first gate conductive layer may include a main conductive layer and a covering layer disposed on the main conductive layer.

[0013] In an embodiment of the present invention, the main conductive layer is formed of a single layer of aluminum or an aluminum alloy, and the covering layer includes titanium (Ti) and may have the following thickness.

[0014] In an embodiment of the present invention, the display device may further include: a sealing member disposed between a display area for displaying an image and a peripheral area surrounding the display area; and a sealing substrate that seals a structure within the display area together with the sealing member. The first gate conductive layer may further include a first connection wiring overlapping with the sealing member. The third gate conductive layer may further include a shielding electrode disposed between the first connection wiring and the sealing member.

[0015] A display device according to an embodiment for achieving the object of the present invention described above includes: a substrate substrate including a display area for displaying an image and a peripheral area adjacent to the display area as a non-display area; an active layer disposed on the substrate substrate; a first insulating layer disposed on the active layer; a first gate conductive layer disposed on the first insulating layer and including a first connection wiring; a second insulating layer disposed on the first gate conductive layer; a third gate conductive layer disposed on the second insulating layer and including a first shielding electrode overlapping the first connection wiring; a fourth insulating layer disposed on the third gate conductive layer; a sealing member disposed on the fourth insulating layer between the display area and the peripheral area and overlapping the first shielding electrode; and a sealing substrate for sealing a structure in the display area together with the sealing member.

[0016] A method of manufacturing a display device according to an embodiment for achieving the object of the present invention described above includes: a step of forming an active layer including a first active pattern on a substrate substrate; a step of forming a first insulating layer on the active layer; a step of forming a first gate conductive layer on the first insulating layer; a step of forming a second insulating layer on the first gate conductive layer; a step of forming a first contact hole exposing the first active pattern through the second insulating layer and the first insulating layer; and a step of forming a third gate conductive layer on the second insulating layer, the third gate conductive layer including a third a gate pattern directly connected to the first active pattern through the first contact hole. In the step of forming the first contact hole, the first gate conductive layer is entirely covered by the second insulating layer.

[0017] In an embodiment of the present invention, after the step of forming the first contact hole and before forming the third gate conductive layer, the manufacturing method may further include: a step of cleaning a surface of the first active pattern exposed through the first contact hole using a cleaning solution having an etching force for a metal.

[0018] In an embodiment of the present invention, in the step of performing the cleaning, wet cleaning may be performed using a BOE (Buffered Oxide Etchant) cleaning solution.

[0019] In an embodiment of the present invention, after forming the first gate conductive layer and before forming the second insulating layer, the manufacturing method may further include: a step of doping impurities into a part of the active layer to form a source-drain region; and a step of performing heat treatment to activate the dopant of the active layer to activate the active layer.

[0020] In an embodiment of the present invention, the first gate conductive layer may include a connection wiring. The third gate conductive layer may include a shielding electrode overlapping with the connection wiring.

[0021] In an embodiment of the present invention, the manufacturing method may further include: a step of forming a sealing member on a sealing substrate; a step of attaching the sealing substrate and the base substrate on which the third gate conductive layer is formed by using the sealing member; and a step of irradiating the sealing member with a laser through the sealing substrate to cure the sealing member. The shielding electrode is located between the sealing member and the connection wiring, so that the laser can be blocked from irradiating the connection wiring.

[0022] In an embodiment of the present invention, before the step of forming the third gate conductive layer, the manufacturing method may further include: a step of forming a second gate conductive layer on the second insulating layer; and a step of forming a third insulating layer on the second gate conductive layer.

[0023] In an embodiment of the present invention, the first gate conductive layer may be formed of a single layer of aluminum or an aluminum alloy.

[0024] In an embodiment of the present invention, the third gate conductive layer may include molybdenum or a molybdenum alloy.

[0025] According to this embodiment, the display device includes: a base substrate; an active layer disposed on the base substrate and including a first active pattern; a first insulating layer disposed on the active layer; a first gate conductive layer disposed on the first insulating layer; a second insulating layer disposed on the first gate conductive layer; and a third gate conductive layer including a third a gate pattern disposed on the second insulating layer. The third gate conductive layer is not directly connected to the first gate conductive layer or the second gate conductive layer through a contact hole. Thus, when a cleaning process using a cleaning solution is required, the first gate conductive layer and the second gate conductive layer are entirely covered by the second insulating layer and the third insulating layer. Therefore, the first gate conductive layer and the second gate conductive layer do not require an additional covering layer, or it is not a problem even with a very thin covering layer. Thus, the display device can be realized with a simple structure that reduces the wiring resistance, solves the process problems, and reduces the manufacturing cost.

[0026] In addition, the laser for curing the sealing member is irradiated onto the sealing member through the sealing substrate, so the shielding electrode can block the laser from irradiating the connection wiring. Thus, the problem that the connection wiring including aluminum or the like is damaged due to the irradiation of the laser can be prevented.

[0027] However, the effects of the present invention are not limited to the above effects, and various expansions can be made without departing from the spirit and purpose of the present invention. Brief Description of the Drawings

[0028] Figure 1 is a cross-sectional view of a display device according to an embodiment of the present invention.

[0029] Figure 2 is a top view of a display device according to an embodiment of the present invention.

[0030] Figure 3 is along Figure 2 the cross-sectional views taken along the I-I' line and the II-II' line.

[0031] Figure 4 is a partially enlarged cross-sectional view of a display device according to an embodiment of the present invention.

[0032] Figures 5A to 5F is a cross-sectional view for explaining Figure 3 the manufacturing method of the display device.

[0033] Figure 6 is a block diagram showing an electronic device according to an embodiment of the present invention.

[0034] Figure 7A is a diagram showing an example of an electronic device implemented by a television Figure 6 device.

[0035] Figure 7B is a diagram showing an example of an electronic device implemented by a smartphone Figure 6 device.

[0036] In the figure: 100 - base substrate; 110 - buffer layer; 120 - first insulating layer; 130 - second insulating layer; 140 - third insulating layer; 150 - fourth insulating layer; 180 - light-emitting structure; 200 - sealing substrate. Detailed Description of the Invention

[0037] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail.

[0038] Figure 1 is a cross-sectional view of a display device according to an embodiment of the present invention.

[0039] Referring to Figure 1 , the display device may include a base substrate 100, a buffer layer 110, an active layer, a first insulating layer 120, a first gate conductive layer, a second insulating layer 130, a second gate conductive layer, a third insulating layer 140, a third gate conductive layer, a fourth insulating layer 150, and a source-drain conductive layer.

[0040] The base substrate 100 may be made of a transparent or opaque material. For example, the base substrate 100 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, an F-doped quartz substrate, a sodalime glass substrate, a non-alkali glass substrate, etc. Optionally, the base substrate 100 may also be formed of a flexible transparent resin substrate. As an example of the transparent resin substrate that can be used as the base substrate 100, a polyimide substrate can be cited.

[0041] The buffer layer 110 may be disposed over the entire base substrate 100. The buffer layer 110 can prevent the diffusion of metal atoms or impurities from the base substrate 100 to the active layer, and can adjust the heat transfer rate during the crystallization process for forming the active layer, so that a substantially uniform active layer can be obtained. In addition, in the case where the surface of the base substrate 100 is uneven, the buffer layer 110 can function to improve the flatness of the surface of the base substrate 100.

[0042] The active layer may be disposed over the buffer layer 110. The active layer may include a first active pattern ACTa and a second active pattern ACTb. The active layer may include poly crystal silicon. The active pattern ACT may include: a drain region and a source region doped with impurities; and a channel region between the drain region and the source region. The polycrystalline silicon may be formed by depositing amorphous silicon first and then crystallizing it. Here, the amorphous silicon can be crystallized by various methods such as RTA (rapid thermal annealing), SPC (solid phase crystallization), ELA (excimer laser annealing), MIC (metal induced crystallization), MILC (metal induced lateral crystallization), SLS (sequential lateral solidification), etc.

[0043] The first insulating layer 120 may be disposed on the buffer layer 110 on which the active layer is provided. The first insulating layer 120 may sufficiently cover the active layer on the buffer layer 110 and may have an upper surface that is substantially flat without generating height differences around the active layer. Differently, the first insulating layer 120 may cover the active layer on the buffer layer 110 and may be disposed with a substantially equal thickness along the profile of the active layer. The first insulating layer 120 may include inorganic insulating materials such as silicon compounds and metal oxides.

[0044] The first gate conductive layer may be disposed on the first insulating layer 120. The first gate conductive layer may include a first a gate pattern GAT1a and a first b gate pattern GAT1b separated from the first a gate pattern GAT1a. The first a gate pattern GAT1a may overlap with the first active pattern ACTa to form a gate electrode of the first thin film transistor. The first b gate pattern GAT1b may overlap with the second active pattern ACTb to form a gate electrode of the second thin film transistor. The first gate conductive layer may further include signal wirings such as scan lines for transmitting scan signals. The first thin film transistor may be a switching element of a pixel, and the second thin film transistor may be a driving element of the pixel.

[0045] The first gate conductive layer may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. For example, the first gate conductive layer may be a single layer including aluminum (Al) or an aluminum alloy with low resistance and high conductivity. Thereby, the wiring resistance can be reduced.

[0046] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the first gate conductive layer is provided. The second insulating layer 130 may sufficiently cover the first gate conductive layer on the first insulating layer 120 and may have an upper surface that is substantially flat without generating height differences around the first gate conductive layer. Differently, the second insulating layer 130 may cover the first gate conductive layer on the first insulating layer 120 and may be disposed with a substantially equal thickness along the profile of the first gate conductive layer. The second insulating layer 130 may include inorganic insulating materials such as silicon compounds and metal oxides.

[0047] The second gate conductive layer may be disposed on the second insulating layer 130. The second gate conductive layer may include a second a gate pattern GAT2a and a second b gate pattern GAT2b separated from the second a gate pattern GAT2a. The second gate conductive layer may further include signal wirings such as scan lines for transmitting scan signals.

[0048] The second gate conductive layer may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the second gate conductive layer may be a single layer including aluminum (Al) or an aluminum alloy having a low resistance and a high conductivity. Thereby, the wiring resistance can be reduced.

[0049] The third insulating layer 140 may be disposed on the second insulating layer 130 provided with the second gate conductive layer. The third insulating layer 140 may sufficiently cover the second gate conductive layer on the second insulating layer 130, and may have an upper surface that is substantially flat without generating a height difference around the second gate conductive layer. Differently, the third insulating layer 140 may cover the second gate conductive layer on the second insulating layer 130, and may be disposed with a substantially equal thickness along the contour of the second gate conductive layer. The third insulating layer 140 may include an inorganic insulating material such as a silicon compound or a metal oxide.

[0050] The third gate conductive layer may be disposed on the third insulating layer 140. The third gate conductive layer may include a third a gate pattern GAT3a and a third b gate pattern GAT3b separated from the third a gate pattern GAT3a.

[0051] The third gate conductive layer may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the third gate conductive layer may be a single layer including molybdenum (Mo) or a molybdenum alloy. According to another embodiment, the third gate conductive layer may have a stacked structure including: a main conductive layer including molybdenum (Mo) or a molybdenum alloy; and a covering layer including titanium (Ti) disposed on the main conductive layer.

[0052] The third gate conductive layer may be directly connected to the active layer through a contact hole, where the contact hole is formed through the third insulating layer 140 to the first insulating layer 120. However, the third gate conductive layer will not be directly connected to the first gate conductive layer or the second gate conductive layer through the contact hole.

[0053] For example, the third a gate pattern GAT3a may be directly connected to the first active pattern ACTa through a first contact hole, where the first contact hole is formed through the third insulating layer 140 to the first insulating layer 120.

[0054] The fourth insulating layer 150 may be disposed on the third insulating layer 140 provided with the third gate conductive layer. The fourth insulating layer 150 may sufficiently cover the third gate conductive layer on the third insulating layer 140, and may have an upper surface that is substantially flat without generating height differences around the third gate conductive layer. Differently, the fourth insulating layer 150 may cover the third gate conductive layer on the third insulating layer 140, and may be disposed with a substantially equal thickness along the contour of the third gate conductive layer. The fourth insulating layer 150 may include inorganic insulating materials such as silicon compounds and metal oxides.

[0055] The source-drain conductive layer may be disposed on the fourth insulating layer 150. The source-drain conductive layer may include a first SD (source-drain) pattern Sda, a second SD pattern Sdb, and a third SD pattern Sdc.

[0056] The source-drain conductive layer may be directly connected to the third gate conductive layer, the second gate conductive layer, or the first gate conductive layer through a contact hole. For example, the first SD pattern Sda may be directly connected to the third a gate pattern GAT3a through a second contact hole, where the second contact hole is formed through the fourth insulating layer 150. The second SD pattern Sdb may be directly connected to the second a gate pattern GAT2a through a third contact hole, where the third contact hole is formed through the fourth insulating layer 150 and the third insulating layer 140. The third SD pattern Sdc may be directly connected to the first b gate pattern GAT1b through a fourth contact hole, where the fourth contact hole is formed through the fourth insulating layer 150, the third insulating layer 140, and the second insulating layer 130.

[0057] The source-drain conductive layer may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. The source-drain conductive layer may be formed as multiple layers. For example, the source-drain conductive layer may include a titanium (Ti) layer and a molybdenum (Mo) layer on the titanium layer (Ti / Mo structure). Or, the source-drain conductive layer may include a titanium (Ti) layer, an aluminum (Al) layer on the titanium layer, and a titanium (Ti) layer on the aluminum layer (Ti / Al / Ti structure).

[0058] The display device may further include a light-emitting structure disposed on the source-drain conductive layer, etc. (refer to Figure 3 etc.). Details thereof are omitted.

[0059] As the display device becomes larger in size, the resolution increases, thereby increasing the necessity for high-speed driving. Consequently, it is necessary to reduce the wiring resistance of the first gate conductive layer or the second gate conductive layer. When the first gate conductive layer or the second gate conductive layer is formed as a conductive layer including molybdenum, increasing the thickness of the conductive layer to reduce the wiring resistance is limited.

[0060] On the contrary, even if a metal with a low resistance value, excellent conductivity, and easy processing is used as the first gate conductive layer or the second gate conductive layer, due to heat treatment of the first gate conductive layer or the second gate conductive layer, BOE (Buffered Oxide Etchant) cleaning solution, etc. during the process, the possibility of defects still exists. Therefore, it is necessary to further provide a covering layer with a relatively thick thickness on the order of thousands levels on the conductive layer. In this way, there will be the following problems, that is, it is not conducive to wiring design corresponding to the increased thickness, and it is difficult to achieve fine processing of the pattern.

[0061] On the contrary, according to the present embodiment, the third gate conductive layer is not directly connected to the first gate conductive layer or the second gate conductive layer through the contact hole. Therefore, when performing a cleaning process that requires the use of the BOE cleaning solution, the entire first gate conductive layer and the second gate conductive layer are covered by the second insulating layer 130 and the third insulating layer 140. Therefore, the first gate conductive layer and the second gate conductive layer do not require an additional covering layer, or it is not a problem to use only a very thin covering layer. Thus, the display device can be realized with a simple structure that reduces the wiring resistance, solves the process problems, and reduces the manufacturing cost.

[0062] Figure 2 is a top view of a display device according to an embodiment of the present invention. Figure 3 is along Figure 2 the cross-sectional views taken along the I-I' line and the II-II' line of

[0063] Referring to Figure 2 and Figure 3 , the display device may include a display area DA for displaying an image and a peripheral area PA that surrounds the display area DA and serves as a non-display area.

[0064] The display device may include a plurality of pixels PX arranged in a matrix form within the display area DA.

[0065] The display device may further include: a driving circuit disposed in the peripheral area PA and generating driving signals for driving the plurality of pixels PX; and connection wirings SL for transmitting the driving signals into the display area DA. For example, the connection wirings SL may include a first connection wiring SL1 and a second connection wiring SL2.

[0066] A sealing member CS may be disposed between the display area DA and the peripheral area PA. The sealing member CS may be disposed between the sealing substrate 200 and the base substrate 100 to seal the display area DA in which the light-emitting structure 180 is formed. The sealing member CS may be made of a material that melts when a predetermined thermal energy is applied. The sealing member CS may include a material that cures by light. For example, the sealing member CS may include glass frit.

[0067] Here, the connection wiring SL may be configured to pass through the boundary between the display area DA and the peripheral area PA and may be configured to overlap with the sealing member CS.

[0068] Refer again to Figure 3 , the display device may include a base substrate 100, a buffer layer 110, an active layer, a first insulating layer 120, a first gate conductive layer, a second insulating layer 130, a second gate conductive layer, a third insulating layer 140, a third gate conductive layer, a fourth insulating layer 150, a source-drain conductive layer, a via insulation layer 160, a pixel definition film PDL, the light-emitting structure 180, the sealing member CS, and the sealing substrate 200.

[0069] Each component of the display device, except for the first connection wiring SL1, the second connection wiring SL2, the shielding electrode, the sealing member CS, the via insulation layer 160, the pixel definition film PDL, the light-emitting structure 180, and the sealing substrate 200, is substantially the same as Figure 1 the components of the display device described in. Therefore, repeated descriptions are omitted.

[0070] The buffer layer 110 may be disposed on the base substrate 100. The active layer may be disposed on the buffer layer 110. The active layer may include a first active pattern ACTa and a second active pattern ACTb. The first insulating layer 120 may be disposed on the buffer layer 110 provided with the active layer.

[0071] The first gate conductive layer may be disposed on the first insulating layer 120. The first gate conductive layer may include a first a gate pattern GAT1a and a first b gate pattern GAT1b separated from the first a gate pattern GAT1a. The first gate conductive layer may further include the first connection wiring SL1.

[0072] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the first gate conductive layer is provided.

[0073] The second gate conductive layer may be disposed on the second insulating layer 130. The second gate conductive layer may include a second a gate pattern GAT2a and a second b gate pattern GAT2b ( Figure 3 not shown in the figure). The second gate conductive layer may further include the second connection wiring SL2.

[0074] The third insulating layer 140 may be disposed on the second insulating layer 130 on which the second gate conductive layer is provided.

[0075] The third gate conductive layer may be disposed on the third insulating layer 140. The third gate conductive layer may include a third a gate pattern GAT3a and a third b gate pattern GAT3b ( Figure 3 not shown in the figure). The third gate conductive layer may further include the shielding electrode. The shielding electrode may include a first shielding electrode SE1 and a second shielding electrode SE2. The first shielding electrode SE1 may be configured to overlap with the first connection wiring SL1. The second shielding electrode SE2 may be configured to overlap with the second connection wiring SL2. According to other embodiments, the first shielding electrode SE1 and the second shielding electrode SE2 may be formed as one pattern, and thus may also overlap with the first connection wiring SL1 and the second connection wiring SL2 at the same time. The first shielding electrode SE1 and the second shielding electrode SE2 may be floating, or a certain voltage may be applied thereto.

[0076] The fourth insulating layer 150 may be disposed on the third insulating layer 140 on which the third gate conductive layer is provided. The source / drain conductive layer may be disposed on the fourth insulating layer 150. The source / drain conductive layer may include a first SD pattern Sda, a second SD pattern Sdb, and a third SD pattern Sdc.

[0077] The via insulating layer 160 may be disposed on the source-drain conductive layer. The via insulating layer 160 may be formed as a single-layer structure or a multi-layer structure including at least two or more insulating films. The via insulating layer 160 may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

[0078] The light-emitting structure 180 may include a first electrode 181, a light-emitting layer 182, and a second electrode 183.

[0079] The first electrode 181 may be disposed on the via insulating layer 160. Depending on the light-emitting mode of the display device, the first electrode 181 may be formed using a reflective material or a light-transmissive material. In an exemplary embodiment, the first electrode 181 may be formed of a single-layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive material film.

[0080] The pixel definition layer PDL may be disposed on the via insulating layer 160 provided with the first electrode 181. The pixel definition layer PDL may be formed using an organic material, an inorganic material, etc. For example, the pixel definition layer PDL may be formed using a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, or a silicon compound. According to an exemplary embodiment, the pixel definition layer PDL may be etched to form an opening that exposes a part of the first electrode 181. The light-emitting area and the non-light-emitting area of the display device may be defined through such an opening of the pixel definition layer PDL. For example, the part where the opening of the pixel definition layer PDL is located may correspond to the light-emitting area, and the non-light-emitting area may correspond to the part adjacent to the opening of the pixel definition layer PDL.

[0081] The light-emitting layer 182 may be disposed on the first electrode 181 exposed through the opening of the pixel definition film PDL. In addition, the light-emitting layer 182 may extend to the sidewall of the opening of the pixel definition film PDL. In an exemplary embodiment, the light-emitting layer 182 may have a multi-layer structure including an organic light-emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), etc. In other embodiments, except for the organic light-emitting layer, the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer, etc. may be commonly formed corresponding to a plurality of pixels. The organic light-emitting layer of the light-emitting layer 182 may be formed using a light-emitting material that can generate mutually different colors of light such as red light, green light, and blue light according to each pixel of the display device. According to other exemplary embodiments, the organic light-emitting layer of the light-emitting layer 182 may have the following structure, that is, a plurality of light-emitting materials that can emit different colors of light such as red light, green light, and blue light are stacked to emit white light. At this time, the light-emitting structure may be commonly formed corresponding to a plurality of pixels, and each pixel may be distinguished by a color filter layer.

[0082] The second electrode 183 may be disposed on the pixel definition film PDL and the light-emitting layer 182. According to the light-emitting mode of the display device, the second electrode 183 may include a light-transmissive material or a reflective material. In an exemplary embodiment, the second electrode 183 may also be formed of a single-layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive material film.

[0083] The sealing member CS may be disposed on the fourth insulating layer 150 to overlap with the first connection wiring SL1, the second connection wiring SL2, the first shielding electrode SE1, and the second shielding electrode SE2. The sealing substrate 200 and the sealing member CS may seal the light-emitting structure 180 disposed in the display area DA to prevent the penetration of external moisture and oxygen.

[0084] After the sealing member CS is formed on the sealing substrate 200, it is attached to the base substrate 100 and then cured by laser irradiation or the like, so that the display area DA in which the light-emitting structure 180 is disposed can be sealed. At this time, the laser irradiates the sealing member CS through the sealing substrate 200. Thus, the shielding electrode including molybdenum can block the laser from irradiating the first connection wiring SL1 and the second connection wiring SL2. Thereby, problems such as damage to the first connection wiring SL1 and the second connection wiring SL2 including aluminum due to the irradiation of the laser can be prevented.

[0085] Figure 4 is a partially enlarged cross-sectional view of a display device according to an embodiment of the present invention.

[0086] Referring to Figure 1 and Figure 4 , in the display device, except that the first gate conductive layer is formed of a first main conductive layer and a first covering layer and the second gate conductive layer is formed of a second main conductive layer and a second covering layer, it is the same as the Figure 1 display device. Therefore, repeated descriptions are omitted.

[0087] The first gate conductive pattern GAT1b may include a first main conductive layer M1 and a first covering layer C1 disposed on the first main conductive layer M1. The first main conductive layer M1 may be formed of a single layer of aluminum or an aluminum alloy, and the first covering layer C1 may include titanium (Ti) and have the following thickness.

[0088] The second gate conductive pattern GAT2a may include a second main conductive layer M2 and a second covering layer C2 disposed on the second main conductive layer M2. The second main conductive layer M2 may be formed of a single layer of aluminum or an aluminum alloy, and the second covering layer C2 may include titanium (Ti) and have the following thickness.

[0089] Figures 5A to 5F is a cross-sectional view for explaining Figure 3 a method of manufacturing a display device.

[0090] Referring to Figure 5A , a buffer layer 110 may be formed on a substrate 100. An active layer may be formed on the buffer layer 110. The active layer may include a first active pattern ACTa and a second active pattern ACTb. A first insulating layer 120 may be formed on the buffer layer 110 on which the active layer is disposed.

[0091] A first gate conductive layer may be formed on the first insulating layer 120. The first gate conductive layer may include a first gate pattern GAT1a and a first gate pattern GAT1b separated from the first gate pattern GAT1a. The first gate conductive layer may further include the first connection wiring SL1.

[0092] Then, impurities may be doped into a part of the active layer to form source / drain regions. Then, in order to activate dopants in the active layer, heat treatment is performed, so that the active layer can be activated (rapid thermal annealing: RTA, rapid thermal annealing).

[0093] The second gate conductive layer may be formed on the first insulating layer 120 on which the first gate conductive layer is disposed. The second gate conductive layer may include a second a gate pattern GAT2a and a second b gate pattern GAT2b separated from the second a gate pattern GAT2a (not shown in Figure 5A ). The second gate conductive layer may further include the second connection wiring SL2.

[0094] The third insulating layer 140 may be formed on the second insulating layer 130 on which the second gate conductive layer is disposed.

[0095] Referring to Figure 5B , a first contact hole CNT1 may be formed to penetrate the third insulating layer 140, the second insulating layer 130, and the first insulating layer 120 to expose the first active pattern ACTa.

[0096] Here, in order to improve the electrical connection based on the first contact hole CNT1, the upper surface of the first active pattern ACTa exposed through the first contact hole CNT1 may be cleaned. For example, a wet cleaning process may be performed using a BOE (Buffered Oxide Etchant) cleaning solution having an etching force for metals. The cleaning process may be performed using the BOE solution to remove the residue below the first contact hole CNT1 and the oxide film of the exposed first active pattern ACTa.

[0097] At this time, during the formation of the first contact hole CNT1, the first gate conductive layer and the second gate conductive layer are entirely covered by the second insulating layer 130 and the third insulating layer 140, so there is no need to worry about the first gate conductive layer and the second gate conductive layer being etched by the cleaning solution. That is, even if the first gate conductive layer and the second gate conductive layer are formed of a material such as aluminum that is easily affected by the BOE (Buffered Oxide Etchant) cleaning solution, problems of damage during the process can be prevented.

[0098] Referring to Figure 5C , a third gate conductive layer may be formed on the third insulating layer 140 on which the first contact hole CNT1 is disposed. The third gate conductive layer may include a third a gate pattern GAT3a and a third b gate pattern GAT3b separated from the third a gate pattern GAT3a (not shown in Figure 5C ). The third gate conductive layer may further include the shielding electrode. The shielding electrode may include a first shielding electrode SE1 and a second shielding electrode SE2.

[0099] Referring to Figure 5D , the fourth insulating layer 150 may be formed on the third insulating layer 140 provided with the third gate conductive layer. The following may be formed: a second contact hole CNT2 penetrating the fourth insulating layer 150; a third contact hole CNT3 penetrating the fourth insulating layer 150 and the third insulating layer 140; a fourth contact hole CNT4 penetrating the fourth insulating layer 150, the third insulating layer 140, and the second insulating layer 130.

[0100] The second contact hole CNT2 to the fourth contact hole CNT4 expose the third gate conductive layer, the second gate conductive layer, and the first gate conductive layer, but do not expose the active layer. Therefore, a cleaning solution that does not have an etching force for metal can be used to sufficiently clean the second contact hole CNT2 to the fourth contact hole CNT4. For example, even if DI water is used for cleaning, it can be sufficiently cleaned. Thus, the first gate conductive layer and the second gate conductive layer formed of aluminum or the like can be undamaged.

[0101] According to another embodiment, the first gate conductive layer and the second gate conductive layer may include a covering layer on a main conductive layer formed of aluminum or the like, and the covering layer includes titanium or the like. In this case, the covering layer only needs to function as an etching stop layer when forming the second contact hole CNT2 to the fourth contact hole CNT4, and thus may have a relatively thin thickness.

[0102] Referring to Figure 5E , a source-drain conductive layer may be formed on the fourth insulating layer 150. The source-drain conductive layer may include a first SD pattern Sda, a second SD pattern Sdb, and a third SD pattern Sdc.

[0103] The via insulating layer 160 may be formed on the source-drain conductive layer. A first electrode 181 may be formed on the via insulating layer 160. A pixel defining film PDL may be formed on the via insulating layer 160 on which the first electrode 181 is disposed. A light-emitting layer 182 may be formed on the first electrode 181 exposed through an opening of the pixel defining film PDL. A second electrode 183 may be formed on the pixel defining film PDL and the light-emitting layer 182.

[0104] Referring to Figure 5F , a sealing member CS may be formed on the sealing substrate 200. After the sealing member CS is bonded to the base substrate 100, laser (LASER) may be irradiated to the sealing member CS to cure the sealing member CS. Thus, the display area in which the light-emitting structure 180 is disposed can be sealed.

[0105] At this time, the laser is irradiated to the sealing member CS through the sealing substrate 200, and thus, the shielding electrode including molybdenum or the like can block the laser from irradiating to the first connection wiring SL1 and the second connection wiring SL2. Thus, the problem that the first connection wiring SL1 and the second connection wiring SL2 including aluminum or the like are damaged by the irradiation of the laser can be prevented.

[0106] Thus, the display device can be manufactured.

[0107] Figure 6 is a block diagram showing an electronic device according to an embodiment of the present invention, Figure 7A It is shown that the TV is implemented Figure 6 A diagram of an example of an electronic device, Figure 7B It is shown that the smart phone can realize Figure 6 A diagram of an example of an electronic device.

[0108] Reference Figures 6 to 7B , the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input / output device 540, a power supply device 550, and a display device 560. At this time, the display device 560 may correspond to Figure 1 The electronic device 500 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a USB device, etc. or for communicating with other systems. In one embodiment, Figure 7A As shown, the electronic device 500 may be implemented by a television. Figure 7B As shown, the electronic device 500 can be implemented by a smart phone. However, these are exemplary, and the electronic device 500 is not limited thereto. For example, the electronic device 500 can also be implemented by a portable mobile phone, a video phone, a smart pad, a smart watch, a tablet PC, a vehicle navigation device, a computer display, a notebook computer, a head mounted display (HMD), etc.

[0109] The processor 510 may perform specific calculations or tasks. According to an embodiment, the processor 510 may be a microprocessor, a Central Processing Unit (CPU), an Application Processor (AP), etc. The processor 510 may be connected to other components through an address bus, a control bus, a data bus, etc. According to an embodiment, the processor 510 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus. The storage device 520 may store data required for the operation of the electronic device 500. For example, the storage device 520 may include non-volatile storage devices such as an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM) device, etc.; and / or volatile storage devices such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile DRAM device, etc. The storage device 530 may include a Solid State Drive (SSD), a Hard Disk Drive (HDD), a CD-ROM, etc.The input / output device 540 may include an input unit such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc., and an output unit such as a speaker, a printer, etc. The power supply device 550 may supply power required when the electronic device 500 operates.

[0110] The display device 560 may be connected to other components through the bus or other communication links. According to an embodiment, the display device 560 may also be included in the input / output device 540. As described above, the display device 560 may reduce the wiring resistance to improve the display quality and may prevent problems that may occur in the manufacturing process. However, this has been described above, so the repeated description thereof is omitted.

[0111] The present invention can be applied to an organic light-emitting display device and various electronic devices including the organic light-emitting display device. For example, the present invention can be applied to a portable phone, a smart phone, a video phone, a smart tablet device, a smart watch, a tablet PC, a vehicle navigation device, a television, a computer monitor, a laptop computer, a head-mounted display, etc.

[0112] As described above, the present invention has been described with reference to exemplary embodiments of the present invention. However, those skilled in the art can understand that the present invention can be modified and changed without departing from the spirit and scope of the present invention described in the claims.

Claims

1. A display device, characterized in that, Comprising: A base substrate; An active layer disposed on the base substrate and including a first active pattern; A first insulating layer disposed on the active layer; A first gate conductive layer disposed on the first insulating layer; A second insulating layer disposed on the first gate conductive layer; A second gate conductive layer disposed on the second insulating layer; A third insulating layer disposed on the second gate conductive layer; A third gate conductive layer including a third a gate pattern disposed on the third insulating layer; The third gate conductive layer is not directly connected to the first gate conductive layer, and the third gate conductive layer is not directly connected to the second gate conductive layer, The third a gate pattern is directly connected to the first active pattern through a first contact hole, wherein the first contact hole is formed through the third insulating layer, the second insulating layer, and the first insulating layer.

2. The display device according to claim 1, characterized in that, Further comprising: A fourth insulating layer disposed on the third gate conductive layer; And A source-drain conductive layer disposed on the fourth insulating layer and including a first source-drain pattern and a second source-drain pattern, The first gate conductive layer includes a first a gate pattern and a first b gate pattern, the first a gate pattern overlaps with the first active pattern, and the first b gate pattern is separated from the first a gate pattern, The first source-drain pattern is directly connected to the third a gate pattern through a second contact hole, wherein the second contact hole is formed through the fourth insulating layer, The second source-drain pattern is directly connected to the first b gate pattern through a third contact hole, wherein the third contact hole is formed through the fourth insulating layer, the third insulating layer, and the second insulating layer.

3. The display device according to claim 1, wherein The active layer includes polysilicon.

4. The display device according to claim 1, wherein The first gate conductive layer is formed of a single layer of aluminum or an aluminum alloy.

5. The display device according to claim 4, wherein The first gate conductive layer includes a main conductive layer and a covering layer disposed on the main conductive layer.

6. The display device according to claim 5, wherein The main conductive layer is formed of a single layer of aluminum or aluminum alloy, and the covering layer includes titanium and has the following thickness.

7. The display device according to claim 1, wherein Further comprising: A sealing member disposed between a display area for displaying an image and a peripheral area surrounding the display area; And A sealing substrate that seals the structures within the display area together with the sealing member, The first gate conductive layer further includes a first connection wiring overlapping with the sealing member, The third gate conductive layer further includes a shielding electrode disposed between the first connection wiring and the sealing member.

8. A display device, characterized in that, Comprising: A base substrate including a display area for displaying an image and a peripheral area as a non-display area, wherein the peripheral area is adjacent to the display area; An active layer disposed on the base substrate and including a first active pattern; A first insulating layer disposed on the active layer; A first gate conductive layer disposed on the first insulating layer and including a first connection wiring; A second insulating layer disposed on the first gate conductive layer; A second gate conductive layer disposed on the second insulating layer; A third insulating layer disposed on the second gate conductive layer; A third gate conductive layer disposed on the third insulating layer and including a third a gate pattern and a first shielding electrode overlapping with the first connection wiring; A fourth insulating layer disposed on the third gate conductive layer; A sealing member disposed on the fourth insulating layer and disposed between the display area and the peripheral area, and overlapping with the first shielding electrode; And A sealing substrate that, together with the sealing member, seals the structure in the display area, The third a gate pattern is directly connected to the first active pattern through a first contact hole, wherein the first contact hole is formed through the third insulating layer, the second insulating layer, and the first insulating layer.

9. A method for manufacturing a display device, characterized in that, Comprising: A step of forming an active layer including a first active pattern on a base substrate; A step of forming a first insulating layer on the active layer; A step of forming a first gate conductive layer on the first insulating layer; A step of forming a second insulating layer on the first gate conductive layer; A step of forming a first contact hole exposing the first active pattern through the second insulating layer and the first insulating layer; And A step of forming a third gate conductive layer on the second insulating layer, the third gate conductive layer including a third a gate pattern directly connected to the first active pattern through the first contact hole, Before the step of forming the third gate conductive layer, it further includes: A step of forming a second gate conductive layer on the second insulating layer; And A step of forming a third insulating layer on the second gate conductive layer, In the step of forming the first contact hole, the first gate conductive layer is entirely covered by the second insulating layer, and the second gate conductor is entirely covered by the third insulating layer.

10. The method for manufacturing a display device according to claim 9, wherein After the step of forming the first contact hole and before forming the third gate conductive layer, it further includes: A step of cleaning the surface of the first active pattern exposed through the first contact hole with a cleaning solution having an etching force for metal.

11. The method for manufacturing a display device according to claim 10, wherein In the step of performing the cleaning, wet cleaning is performed using a buffered oxide etchant cleaning solution.

12. The method for manufacturing a display device according to claim 9, wherein After forming the first gate conductive layer and before forming the second insulating layer, it further includes: A step of doping impurities into a part of the active layer to form source and drain regions; and A step of performing heat treatment to activate the dopants in the active layer to activate the active layer.

13. The method for manufacturing a display device according to claim 9, wherein The first gate conductive layer includes a connection wiring, The third gate conductive layer includes a shielding electrode overlapping with the connection wiring.

14. The manufacturing method of the display device according to claim 13, wherein, It further includes: A step of forming a sealing member on the sealing substrate; A step of bonding the sealing substrate and the base substrate formed with the third gate conductive layer using the sealing member; And A step of irradiating a laser through the sealing substrate to the sealing member to cure the sealing member The shielding electrode is located between the sealing member and the connection wiring, thereby blocking the laser from irradiating the connection wiring.

15. The method of manufacturing a display device according to claim 9, wherein The first gate conductive layer is formed of a single layer of aluminum or an aluminum alloy.

16. The method of manufacturing a display device according to claim 9, wherein The third gate conductive layer includes molybdenum or a molybdenum alloy.

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