Display device

Abstract

A display device is disclosed. The display device includes a display unit, a gate driver, and a source driver, wherein the display unit includes a scan line, a data line, and a pixel, the gate driver supplies a scan signal, and the source driver supplies a data voltage, wherein the source driver includes a gamma voltage generator that generates different gamma voltages in response to a gamma enable signal, a digital-to-analog converter that uses the gamma voltage to generate a data voltage corresponding to a grayscale value, and a source buffer that outputs the data voltage, the gamma voltage generator includes a first resistor string that sets a voltage range of the gamma voltage, a gamma buffer that outputs a voltage selected from divided voltages within the voltage range, and a second resistor string that includes contacts to divide a voltage between the contacts to generate the gamma voltage, and at least some of the gamma buffers are turned on in a first period and turned off in a second period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0026480, filed on March 7, 2019, and Korean Patent Application No. 10-2019-0050928, filed on April 30, 2019, each of which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to a gamma voltage generating circuit, a source driver including the gamma voltage generating circuit, and a display device. Background Art

[0004] The display device includes a display panel and a driver. The display panel includes scan lines, data lines and pixels. The driver includes a scan driver and a data driver, wherein the scan driver sequentially supplies scan signals to the scan lines, and the data driver supplies data signals to the data lines. Each of the pixels can emit light of brightness corresponding to the data signal provided by the corresponding data line in response to the scan signal provided by the corresponding scan line.

[0005] The data driver may generate gamma voltages corresponding to a plurality of grayscales, and may convert grayscale values ​​of image data into data signals using the gamma voltages.

[0006] The range of the gamma voltage may vary according to brightness, and in some cases, the characteristics of the gamma voltage having the changed voltage level may be different from the ideal gamma voltage.

[0007] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0008] Exemplary embodiments of the present invention relate to a gamma voltage generating circuit that generates an ideal gamma voltage, and a source driver and a display device including the gamma voltage generating circuit.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0010] A display device according to an exemplary embodiment includes a display unit, a gate driver, and a source driver, wherein the display unit includes scan lines, data lines, and pixels connected to the scan lines and the data lines, the gate driver is configured to supply scan signals to the scan lines, and the source driver is configured to supply data voltages to the data lines, wherein the source driver includes a gamma voltage generator, a digital-to-analog converter, and a source buffer, wherein the gamma voltage generator is configured to generate gamma voltages having voltage levels different from each other in response to a gamma enable signal, the digital-to-analog converter is configured to generate data voltages corresponding to grayscale values ​​using the gamma voltages, and The source buffer is configured to output the data voltage to the data line, the gamma voltage generator includes a first resistor string, a gamma buffer and a second resistor string, wherein the first resistor string is configured to set a voltage range of the gamma voltage, the gamma buffer is configured to output a voltage selected from the divided voltages within the voltage range, and the second resistor string includes contacts respectively connected to the output terminals of the gamma buffer, the second resistor string is configured to divide the voltage between the contacts to generate the gamma voltage, and at least some of the gamma buffers are configured to be turned on in a first cycle and turned off in a second cycle different from the first cycle.

[0011] The gamma voltage generator may include a digital gamma voltage generator.

[0012] The gamma voltage generator may further include a first buffer and a second buffer, wherein the first buffer is configured to apply a maximum gamma voltage to one terminal of the first resistor string, and the second buffer is configured to apply a minimum gamma voltage to another terminal of the first resistor string, and the minimum gamma voltage of the second buffer may be changed according to a display brightness of the display unit.

[0013] The gamma voltage may be non-linear in a first period and linear in a second period.

[0014] The first period and the second period may be included in one horizontal period, and the source driver may be configured to supply the data voltage to the data line at intervals of one horizontal period.

[0015] The scan signal may have an off voltage level in a first period and an on voltage level in a second period.

[0016] At least some of the gamma buffers may be turned off at a point in time when the scan signal transitions from an off voltage level to an on voltage level.

[0017] At least some of the gamma buffers may be turned off after a time point when the scan signal transitions from an off voltage level to an on voltage level.

[0018] A first gamma buffer connected to an uppermost node of the second resistor string among the gamma buffers may maintain an on state in the second period, and a second gamma buffer connected to a lowermost node of the second resistor string among the gamma buffers may maintain an on state in the second period.

[0019] The remaining gamma buffers except the first gamma buffer and the second gamma buffer may be turned off in the second period.

[0020] A third gamma buffer, which is farthest from the first gamma buffer and the second gamma buffer among the gamma buffers, may maintain a turned-on state in the second period.

[0021] A fourth gamma buffer adjacent to the first gamma buffer or the second gamma buffer among the gamma buffers may maintain a turned-on state in the second period.

[0022] The frame period may include a display period for displaying an image and a threshold period between the display period and another display period, the display period may include a first period and a second period, the source buffer may be turned off in the threshold period and turned on in the display period, and at least some of the gamma buffers may be turned off in the threshold period and turned on in the display period.

[0023] At least some of the gamma buffers may be turned off after a time point at which the threshold period starts, and may be turned on before a time point at which the threshold period ends.

[0024] The display period may include a black period providing a black data voltage corresponding to black and an effective period different from the black period, the source buffer may be turned off in the black period and turned on in the effective period, and at least some of the gamma buffers may be turned off in the black period and turned on in the effective period.

[0025] The first period and the second period may be included in the valid period.

[0026] The first gamma buffer connected to the uppermost connection point of the second resistor string may maintain a turned-on state in the black period, and the remaining gamma buffers except the first gamma buffer may be turned off.

[0027] At least some of the gamma buffers may be turned off after a time point at which a black period starts, and may be turned on before a time point at which a black period ends.

[0028] A source driver according to another exemplary embodiment includes a gamma voltage generator, a digital-to-analog converter, and a source buffer, wherein the gamma voltage generator is configured to generate gamma voltages having voltage levels different from each other in response to a gamma enable signal, the digital-to-analog converter is configured to generate a data voltage corresponding to a grayscale value using the gamma voltage, and the source buffer is configured to output the data voltage, wherein the gamma voltage generator includes a first resistor string, a gamma buffer, and a second resistor string, wherein the first resistor string is configured to set a voltage range of the gamma voltage, the gamma buffer is configured to output a voltage selected from divided voltages within the voltage range, and the second resistor string includes junctions respectively connected to output terminals of the gamma buffer, the second resistor string is configured to divide the voltage between the junctions to generate the gamma voltage, and at least some of the gamma buffers can be configured to be turned on in a first period and turned off in a second period different from the first period.

[0029] According to another exemplary embodiment, a gamma voltage generating circuit includes a first resistor string, a gamma buffer, and a second resistor string, wherein the first resistor string is configured to set a voltage range of the gamma voltage, the gamma buffer is configured to output a voltage selected from voltages divided within the voltage range, and the second resistor string includes contacts respectively connected to output terminals of the gamma buffer, the second resistor string is configured to divide the voltage between the contacts to generate the gamma voltage, wherein at least some of the gamma buffers are configured to be turned on in a first cycle and turned off in a second cycle different from the first cycle.

[0030] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0032] Figure 1 is a block diagram of a display device according to an exemplary embodiment.

[0033] Figure 2 is included in Figure 1 An exemplary circuit diagram of a pixel in a display device of FIG.

[0034] Figure 3 is included in Figure 1 An exemplary block diagram of a data driver in a display device of FIG.

[0035] Figure 4 yes Figure 3An exemplary block diagram of a data driver is shown in FIG.

[0036] Figure 5 is included in Figure 3 An exemplary circuit diagram of a gamma voltage generator in a data driver of FIG.

[0037] Figure 6 is included in Figure 5 An exemplary circuit diagram of a gamma buffer connected in series with a third resistor in a gamma voltage generator.

[0038] Figure 7 is from Figure 5 An example diagram of gamma voltages output by a gamma voltage generator is shown in FIG.

[0039] Fig. 8A and Figure 8B It is shown Figure 5 A waveform diagram of the operation of the gamma voltage generator.

[0040] Fig. 9 It is shown Figure 5 An exemplary circuit diagram of the operation of a gamma voltage generator.

[0041] Fig.10 It is shown Figure 5 FIG. 1 is another exemplary circuit diagram of the operation of a gamma voltage generator.

[0042] Fig.11 It is shown Figure 5 1. Still another exemplary circuit diagram of the operation of a gamma voltage generator.

[0043] Fig.12 It is shown Figure 3 FIG. 1 is an exemplary waveform diagram of the operation of a data driver.

[0044] Fig.13 It is shown Figure 3 FIG. 1 is another exemplary waveform diagram of the operation of a data driver.

[0045] Fig.14 It is shown Figure 3 FIG. 1 is another exemplary waveform diagram of the operation of a data driver of FIG. DETAILED DESCRIPTION

[0046] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "implementation" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more of the inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without specific details or with one or more equivalent arrangements. In other examples, known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0047] Unless otherwise specified, the exemplary embodiments shown should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0048] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross hatching or shading will not convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, performances, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented in different ways, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, similar reference numerals represent similar elements.

[0049] When an element (e.g., layer) is referred to as being "on", "connected to" or "coupled to" another element or layer, the element (e.g., layer) may be directly on, connected to or coupled to another element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. For this reason, the term "connected" may indicate a physical, electrical and / or fluid connection with or without an intermediate element. In addition, the D1-axis, D2-axis and D3-axis are not limited to the three axes of a rectangular coordinate system (such as an x-axis, a y-axis and a z-axis), and may be interpreted as a broader meaning. For example, the D1-axis, the D2-axis and the D3-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these components should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0051] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the exemplary term "below" may include both orientations of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0052] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the words "comprise", "comprising", "include" and / or "including" are used in this specification, the existence of the stated features, integers, steps, operations, elements, parts and / or clusters thereof is indicated, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or clusters thereof is not excluded. It is also noted that, as used herein, the words "substantially", "about" and similar words are used as approximate words rather than words of degree, and thus, are used to take into account the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0053] As is customary in the art, in terms of functional blocks, units and / or modules, some exemplary embodiments are shown and described in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and associated circuits) that perform some functions to perform other functions. Moreover, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense.

[0055] Figure 1 is a block diagram of a display device according to an exemplary embodiment.

[0056] Reference Figure 1 , the display device 100 may include a display unit 110 (or a display panel), a scan driver 120 (or a gate driver), a data driver 130 (or a source driver), a timing controller 140 and a light emitting driver 150 (or an EM driver).

[0057] The display unit 110 may include scan lines (or gate lines) SL1 to SLn, data lines DL1 to DLm, light emission control lines EL1 to ELn, and pixels PXL, where n is a positive integer and m is a positive integer. The pixels PXL may be arranged in a region (e.g., a pixel region) divided by the scan lines SL1 to SLn, the data lines DL1 to DLm, and the light emission control lines EL1 to ELn.

[0058] The pixel PXL may be connected to at least one of the scan lines SL1 to SLn, one of the data lines DL1 to DLm, and at least one of the emission control lines EL1 to ELn. For example, the pixel PXL may be connected to the scan line SLi, the previous scan line SLi-1 adjacent to the scan line SLi, the data line DLj, and the emission control line ELi, where i and j are positive integers.

[0059] The pixel PXL can be initialized in response to a scan signal provided through the previous scan line SLi-1 (or a scan signal provided at a previous time point or a previous gate signal), store or record a data signal provided through the data line DLj in response to a scan signal provided through the scan line SLi (or a scan signal or a gate signal provided at a current time point), and emit light having a brightness corresponding to the stored data signal in response to a control signal provided through the light emitting control line ELi.

[0060] The display unit 110 may receive a first power supply voltage VDD and a second power supply voltage VSS. The first power supply voltage VDD and the second power supply voltage VSS may be used for the operation of the pixel PXL, and the first power supply voltage VDD may have a voltage level higher than that of the second power supply voltage VSS. An initialization power supply voltage Vint may be provided to the display unit 110. The first power supply voltage VDD, the second power supply voltage VSS, and the initialization power supply voltage Vint may be provided to the display unit 110 from a separate power supply unit.

[0061] The scan driver 120 may generate a scan signal based on the scan control signal SCS, and may sequentially provide the scan signal to the scan lines SL1 to SLn. The scan control signal SCS may include a start signal, a clock signal, and the like, and may be provided from the timing controller 140. For example, the scan driver 120 may include a shift register (or stage) that sequentially generates and outputs a pulse-shaped scan signal corresponding to a pulse-shaped start signal using a clock signal.

[0062] The light emitting driver 150 may generate a light emitting control signal based on the light emitting drive control signal ECS, and may sequentially or synchronously provide the light emitting control signal to the light emitting control lines EL1 to ELn. The light emitting drive control signal ECS may include a light emitting start signal, a light emitting clock signal, and the like, and may be provided from the timing controller 140. For example, the light emitting driver 150 may include a shift register that sequentially generates and outputs a pulse-shaped light emitting control signal corresponding to the pulse-shaped light emitting start signal using the light emitting clock signal.

[0063] The data driver 130 may generate a data signal based on the image data DATA2 and the data control signal DCS provided from the timing controller 140, and output the data signal to the display unit 110 (or the pixel PXL). The data control signal DCS controls the operation of the data driver 130, and may include a load signal (or a data enable signal) for instructing the output of a valid data signal.

[0064] The data driver 130 according to an exemplary embodiment may generate a gamma voltage and output a data signal (or data voltage) by selecting one of the gamma voltages corresponding to the grayscale value of the image data DATA2. The data driver 130 may output at least some of the gamma voltages (e.g., representative gamma voltages) through a gamma buffer (or gamma amplifier) ​​and periodically turn off at least some of the gamma buffers.

[0065] The total voltage range of the gamma voltage and the target voltage level of the gamma voltage may be changed according to the brightness. In this case, the actual voltage level of the gamma voltage output from the gamma buffer may have an error compared to the target voltage level based on the offset of the gamma buffer (or the offset voltage, difference between the ideal output voltage and the actual output voltage). That is, the gamma voltage output from the gamma buffer may have a nonlinear characteristic. Accordingly, the display device 100 (or the data driver 130) according to the exemplary embodiment may turn on the gamma buffer in the first cycle, and turn off at least some of the gamma buffers (for example, the gamma buffer that outputs the intermediate gamma voltage corresponding to the intermediate grayscale) in the second cycle. The second cycle may be a data signal generation cycle for generating a data signal by selecting one of the gamma voltages corresponding to the grayscale value, and the first cycle may be a cycle before the second cycle. In this case, during the first cycle, the gamma voltage is quickly changed or charged to a voltage level similar to the target voltage level by the turned-on gamma buffer, and during the second cycle, the offset component of the gamma buffer is removed. In this way, the linearity of each of the gamma voltages (especially the intermediate gamma voltage) can be ensured.

[0066] The configuration for generating the gamma voltage and the configuration for controlling the gamma buffer will be referred to below. Figures 5 to 11 A more detailed description is given.

[0067] The data driver 130 according to an exemplary embodiment may turn off at least some of the gamma buffers in a threshold period (or blank period) and a black period. The threshold period may be a period between display periods (e.g., a period in which an image is displayed), and the black period may be a period in which only a black image is displayed in the display period. No valid data signal is generated in the threshold period, and only a gamma voltage corresponding to black is required in the black period. Accordingly, the power consumption of the data driver 130 (and the display device 100) may be reduced.

[0068] The configuration for controlling the gamma buffer during the threshold period and the black period will be referred to below. Figure 12 to Figure 14 A more detailed description is given.

[0069] The timing controller 140 may receive input image data DATA1 and a control signal CS from an external device such as a graphics processor, generate a scan control signal SCS, a data control signal DCS, and a light-emitting drive control signal ECS based on the control signal CS, and generate image data DATA2 by converting the input image data DATA1. The control signal CS may include a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a clock CLK, and the like. The vertical synchronization signal may indicate the start of a frame data (e.g., data corresponding to a frame period for displaying one frame of an image), and the horizontal synchronization signal may indicate the start of a data row (e.g., one of a plurality of data rows included in the frame data). For example, the timing controller 140 may convert the input image data DATA1 in an RGB format into image data DATA2 in an RGBG format to conform to the arrangement of pixels in the display unit 110.

[0070] At least one of the scan driver 120, the data driver 130, the timing controller 140, and the light emitting driver 150 may be formed in the display unit 110, or may be implemented as an integrated circuit (IC) and connected to the display unit 110 in a tape carrier package form. In some exemplary embodiments, at least two of the scan driver 120, the data driver 130, the timing controller 140, and the light emitting driver 150 may be implemented as a single IC.

[0071] Figure 2 is included in Figure 1 An exemplary circuit diagram of a pixel in a display device of FIG.

[0072] Reference Figure 2 , the pixel PXL may include first to seventh transistors T1 to T7 , a storage capacitor Cst, and a light emitting element LD.

[0073] Each of the first to seventh transistors T1 to T7 may be implemented as a P-type transistor, but is not limited thereto. For example, at least some of the first to seventh transistors T1 to T7 may also be implemented as an N-type transistor.

[0074] A first electrode of the first transistor (e.g., a driving transistor) T1 may be connected to a second node N2, or may be connected to a first power line (e.g., a power line to which a first power voltage VDD is applied) through a fifth transistor T5. A second electrode of the first transistor T1 may be connected to a first node N1, or may be connected to an anode of the light emitting element LD through a sixth transistor T6. A gate electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may control the amount of current flowing from the first power line to the second power line (e.g., a power line to which a second power voltage VSS is transmitted) through the light emitting element LD in correspondence with a voltage of the third node N3.

[0075] The second transistor T2 (e.g., a switching transistor) may be connected between the data line DLj and the second node N2. The gate electrode of the second transistor T2 may be connected to the scan line SLi. When a scan signal is supplied to the scan line SLi, the second transistor T2 may be turned on to electrically connect the data line DLj to the first electrode of the first transistor T1.

[0076] The third transistor T3 may be connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 may be connected to the scan line SLi. When the scan signal is supplied to the scan line SLi, the third transistor T3 may be turned on to electrically connect the first node N1 to the third node N3. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in a diode form.

[0077] The storage capacitor Cst may be connected between the first power line and the third node N3. The storage capacitor Cst may store the data signal and a voltage corresponding to the threshold voltage of the first transistor T1.

[0078] The fourth transistor T4 may be connected between the third node N3 and an initialization power line (e.g., a power line for transmitting an initialization power voltage Vint). A gate electrode of the fourth transistor T4 may be connected to a previous scan line SLi-1. When a scan signal is supplied to the previous scan line SLi-1, the fourth transistor T4 may be turned on to supply the initialization power voltage Vint to the first node N1. Here, the initialization power voltage Vint may be set to have a voltage level lower than that of the data signal.

[0079] The fifth transistor T5 may be connected between the first power line and the second node N2. A gate electrode of the fifth transistor T5 may be connected to the light emission control line ELi. The fifth transistor T5 may be turned off when a light emission control signal is supplied to the light emission control line ELi, and may be turned on in other cases.

[0080] The sixth transistor T6 may be connected between the first node N1 and the light emitting element LD. A gate electrode of the sixth transistor T6 may be connected to the light emitting control line ELi. The sixth transistor T6 may be turned off when a light emitting control signal is supplied to the light emitting control line ELi, and may be turned on in other cases.

[0081] The seventh transistor T7 may be connected between the initialization power line and the anode of the light emitting element LD. The gate electrode of the seventh transistor T7 may be connected to the scan line SLi. When the scan signal is supplied to the scan line SLi, the seventh transistor T7 may be turned on to supply the initialization power voltage Vint to the anode of the light emitting element LD.

[0082] The anode of the light emitting element LD may be connected to the first transistor T1 via the sixth transistor T6, and the cathode thereof may be connected to the second power supply line. The light emitting element LD may emit light of a predetermined brightness corresponding to the current supplied from the first transistor T1. The first power supply voltage VDD may be set to have a voltage level higher than the second power supply voltage VSS so that current flows through the light emitting element LD.

[0083] Figure 3 is included in Figure 1 An exemplary block diagram of a data driver in a display device of FIG.

[0084] Reference Figure 1 and Figure 3 The data driver 130 (or source driver) may include a controller 310 (or control logic), a bias voltage generator 320 (or a bias voltage generating circuit), a gamma voltage generator 330 (or a gamma voltage generating circuit), a shift register 340, a latch 350, a decoder 360 (or a digital-to-analog converter DEC), and an output buffer 370.

[0085] The controller 310 may receive the data control signal DCS from the timing controller 140 .

[0086] The controller 310 may generate a bias control signal BCS based on the data control signal DCS. The bias control signal BCS may be used to adjust a bias voltage Vbias applied to a source buffer (or source amplifier) ​​configuring the output buffer 370 .

[0087] As will be referred to below Fig.12 As described, the bias voltage Vbias can be reduced during the threshold period (and the black period). In this way, the power consumption of the output buffer 370 and the data driver 130 can be reduced.

[0088] The controller 310 may generate a gamma enable signal G_EN. The gamma enable signal G_EN may control the gamma voltage generator 330 so that the gamma voltage generator 330 generates gamma voltages VG0 to VG2047. The gamma voltages VG0 to VG2047 may be used to transmit data DATA (eg, Figure 1 The gamma voltages VG0 to VG2047 may include 2048 gamma voltages corresponding to 11-bit data, but the inventive concept is not limited thereto.

[0089] The controller 310 may convert serial data received from the timing controller 140 into parallel data DATA. The controller 310 may provide the parallel data DATA to the shift register 340.

[0090] The bias voltage generator 320 may generate a bias voltage Vbias having various voltage levels in response to the bias control signal BCS.

[0091] The gamma voltage generator 330 may receive the gamma enable signal G_EN and generate gamma voltages VG0 to VG2047 having various voltage levels.

[0092] In an exemplary embodiment, the gamma voltage generator 330 may include a gamma buffer, wherein the gamma buffer transmits a representative gamma voltage to a resistor string and a junction of the resistor string, turns on the gamma buffer in a first period, and turns off at least some of the gamma buffers in a second period, the gamma buffer being, for example, a gamma buffer that outputs an intermediate gamma voltage corresponding to an intermediate grayscale.

[0093] In one exemplary embodiment, the gamma voltage generator 330 may turn off at least some of the gamma buffers in the threshold period and the black period.

[0094] In one exemplary embodiment, the gamma voltage generator 330 may be a digital gamma voltage generator. In this case, the gamma voltages output from the gamma voltage generator 330 may be linear.

[0095] The shift register 340 may provide the parallel data DATA to the latch 350. The shift register 340 may generate a latch clock signal and provide the latch signal to the latch 350, and the latch clock signal may be used to control the timing of outputting the parallel data DATA.

[0096] The latch 350 may latch or temporarily store data sequentially received from the shift register 340 , and transfer the latched data to the decoder 360 .

[0097] The decoder 360 may convert digital type data (eg, grayscale values ​​of the parallel data DATA) into analog type data signals (or data voltages) using the gamma voltages VG0 to VG2047 .

[0098] The output buffer 370 may receive the data signal and output the data signal to the data line DLs (eg, refer to Figure 1 The output buffer 370 may include a source buffer connected to the data lines DL1 to DLm of the display unit 110 as described above.

[0099] Figure 4 yes Figure 3 An exemplary block diagram of a data driver is shown in FIG. Figure 4In the embodiment, the data driver 130 is schematically shown as including a bias voltage generator 320, a gamma voltage generator 330, a decoder 360 and an output buffer 370, which can be used to drive one pixel PXL, however, the data driver 130 may include various other components. Figure 3 The bias voltage generator 320 , the gamma voltage generator 330 , the decoder 360 , and the output buffer 370 are described, and thus redundant descriptions thereof will not be repeated.

[0100] The gamma voltages VG0 to VG2047 output from the gamma voltage generator 330 may be linear. For example, the gamma voltages VG0 to VG2047 may be located on a straight line corresponding to a linear equation for the gamma code CODE (or digital input value).

[0101] The decoder 360 may select one of the gamma voltages VG0 to VG2047 based on the gray value of the data DATA, and output the selected gamma voltage as the data voltage VGS. For example, the decoder 360 may output the data voltage VGS corresponding to the gray value by using a separate lookup table defining the relationship between the gray value GRAY and the gamma voltages VG0 to VG2047 or by performing logic processing on the gray value. For example, the data voltage VGS may have 265 voltage levels corresponding to an 8-bit gray value. The data voltage VGS of each gray may be located on a gamma curve (e.g., a 2.2 gamma curve 2.2 curve). More specifically, the decoder 360 may output the data voltage VGS corresponding to the 2.2 gamma curve by logic processing of the linear gamma voltages VG0 to VG2047.

[0102] The output buffer 370 may include a source buffer 381 (or a source amplifier).

[0103] The source buffer 381 may receive a data voltage VGS (or a data signal, a grayscale voltage) from the decoder 360, and may drive the data voltage VGS according to the level of the bias voltage Vbias. The driven data voltage VGS may be output to the pixel PXL via the data line DL. Since a large amount of current may be consumed to drive the pixel PXL, according to an exemplary embodiment, the data voltage VGS may be supplied to the pixel PXL through the source buffer 381.

[0104] Figure 5 is included in Figure 3 An exemplary circuit diagram of a gamma voltage generator in a data driver of FIG. Figure 6 is included in Figure 5 An exemplary circuit diagram of a gamma buffer connected in series with a third resistor in a gamma voltage generator.

[0105] Reference Figures 3 to 5, the gamma voltage generator 330 may include a first resistor string RST1, a second resistor string RST2, a third resistor string RST3, a first reference selector DEC_TOP, a second reference selector DEC_BOT, selectors DEC1 to DEC10, a first reference buffer AMP_REF1, a second reference buffer AMP_REF2, a first buffer AMP_TOP, a second buffer AMP_BOT, and first to tenth gamma buffers AMP_G1 to AMP_G10 (or first to tenth gamma amplifiers). Although in Figure 5 Ten gamma buffers (AMP_G1 to AMP_G10) are shown in FIG. 4 , however, the inventive concept is not limited to a specific number of gamma buffers.

[0106] The first reference buffer AMP_REF1 may output a first reference voltage VREF1, and the second reference buffer AMP_REF2 may output a second reference voltage VREF2. The first reference voltage VREF1 is a minimum voltage that the gamma voltages VG0 to VG2047 may have, and the second reference voltage VREF2 is a maximum voltage that the gamma voltages VG0 to VG2047 may have. For example, each of the first reference voltage VREF1 and the second reference voltage VREF2 may be set based on a driving voltage (or a power supply voltage) applied to a gamma voltage generating circuit. For example, each of the first reference voltage VREF1 and the second reference voltage VREF2 may be selected from voltages obtained by dividing the driving voltage applied to the gamma voltage generating circuit, and may be supplied to the first reference buffer AMP_REF1 and the second reference buffer AMP_REF2, respectively.

[0107] The first resistor string RST1 may include a plurality of resistors, and a voltage between the first reference voltage VREF1 and the second reference voltage VREF2 may be divided by the resistors.

[0108] The first reference selector DEC_TOP may select one of the voltages divided by the first resistor string RST1 and output the selected voltage from the divided voltages as the maximum gamma voltage VG_TOP. The maximum gamma voltage VG_TOP may be set to a gamma voltage having a highest voltage level (e.g., a reference gamma voltage VG0 corresponding to the minimum grayscale) among the gamma voltages VG0 to VG2047.

[0109] Similarly, the second reference selector DEC_BOT may select another one of the voltages divided by the first resistor string RST1 and output the selected voltage among the divided voltages as the minimum gamma voltage VG_BOT. The minimum gamma voltage VG_BOT may define a minimum value of the range of the gamma voltages VG0 to VG2047.

[0110] Both the first reference selector DEC_TOP and the second reference selector DEC_BOT may be implemented as 12-bit decoders, however, the inventive concept is not limited thereto.

[0111] The second resistor string RST2 may include a plurality of first resistors Ra, and a range of gamma voltages VG0 to VG2047 is set. A maximum gamma voltage VG_TOP may be provided at one end (e.g., an upper connection point) of the second resistor string RST2, a minimum gamma voltage VG_BOT may be provided at the other end (e.g., a lower connection point) of the second resistor string RST2, and a voltage between the maximum gamma voltage VG_TOP and the minimum gamma voltage VG_BOT may be divided by the first resistors Ra. The first resistors Ra may have the same resistance value.

[0112] The first selector DEC1 can select one of the voltages divided by the second resistor string RST2, and the first gamma buffer AMP_G1 can output a voltage selected from the voltages divided by the second resistor string RST2, and the voltage selected from the divided voltages can be set to the lowest grayscale gamma voltage (the first gamma voltage VG1, the first representative gamma voltage VGR1 or the first contact gamma voltage).

[0113] Similarly, each of the second to tenth selectors DEC2 to DEC10 may select one of the voltages divided by the second resistor string RST2 , and the second to tenth gamma buffers AMP_G2 to AMP_G10 may output the voltages selected by the second to tenth selectors DEC2 to DEC10 , respectively. For example, the voltage selected by the tenth selector DEC10 and output through the tenth gamma buffer AMP_G10 can be set to the highest grayscale gamma voltage VG2047 (the tenth representative gamma voltage VGR10 or the tenth contact gamma voltage), and the voltage output through the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G9 can be set to the intermediate grayscale gamma voltages VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591 and VG1823 (the second representative gamma voltage VGR2 to the ninth representative gamma voltage VGR9, the second contact gamma voltage to the ninth contact gamma voltage, or the intermediate grayscale contact gamma voltage.

[0114] Each of the first to tenth selectors DEC1 to DEC10 may be implemented as a 13-bit decoder, but the inventive concept is not limited thereto.

[0115] The gamma voltages VG1 , VG223 , VG455 , VG679 , VG911 , VG1135 , VG1367 , VG1591 , VG1823 , and VG2047 (or contact gamma voltages) output through the first to tenth gamma buffers AMP_G1 to AMP_G10 may be provided with equal intervals from one another.

[0116] The third resistor string RST3 may include a plurality of second resistors Rb and generate gamma voltages VG1 to VG2047 within the gamma voltage range set in the second resistor string RST2. The second resistors Rb may have the same resistance value.

[0117] like Figure 6 As shown in, the first gamma buffer AMP_G1 to the tenth gamma buffer AMP_G10 can be connected to specific contacts (or specific wiring points) TAB1 to TAB10 of the third resistor string RST3 to reduce the RC delay of the gamma voltages VG1, VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591, VG1823 and VG2047, and to reduce the setup time of the gamma voltages VG1, VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591, VG1823 and VG2047. More specifically, the first to tenth gamma buffers AMP_G1 to AMP_G10 may quickly charge the gamma voltages VG1, VG223, VG455, VG679, VG911, VG1135, VG1367, VG1591, VG1823, and VG2047 to the target gamma voltages, and thus, may be able to improve the linearity of the gamma voltages and facilitate control of the gamma voltages.

[0118] According to an exemplary embodiment, the second buffer AMP_BOT may change the minimum gamma voltage VG_BOT in response to a brightness control signal. The brightness control signal may be provided from the outside, such as from the timing controller 140. More specifically, the second buffer AMP_BOT may change the minimum gamma voltage VG_BOT according to the display brightness of the display device 100, and thus, may be able to adjust the range of the gamma voltages VG0 to VG2047.

[0119] However, in this case, nonlinear characteristics may be generated in the gamma voltages due to offsets of the first to tenth gamma buffers AMP_G1 to AMP_G10. That is, the analog output may have nonlinear characteristics compared to the digital input value CODE.

[0120] Meanwhile, at least some of the first to tenth gamma buffers AMP_G1 to AMP_G10 can be enabled by the gamma buffer control signal CS_AMP (or the gamma enable signal G_EN (see Figure 3 )) to turn on or off. Fig. 8A and Figure 8B The turning-on or turning-off operations of the first to tenth gamma buffers AMP_G1 to AMP_G10 are described in more detail.

[0121] Figure 7 It is shown from Figure 5 An example diagram of gamma voltages output by a gamma voltage generator is shown in FIG.

[0122] Reference Figures 5 to 7 , the first resistor CURVE1 indicates the gamma voltage outputted by the third resistor string RST3 corresponding to the first brightness when only the first gamma buffer AMP_G1 and the tenth gamma buffer AMP_G10 are in operation or turned on (for example, the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G9 are not in operation or turned off). The second curve CURVE2 indicates the gamma voltage outputted by the third resistor string RST3 corresponding to the first brightness when the first gamma buffer AMP_G1 to the tenth gamma buffer AMP_G10 are in operation. The third curve CURVE3 and the fourth curve CURVE4 respectively indicate the gamma voltages outputted by the third resistor string RST3 corresponding to the second brightness and the third brightness respectively when the first gamma buffer AMP_G1 to the tenth gamma buffer AMP_G10 are in operation.

[0123] Referring to the first curve CURVE1, when only the first gamma buffer AMP_G1 and the tenth gamma buffer AMP_G10 operate and the second to ninth gamma buffers AMP_G2 to AMP_G9 do not operate or are turned off, as shown in FIG. Figure 7 As shown in , the contact gamma voltage (especially the middle gamma voltage) may fail to reach the target gamma voltage (eg, the gamma voltage on the second curve CURVE2) within a certain time due to RC delay and exhibit nonlinear characteristics.

[0124] Referring to the second curve CURVE2, when all of the first to tenth gamma buffers AMP_G1 to AMP_G10 operate, RC delay of the gamma voltage is reduced by the first to tenth gamma buffers AMP_G1 to AMP_G10, and thus the gamma voltage may reach a target gamma voltage within a certain time and have a linear characteristic.

[0125] Referring to the third curve CURVE3, when the display brightness of the display device 100 changes from the first brightness to the second brightness, the above reference Figure 5 The minimum gamma voltage VG_BOT described may be changed, and therefore, the first gamma buffer AMP_G1 to the tenth gamma buffer AMP_G10 may output a contact gamma voltage corresponding to the second brightness. However, although the offset of each of the first gamma buffer AMP_G1 to the tenth gamma buffer AMP10 changes according to the change of the minimum gamma voltage VG_BOT, the gamma voltages VG1, VG233, VG455, VG1135, VG1823, and VG2047 may have errors (e.g., a dotted line intersecting with the third curve CURVE3) based on the target gamma voltage, and may have nonlinear characteristics as a whole. Accordingly, the display device 100 cannot accurately display the desired image, and its display quality may be deteriorated.

[0126] Although the settings of the first to tenth gamma buffers AMP_G1 to AMP_G10 may be changed or the control values ​​of the first to tenth selectors DEC1 to DEC10 may be changed according to the second brightness, the related costs may increase when the control values ​​of the first to tenth selectors DEC1 to DEC10 need to be set for all modifiable brightnesses.

[0127] Similar to the third curve CURVE3 , when the display brightness of the display device 100 is changed to the third brightness, the gamma voltage according to the fourth curve CURVE4 has a nonlinear characteristic.

[0128] Accordingly, the gamma voltage generator 330 according to the exemplary embodiment can quickly charge the gamma voltage to the vicinity of the target gamma voltage by turning on the gamma buffer in the first cycle (e.g., the cycle before generating the data voltage), and can remove the error of the gamma voltage by turning off at least some of the gamma buffers (e.g., at least one of the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G9) in the second cycle (e.g., the cycle of generating the data voltage). For example, when the first gamma buffer AMP_G1 and the tenth gamma buffer AMP_G10 are kept in the on state in the second cycle to prevent the change in the maximum gamma voltage and the minimum gamma voltage, the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G9 are turned off. Thus, the gamma wiring point can be in a floating state (e.g., a state when the voltage of the corresponding point is variable), and each of the gamma voltages can be adjusted by the third resistor string RST3. In this way, the error component of the gamma voltage in the first cycle can be removed.

[0129] Fig. 8A and Figure 8B It is shown Figure 5A waveform diagram of the operation of the gamma voltage generator. Fig. 8A and Figure 8B shows the control referenced above Figure 1 The gamma buffer AMP_G1 to AMP_G10 described above may include a scanning signal SCAN, a horizontal synchronization signal HSYNC, and a gamma buffer control signal CS_AMP. The gamma buffer control signal CS_AMP may include the gamma buffer AMP_G1 to AMP_G10 described above. Figure 3 The gamma enable signal G_EN described above may be included in the gamma enable signal G_EN described above, or may be provided from the controller 310 to the gamma voltage generator 330 together with the gamma enable signal G_EN. Fig. 9 It is shown Figure 5 An exemplary circuit diagram of the operation of a gamma voltage generator. Fig. 9 Shown in Fig. 8A and Figure 8B The operation of the gamma voltage generator 330 in the first period is described in FIG.

[0130] First, refer to Figure 1 , Figure 5 and Fig. 8A , the scan signal SCAN may have an off voltage level (or a logic high level) at the first time point t1. Accordingly, the data signal may not be provided to the pixel PXL.

[0131] The horizontal synchronization signal HSYNC may be changed from the off voltage level to the on voltage level (e.g., a logic low level), and may maintain the on voltage level for a certain period of time. More specifically, the horizontal synchronization signal HSYNC has a first pulse of the on voltage level at a first time point t1, and, for example, the first pulse may have a first pulse width PW1.

[0132] The gamma buffer control signal CS_AMP may have a first value, for example, FULL (or a first state). The gamma buffer control signal CS_AMP may have a first value in response to the horizontal synchronization signal HSYNC of the turn-on voltage level, and for example, as described above with reference to Figure 3 The controller 310 is described to generate the gamma buffer control signal CS_AMP based on the horizontal synchronization signal HSYNC.

[0133] In this case, each of the first to tenth gamma buffers AMP_G1 to AMP_G10 may be turned on or maintain a turned-on state in response to the gamma buffer control signal CS_AMP having the first value. Figure 7 As shown in the third curve CURVE3 (or the fourth curve CURVE4 ) described above, the gamma voltages may be quickly charged to a voltage close to the target gamma voltages, and the gamma voltages may have errors or may exhibit nonlinear characteristics due to the gamma buffers AMP_G1 to AMP_G10 .

[0134] Thereafter, at a second time point t2, the gamma buffer control signal CS_AMP may change from the first value to have a second value, for example, LESS (or a second state). In this case, at least some of the first to tenth gamma buffers AMP_G1 to AMP_G10 may be turned off in response to the gamma buffer control signal CS_AMP having the second value.

[0135] For example, Fig. 9 As shown in FIG. 1 , the second to ninth gamma buffers AMP_G2 to AMP_G9 included in the first group GROUP1 may be turned off. Meanwhile, the first to tenth gamma buffers AMP_G1 and AMP_G10 may maintain a turned-on state.

[0136] In this case, the maximum gamma voltage and the minimum gamma voltage among the gamma voltages are maintained at a fixed voltage level according to the outputs of the first gamma buffer AMP_G1 and the tenth gamma buffer AMP_G10, and the intermediate gamma voltage (e.g., the gamma voltage corresponding to the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G9) may be independent of the outputs of the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G9. Accordingly, the intermediate gamma voltage may be adjusted by the third resistor string RST3, and the error component caused by the offset of the gamma buffers AMP_G1 to AMP_G10 may be removed. In this way, the intermediate gamma voltage may have a linear characteristic.

[0137] At the same time, the scan signal SCAN may have a turn-on voltage level at the second time point t2. For example, the scan signal SCAN may have a pulse having a turn-on voltage level during the second pulse width PW2. The data driver 130 may generate a data signal using a gamma voltage (e.g., a gamma voltage having a linear characteristic at the second time point t2) corresponding to the scan signal SCAN, and the above reference Figure 1 The described pixel PXL may emit light having brightness corresponding to a data signal (more specifically, a data voltage having a more precise voltage level) in response to a scan signal SCAN.

[0138] Meanwhile, the scan signal SCAN, the horizontal synchronization signal HSYNC, and the gamma buffer control signal CS_AMP at the third time point t3 may be substantially the same as the scan signal SCAN, the horizontal synchronization signal HSYNC, and the gamma buffer control signal CS_AMP at the first time point t1. More specifically, the scan signal SCAN, the horizontal synchronization signal HSYNC, and the gamma buffer control signal CS_AMP may have a cycle between the first time point t1 and the third time point t3.

[0139] As reference Fig. 8A and Fig. 9 As described, in the first period P1 in which the scan signal SCAN has an off voltage level (or a period in which the horizontal synchronization signal HSYNC has an on voltage level), each of the gamma buffers AMP_G1 to AMP_G10 may be turned on, and in the second period P2 in which the scan signal SCAN has an on voltage level (or a period in which the horizontal synchronization signal HSYNC has an off voltage level), at least some of the gamma buffers AMP_G1 to AMP_G10 (e.g., the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G9) may be turned off. Accordingly, the gamma voltage may be more easily controlled, and the linear characteristics of the gamma voltage may be ensured.

[0140] Although the reference Fig. 8A It is described that at least some of the gamma buffers AMP_G1 to AMP_G10 are turned off at the second time point t2, wherein the second time point t2 may be a time point when the scan signal SCAN is changed from the off voltage level to the on voltage level, but the inventive concept is not limited thereto. Figure 8B As shown in FIG. 1 , at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned off at a third time point t3, and the third time point t3 may be a time point after the second time point t2, which may be a time point when the scan signal SCAN is changed from the off voltage level to the on voltage level. In this case, even if the data voltage is recorded in the pixel PXL (see Figure 4 ), a delay may also occur, and considering this, the first period P1′ may partially overlap with a period in which the scan signal SCAN has the on voltage.

[0141] As reference FIG. 8A to FIG. 9 As described, in the first period P1 in which the scan signal SCAN has an off voltage level (or a period in which the horizontal synchronization signal HSYNC has an on voltage level), each of the gamma buffers AMP_G1 to AMP_G10 may be turned on, and in the second period P2 in which the scan signal SCAN has an on voltage level (or a period in which the horizontal synchronization signal HSYNC has an off voltage level), at least some of the gamma buffers AMP_G1 to AMP_G10 (e.g., the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G9) may be turned off. Accordingly, the gamma voltage may be more easily controlled, and the linear characteristics of the gamma voltage may be ensured.

[0142] Fig.10 It is shown Figure 5 FIG. 1 is another exemplary circuit diagram of the operation of a gamma voltage generator. Fig.11 It is shown Figure 51. Still another exemplary circuit diagram of the operation of a gamma voltage generator. Fig.10 and Fig.11 It is shown as an example Fig. 8A The operation of the gamma voltage generator 330 in the second period P2 is shown in FIG.

[0143] Reference Fig. 8A and Fig.10 , in the second period P2, the first gamma buffer AMP_G1 and the tenth gamma buffer AMP_G10 corresponding to the maximum gamma voltage and the minimum gamma voltage among the first gamma buffer AMP_G1 to the tenth gamma buffer AMP_G10 may remain in the on state. In addition, the gamma buffer closest to the average value of the maximum gamma voltage and the minimum gamma voltage (or the gamma buffer farthest from the first gamma buffer AMP_G1 and the tenth gamma buffer AMP_G10) may remain in the on state. For example, Fig.10 As shown in , the fifth gamma buffer AMP_G5 and the sixth gamma buffer AMP_G6 may remain in a turned-on state. The average value of the first gamma voltage VG1 and the 2047th gamma voltage VG2047 may be the 1024th gamma voltage, and the 1135th gamma voltage (and / or the 911th gamma voltage) may be closest to the 1024th gamma voltage. Accordingly, the fifth gamma buffer AMP_G5 and the sixth gamma buffer AMP_G6 may remain in a turned-on state. At the same time, the second gamma buffer AMP_G2 to the fourth gamma buffer AMP_G4 included in the second group GROUP2 and the seventh gamma buffer AMP_G7 to the ninth gamma buffer AMP_G9 included in the third group GROUP3 may be turned off.

[0144] Generally, the possibility of a gamma voltage deviating from a target gamma voltage increases as it is farther away from a maximum gamma voltage and a minimum gamma voltage. Accordingly, an intermediate gamma voltage farthest from the maximum gamma voltage and the minimum gamma voltage may be fixed by a gamma buffer.

[0145] although Fig.10 The second to fourth gamma buffers AMP_G2 to AMP_G4 and the seventh to ninth gamma buffers AMP_G7 to AMP_G9 are shown as being turned off, but the inventive concept is not limited thereto. For example, at least one of the third gamma buffer AMP_G3 and the eighth gamma buffer AMP_G8 may maintain a turned-on state.

[0146] Reference Fig. 8A and Fig.11 , in the second period P2, only the gamma buffer corresponding to the specific grayscale area can be turned off. Fig.11As shown in FIG. 1 , the second to fourth gamma buffers AMP_G2 to AMP_G4 included in the second group GROUP2 corresponding to the low grayscale area are turned off, and the first to fifth gamma buffers AMP_G5 to AMP_G10 may maintain a turned-on state.

[0147] More specifically, only the gamma buffer corresponding to the grayscale area having the gamma voltage visually recognized by the user due to distortion due to an offset or the like may be turned off.

[0148] although Fig.11 The second to fourth gamma buffers AMP_G2 to AMP_G4 are shown to be turned off, but the inventive concept is not limited thereto. For example, at least one of the sixth to ninth gamma buffers AMP_G6 to AMP_G9 may be turned on.

[0149] Fig.12 It is shown Figure 3 FIG. 1 is an exemplary waveform diagram of the operation of a data driver. Fig.12 The above reference Figure 1 The vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal D_EN, the source buffer control signal CS_SAP (or the above reference Figure 3 The bias voltage Vbias described above), the source buffer 381 (see Figure 4 ) and the above reference Fig. 8A The gamma buffer control signal CS_AMP is described above. Figure 1 As described above, the vertical synchronization signal VSYNC defines a frame period during which a frame image is displayed, and the horizontal synchronization signal HSYNC defines a horizontal period during which the data driver 130 outputs a data signal. The data enable signal D_EN may define a display period DISP (or an active period ACTIVE for providing an effective data signal) and a threshold period PORCH (or a blank period). The display period DISP may be a period during which an image corresponding to the frame data may be displayed, and the threshold period PORCH may be a period between an end time point and a start time point of the display period DISP.

[0150] Reference Figure 1 , Figure 3 , Figure 4 , Figure 5 and Fig.12 The horizontal synchronization signal HSYNC may be a pulse signal having a periodic logic low level. The cycle of the horizontal synchronization signal HSYNC may be defined as one horizontal time 1H.

[0151] At the first time point t1, the display period DISP may end according to the data enable signal D_EN, and the threshold period PORCH may start. For example, the data enable signal D_EN may have a logic low level in the display period DISP and may have a logic high level in the threshold period PORCH.

[0152] At the second time point t2, the source buffer control signal CS_SAP may change from the first state value FULL SAP to the second state value LESS SAP. When the source buffer control signal CS_SAP has the first state value FULL SAP, the full buffer voltage may be applied to the source buffer 381, and when the source buffer control signal CS_SAP has the second state value LESSSAP, a relatively low bias voltage may be applied to the source buffer 381. That is, the source buffer 381 that boosts the data voltage may not require large power consumption in the threshold period PORCH.

[0153] The source buffer control signal CS_SAP may change based on the data enable signal D_EN. For example, when the value of the data enable signal D_EN changes from a logic low level to a logic high level, the state value of the source buffer control signal CS_SAP may change after one horizontal time 1H.

[0154] The power consumption SAP of the source buffer 381 may be reduced in response to the second state value LESS SAP of the source buffer control signal CS_SAP.

[0155] The gamma buffer control signal CS_AMP may change from a first value FULL to have a second value LESS. As described above with reference to FIG. 8 , when the gamma buffer control signal CS_AMP has a first value FULL, each of the gamma buffers AMP_G1 to AMP_G10 may be turned on or maintained in an on state, and when the gamma buffer control signal CS_AMP has a second value LESS, at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned off. For example, each of the gamma buffers AMP_G1 to AMP_G10 may be turned off.

[0156] Since no valid data signal is generated in the threshold period PORCH, at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned off. Accordingly, power consumption may be reduced.

[0157] At the third time point t3 , the vertical synchronization signal VSYNC may transition from a logic high level to a logic low level.

[0158] Thereafter, at a fourth time point t4, the source buffer control signal CS_SAP may change from the second state value LESS SAP to have the first state value FULL SAP. For example, in response to the vertical synchronization signal VSYNC, the source buffer control signal CS_SAP may change from the second state value LESS SAP to have the first state value FULL SAP.

[0159] The power consumption SAP of the source buffer 381 may increase in response to the first state value FULL SAP of the source buffer control signal CS_SAP.

[0160] In addition, the gamma buffer control signal CS_AMP may be changed from the second value LESS to have the first value FULL. Each of the gamma buffers AMP_G1 to AMP_G10 may be turned on in response to the first value FULL of the gamma buffer control signal CS_AMP.

[0161] That is, at the fourth time point t4 , the gamma buffers AMP_G1 to AMP_G10 and the source buffer 381 may prepare for generation of valid data signals (or generation of gamma voltages for generating data signals) and output.

[0162] Thereafter, at a fifth time point t5, in response to the data enable signal D_EN, the threshold period PORCH may end and the display period DISP may start. More specifically, the source buffer 381 and the gamma buffers AMP_G1 to AMP_G10 may be normally driven before the display period DISP starts (e.g., before one horizontal time 1H), and the charging time of the source buffer 381 and the gamma buffers AMP_G1 to AMP_G10 may be ensured.

[0163] The period in which the source buffer control signal CS_SAP and the gamma buffer control signal CS_AMP have a logic low level has a width smaller than the threshold period PORCH and may be included in the threshold period PORCH. In this way, a margin (e.g., one horizontal time 1H) may be ensured based on the start time point and the end time point of the threshold period PORCH.

[0164] Since the operation of the data driver 130 at the sixth time point t6 is substantially the same as the operation of the data driver 130 at the first time point t1 , a redundant description thereof will not be repeated.

[0165] Fig.12It is shown that the gamma buffer control signal CS_AMP has only the first state value FULL (or logic high level) in the display period DISP, but the inventive concept is not limited thereto. For example, as described above with reference to FIG. 8 , the gamma buffer control signal CS_AMP may change its state within one horizontal time 1H in response to the horizontal synchronization signal HSYNC. In this case, at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned on and off at intervals of one horizontal time 1H in the display period DISP.

[0166] Fig.13 It is shown Figure 3 FIG. 1 is another exemplary waveform diagram of the operation of a data driver. Fig.14 It is shown Figure 3 FIG. 1 is another exemplary waveform diagram of the operation of a data driver of FIG. Fig.13 and Fig.14 Shown with Fig.12 The corresponding signal.

[0167] Reference Fig.13 The operation of the data driver 130 in each of the first time point t1 to the sixth time point t6 is the same as that in the above reference Fig.12 The descriptions are substantially the same, and therefore, a redundant description thereof will not be repeated.

[0168] The data enable signal D_EN may include an active period ACTIVE and a black period BLACK within the display period DISP. For example, when the display device 100 is driven in a low power mode in which an image (such as a clock image) is displayed only in a specific area of ​​the display unit 110, the image data DATA2 (see Figure 1 ) may have a gray value valid only for an image (e.g., a clock image) in a specific area, and may have a black gray value (e.g., a minimum gray value) in the remaining areas. The active period ACTIVE may be a period for displaying an image corresponding to a valid gray value, and the black period BLACK may be a period for displaying only an image corresponding to a black gray value.

[0169] At a fifth time point t5 , the display period DISP starts in response to the data enable signal D_EN, and the black period BLACK may start.

[0170] At the seventh time point t7, the source buffer control signal CS_SAP may change from the first state value FULL SAP to have the second state value LESS SAP. This is because the power consumption requirement of the source buffer 381 that only boosts the black data voltage is relatively low.

[0171] From the time point when the black period BLACK starts, after one horizontal time 1H, the state value of the source buffer control signal CS_SAP may be changed.

[0172] The power consumption SAP of the source buffer 381 may be reduced in response to the second state value LESS SAP of the source buffer control signal CS_SAP.

[0173] The gamma buffer control signal CS_AMP may be changed from the first value FULL to have a second value LESS. Since only a data signal corresponding to black may be generated in the threshold period PORCH, at least some of the gamma buffers AMP_G1 to AMP_G10 may be turned off. For example, each of the gamma buffers AMP_G1 to AMP_G10 may be turned off. As another example, the second gamma buffer AMP_G2 to the tenth gamma buffer AMP_G10 of the gamma buffers AMP_G1 to AMP_G10 may be turned off, and the first gamma buffer AMP_G1 may remain in a turned-on state. Accordingly, power consumption may be reduced.

[0174] In an exemplary embodiment, at the seventh time point t7, the source buffer control signal CS_SAP may have a third state value. When the source buffer control signal CS_SAP has the third state value, only the first gamma buffer AMP_G1 may maintain a turned-on state, and the second gamma buffer AMP_G2 to the ninth gamma buffer AMP_G10 may be turned off. Thus, since only the first gamma voltage GV1 is used to implement black, only the first gamma buffer AMP_G1 corresponding thereto may maintain a turned-on state. Therefore, power consumption may be further reduced.

[0175] Thereafter, at an eighth time point t8, the source buffer control signal CS_SAP may change from the second state value LESS SAP to have the first state value FULL SAP, and the gamma buffer control signal CS_AMP may change from the second value LESS to have the first value FULL. Thereafter, at a ninth time point t9, an active period ACTIVE may start in response to the data enable signal D_EN.

[0176] More specifically, as mentioned above Fig.12 As in the operation of the data driver 130 at the fourth time point t4 and the fifth time point t5 described, at the eighth time point t8 which is one horizontal time 1H earlier than the ninth time point t9 when the effective period ACTIVE starts, the source buffer 381 and the gamma buffers AMP_G1 to AMP_G10 can be driven normally, and the charging time of the source buffer 381 and the gamma buffers AMP_G1 to AMP_G10 can be ensured.

[0177] The operations of the data driver 130 at the tenth time point t10, the eleventh time point t11, and the twelfth time point t12 are substantially the same as or similar to the operations of the data driver 130 at the fifth time point t5, the seventh time point t7, and the eighth time point t8, and therefore, a redundant description thereof will not be repeated.

[0178] although Fig.13 It is shown that the black period BLACK is located between the threshold period PORCH and the active period ACTIVE, however, the inventive concept is not limited thereto.

[0179] For example, Fig.14 As shown in FIG. 1 , the black period BALCK may be included in the display period DISP and may be located between the active period ACTIVE and another active period ACTIVE. The data driver 130 at the thirteenth time point t13, the fourteenth time point t14, the fifteenth time point t15, and the sixteenth time point t16 (see FIG. 14 ) Figure 1 )In operation and refer to above Fig.13 The operations of the data driver 130 at the described fifth time point t5 , seventh time point t7 , eighth time point t8 , and ninth time point t9 are substantially the same, and thus, a redundant description thereof will not be repeated.

[0180] The gamma voltage generating circuit, source driver and display device according to the exemplary embodiment can generate the gamma voltage using the resistor string, quickly change the gamma voltage to the ideal gamma voltage by applying the representative gamma voltage to the junction of the resistor string using the gamma buffer (or gamma amplifier) ​​in the first cycle, and remove the error component caused by the offset of the gamma buffer by turning off (or blocking the output) at least some of the gamma buffers in the second cycle. In this way, the linearity of the gamma voltage can be ensured so that the generated gamma voltage can be the same as the ideal gamma voltage.

[0181] In addition, the source driver and the display device according to the exemplary embodiment can reduce the output of the source buffer (or source amplifier) ​​and turn off at least some of the gamma buffers in the threshold period (e.g., the period between display periods in which an image is displayed) and the black period in the display period (e.g., the period in which only a black image is displayed). Accordingly, power consumption can be reduced.

[0182] Although certain exemplary embodiments and implementations have been described herein, other embodiments and variations will be apparent from this description. Accordingly, it will be apparent to those skilled in the art that the inventive concept is not limited to these embodiments, but to the broader scope of the appended claims and various obvious variations and equivalent arrangements.

Claims

1. A display device, comprising: A display unit, the display unit comprising scan lines, data lines, and pixels connected to the scan lines and the data lines; a gate driver configured to supply a scan signal to the scan line; as well as a source driver configured to supply a data voltage to the data line, Wherein, the source driver comprises: a gamma voltage generator configured to generate gamma voltages having voltage levels different from each other in response to a gamma enable signal; a digital-to-analog converter configured to generate the data voltage corresponding to a grayscale value using the gamma voltage; and a source buffer configured to output the data voltage to the data line, Wherein, the gamma voltage generator comprises: a first resistor string configured to set a voltage range of the gamma voltage; a gamma buffer configured to output a voltage selected from among the divided voltages within a voltage range; and a second resistor string including contacts respectively connected to output terminals of the gamma buffer, the second resistor string being configured to divide a voltage between the contacts to generate the gamma voltage, Wherein, one horizontal time includes a first period and a second period after the first period, wherein a first group of the gamma buffers is configured to be turned on in both the first period and the second period, wherein the second group of gamma buffers is configured to be turned on in the first cycle and turned off in the second cycle, and The second group of the gamma buffers is repeatedly turned on and off with a cycle of the one horizontal time.

2. The display device according to claim 1, wherein: The gamma voltage generator includes a digital gamma voltage generator.

3. The display device according to claim 1, wherein: The gamma voltage generator further comprises: a first buffer configured to apply a maximum gamma voltage to one terminal of the first resistor string; and a second buffer configured to apply a minimum gamma voltage to another terminal of the first resistor string, and The minimum gamma voltage of the second buffer is changed according to the display brightness of the display unit.

4. The display device according to claim 1, wherein: The gamma voltage is non-linear in the first period and is linear in the second period.

5. The display device according to claim 4, wherein: The source driver is configured to supply the data voltage to the data line at intervals of the one horizontal time.

6. The display device according to claim 1, wherein: The first gamma buffer of the gamma buffer connected to the uppermost node of the second resistor string remains turned on during the second period, and The second gamma buffer in the gamma buffer connected to the lowest connection point of the second resistor string maintains the on state in the second period.

7. The display device according to claim 6, wherein: A third gamma buffer of the gamma buffers, which is farthest from the first gamma buffer and the second gamma buffer, maintains a turned-on state in the second period.

8. The display device according to claim 1, wherein: The frame period includes a display period for displaying an image and a threshold period between the display period and another display period. The display period includes the first period and the second period. wherein the source buffer is turned off in the threshold period and turned on in the display period, and At least some of the gamma buffers are turned off during the threshold period and turned on during the display period.

9. The display device according to claim 8, wherein: At least some of the gamma buffers are turned off after a time point at which the threshold period starts, and are turned on before a time point at which the threshold period ends.

10. The display device according to claim 8, wherein: The display period includes a black period for providing a black data voltage corresponding to black and an effective period different from the black period, wherein the source buffer is turned off in the black period and turned on in the effective period, and At least some of the gamma buffers are turned off during the black period and turned on during the active period.

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