MBUS master node circuit with strong anti-interference capability

Abstract

This invention relates to an MBUS master node circuit with strong anti-interference capabilities, comprising: a receiving control module, an overload detection module, an interface protection module, a current-to-voltage conversion and shifting module, and an identification and output module. The overload detection module monitors the current signal and sends an overload indication signal to the host computer when the current exceeds a set threshold. The host computer then cuts off the output of the current signal through the receiving control module. The current-to-voltage conversion and shifting module converts the modulated current signal into a voltage signal, adjusts its amplitude, and outputs it to the identification and output module. The identification and output module identifies the amplitude-adjusted voltage signal and outputs the corresponding current modulation signal to the host computer. This invention employs a voltage shifting + voltage sampling and holding + comparator scheme to achieve I-V conversion of the MBUS bus current signal and differential identification and output of the useful signal, improving anti-interference capabilities and solving the problem of incorrect identification of the useful signal due to interference signals introduced in EFT or similar EFT environments.

Description

Technical Field

[0001] The present invention relates to the technical field of positioning methods, and in particular to an MBUS master node circuit with strong anti-interference capability. Background Art

[0002] The existing MBUS master node circuit adopts a two-stage operational amplifier circuit to sample and amplify the current signal, which has the following disadvantages:

[0003] 1. Poor anti-interference ability: Under EFT conditions, the interference signal is amplified by the operational amplifier circuit, causing the normal signal to be interfered with and unable to communicate.

[0004] 2. Lack of MBUS bus interface protection function: When the field bus is mistakenly connected to a voltage within ±60VDC, the existing MBUS master node circuit does not have an interface protection function, and the external voltage will damage the MBUS master node circuit chip. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides an MBUS master node circuit with strong anti-interference capability, which improves the anti-interference capability and solves the problem of the introduction of interference signals in EFT or similar EFT environments and the inability to correctly identify useful signals.

[0006] To achieve the above object, the present invention provides an MBUS master node circuit with strong anti-interference capability, comprising: a receiving control module, an overload detection module, an interface protection module, a current and voltage conversion and translation module, and an identification and output module;

[0007] The receiving control module receives a bus signal sent by the host computer, and outputs a bus current signal corresponding to the bus signal and conforming to the MBUS bus standard;

[0008] The overload detection module monitors the bus current signal, and when it exceeds a set threshold, sends an overload indication signal to the host computer, and the host computer cuts off the output of the bus current signal through the receiving control module;

[0009] Interface protection module, when the voltage at the external bus access terminal is higher than the normal value, stabilizes the voltage value accessed through the interface protection module;

[0010] The current-voltage conversion and translation module converts the modulated current signal emitted by the MUS device into a voltage signal, and outputs it to the identification and output module after adjusting the amplitude;

[0011] The identification and output module performs differential processing on the voltage signal after the amplitude adjustment, and identifies it through a comparator, and outputs a logic voltage signal that can be identified by a host computer.

[0012] Furthermore, the identification and output module includes a filtering unit, a voltage sampling and holding unit and a first comparator;

[0013] The filtering unit performs low-pass filtering on the amplitude-adjusted voltage signal and outputs it to the positive input terminal of the first comparator; the voltage sampling and holding unit smoothes the amplitude-adjusted voltage signal through RC charging and discharging, and keeps the voltage value within a certain range, and finally forms a stable voltage output to the negative input terminal of the first comparator; the first comparator finally converts the modulated current signal into a voltage signal and outputs it to the host computer.

[0014] Furthermore, the voltage sampling and holding unit includes a diode V9, a resistor R124, a resistor R125 connected in series, and a capacitor C59 connected in parallel with the resistor R125; the common end of the resistor R124 and the resistor R125 is connected to the negative input end of the first comparator; when the voltage signal after the amplitude adjustment is at a high level, the resistor R124 and the capacitor C59 form a charging circuit to charge the capacitor C59; when the voltage signal after the amplitude adjustment is at a low level, the resistor R125 and the capacitor C59 form a discharging circuit, and the capacitor C59 discharges.

[0015] Furthermore, the current-voltage conversion and translation module includes a resistor R111, a diode D13, a diode D16 and a resistor R126 connected in series in sequence; one end of the resistor R111 is connected to the output end of the bus voltage signal, and the other end is connected to the cathode of the diode D13, the anode of the diode D13 is connected to the cathode of the diode D16, and the anode of the diode D16 is grounded via the resistor R126.

[0016] Furthermore, the overload detection module collects the voltage across the resistor R111 and inputs it into the two input terminals of the second comparator. When the voltage difference between the two input terminals of the second comparator is higher than the set threshold, it indicates that the load current signal is out of tolerance, and the second comparator sends an overload indication signal to the host computer.

[0017] Furthermore, the interface protection module includes a thermistor RT3, a diode D21, a diode D24, a resistor R127 and a resistor R237; one end of the thermistor RT3 is connected to the external bus access end, and the other end is connected to the cathode of the diode D21, the anode of the diode D21 is connected to the other end of the resistor R111, the resistor R127 and the resistor R237 are connected in series between the anode of the diode D21 and the ground, the anode of the diode D21 is connected to the cathode of the diode D24, and the anode of the diode D24 is grounded; when the voltage at the external bus access end is higher than the normal value, the resistance of the thermistor RT3 increases and the voltage at both ends increases.

[0018] Furthermore, the receiving control module includes a switch tube V8. After the second comparator sends an overload indication signal to the host computer, the host computer turns off the switch tube V8 to cut off the connection between the MBUS main node circuit and the load.

[0019] The above technical solution of the present invention has the following beneficial technical effects:

[0020] (1) The present invention adopts a voltage migration + voltage sampling and holding + comparator solution to realize the IV conversion of the MBUS bus current signal and the differential identification output of the useful signal, thereby improving the anti-interference ability and solving the problem of the introduction of interference signals in EFT or similar EFT environments and the inability to correctly identify useful signals.

[0021] (2) The present invention adopts a dual diode + thermistor solution, which realizes that when the bus is mistakenly connected to a DC voltage, the external voltage is limited to a loop outside the bus through a diode or a thermistor, ensuring that the MBUS master node circuit is not damaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is the block diagram of the MBUS master node

[0023] Figure 2 This is the schematic diagram of the MBUS master node circuit. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0025] The present invention provides an MBUS master node circuit with strong anti-interference capability, combined with Figure 1-2 , including a receiving control module, an overload detection module, a current-voltage conversion, a translation module, an identification and output module, and an interface protection module;

[0026] (1) The receiving control module receives a bus signal sent by a host computer and outputs a bus current signal corresponding to the bus signal and conforming to the MBUS bus standard; Figure 1 The basic MBUS bus, voltage signal transmission and bus disconnection control circuit is composed of +36V power supply, +24V power supply, diode D20, resistor R109, resistor R110, resistor R108, transistor Q15, switch tube V6, and switch tube V8. The host computer controls the output bus voltage signal through switch tube V8. The receiving control module is used to build a hardware channel that complies with the MBUS bus specification.

[0027] (2) The overload detection module monitors the load current signal and sends an overload indication signal to the host computer when it exceeds the set threshold. The host computer cuts off the output of the bus current signal through the receiving control module and executes the MBUS bus disconnection command of the MCU. The bus voltage signal is connected to the load through the resistor R111, the diode D21, and the thermistor RT3 to form a bus current.

[0028] The resistor R111, the resistor R112, the resistor R114, the resistor R113, the resistor R115, the second comparator in U13 and the switch tube V8 constitute an MBUS bus overload detection module.

[0029] The overload detection module collects the voltage across the resistor R111, and after voltage division adjustment, inputs it to the two input terminals of the second comparator. When the voltage difference between the two input terminals of the second comparator is higher than the set threshold, it indicates that the bus current signal is out of tolerance, and the second comparator sends an overload indication signal to the host computer.

[0030] The load current value on the bus is converted into a differential voltage signal through the sampling resistor R111. This differential voltage signal is sent to the input of the comparator. According to the threshold set by R112-R115 and the comparator parameters, the bus load current is determined to be greater than a certain mA, and the comparator sends an overload indication signal. After receiving the overload indication signal, the MCU disconnects V8 and cuts off the bus loop to avoid other problems caused by excessive bus load.

[0031] (3) The current-voltage conversion and translation module converts the modulated current signal emitted from the MUS device into a voltage signal, and transmits it to the identification and output module after adjusting the amplitude; it includes a resistor R111, a diode D13, a diode D16 and a resistor R126 connected in series in sequence; the other end of the resistor R111 is connected to the modulated current signal emitted from the MUS device, and is connected to the +36V power supply through the switch tubes V6 and V8, the other end of the resistor R111 is connected to the cathode of the diode D13, the anode of the diode D13 is connected to the cathode of the diode D16, and the anode of the diode D16 is grounded through the resistor R126.

[0032] The modulated current signal emitted from the MUS device is transmitted through the thermistor RT3, the diode D21, the resistor R111 and the switch tube V8. R123, C58, V9, R124, R125, C57, C59, D13, D16, R126, R111 and the comparator chip U13 constitute the current modulation receiving circuit of the main M-BUS node.

[0033] The modulated current signal sent by the MBUS slave node on the bus is converted into a voltage signal of corresponding amplitude through IV conversion, and this IV conversion circuit has a relatively high inhibitory effect on the voltage noise signal on the bus; this voltage signal is then passed through the voltage shift circuit composed of D13, D16, and R126 to further amplify the amplitude of the changing voltage signal and shift the voltage signal from near the bus voltage to within the range required by the input end of the subsequent comparator.

[0034] (4) The identification and output module includes a filtering unit, a voltage sampling and holding unit, and a first comparator;

[0035] The filtering unit performs low-pass filtering on the voltage signal after amplitude adjustment and outputs it to the positive input terminal of the first comparator; the resistor R123 and the capacitor C58 are connected in series to form a low-pass filtering unit, and the common terminal of the two is output to the positive electrode of the first comparator.

[0036] The voltage sampling and holding unit smoothes the amplitude-adjusted voltage signal through RC charging and discharging, and keeps the voltage value within a certain range, and finally forms a stable voltage output to the negative input terminal of the first comparator; the first comparator finally converts the current signal into a voltage signal and outputs it to the host computer.

[0037] The voltage sampling and holding unit includes a diode V9, a resistor R124, a resistor R125 connected in series, and a capacitor C59 connected in parallel with the resistor R125; the common end of the resistor R124 and the resistor R125 is connected to the negative input end of the first comparator; when the voltage signal after the amplitude adjustment is at a high level, the resistor R124 and the capacitor C59 form a charging circuit to charge the capacitor C59; when the voltage signal after the amplitude adjustment is at a low level, the resistor R125 and the capacitor C59 form a discharging circuit, and the capacitor C59 discharges.

[0038] After the current modulation signal from the node M-BUS undergoes IV conversion (bus series resistance and voltage shift of the Zener diode), a small-amplitude fluctuating voltage is superimposed on the DC voltage; when the fluctuating voltage rises and remains at a certain amplitude, it is equivalent to charging C59 through the diode V9 and R124. The voltage at the IN1- terminal corresponding to this charging process rises according to the RC charging characteristics; when the voltage drops, the corresponding diode is reverse biased, and C59 discharges through R125. The voltage at the IN1- terminal corresponding to this discharge process follows the RC discharge characteristics; due to the large difference in the RC constants corresponding to the charging and discharging processes, the charging energy is much greater than the discharging energy, which is reflected at the IN1- terminal as a small voltage fluctuation; compared with the IN1+ terminal, the voltage can be approximately considered to be unchanged, thereby providing good physical conditions for the differential input voltage comparison of the comparator.

[0039] (5) Interface protection module, which is used to ensure that when the bus interface is mistakenly connected to a voltage within ±60VDC, the relevant protection devices will be activated and no damage will be caused to the internal MBUS master node circuit.

[0040] The diode D21, the diode D24, the resistor R127, the resistor R237, and the thermistor RT3 constitute an interface protection circuit of the MBUS master node circuit.

[0041] In the case that the MBUS bus is mistakenly connected to a voltage within ±60VDC, if MBUS1+ is connected to the positive pole and GND485 is connected to the negative pole, the external voltage will pass through the RT3, R137, R127 circuit due to the protection of diode D21 and the current limiting effect of RT3, R137, R127, forming a very small current, which will not damage other circuits inside D21.

[0042] If MBUS1+ is connected to the negative pole and GND485 is connected to the positive pole, the external voltage forms a loop through D24 and RT3, and RT3 will quickly protect the device so that most of the external voltage falls on RT3, thereby playing a protective role.

[0043] In summary, the present invention relates to an MBUS main node circuit with strong anti-interference ability, including: a receiving control module, an overload detection module, an interface protection module, a current voltage conversion and translation module, and an identification and output module; the overload detection module monitors the current signal, and when it exceeds the set threshold, it sends an overload indication signal to the host computer, and the host computer cuts off the output of the current signal through the receiving control module; the current voltage conversion and translation module converts the modulated current signal into a voltage signal, adjusts the amplitude and outputs it to the identification and output module; the identification and output module identifies the voltage signal after the amplitude adjustment, and outputs the corresponding current modulation signal to the host computer. The present invention adopts the scheme of voltage migration + voltage sampling and holding + comparator to realize the IV conversion of the MBUS bus current signal and the differential identification and output of the useful signal, improves the anti-interference ability, and solves the problem of introducing interference signals in EFT or similar EFT environments and failing to correctly identify useful signals.

[0044] It should be understood that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. An MBUS master node circuit with strong anti-interference capability, characterized in that: include: Receiving control module, overload detection module, interface protection module, current and voltage conversion and translation module and identification and output module; The receiving control module receives the bus signal sent by the host computer, and outputs a bus voltage signal corresponding to the bus signal and conforming to the MBUS bus standard; The overload detection module monitors the load current signal, and sends an overload indication signal to the upper computer when the load current exceeds the set threshold. The upper computer cuts off the output of the bus current signal through the receiving control module and executes the MBUS bus disconnection command of the MCU; Interface protection module, when the voltage at the external bus access terminal is higher than the normal value, stabilizes the voltage value accessed through the interface protection module; The current-voltage conversion and translation module converts the modulated current signal emitted by the MUS device into a voltage signal, and transmits it to the identification and output module after adjusting the amplitude; The identification and output module performs differential processing on the voltage signal after the amplitude adjustment, identifies it through a comparator, and outputs a logic voltage signal that can be identified by the host computer; The identification and output module includes a filtering unit, a voltage sampling and holding unit and a first comparator; The filtering unit performs low-pass filtering on the voltage signal after amplitude adjustment and outputs it to the positive input terminal of the first comparator; the voltage sampling and holding unit performs smoothing processing on the voltage signal after amplitude adjustment through RC charging and discharging, and keeps the voltage value within a certain range, and finally forms a stable voltage and outputs it to the negative input terminal of the first comparator; the first comparator finally converts the modulated current signal into a voltage signal and outputs it to the host computer; The voltage sampling and holding unit includes a diode V9, a resistor R124, a resistor R125 connected in series, and a capacitor C59 connected in parallel with the resistor R125, and a common end of the resistor R124 and the resistor R125 is connected to the negative input end of the first comparator; when the voltage signal after the amplitude adjustment is at a high level, the resistor R124 and the capacitor C59 form a charging circuit to charge the capacitor C59; when the voltage signal after the amplitude adjustment is at a low level, the resistor R125 and the capacitor C59 form a discharging circuit, and the capacitor C59 discharges; The current-voltage conversion and translation module includes a resistor R111, a diode D13, a diode D16 and a resistor R126 connected in series in sequence, one end of the resistor R111 is connected to the output end of the bus voltage signal, and the other end is connected to the cathode of the diode D13, the anode of the diode D13 is connected to the cathode of the diode D16, and the anode of the diode D16 is grounded via the resistor R126; The interface protection module includes a thermistor RT3, a diode D21, a diode D24, a resistor R127 and a resistor R237. The thermistor RT3, the diode D21, the diode D24, the resistor R127 and the resistor R237 constitute an interface protection circuit of the MBUS master node circuit. One end of the thermistor RT3 is connected to the external bus access end, and the other end is connected to the cathode of the diode D21. The anode of the diode D21 is connected to the other end of the resistor R111. The resistor R127 and the resistor R237 are connected in series between the anode of the diode D21 and the ground. The anode of the diode D21 is connected to the cathode of the diode D24, and the anode of the diode D24 is grounded.

2. The MBUS master node circuit with strong anti-interference capability according to claim 1, characterized in that: The overload detection module collects the voltage across the resistor R111 and inputs it into the two input terminals of the second comparator. When the voltage difference between the two input terminals of the second comparator is higher than the set threshold, it indicates that the load current signal is out of tolerance, and the second comparator sends an overload indication signal to the host computer.

3. The MBUS master node circuit with strong anti-interference capability according to claim 1, characterized in that: When the voltage at the external bus access terminal is higher than the normal value, the resistance of thermistor RT3 increases and the voltage at both ends increases.

4. The MBUS master node circuit with strong anti-interference capability according to claim 1, characterized in that: The receiving control module includes a switch tube V8. After the second comparator sends an overload indication signal to the host computer, the host computer turns off the switch tube V8 to cut off the connection between the MBUS main node circuit and the load.

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