Memory management methods and related products

Abstract

The embodiment of the present application discloses a memory management method and related products, the method comprising: a first processing device allocates a first cache block of a cache pool to a first task; the first processing device allocates a second cache block of the cache pool to the second task when it is determined that the second processing device needs to execute the second task and the first task in sequence, wherein at least a portion of the second cache block is included in the first cache block. In the embodiment of the present application, when the first processing device determines that the second processing device needs to execute the second task and the first task in sequence, the first task and the second task can reuse a portion of the cache block; memory utilization can be improved.

Description

Technical Field

[0001] The present application relates to the computer field, and in particular to a memory management method and related products. Background Art

[0002] In a heterogeneous acceleration system consisting of a central processing unit (CPU) and an acceleration device, the memory management strategy on the acceleration device will greatly affect the performance and efficiency of the entire system. Acceleration devices refer to devices other than CPUs that are used to accelerate computing, such as graphics processing units (GPUs), neural-network processing units (NPUs), and field-programmable gate arrays (FPGAs). Since the memory utilization rate of the current memory management strategy is low, it is necessary to study a memory management strategy with higher memory utilization rate. Summary of the invention

[0003] The embodiments of the present application disclose a memory management method and related products.

[0004] In a first aspect, an embodiment of the present application provides a memory management method, the method comprising: a first processing device allocates a first cache block of a cache pool to a first task; when the first processing device determines that a second processing device needs to execute a second task and the first task in sequence, the first processing device allocates a second cache block of the cache pool to the second task, wherein at least a portion of the second cache block is included in the first cache block.

[0005] The situation where the first processing device determines that the second processing device needs to execute the second task and the first task in sequence means that the first processing device determines that the second processing device will not execute the first task and the second task in parallel. In other words, the second processing device will not execute the first task and the second task at the same time. It should be understood that in the case where the second processing device executes the second task and the first task in sequence, it is impossible for the second processing device to occupy the same cache block at the same time when executing the first task and the second task. Therefore, the first processing device can allocate the first cache block of the cache pool to the first task, and can allocate the second cache block to the second task, that is, the first task and the second task can reuse a part of the cache block.

[0006] In an embodiment of the present application, when the first processing device determines that the second processing device needs to execute the second task and the first task in sequence, the first task and the second task can reuse a portion of the cache blocks, thereby improving memory utilization.

[0007] In a possible implementation, after the first processing device allocates a first cache block in a cache pool for a first task, the method further includes: in response to sending the first task to the second processing device, the first processing device puts the first cache block back into the cache pool.

[0008] The first processing device sending the first task to the second processing device may be that the first processing device calls the second processing device to execute the first task, or the first task is submitted to a task queue processed by the second processing device. After sending the first task to the second processing device, the first processing device may immediately put the first cache block back into the cache pool.

[0009] In this implementation, the first processing device may put the first cache block back into the cache pool in a timely manner to facilitate reuse of the first cache pool.

[0010] In one possible implementation, after the first processing device allocates a first cache block of a cache pool to a first task, the method further includes: the first processing device records a first operation queue in which the first task corresponding to the first cache block is located; and determining that the second processing device needs to execute the second task and the first task in sequence includes: the first processing device determines that the first task and the second task are located in the same operation queue based on the first operation queue in which the first task is recorded.

[0011] Optionally, in response to sending the first task to the second processing device, the first processing device records the first operation queue in which the first task corresponding to the first cache block is located. Optionally, the operation of the first processing device putting the first cache block back into the cache pool and the operation of recording the first operation queue in which the first task corresponding to the first cache block is located can be considered to be executed simultaneously. That is, the operation of the first processing device putting the first cache block back into the cache pool and the operation of recording the first operation queue in which the first task corresponding to the first cache block is located can be bound together. Before allocating a cache block to the second task, the first processing device knows the operation queue in which the second task is located. Therefore, based on the record of the first operation queue in which the first task is located, the first processing device can determine whether the operation queues in which the first task and the second task are located are the same.

[0012] In this implementation, the first processing device can accurately and quickly determine that the first task and the second task are located in the same operation queue based on the first operation queue in which the first task is recorded.

[0013] In a possible implementation, allocating the second cache block of the cache pool to the second task includes: the first processing device allocating the second cache block of the cache pool to the second task during the process in which the second processing device executes the first task.

[0014] In this implementation, the first processing device and the second processing device work in parallel, with high working efficiency.

[0015] In a possible implementation, before allocating the second cache block of the cache pool to the second task, the method further includes: the first processing device searches the cache pool for at least one candidate cache block to which a task is currently allocated; when the first processing device determines that the second processing device needs to execute the second task and the first task in sequence, the second cache block of the cache pool to the second task is allocated, including: the first processing device allocates the second cache block determined from the at least one candidate cache block to the second task based on the execution order relationship between the task currently allocated to the at least one candidate cache block and the second task.

[0016] In this implementation, the first processing device allocates a second cache block determined from at least one candidate cache block to the second task based on the execution order relationship between the task to which at least one candidate cache block is currently allocated and the second task; so that the second task can reuse the allocated cache block, thereby improving memory utilization.

[0017] In a possible implementation, the first processing device searches for at least one candidate cache block currently assigned with a task from the cache pool, including: the first processing device searches for multiple candidate cache blocks that meet the cache size required by the second task from the cache pool; the first processing device searches for at least one candidate cache block currently assigned with a task from the multiple candidate cache blocks. The multiple candidate cache blocks may all be cache blocks currently assigned with a task; or may include both cache blocks currently assigned with a task and cache blocks currently not assigned with a task.

[0018] In this implementation, at least one candidate cache block currently assigned with a task is preferentially searched from multiple candidate cache blocks, so that at least one candidate cache block currently assigned with a task and meeting the cache size required by the second task can be quickly found.

[0019] In a possible implementation, the first processing device searches for at least one candidate cache block currently assigned with a task from the cache pool, including: the first processing device searches for the plurality of candidate cache blocks that meet the cache size required by the second task from the cache blocks currently assigned with a task in the cache pool. It should be understood that each candidate cache block is a cache block currently assigned with a task.

[0020] In this implementation, the first processing device directly searches for a cache block that meets the cache size required by the second task from the cache blocks currently assigned to the task in the cache pool, and then reassigns the cache block currently assigned to the task to the second task; thus improving memory utilization.

[0021] In a possible implementation, the first processing device allocates the second cache block determined from the at least one candidate cache block to the second task based on the execution order relationship between the task currently assigned to the at least one candidate cache block and the second task, including: the first processing device allocates the second cache block determined from the at least one candidate cache block to the second task based on the execution order relationship between the task currently assigned to the at least one candidate cache block and the second task and the size of the at least one candidate cache block.

[0022] The first processing device allocates the second cache block determined from the at least one candidate cache block to the second task based on the execution order relationship between the task currently assigned to the at least one candidate cache block and the second task and the size of the at least one candidate cache block. This may be: when the first processing device determines that the task currently assigned to the at least one candidate cache block and the second task are executed in sequence, the second cache block determined from the at least one candidate cache block is allocated to the second task based on the size of the at least one candidate cache block.

[0023] In this implementation, the second cache block determined from at least one candidate cache block currently assigned with a task is allocated to the second task, so that the cache block currently assigned with a task can be reused, thereby improving the memory reuse rate.

[0024] In one possible implementation, the method further includes: when the first processing device determines that the at least one candidate cache block does not include a cache block that meets the requirements of the second task, determining a target cache block to be assigned to the second task from at least one cache block included in the cache pool that is not currently assigned a task.

[0025] In this implementation, the target cache block allocated to the second task is determined from at least one cache block currently not allocated to a task and included in the cache pool, so that the second task can be successfully executed.

[0026] In a possible implementation, the method further includes: if the first processing device fails to find a cache block in the cache pool that meets the requirements of the second task, expanding the cache pool; and the first processing device searches for a target cache block assigned to the second task from the expanded cache pool.

[0027] In this implementation, the cache block that meets the requirement of the second task is searched from the expanded cache pool, so that the cache block that meets the requirement can be quickly allocated to the second task.

[0028] In a second aspect, an embodiment of the present application provides a data processing device, which includes: a memory allocation unit, used to allocate a first cache block of a cache pool to a first task; a processing unit, used to determine a situation where a second processing device needs to execute a second task and the first task in sequence; the memory allocation unit is also used to allocate a second cache block of the cache pool to the second task when the processing unit determines that the second processing device needs to execute the second task and the first task in sequence, wherein at least a portion of the second cache block is included in the first cache block.

[0029] The processing unit and the memory allocation unit can be the same unit or two independent units. In some possible implementations, the processing unit is a processor, such as a CPU, and the memory allocation unit is a hardware. In some possible implementations, the processing unit is a processor, such as a CPU, and the function of the memory allocation unit is implemented by software or a program run by the processor. In other words, the function of the processing unit and the function of the memory allocation unit are both implemented by the processor.

[0030] In a possible implementation, the processing unit is further configured to send the first task to the second processing device; and the memory allocation unit is further configured to put the first cache block back into the cache pool in response to sending the first task to the second processing device.

[0031] In one possible implementation, the processing unit is also used to record the first operation queue in which the first task corresponding to the first cache block is located; the processing unit is specifically used to determine that the operation queues in which the first task and the second task are located are the same based on the record of the first operation queue in which the first task is located.

[0032] In a possible implementation, the memory allocation unit is further configured to allocate the second cache block of the cache pool to the second task during the process of the second processing device executing the first task.

[0033] In one possible implementation, the memory allocation unit is further used to search from the cache pool for at least one candidate cache block to which a task is currently assigned; the memory allocation unit is specifically used to allocate the second cache block determined from the at least one candidate cache block to the second task when the processing unit determines that the second processing device needs to execute the second task and the first task in sequence based on the execution order relationship between the task currently assigned to the at least one candidate cache block and the second task.

[0034] In a possible implementation, the memory allocation unit is specifically configured to search for the multiple candidate cache blocks that meet the cache size required by the second task from the cache blocks in the cache pool that are currently allocated with tasks.

[0035] In a possible implementation, the memory allocation unit is specifically configured to search the cache pool for multiple candidate cache blocks that meet the cache size required by the second task; and search the multiple candidate cache blocks for at least one candidate cache block that is currently assigned a task.

[0036] In one possible implementation, the memory allocation unit is specifically used to allocate the second cache block determined from the at least one candidate cache block to the second task based on the size of the at least one candidate cache block, when the processing unit determines that the second processing device needs to execute the second task and the first task in sequence based on the execution order relationship between the task currently allocated by the at least one candidate cache block and the second task.

[0037] In one possible implementation, the memory processing unit is further used to determine a target cache block to be assigned to the second task from at least one cache block included in the cache pool that is not currently assigned a task, when the processing unit determines that the at least one candidate cache block does not include a cache block that meets the requirements of the second task.

[0038] In a possible implementation, the memory processing unit is further configured to expand the cache pool if no cache block meeting the requirements of the second task is found in the cache pool; and search for a target cache block allocated to the second task from the expanded cache pool.

[0039] Regarding the technical effects brought about by the second aspect or various possible implementation methods, reference may be made to the introduction to the technical effects of the first aspect or corresponding implementation methods.

[0040] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory and a first processor, wherein the memory is used to store instructions, and the first processor is used to execute the instructions stored in the memory, so that the first processor executes the method as in the first aspect and any possible implementation method.

[0041] In a possible implementation, the electronic device further includes a second processor, and the second processor is used to execute the task sent by the first processor using the cache block allocated by the first processor. Exemplarily, the first processor is a CPU, and the second processor is a GPU.

[0042] In a fourth aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: a first processing device, a memory, and a second processing device, wherein the memory is used to store instructions and data, the first processor is used to execute the instructions stored in the memory, so that the first processor performs the method of the first aspect and any possible implementation, and the second processing device is used to use the cache block allocated by the first processing device to execute the task sent by the first processor. Exemplarily, the first processing device is a CPU and the second processing device is a GPU.

[0043] In a fifth aspect, an embodiment of the present application provides a chip, comprising a data interface and the first processing device described in the first aspect, wherein the first processing device is used to execute the method in the first aspect or any possible implementation of the first aspect.

[0044] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program, and the computer program includes program instructions, which, when executed by a processor, enable the processor to execute the method of the first aspect and any optional implementation method.

[0045] In a seventh aspect, an embodiment of the present application provides a computer program product, which includes program instructions, and when the program instructions are executed by a processor, the processor executes the method of the first aspect and any optional implementation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0047] Figure 1 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0048] Figure 2 A flow chart of a memory management method provided in an embodiment of the present application;

[0049] Figure 3 A flowchart of another memory management method provided in an embodiment of the present application;

[0050] Figure 4 A flowchart of another memory management method provided in an embodiment of the present application;

[0051] Figure 5 A flowchart of another memory management method provided in an embodiment of the present application;

[0052] Figure 6 A timing diagram of a memory management method provided in an embodiment of the present application;

[0053] Figure 7 A flowchart of another memory management method provided in an embodiment of the present application;

[0054] Figure 8 A timing diagram of another memory management method provided in an embodiment of the present application;

[0055] Fig. 9 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0056] Fig.10 A schematic diagram of the structure of another data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The terms "first", "second", and "third" in the specification embodiments and claims and drawings of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or precedence. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0058] As described in the background technology, the memory utilization of the memory management strategy currently used in the heterogeneous acceleration system is usually low, so it is necessary to study a memory management strategy with higher memory utilization. The embodiment of the present application provides a memory management method with higher memory utilization, which is applicable to a data processing device (corresponding to a heterogeneous acceleration system) having a first processing device (such as a CPU) and a second processing device (corresponding to an acceleration device). The structure of the data processing device to which the memory management method provided in the embodiment of the present application is applicable is first introduced below, so as to more conveniently describe the memory management method provided in the embodiment of the present application.

[0059] Figure 1A schematic diagram of the structure of a data processing device provided in an embodiment of the present application. Figure 1 As shown, the data processing device includes: a first processing device 101, a memory allocator 102, a second processing device 103 and a device memory 104, wherein the first processing device 101 and the memory allocator 102 are independently set or integrated in the same device, the second processing device 103 and the first processing device 101 are different types of processing devices, and the device memory 104 can be a part of the second processing device 103, or be set independently of the second processing device 103, which is not limited in the embodiment of the present disclosure. In some examples, the first processing device 101 corresponds to a processing unit, and the memory allocator 102 corresponds to a memory allocation unit. The first processing device 101 can be a CPU or other types of processors. In some embodiments, the first processing device 101 can be a main processing device, such as a CPU; the second processing device 103 is an acceleration device, such as a GPU. The second processing device 103 can be a processor or processing device different from the first processing device 101, such as a GPU, an NPU, an FPGA, a digital signal processor (DSP), an application specific integrated circuit (ASIC), etc. In some possible implementations, the first processing device is a CPU, and the memory allocation unit is hardware independent of the CPU. In some possible implementations, the first processing device is a CPU, and the function of the memory allocator 102 is implemented by software or a program run by the first processing device. That is, in some possible implementations, the physical hardware corresponding to the memory allocator 102 is the first processing device 101. The device memory 104 can be memory available to the second processing device 103. Exemplarily, the second processing device 103 is a GPU, and the device memory 104 is the video memory of the second processing device 103. In some embodiments, the device memory 104 is a part of the second processing device 103.

[0060] The following describes the functions of the first processing device 101, the memory allocator 102, the second processing device 103, and the device memory 104 when the data processing apparatus implements the memory management method provided in the embodiment of the present application.

[0061] The first processing device (e.g., CPU) 101 is used to submit tasks to the second processing device, and control the memory allocator 102 to allocate and / or release the cache in the cache pool, that is, to manage the device memory 104 of the second processing device 103 through the memory allocator. The first processing device submitting tasks to the second processing device may be that the first processing device adds the task to the operation queue that needs to be processed by the second processing device; it may also be that the task is sent to the second processing device, such as sending an instruction to instruct the second processing device to perform a certain task; it may also be that the task is added to the operation queue that the first processing device needs to call the interface of the second processing device to complete; it may also be other ways to notify the second processing device to perform the task. The first processing device 101 can also be used to call the interface of the second processing device to perform the task. Exemplarily, the operation queue is cudaStream in the compute unified device architecture (CUDA). Tasks on the same cudStream are executed in the order of submission, and tasks on different cudaStreams have no order and can be executed concurrently. Exemplarily, the operation queue is cl_command_queue in the open computing language (OpenComputingLanguag, OpenCL). OpenCL is a framework for writing programs for heterogeneous platforms, which can be composed of CPUs, GPUs, or other types of processors. Exemplarily, the operation queue is accelerator_view in C++AMP. C++AMP is a new extension for Microsoft Visual Studio and C++ programming language to help developers fully adapt to the highly parallel and heterogeneous computing environment of today and the future.

[0062] The memory allocator 102 is responsible for managing the device memory 104. The memory allocator 102 may be a physical hardware. Alternatively, the function of the memory allocator 102 may be implemented by software or a program executed by the first processing device 101.

[0063] The second processing device 103 is used to read and write data through the device memory 104, and execute tasks submitted by the first processing device 101 or complete tasks by calling at least one interface of the first processing device 101. The second processing device 103 can be understood as an acceleration device other than the CPU, such as a GPU, NPU, ASIC, FPGA, etc.

[0064] Device memory 104 refers to a storage device (corresponding to a memory space) on the second processing device, which is used by the second processing device, such as a video memory of a GPU (corresponding to the second processing device).

[0065] In some embodiments, a cache pool is set in the memory allocator 102 for pre-allocating and caching device memory. This cache pool may be a whole block of device memory, or it may be composed of multiple blocks of device memory of arbitrary size. When the second processing device 103 needs to use device memory to perform a task, the memory allocator 102 can directly allocate cache from the cache pool to the second processing device. After the second processing device does not need to use the cache allocated to it, the memory allocator puts the cache back into the cache pool, that is, returns the cache to the cache pool. In some embodiments, the first processing device 101 is a CPU, the second processing device 103 is a GPU, and the device memory 104 is the video memory on the second processing device 103; in a heterogeneous computing system including a CPU and a GPU, the CPU is responsible for the preparation and initiation of tasks (such as computing tasks or image processing tasks, etc.), and the GPU is responsible for the actual execution of tasks. Before the CPU initiates a task, it needs to specify the video memory used by the GPU to execute the task. The allocation and release of the video memory by the CPU is actually completed by the memory allocator. The memory allocator is actually responsible for the management of the video memory on the GPU. When the GPU executes a task, it directly uses part of the video memory allocated by the CPU through the memory allocator.

[0066] Combine the following Figure 2 To describe the operations performed by each component when the data processing device executes the memory management method provided in the embodiment of the present application. Figure 2 A flow chart of a memory management method provided in an embodiment of the present application. Figure 2 As shown, the memory management method includes:

[0067] 201. A first processing device allocates a first cache block in a cache pool to a first task.

[0068] The first processing device may be a CPU or other types of processors. In some embodiments, the first cache block of the cache pool allocated by the first processing device for the first task may be the first cache block of the cache pool allocated by the first processing device 101 for the first task through the memory allocator 102; wherein the function of the memory allocator is implemented by the software or program run by the first processing device. The first task may be an image processing task, a computing task, or a task that needs to be executed by the second processing device (such as a GPU) or a task that needs to be executed by the second processing device. The first cache block may be any cache block in the cache pool. The cache pool may be understood as a pool of cache device memory (such as video memory) provided inside the memory allocator. For example, the video memory managed by the memory allocator is cached in a pool (i.e., the cache pool), and when the second processing device needs video memory, the memory allocator allocates it from the pool, and when the video memory allocated to the second processing device is used up, the video memory is released without waiting for the second processing device to complete the task. In this way, by using the cache pool, device synchronization in the process of device memory allocation and release can be eliminated. Device synchronization can be understood as the first processing device (such as a CPU) stopping the execution of the program and waiting for the second processing device (corresponding to the acceleration device) to complete the task. In some embodiments, the first processing device allocates the first cache block of the cache pool to the first task by: preferentially allocating the cache block that meets the requirements of the first task from the cache pool; if there is no cache block that meets the requirements of the first task in the cache pool, calling cudaMalloc to allocate more memory from the device memory to expand the cache pool. cudaMalloc is an interface for allocating video memory in CUDA.

[0069] In some embodiments, the first task may be a computing task or an image processing task or other types of deep learning tasks. In some embodiments, before executing step 201, the first processing device may perform the following operations: the first processing device may split a larger task to obtain a first task. The data processing device in the embodiment of the present application may be a heterogeneous computing system. The heterogeneous computing system divides code segments of the same type into the same subtask on the basis of extracting the parallelism type of the computing task, and then assigns each subtask to the computing resource (such as the second processing device) that is most suitable for executing it according to different parallelism types to execute it, so as to minimize the total execution time of the computing task. In this way, the first task can be understood as a subtask that needs to be executed by the second processing device or a subtask that calls the second processing device to execute after the first processing device splits a larger task. Alternatively, the first task is the task itself determined by the first processing device to be executed, and the embodiment of the present disclosure does not limit this.

[0070] In some embodiments, after executing step 201, the first processing device may perform the following operations: in response to sending the first task to the second processing device, the first processing device puts the first cache block back into (also referred to as returning) the cache pool. The first processing device sending the first task to the second processing device may be the first processing device adding the task to an operation queue that needs to be processed by the second processing device; it may also be sending an instruction instructing the second processing device to execute a certain task; it may also be adding the task to an operation queue that the first processing device needs to call the interface of the second processing device to complete; it may also be other ways to notify the second processing device to execute the task, which is not limited in the embodiments of the present disclosure.

[0071] In some embodiments, after sending the first task to the second processing device, the first processing device can immediately put the first cache block back into the cache pool without waiting for the second processing device to complete the first task using the first cache block. In the disclosed embodiment, the first processing device can put the first cache block back into the cache pool in a timely manner to facilitate the reuse of the first cache block.

[0072] In some embodiments, the first processing device or the memory allocator may set an identifier for each cache block in the cache pool to indicate the current state of the cache block. As an example, the first processing device assigning the first cache block of the cache pool to the first task may be that the first processing device assigns the first cache block of the cache pool to the first task, and sets the state of the first cache block to unavailable, indicating that the first cache block cannot be assigned to other tasks; putting the first cache block back into (also referred to as returning) the cache pool may be setting the state of the first cache block to available, indicating that the first cache block can be assigned to other tasks. The embodiments of the present disclosure may also indicate whether each cache block is currently available in other ways. For example, the first processing device assigning the first cache block to the first task may refer to removing the first cache block from the cache resources contained in the cache pool, and putting the first cache block back into the cache pool may refer to adding the first cache block back into the cache resources contained in the cache pool.

[0073] 202. When determining that the second processing device needs to execute the second task and the first task in sequence, the first processing device allocates a second cache block of the cache pool to the second task.

[0074] At least a portion of the second cache block is included in the first cache block. The second task may be an image processing task, a computing task, or other task that requires a second processing device (eg, GPU) to execute or a task that requires calling a second processing device to execute.

[0075] The first processing device determines that the second processing device needs to execute the second task and the first task in sequence, which means that the first processing device determines that the second processing device will not execute the first task and the second task in parallel. That is to say, the second processing device will not execute the first task and the second task at the same time. The first task and the second task can be tasks of the same or different types, for example, they can be different subtasks of the same task, or subtasks of different tasks, etc., which are not limited in the embodiments of the present disclosure. It should be understood that when the second processing device executes the second task and the first task in sequence, it is impossible for the second processing device to use the cache block at the same time when executing the first task and the second task. Therefore, when the first processing device determines that the second processing device needs to execute the second task and the first task in sequence, the second cache block can be allocated to the second task, that is, the first task and the second task can reuse a part of the cache block. The implementation method of the first processing device determining that the second processing device needs to execute the second task and the first task in sequence will be described in detail later.

[0076] In some embodiments, memory allocation of the first processing device and task processing of the second processing device can be performed in parallel, thereby improving processing efficiency. For example, the first processing device allocates a second cache block of the cache pool to the second task while the second processing device is executing the first task.

[0077] In an embodiment of the present application, when the first processing device determines that the second processing device needs to execute the second task and the first task in sequence, the first task and the second task can reuse a portion of the cache blocks, thereby improving memory utilization.

[0078] An optional example of determining that the second processing device needs to execute the second task and the first task in sequence is described below.

[0079] After the first cache block is put back into the cache pool or in the process of putting the first cache block back into the cache pool, the first processing device records the first operation queue where the first task corresponding to the first cache block is located; in the process of allocating the cache block to the second task, based on the first operation queue where the first task is recorded, it is determined that the operation queues where the first task and the second task are located are the same. The first operation queue can be an operation queue that needs to be executed by the second processing device or an operation queue where the second task is located. For example, the first processing device submits the task to the first operation queue of the second processing device, and the second processing device executes the tasks in the first operation queue in sequence according to the order in which each task is submitted to the first operation queue. The first operation queue can be an operation queue that the first processing device needs to call the interface of the second processing device to complete. For example, the first processing device adds the task to the operation queue that needs to call the interface of the second processing device to complete, and calls the interface of the second processing device in sequence according to the order in which each task is added to the operation queue to execute each task.

[0080] In some embodiments, the operation of the first processing device re-placing the first cache block into the cache pool and the operation of recording the first operation queue where the first task corresponding to the first cache block is located can be performed simultaneously or in any order. For example, after re-placing the first cache block into the cache pool, the current task allocation information of the first cache block is recorded, and the task allocation information includes information about the operation queue where the first task is located. For another example, the first processing device records the first operation queue where the first task corresponding to the first cache block is located, and then re-placing the first cache block into the cache pool.

[0081] Then, in the process of allocating a cache block for the second task, the first processing device can determine whether the operation queues where the first task and the second task are located are the same, based on the first operation queue where the first task is recorded, for example, by querying the task allocation information of the first cache block, that is, the second task to be allocated belongs to the same operation queue as the first task allocated to the first cache block. In this way, different tasks in the same operation queue are executed in sequence in a specific order, and the first task and the second task are located in the same operation queue, indicating that the first task and the second task will not be executed at the same time.

[0082] Figure 3 Another memory management method flow chart provided in the embodiment of the present application. Figure 2 The description of the same points in the illustrated embodiments will be briefly omitted.

[0083] 301. A first processing device allocates a first cache block in a cache pool to a first task.

[0084] 302. The first processing device puts the first cache block back into the cache pool, and records the first operation queue where the first task corresponding to the first cache block is located.

[0085] In some embodiments, the first processing device may record the operation queues corresponding to the tasks corresponding to each cache block re-placed into the cache pool. That is, the first processing device may record the operation queues corresponding to the cache blocks currently assigned with tasks in the cache pool. The operation queue corresponding to a cache block is the operation queue to which the tasks assigned to the cache block are located.

[0086] In some embodiments, the first processing device may release the first cache block before putting the first cache block back into the cache pool. For example, the cache block in the cache pool is the video memory of the second processing device, and the first processing device releases the first cache block by calling the interface of the memory allocator before putting the first cache block back into the cache pool. The cudaFree interface is an interface for releasing video memory in CUDA. In some embodiments, releasing the first cache block may mean putting the first cache block into the cache pool, but the first cache block cannot be allocated, for example, setting the status of the first cache block to unavailable; putting the first cache block back into the cache pool may mean that the first cache block can be allocated, for example, setting the status of the first cache block to available.

[0087] 303. When the first processing device determines that the first task and the second task are located in the same operation queue based on the first operation queue in which the first task is recorded, the first processing device allocates a second cache block of the cache pool to the second task.

[0088] Step 303 is a possible implementation of step 302. At least a portion of the second cache block is included in the first cache block.

[0089] In some embodiments, before allocating a second cache block of the cache pool to the second task, the first processing device may search the cache pool for at least one candidate cache block currently assigned with a task; one implementation of step 303 is as follows: based on the execution order relationship between the task currently assigned to the at least one candidate cache block and the second task, allocate a second cache block determined from the at least one candidate cache block to the second task.

[0090] The first processing device searches for at least one candidate cache block currently assigned with a task from the cache pool, which may be: the first processing device searches for multiple candidate caches that meet the cache size required by the second task from the cache pool; the first processing device searches for at least one candidate cache block currently assigned with a task from multiple candidate cache blocks. Exemplarily, the first processing device allocates a second cache block determined from at least one candidate cache block to the second task based on the execution order relationship between the task currently assigned to the at least one candidate cache block and the second task, which may be: selecting a candidate cache block that is executed in sequence with the currently assigned task and the second task from at least one candidate cache block, to obtain one or more target cache blocks (corresponding to the first cache block); and allocating the second cache block determined from the one or more target cache blocks to the second task. For example, the first processing device finds 10 candidate cache blocks that meet the cache size required by the second task from the cache pool; selects a candidate cache block that is executed in sequence with the currently assigned task and the second task from the 10 candidate cache blocks, to obtain a target cache block; and allocates the second cache block determined from the target cache block to the second task.

[0091] In the embodiment of the present application, based on the first operation queue where the recorded first task is located, it can be accurately and quickly determined that the operation queues where the first task and the second task are located are the same, and then a second cache block is allocated to the second task; thus, memory utilization can be improved.

[0092] Figure 4 Another memory management method flow chart provided in the embodiment of the present application. Figure 2 The description of the same points in the illustrated embodiments will be briefly omitted.

[0093] 401. A first processing device allocates a first cache block in a cache pool to a first task.

[0094] 402. The first processing device puts the first cache block back into the cache pool, and records the first operation queue where the first task corresponding to the first cache block is located.

[0095] 403. The first processing device searches the cache pool for multiple candidate cache blocks that meet the cache size required by the second task.

[0096] If at least one candidate cache block that meets the cache size required by the second task is found, step 404 is executed; if no candidate cache block that meets the cache size required by the second task is found, step 408 is executed.

[0097] 404. The first processing device searches for at least one candidate cache block currently assigned with a task from among multiple candidate cache blocks.

[0098] If at least one candidate cache block assigned with a task is found, step 405 is executed; if no candidate cache block assigned with a task is found, step 406 is executed.

[0099] 405. The first processing device determines, from at least one candidate cache block, a second cache block to be allocated to the second task based on an execution order relationship between the task currently allocated to the at least one candidate cache block and the second task.

[0100] Exemplarily, a possible implementation of step 405 is as follows: select a candidate cache block that is executed in sequence by the currently assigned task and the second task from at least one candidate cache block to obtain one or more target cache blocks (such as the first cache block mentioned above); determine a second cache block assigned to the second task from the one or more target cache blocks. Step 405 corresponds to Figure 2 Step 202 in .

[0101] Exemplarily, a possible implementation of step 405 is as follows: the first processing device determines the second cache block to be allocated to the second task from at least one candidate cache block based on the execution order relationship between the task currently allocated to at least one candidate cache block and the second task and the size of at least one candidate cache block. For example, a candidate cache block to which the currently allocated task and the second task are executed in sequence is selected from at least one candidate cache block to obtain one or more target cache blocks (such as the first cache block described above); a second cache block that meets the cache size required by the second task is selected from the one or more target cache blocks, and the second cache block is allocated to the second task, where, as an example, if there are multiple target cache blocks that meet the cache size required by the second task, the smallest target cache block can be selected from the target cache blocks that meet the requirements of the second task as the second cache block, but this is not limited in the embodiments of the present disclosure.

[0102] 406. The first processing device determines a third cache block allocated to the second task from at least one cache block included in the cache pool and currently not allocated with a task.

[0103] 407. The first processing device allocates a third cache block to the second task.

[0104] 408. The first processing device expands the cache pool, and searches the expanded cache pool for a fourth cache block allocated to the second task.

[0105] The fourth cache block may be a cache block that meets the cache size required by the second task. For example, if there is no cache block in the cache pool that meets the requirements of the second computing task, the cudaMalloc interface is called to allocate more video memory from the device memory to expand the cache pool. The cudaMalloc interface is an interface for allocating video memory in CUDA.

[0106] 409. The first processing device allocates a fourth cache block to the second task.

[0107] In this way, the cache allocation to the second task is completed. In some embodiments, the method may further include 410.

[0108] 410. The first processing device clears the cache pool.

[0109] In some embodiments, when the first processing device does not need to call the second processing device to execute a task, the cache in the cache pool can be returned to the device memory of the second processing device. For example, the first processing device calls the cudaFree interface to return the video memory in the cache pool to the GPU (i.e., the second processing device), i.e., clearing the cache pool.

[0110] In an embodiment of the present application, the first processing device first determines multiple candidate cache blocks that meet the cache size required by the second task, and then preferentially selects from the multiple candidate cache blocks the cache blocks that are currently assigned tasks and to which the assigned tasks and the second task are executed in sequence; the cache blocks that meet the needs of the second task can be quickly assigned to the second task, and memory utilization can be improved.

[0111] Figure 5 A flowchart of another memory management method provided in an embodiment of the present application.

[0112] 501. A first processing device allocates a first cache block in a cache pool to a first task.

[0113] 502. The first processing device puts the first cache block back into the cache pool, and records the first operation queue where the first task corresponding to the first cache block is located.

[0114] 503. The first processing device searches the cache pool for a candidate cache block that is currently assigned a task and meets the second task requirement.

[0115] If at least one candidate cache block currently assigned with a task and meeting the second task requirement is found, step 504 is executed; if no candidate cache block currently assigned with a task and meeting the second task requirement is found, step 505 is executed.

[0116] 504. The first processing device allocates a second cache block determined from the at least one candidate cache block to the second task based on an execution order relationship between the task currently allocated to the at least one candidate cache block and the second task.

[0117] The at least one candidate cache block is a cache block that is currently assigned a task and meets the second task requirement in the cache pool found in step 503. The implementation of step 504 may be the same as the implementation of step 405.

[0118] 505 : Whether the first processing device searches the cache block in the cache pool for a cache block that is not currently assigned with a task and that meets the requirement of the second task.

[0119] If the first processing device finds a cache block from the cache pool that is not currently assigned a task and meets the second task requirement, execute step 506; if the first processing device does not find a cache block from the cache pool that is not currently assigned a task and meets the second task requirement, execute step 507.

[0120] 506. The first processing device determines a third cache block allocated to the second task from the cache blocks found to be not currently allocated with a task and to meet the requirements of the second task.

[0121] 507 . The first processing device expands the cache pool, and searches the expanded cache pool for a fourth cache block allocated to the second task.

[0122] In the embodiment of the present application, priority is given to searching for a cache block to be allocated to the second task from the cache blocks that are currently assigned tasks and meet the requirements of the second task, which can improve both the search speed and the memory reuse rate.

[0123] Combine the following Figure 6 The timing diagram of the memory management method in Figures 2 to 5 Memory management methods in . Figure 6 A timing diagram of a memory management method provided in an embodiment of the present application, corresponding to Figures 2 to 5 Memory management methods in . Figure 6 As shown, the first processing device sequentially performs the following operations: allocation 1, submitting task 1 (corresponding to the first task), release 1, allocation 2, submitting task 2 (corresponding to the second task) and release 2; the second processing device sequentially performs the following operations: task 1 and task 2. Among them, allocation 1 means that the first processing device allocates the first cache block to task 1, and allocation 2 means that the first processing device allocates the second cache block to task 2; submitting task 1 means that the first processing device submits task 1 to the operation queue of the second processing device, and submitting task 2 means that the first processing device submits task 2 to the operation queue of the second processing device; release 1 means that the first processing device controls the memory allocator to release the first cache block and puts the first cache block back into the cache pool, and release 2 means that the first processing device controls the memory allocator to release the second cache block and puts the second cache block back into the cache pool; task 1 means that the second processing device executes task 1, and task 2 means that the second processing device executes task 2. Figure 6 In the example, the first cache block allocated by the first processing device for executing allocation 1 and the second cache block allocated for executing allocation 2 are the same or overlap. In other words, the second processing device can reuse cache blocks when executing tasks in the same operation queue. It should be understood that in some embodiments, the first cache block used by the second processing device to execute the first computing task and the second cache block used to execute the second computing task are the same. For example, the second processing device is a GPU, and the GPU can reuse the same video memory when executing computing tasks in the same operation queue. Figure 6 As shown, when the first processing device performs the operations of submitting task 1, releasing 1, allocating 2, and submitting task 2, the second processing device simultaneously performs task 1; when the second processing device performs task 2, the first processing device performs the operation of releasing 2. It can be seen that the first processing device does not need to wait for the second processing device to complete task 1 before performing the operations of releasing 1, allocating 2, and submitting task 2. In other words, the first processing device and the second processing device do not need to be synchronized, and an asynchronous computing mode can be implemented to improve computing performance.

[0124] In an embodiment of the present application, the second processing device can reuse the cache according to the order in which tasks are executed, and the first processing device and the second processing device can implement an asynchronous computing mode; both memory utilization and computing efficiency can be improved.

[0125] Figure 7 Another memory management method flow chart provided in the embodiment of the present application. Figure 7 As shown, the method includes:

[0126] 701. A first processing device allocates a fifth cache block in a cache pool to a third task.

[0127] The implementation of step 701 may be similar to the implementation of step 301 .

[0128] 702. The first processing device submits the third task to the operation queue of the second processing device.

[0129] In some embodiments, after the first processing device submits the third task to the operation queue of the second processing device, the fifth buffer block is released immediately.

[0130] 703. The first processing device checks whether the third task is completed.

[0131] If so, execute step 704; if not, execute step 703 again. In some embodiments, the first processing device may periodically (for example, every 5ms, 10ms, etc.) check whether the third task is completed; if it is checked that the third task is completed, the memory allocator is called to put the fifth cache block back into the cache pool; if not, continue to check regularly. In some embodiments, step 703 can be replaced by: before each release of a cache block (for example, the fifth cache block), check whether the third task is completed. In some embodiments, step 703 can be replaced by: before each application for a cache block (for example, the fifth cache block), check whether the third task is completed. It should be understood that the first processing device can also use other methods to check whether the third task is completed, which is not limited to the embodiments of the present application.

[0132] 704. The first processing device puts the fifth cache block back into the cache pool.

[0133] 705. The first processing device allocates a sixth cache block in the cache pool to the fourth task.

[0134] The fifth cache block and the sixth cache block do not store overlap.

[0135] 706. The first processing device submits the fourth task to the operation queue of the second processing device.

[0136] It should be understood that the second processing device occupies the fifth cache block to execute the third task, and occupies the sixth cache block to execute the fourth task.

[0137] In an embodiment of the present application, the first processing device periodically checks whether the tasks on the second processing device are completed, and releases the cache corresponding to any computing task when the computing task is completed, without waiting for all computing tasks on the second processing device to be completed; thus, processing efficiency can be improved.

[0138] Combine the following Figure 8 The timing diagram of the memory management method in Figure 7 Memory management method. Figure 8 A timing diagram of a memory management method provided in an embodiment of the present application, corresponding to Figure 7 Memory management methods in . Figure 8 As shown, the first processing device performs the following operations in sequence: allocation 1, submission of task 1 (corresponding to the third task), release 1, allocation 2, submission of task 2 (corresponding to the fourth task) and release 2; the second processing device performs the following operations in sequence: task 1 and task 2. Figure 8 In the figure, allocation 1 indicates that the first processing device allocates the fifth cache block in the cache pool to task 1, and allocation 2 indicates that the first processing device allocates the sixth cache block in the cache pool to task 2; submitting task 1 indicates that the first processing device submits task 1 to the operation queue of the second processing device, and submitting task 2 indicates that the first processing device submits task 2 to the operation queue of the second processing device; releasing 1 indicates that the first processing device releases the fifth cache block, and releasing 2 indicates that the first processing device releases the sixth cache block; task 1 indicates that the second processing device executes task 1, and task 2 indicates that the second processing device executes task 2. Figure 8 In the example, the fifth cache block allocated by the first processing device for executing allocation 1 and the sixth cache block allocated by executing allocation 2 do not have any common cache. In other words, the second processing device cannot reuse cache blocks when executing computing tasks in the same operation queue. Figure 6 Description of the timing diagram, Figure 8 The operation of releasing 1 in the timing diagram is that the first processing device releases the fifth cache block. Figure 6 The operation of release 1 in the timing diagram is that the first processing device releases the first cache block and puts the first cache block back into the cache pool; Figure 8 The release 2 operation in the timing diagram is that the first processing device releases the sixth cache block. Figure 6 The release 2 operation in the timing diagram is that the first processing device releases the second cache block and puts the second cache block back into the cache pool. Figure 7In the memory management method, after submitting any computing task to the operation queue of the second processing device, the first processing device periodically checks whether the computing task has been completed by the second processing device, and does not put the memory space occupied by the computing task back into the cache pool until the computing task is completed. In other words, the cache block allocated by the first processing device to the second processing device to perform a computing task will not be put back into the cache pool until the computing task is completed. Figure 8 As shown, when the first processing device performs the operations of submitting task 1, releasing 1, allocating 2, and calculating task 2, the second processing device simultaneously performs task 1; when the second processing device performs task 2, the first processing device performs the operation of releasing 2. It can be seen that the first processing device does not need to wait for the second processing device to complete task 1 before performing the operations of releasing 1, allocating 2, and calculating 2. In other words, the first processing device and the second processing device do not need to be synchronized, and an asynchronous computing mode can be implemented to improve computing performance.

[0139] In the embodiment of the present application, the first processing device and the second processing device can implement an asynchronous computing mode, which can improve memory utilization.

[0140] The structure of a data processing device that can implement the memory management method provided by the aforementioned embodiment is introduced below.

[0141] Fig. 9 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the data processing device includes:

[0142] A memory allocation unit 901 is used to allocate a first cache block of a cache pool to a first task;

[0143] A processing unit 902 is used to determine a situation where the second processing device needs to execute the second task and the first task in sequence;

[0144] The memory allocation unit 901 is also used to allocate a second cache block of the cache pool to the second task when the processing unit determines that the second processing device needs to execute the second task and the first task in sequence, wherein at least a part of the second cache block is included in the first cache block.

[0145] The processing unit and the memory allocation unit may be the same unit or two independent units. In some possible implementations, the processing unit is a processor, such as a CPU, and the memory allocation unit is a piece of hardware. In some possible implementations, the processing unit is a processor, such as a CPU, and the functions of the memory allocation unit are implemented by software or a program run by the processor. In other words, the functions of the processing unit and the functions of the memory allocation unit are both implemented by the processor.

[0146] In a possible implementation, the processing unit 902 is further configured to send the first task to the second processing device;

[0147] The memory allocation unit 901 is further configured to put the first cache block back into the cache pool in response to sending the first task to the second processing device.

[0148] In a possible implementation, the processing unit 902 is further configured to record the first operation queue where the first task corresponding to the first cache block is located;

[0149] The processing unit 902 is specifically configured to determine, based on the first operation queue in which the first task is recorded to be located, that the operation queues in which the first task and the second task are located are the same.

[0150] In a possible implementation, the memory allocation unit 901 is further configured to allocate a second cache block of the cache pool to the second task during the process in which the second processing device executes the first task.

[0151] In a possible implementation, the memory allocation unit 901 is further configured to search the cache pool for at least one candidate cache block currently allocated with a task;

[0152] The memory allocation unit 901 is specifically used to allocate a second cache block determined from at least one candidate cache block to the second task when the processing unit determines that the second processing device needs to execute the second task and the first task in sequence based on the execution order relationship between the task currently allocated by at least one candidate cache block and the second task.

[0153] In a possible implementation, the memory allocation unit 901 is specifically configured to search the cache pool for multiple candidate cache blocks that meet the cache size required by the second task; and search at least one candidate cache block currently allocated with a task from the multiple candidate cache blocks.

[0154] In one possible implementation, the memory allocation unit 901 is specifically used to allocate a second cache block determined from at least one candidate cache block to the second task based on the size of the at least one candidate cache block, when the processing unit determines that the second processing device needs to execute the second task and the first task in sequence based on the execution order relationship between the task currently allocated by the at least one candidate cache block and the second task.

[0155] In one possible implementation, the memory allocation unit 901 is further used to determine a target cache block to be allocated to the second task from at least one cache block currently not allocated to a task and included in the cache pool, when the processing unit determines that at least one candidate cache block does not include a cache block that meets the requirements of the second task.

[0156] In a possible implementation, the memory processing unit 901 is further configured to expand the cache pool if no cache block meeting the requirements of the second task is found in the cache pool; and search for a target cache block allocated to the second task from the expanded cache pool.

[0157] Fig.10 A structural diagram of another data processing device provided in an embodiment of the present application, such as Fig.10 As shown, the data processing device includes: a first processor 1001, a second processor 1002, and a memory 1003; wherein the memory is used to store instructions and data, the first processor is used to execute the instructions stored in the memory, so that the first processor performs a memory management method, and the second processing device is used to use the cache block allocated by the first processing device to execute the task sent by the first processor. The memory 1003 may include the device memory used by the second processor 1002 and the memory of the first processor 1001. Exemplarily, the first processing device is a CPU, the second processing device is a GPU, and the memory 1003 includes the display memory of the GPU.

[0158] In an embodiment of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following is achieved: a first processing device allocates a first cache block of a cache pool to a first task; when the first processing device determines that a second processing device needs to execute the second task and the first task in sequence, the first processing device allocates a second cache block of the cache pool to the second task, wherein at least a portion of the second cache block is included in the first cache block.

[0159] An embodiment of the present application provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the memory management method provided by the aforementioned embodiment.

[0160] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A memory management method, characterized in that: The method comprises: The first processing device allocates a first cache block of a cache pool to the first task; The first processing device allocates a second cache block of the cache pool to the second task when determining that the second processing device needs to execute the second task and the first task in sequence, wherein at least a portion of the second cache block is included in the first cache block; After the first processing device allocates a first cache block of a cache pool to the first task, the method further includes: The first processing device, in response to sending the first task to the second processing device, puts the first cache block back into the cache pool; Before allocating the second cache block of the cache pool to the second task, the method further includes: The first processing device searches the cache pool for at least one candidate cache block currently assigned with a task; When determining that the second processing device needs to execute the second task and the first task in sequence, the first processing device allocates the second cache block of the cache pool to the second task, including: The first processing device allocates the second cache block determined from the at least one candidate cache block to the second task based on the execution order relationship between the task currently allocated to the at least one candidate cache block and the second task.

2. The method according to claim 1, characterized in that After the first processing device allocates a first cache block of a cache pool to the first task, the method further includes: The first processing device records a first operation queue where the first task corresponding to the first cache block is located; The determining that the second processing device needs to execute the second task and the first task in sequence comprises: The first processing device determines, based on the first operation queue in which the first task is recorded to be located, that the first task and the second task are located in the same operation queue.

3. The method according to claim 1 or 2, characterized in that: The allocating the second cache block of the cache pool to the second task comprises: The first processing device allocates the second cache block of the cache pool to the second task during the process in which the second processing device executes the first task.

4. The method according to claim 1, characterized in that: The first processing device searches the cache pool for at least one candidate cache block currently assigned with a task, including: The first processing device searches the cache pool for a plurality of candidate cache blocks that meet the cache size required by the second task; The first processing device searches for at least one candidate cache block currently assigned with a task from among the plurality of candidate cache blocks.

5. The method according to claim 1, characterized in that The first processing device allocates the second cache block determined from the at least one candidate cache block to the second task based on an execution order relationship between the task currently allocated to the at least one candidate cache block and the second task, including: The first processing device allocates the second cache block determined from the at least one candidate cache block to the second task based on the execution order relationship between the task currently allocated by the at least one candidate cache block and the second task and the size of the at least one candidate cache block.

6. The method according to claim 1, characterized in that The method further comprises: When the first processing device determines that the at least one candidate cache block does not include a cache block that meets the requirements of the second task, the first processing device determines a target cache block to be allocated to the second task from at least one cache block in the cache pool that is not currently allocated a task.

7. The method according to claim 1 or 2, characterized in that: The method further comprises: If the first processing device fails to find a cache block that meets the requirement of the second task in the cache pool, expanding the cache pool; The first processing device searches for a target cache block allocated to the second task from the expanded cache pool.

8. A data processing device, characterized in that: include: A memory allocation unit, configured to allocate a first cache block of a cache pool to a first task; a processing unit, configured to determine a situation where a second processing device needs to execute a second task and the first task in sequence; The memory allocation unit is further configured to allocate a second cache block of the cache pool to the second task if the processing unit determines that the second processing device needs to execute the second task and the first task in sequence, wherein at least a portion of the second cache block is included in the first cache block; The processing unit is further configured to send the first task to the second processing device; The memory allocation unit is further configured to, in response to sending the first task to the second processing device, put the first cache block back into the cache pool; The memory allocation unit is further used to search the cache pool for at least one candidate cache block currently allocated with a task; The memory allocation unit is specifically used to allocate the second cache block determined from the at least one candidate cache block to the second task when the processing unit determines that the second processing device needs to execute the second task and the first task in sequence based on the execution order relationship between the task currently allocated by the at least one candidate cache block and the second task.

9. The data processing device according to claim 8, characterized in that: The processing unit is further used to record the first operation queue where the first task corresponding to the first cache block is located; The processing unit is specifically configured to determine, based on the first operation queue in which the first task is recorded to be located, that the first task and the second task are located in the same operation queue.

10. The data processing device according to claim 8 or 9, characterized in that: The memory allocation unit is further configured to allocate the second cache block of the cache pool to the second task during the process in which the second processing device executes the first task.

11. The data processing device according to claim 8, characterized in that: The memory allocation unit is specifically configured to search the cache pool for a plurality of candidate cache blocks that meet the cache size required by the second task; and search the plurality of candidate cache blocks for at least one candidate cache block that is currently assigned a task.

12. The data processing device according to claim 8, characterized in that: The memory allocation unit is specifically used to allocate the second cache block determined from the at least one candidate cache block to the second task based on the size of the at least one candidate cache block, when the processing unit determines that the second processing device needs to execute the second task and the first task in sequence based on the execution order relationship between the task currently allocated by the at least one candidate cache block and the second task.

13. The data processing device according to claim 8, characterized in that: The memory allocation unit is further used to determine a target cache block to be allocated to the second task from at least one cache block currently not allocated with a task and included in the cache pool, when the processing unit determines that the at least one candidate cache block does not include a cache block that meets the requirements of the second task.

14. The data processing device according to claim 8 or 9, characterized in that: The memory allocation unit is further configured to expand the cache pool if no cache block meeting the requirements of the second task is found in the cache pool; and search for a target cache block allocated to the second task from the expanded cache pool.

15. An electronic device, characterized in that: The method comprises a memory and a first processor, wherein the memory is used to store instructions, and the first processor is used to execute the instructions stored in the memory, so that the first processor executes the method according to any one of claims 1 to 7.

16. The electronic device according to claim 15, characterized in that: The electronic device also includes a second processor, which is used to execute the task sent by the first processor using the cache block allocated by the first processor.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the method according to any one of claims 1 to 7.

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