Light-emitting display device

Abstract

A light-emitting display device is provided, the light-emitting display device comprising: a first sub-pixel emitting light of a first color; and a second sub-pixel emitting light of a second color, wherein each of the first sub-pixel and the second sub-pixel includes: a driving transistor including a first electrode, a second electrode, and a gate electrode, and configured to control a current flowing from the first electrode to the second electrode according to a data voltage applied to the gate electrode; a light-emitting element connected to the second electrode of the driving transistor; and a first capacitor disposed between a first sub-supply voltage line to which a first supply voltage is applied and the second electrode of the driving transistor, the first sub-supply voltage line being configured to overlap with the second electrode of the driving transistor, wherein the capacitance of the first capacitor of the first sub-pixel and the capacitance of the first capacitor of the second sub-pixel are selectively determined to correspond to the amount of overlap between the first sub-supply voltage line and the second electrode of the driving transistor.

Description

Technical Field

[0001] The disclosure relates to a light-emitting display device, and more specifically, to a construction of a light-emitting display device for optimizing the amount of time for delivering a drive current to the light-emitting element of a pixel to ensure proper display of the pixel's color. Background Technology

[0002] With the development of all aspects of the information-oriented society, the demand for display devices is constantly increasing. For example, display devices are being used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays, such as liquid crystal displays (LCDs), field emission displays (FETs), and organic light-emitting diode (OLEDs). In such flat panel displays, OLEDs include light-emitting elements, allowing each pixel of the display panel to emit its own light. Therefore, OLEDs can display images without a backlight unit that supplies light to the display panel.

[0003] Organic light-emitting display devices may include multiple pixels. Each pixel may include a light-emitting element, a driving transistor, and a scanning transistor. The driving transistor controls the amount of driving current supplied to the light-emitting element based on the voltage at its gate electrode. The scanning transistor supplies a data voltage from a data line to the gate electrode of the driving transistor in response to a scan signal from a scan line. When the light-emitting element emits light with low brightness, the driving current is small, which may require a long time to charge the parasitic capacitance of the light-emitting element. As a result, the emission of the light-emitting element may be delayed within the pixel, and the pixel may not represent the desired color but instead represents another color. Consequently, the image quality viewed by the user may be degraded. Summary of the Invention

[0004] The disclosed embodiments provide a light-emitting display device that can prevent or suppress image quality degradation.

[0005] Additional features will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the embodiments herein.

[0006] According to an embodiment, a light-emitting display device may include: a first sub-pixel emitting light of a first color; and a second sub-pixel emitting light of a second color, wherein each of the first and second sub-pixels may include: a driving transistor including a first electrode, a second electrode, and a gate electrode, and configured to control the current flowing from the first electrode to the second electrode according to a data voltage applied to the gate electrode; a light-emitting element connected to the second electrode of the driving transistor; and a first capacitor disposed between a first sub-supply voltage line and the second electrode of the driving transistor, a first supply voltage being applied to the first sub-supply voltage line, the first sub-supply voltage line being configured to overlap with the second electrode of the driving transistor, and wherein the capacitance of the first capacitor of the first sub-pixel and the capacitance of the first capacitor of the second sub-pixel are selectively determined to correspond to the amount of overlap between the first sub-supply voltage line and the second electrode of the driving transistor in the first and second sub-pixels, respectively.

[0007] In the first sub-pixel, the area where the first sub-supply voltage line and the second electrode of the driving transistor overlap can be smaller than the area where the first sub-supply voltage line and the second electrode of the driving transistor overlap in the second sub-pixel.

[0008] In the first sub-pixel, the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor can be smaller than the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor in the second sub-pixel.

[0009] The light-emitting display device may further include: a scan line extending in a first direction; and a data line extending in a second direction intersecting the first direction, wherein a first sub-supply voltage line extends in the first direction.

[0010] The light-emitting display device may further include: a second sub-supply voltage line electrically connected to the first sub-supply voltage line, wherein the second sub-supply voltage line extends in a second direction.

[0011] Each of the first sub-pixel and the second sub-pixel may further include a second capacitor disposed between the first sub-supply voltage line and the gate electrode of the driving transistor, wherein the capacitance of the first capacitor may be smaller than the capacitance of the second capacitor in each of the first sub-pixel and the second sub-pixel.

[0012] The light-emitting display device may further include: a third sub-pixel that emits light of a third color, wherein the third sub-pixel may include a driving transistor, a light-emitting element, a first sub-supply voltage line, and a first capacitor, wherein the capacitance of the first capacitor of the third sub-pixel may be smaller than the capacitance of the first capacitor of the second sub-pixel.

[0013] In the third sub-pixel, the area where the first sub-supply voltage line and the second electrode of the driving transistor overlap can be smaller than the area where the first sub-supply voltage line and the second electrode of the driving transistor overlap in the second sub-pixel.

[0014] In the third sub-pixel, the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor can be smaller than the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor in the second sub-pixel.

[0015] The capacitance of the first capacitor of the third sub-pixel can be equal to the capacitance of the first capacitor of the first sub-pixel.

[0016] In the third sub-pixel, the area where the first sub-supply voltage line and the second electrode of the driving transistor overlap can be equal to the area where the first sub-supply voltage line and the second electrode of the driving transistor overlap in the first sub-pixel.

[0017] In the third sub-pixel, the length of the first sub-supply voltage line superimposed with the second electrode of the driving transistor can be equal to the length of the first sub-supply voltage line superimposed with the second electrode of the driving transistor in the first sub-pixel.

[0018] The capacitance of the first capacitor of the third sub-pixel can be smaller than the capacitance of the first capacitor of the first sub-pixel.

[0019] In the third sub-pixel, the area where the first sub-supply voltage line and the second electrode of the driving transistor overlap can be smaller than the area where the first sub-supply voltage line and the second electrode of the driving transistor overlap in the first sub-pixel.

[0020] In the third sub-pixel, the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor can be smaller than the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor in the first sub-pixel.

[0021] The light-emitting display device may also include at least one insulating layer disposed between the second electrode of the driving transistor and the first sub-supply voltage line.

[0022] The at least one insulating layer may include: a gate insulating layer disposed on the second electrode of the driving transistor; and an interlayer dielectric layer disposed on the gate electrode of the driving transistor.

[0023] The gate electrode of the driving transistor can be disposed on the gate insulating layer.

[0024] The first sub-supply voltage line can be set on the interlayer dielectric layer.

[0025] The second electrode of the driving transistor can be covered by the gate insulating layer.

[0026] According to the foregoing and other disclosed embodiments, the capacitance of the first capacitor in a subpixel that takes longer to charge its parasitic capacitance than in other subpixels can be configured to be larger than the capacitance of the first capacitor in each of the other subpixels. Therefore, the charging current flowing to the parasitic capacitance in this subpixel can be larger than the charging current flowing to the parasitic capacitance in other subpixels. This reduces the time spent charging the parasitic capacitance in this subpixel. Consequently, it is possible to prevent or suppress degradation of the image quality viewed by the user.

[0027] Other features and embodiments may be apparent from the following detailed description, drawings and claims.

[0028] It will be understood that neither the foregoing description nor the following detailed description should be construed as a limitation on the embodiments described or claimed herein. Attached Figure Description

[0029] The accompanying drawings illustrate the disclosed embodiments and are included to provide a further understanding of the disclosure.

[0030] Figure 1 A perspective view of a display device according to a disclosed embodiment is shown.

[0031] Figure 2 A plan view showing a display device according to a disclosed embodiment is shown.

[0032] Figure 3 A block diagram illustrating a display device according to a disclosed embodiment is shown.

[0033] Figure 4 A schematic diagram of the equivalent circuit of a sub-pixel according to a disclosed embodiment is shown.

[0034] Figure 5 The diagram shows the application of... Figure 4 The waveforms of the signals from the (k-1)th scan line, the kth scan line, the (k+1)th scan line, and the kth transmission line.

[0035] Figures 6 to 9 The following is shown for explaining in Figure 5 A schematic diagram of the method for driving the equivalent circuit of the first sub-pixel during the first to fourth time periods.

[0036] Figure 10 The diagram shows a waveform of the driving current flowing in the light-emitting elements of the first to third sub-pixels when the first to third sub-pixels include the same first capacitor.

[0037] Figure 11A waveform diagram showing the driving current flowing in the light-emitting elements in the first to third sub-pixels is shown when the second sub-pixel includes a first capacitor with a capacitance larger than that of the first capacitor of the first sub-pixel and the first capacitor of the third sub-pixel.

[0038] Figures 12 to 14 A plan view showing the first to third sub-pixels according to the disclosed embodiments is shown.

[0039] Figure 15 It shows along Figure 12 A schematic cross-sectional view taken from line I-I'.

[0040] Figure 16 It shows along Figure 12 Line II-II' and Figure 13 A schematic cross-sectional view taken from line III-III'.

[0041] Figures 17 to 19 A plan view is shown, illustrating the first to third sub-pixels respectively according to an embodiment of the present disclosure.

[0042] Figure 20 It shows along Figure 17 A schematic cross-sectional view taken by line V-V'. Detailed Implementation

[0043] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0044] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on said other layer or substrate, or there may be an intermediate layer. Conversely, when an element is referred to as being "directly on" another element, there is no intermediate element.

[0045] Furthermore, in the specification, the phrase "in a plan view" indicates the view of the object portion from above, while the phrase "in a sectional view" indicates the view of the object portion as a section taken by vertically cutting it from the side. Additionally, the term "overlapping" or its variations indicate that the first object may be above or below the second object, or vice versa. The term "facing" and its variations indicate that the first object may be directly or indirectly opposite the second object. Where a third object is inserted between the first and second objects, the first and second objects can be understood as indirectly opposite each other, but still facing each other.

[0046] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “above,” etc., may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device during use or operation. For example, in the case where the device shown in the figures is flipped, the device positioned “below” or “under” another device may be placed “above” said other device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be positioned in other orientations, and thus spatial relative terms can be interpreted differently depending on the orientation.

[0047] Throughout this specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to said other element, or "electrically connected" to said other element with one or more intermediate elements interposed between them. It will also be understood that when the terms "comprising" and variations thereof and / or "including" and variations thereof are used in this specification, they may indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0048] It will be understood that although the terms “first,” “second,” “third,” etc., may be used here to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or for the convenience of their description and explanation. For example, without departing from the teachings herein, when discussing a “first element,” it may be referred to as a “second element” or a “third element,” and “second element” and “third element” may be named in a similar manner.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense, unless clearly defined in the specification.

[0050] Figure 1 This is a perspective view of a display device according to a disclosed embodiment. Figure 2 This is a plan view illustrating a display device according to a disclosed embodiment. Figure 3 This is a block diagram illustrating a display device according to a disclosed embodiment.

[0051] As used herein, the terms “above,” “top,” and “upper surface” refer to the upper side of display panel 100 (i.e., the side indicated by the arrow in the z-axis direction), while the terms “below,” “bottom,” and “lower surface” refer to the lower side of display panel 100 (i.e., the opposite side in the z-axis direction). As used herein, the terms “left side,” “right side,” “upper side,” and “lower side” indicate relative positions when viewing display panel 100 from above. For example, “left side” refers to the opposite direction indicated by the arrow in the x-axis direction, “right side” refers to the direction indicated by the arrow in the x-axis direction, “upper side” refers to the direction indicated by the arrow in the y-axis direction, and “lower side” refers to the opposite direction indicated by the arrow in the y-axis direction.

[0052] Reference Figures 1 to 3 The display device 10 can display moving or still images. The display device 10 can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), as well as for various products such as televisions, laptops, monitors, billboards, and devices related to the Internet of Things.

[0053] Display device 10 may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, and a micro light-emitting display device using micro light-emitting diodes (LEDs). In the following description, organic light-emitting display devices are described as examples of display device 10. However, it will be understood that the disclosure is not limited thereto.

[0054] The display device 10 may include a display panel 100, a display driving circuit 200, and a circuit board 300.

[0055] The display panel 100 can be formed as a rectangular plane having a shorter side in a first direction (i.e., the x-axis direction) and a longer side in a second direction (i.e., the y-axis direction) intersecting the first direction. Each of the corners where the shorter side in the first direction and the longer side in the second direction intersect can be rounded with a predetermined curvature or can be a right angle. When viewed from above, the shape of the display panel 100 is not limited to a quadrilateral shape, but can be formed as various polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 can be formed as flat, but is not limited to being flat. The display panel 100 may include curved portions formed at its left and right ends with constant or varying curvatures. In addition, the display panel 100 can be formed as flexible, such that it can be bent, folded, rolled up.

[0056] The display panel 100 may include a display area DA in which sub-pixels SP are formed to display images, and a non-display area NDA serving as a peripheral area of ​​the display area DA. In the display area DA, in addition to the sub-pixels SP, scan lines SL, emission lines EL, data lines DL, and a first supply voltage line VDDL connected to the sub-pixels SP may be provided. The scan lines SL and EL may extend along a first direction, while the data line DL may extend along a second direction intersecting the first direction. Furthermore, the scan lines SL and EL may be arranged in the second direction, while the data line DL may be arranged in the first direction. The first supply voltage line VDDL may be arranged parallel to each other in the first direction within the display area DA. The first supply voltage lines VDDL formed parallel to each other in the first direction within the display area DA may be connected to each other in the non-display area NDA.

[0057] Each subpixel SP can be connected to at least one scan line SL, at least one data line DL, at least one emitter line EL, and a corresponding first supply voltage line VDDL. Figure 2 In the example shown, each subpixel SP can be connected to two scan lines SL, one data line DL, one emitter line EL, and a first supply voltage line VDDL. However, it will be understood that the disclosure is not limited thereto. For example, each subpixel SP can be connected to three scan lines SL instead of two scan lines SL.

[0058] Each sub-pixel SP may include a driving transistor DT, at least one switching transistor (hereinafter referred to as a transistor) ST, a light-emitting element, and a capacitor. The transistor ST may be turned on in response to a scan signal from a scan line SL, allowing a data voltage from a data line DL to be applied to the gate electrode of the driving transistor DT. When the data voltage is applied to the gate electrode of the driving transistor DT, the driving transistor DT can supply a drive current to the light-emitting element, allowing light to be emitted. The driving transistor DT and the at least one transistor ST may be thin-film transistors. The light-emitting element may emit light according to the drive current from the driving transistor DT. The light-emitting element may be an organic light-emitting diode including a first electrode, an organic emitting layer, and a second electrode. The capacitor may keep the data voltage applied to the gate electrode of the driving transistor DT constant.

[0059] The non-display area NDA can be defined as the region extending from the outer edge of the display area DA to the edge of the display panel 100. Within the non-display area NDA, a scan drive circuit SDC for applying scan signals to the scan line SL, a fan-out line FL located between the data line DL and the display drive circuit 200, and a pad (also called a "soldering pad") DP connected to the display drive circuit 200 can be provided. The display drive circuit 200 and the pad DP can be located at the edge of one side of the display panel 100. The pad DP can be positioned closer to the edge of said side of the display panel 100 than the display drive circuit 200.

[0060] The scan drive circuit SDC can be connected to the display drive circuit 200 via the scan control line SCL. The scan drive circuit SDC can receive the scan control signal SCS and the transmit control signal ECS from the display drive circuit 200 via the scan control line SCL.

[0061] The scan drive circuit SDC may include, for example, Figure 3 The scan driver 410 and the transmit control driver 420 are shown.

[0062] Scan driver 410 can generate scan signals according to scan control signal SCS, and can output scan signals sequentially to scan line SL. Transmit control driver 420 can generate transmit signals according to transmit control signal ECS, and can output transmit signals sequentially to transmit line EL.

[0063] The scan driving circuit SDC may include thin-film transistors. The scan driving circuit SDC may be formed in the same layer as the thin-film transistors of the sub-pixel SP. Although the scan driving circuit SDC is formed on one side of the display area DA, for example, formed on... Figure 2 The non-display area NDA is located on the left side of the display area DA, but the disclosure is not limited thereto. For example, the scan drive circuit SDC can be formed on both sides of the display area DA, for example, in the non-display area NDA on the left and right sides of the display area DA.

[0064] The display driving circuit 200 may include, for example, Figure 3 The timing controller 210, data driver 220, and power supply unit 230 are shown.

[0065] The timing controller 210 receives digital video data DATA and timing signals from the circuit board 300. Based on the timing signals, the timing controller 210 can generate a scan control signal SCS for controlling the operating timing of the scan driver 410, a transmit control signal ECS for controlling the operating timing of the transmit control driver 420, and a data control signal DCS for controlling the operating timing of the data driver 220. The timing controller 210 can output the scan control signal SCS to the scan driver 410 and the transmit control signal ECS to the transmit control driver 420 via the scan control line SCL. The timing controller 210 can also output the digital video data DATA and the data control signal DCS to the data driver 220.

[0066] The data driver 220 converts digital video data DATA into analog positive / negative data voltages, which can be supplied to the data line DL via the fan-out line FL. Sub-pixels SP can be selected via the scan signal of the scan driver circuit SDC, and data voltages can be supplied to the selected sub-pixels SP.

[0067] The power supply unit 230 can generate a first driving voltage (also referred to as a first supply voltage) to supply to the first supply voltage line VDDL. Additionally, the power supply unit 230 can generate a second driving voltage (also referred to as a second supply voltage) to supply to the cathode electrode of the organic light-emitting diode (OLED) of each sub-pixel SP. The first driving voltage can be a high-level voltage for driving the OLED, and the second driving voltage can be a low-level voltage for driving the OLED. That is, the first driving voltage can have a higher level than the second driving voltage.

[0068] The display driving circuit 200 can be implemented as an integrated circuit (IC) and can be attached to the display panel 100 via chip-on-glass (COG) technology, chip-on-plastic (COP) technology, or ultrasonic bonding. However, it is understood that the disclosure is not limited thereto. For example, the display driving circuit 200 can be attached to a circuit board 300.

[0069] The circuit board 300 can be attached to the pad DP using an anisotropic conductive film. The leads of the circuit board 300 can be electrically connected to the pad DP. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0070] Figure 4 A circuit diagram illustrating a sub-pixel according to a disclosed embodiment is shown.

[0071] Reference Figure 4Sub-pixel SP can be connected to the (k-1)th scan line SLk-1, the kth scan line SLk, the (k+1)th scan line SLk+1, and the jth data line DLj, where k can be a positive integer equal to or greater than 2, and j is a positive integer. Additionally, sub-pixel SP can be connected to the first supply voltage line VDDL, the initialization voltage line VIL, and the second supply voltage line VSSL. The first driving voltage can be supplied to the first supply voltage line VDDL, and the initialization voltage Vini (see reference...) Figure 6 The first voltage can be supplied to the initialization voltage line VIL, and the second drive voltage can be supplied to the second supply voltage line VSSL.

[0072] The sub-pixel SP may include a driving transistor DT, a light-emitting element EL, a switching element, a first capacitor C1, a second capacitor C2, etc. The switching element may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6.

[0073] The drain-source current Ids of the driving transistor DT can be controlled based on the data voltage applied to the gate electrode of the driving transistor DT (refer to...). Figure 9 (Hereinafter referred to as the "drive current"). The drive current Ids flowing through the channel of the drive transistor DT can be proportional to the square of the difference between the gate-source voltage Vsg and the threshold voltage of the drive transistor DT, as shown in Equation 1 below:

[0074] [Equation 1]

[0075] Ids=k′×(Vsg-Vth) 2

[0076] Where k' represents the scaling factor determined by the structure and physical properties of the driving transistor DT, Vsg represents the gate-source voltage of the driving transistor DT, and Vth represents the threshold voltage of the driving transistor DT.

[0077] A light-emitting element (EL) emits light as a driving current (Ids) flows through it. The amount of light emitted from the EL is proportional to the driving current (Ids).

[0078] The light-emitting element (EL) can be an organic light-emitting diode (OLED) comprising an anode electrode, a cathode electrode, and an organic emitting layer disposed between the anode and cathode electrodes. As another example, the light-emitting element (EL) can be an inorganic light-emitting element comprising an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode and cathode electrodes. As yet another example, the light-emitting element (EL) can be a quantum dot light-emitting element comprising an anode electrode, a cathode electrode, and a quantum dot emitting layer disposed between the anode and cathode electrodes. As yet another example, the light-emitting element (EL) can be a micro-LED.

[0079] The anode of the light-emitting element EL can be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, while its cathode can be connected to the second supply voltage line VSSL. A parasitic capacitance Cel can be formed between the anode and cathode of the light-emitting element EL.

[0080] The first transistor ST1 can be turned on by the scan signal of the k-th scan line SLk, so that the first electrode of the driving transistor DT is connected to the j-th data line DLj. The gate electrode of the first transistor ST1 can be connected to the k-th scan line SLk, its first electrode can be connected to the first electrode of the driving transistor DT, and its second electrode can be connected to the j-th data line DLj.

[0081] The second transistor ST2 can be implemented as a dual transistor comprising transistors ST2-1 (2-1) and ST2-2 (2-2). Transistors ST2-1 and ST2-2 can be turned on by a scan signal from the k-th scan line SLk, connecting the gate electrode of the driving transistor DT to its second electrode. That is, when transistors ST2-1 and ST2-2 are turned on, the gate electrode of the driving transistor DT can be connected to its second electrode, thus the driving transistor DT can function as a diode. The gate electrode of transistor ST2-1 can be connected to the k-th scan line SLk, its first electrode can be connected to the second electrode of transistor ST2-2 (2-2), and its second electrode can be connected to the gate electrode of the driving transistor DT. The gate electrode of transistor ST2-2 can be connected to the k-th scan line SLk, its first electrode can be connected to the second electrode of the driving transistor DT, and its second electrode can be connected to the first electrode of transistor ST2-1 (2-1).

[0082] The third transistor ST3 can be implemented as a dual transistor comprising transistors ST3-1 (3-1) and ST3-2 (3-2). Transistors ST3-1 and ST3-2 can be turned on by the scan signal of scan line SLk-1 (k-1), connecting the gate electrode of the driving transistor DT to the initialization voltage line VIL. The gate electrode of the driving transistor DT can be discharged to the initialization voltage Vini of the initialization voltage line VIL. The gate electrode of transistor ST3-1 can be connected to scan line SLk-1 (k-1), its first electrode can be connected to the gate electrode of the driving transistor DT, and its second electrode can be connected to the first electrode of transistor ST3-2 (3-2). The gate electrode of transistor ST3-2 can be connected to scan line SLk-1 (k-1), its first electrode can be connected to the second electrode of transistor ST3-1 (3-1), and its second electrode can be connected to the initialization voltage line VIL.

[0083] The fourth transistor ST4 can be turned on by the scan signal of the (k+1)th scan line SLk+1, so that the anode electrode of the light-emitting element EL is connected to the initialization voltage line VIL. The anode electrode of the light-emitting element EL can be discharged to the initialization voltage. The gate electrode of the fourth transistor ST4 can be connected to the (k+1)th scan line SLk+1, the first electrode of the fourth transistor ST4 can be connected to the anode electrode of the light-emitting element EL, and its second electrode can be connected to the initialization voltage line VIL.

[0084] The fifth transistor ST5 can be turned on by the emission signal of the k-th emitter line Ek, so that the first electrode of the driving transistor DT is connected to the first supply voltage line VDDL. The gate electrode of the fifth transistor ST5 can be connected to the k-th emitter line Ek, its first electrode can be connected to the first supply voltage line VDDL, and its second electrode can be connected to the first electrode of the driving transistor DT.

[0085] The sixth transistor ST6 can be connected between the second electrode of the driving transistor DT and the anode electrode of the light-emitting element EL. The sixth transistor ST6 can be turned on by the emission signal from the k-th emitter line Ek, thus connecting the second electrode of the driving transistor DT to the anode electrode of the light-emitting element EL. The gate electrode of the sixth transistor ST6 can be connected to the k-th emitter line Ek, its first electrode can be connected to the second electrode of the driving transistor DT, and its second electrode can be connected to the anode electrode of the light-emitting element EL. When both the fifth transistor ST5 and the sixth transistor ST6 are turned on, the drive current Ids can be supplied to the light-emitting element EL.

[0086] A first capacitor C1 may be formed between the second electrode of the driving transistor DT and the first supply voltage line VDDL. One electrode of the first capacitor C1 may be connected to the second electrode of the driving transistor DT, while its other electrode may be connected to the first supply voltage line VDDL.

[0087] A second capacitor C2 can be formed between the gate electrode of the driving transistor DT and the first supply voltage line VDDL. One electrode of the second capacitor C2 can be connected to the gate electrode of the driving transistor DT, while its other electrode can be connected to the first supply voltage line VDDL. Since the second capacitor C2 maintains the voltage at the gate electrode of the driving transistor DT for one frame period, the capacitance of the second capacitor C2 can be larger than that of the first capacitor C1.

[0088] When the first electrode of each of the first transistor ST1, second transistor ST2, third transistor ST3, fourth transistor ST4, fifth transistor ST5, sixth transistor ST6, and driving transistor DT can be a source electrode, its second electrode can be a source electrode.

[0089] The active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, as well as the driving transistor DT, can be formed from polycrystalline silicon, amorphous silicon, and oxide semiconductor. When the semiconductor layer of each of the first transistors ST1 to ST6 and the driving transistor DT can be formed from polycrystalline silicon, a low-temperature polycrystalline silicon (LTPS) process can be used.

[0090] While the first transistor ST1, second transistor ST2, third transistor ST3, fourth transistor ST4, fifth transistor ST5, and sixth transistor ST6, as well as the driving transistor DT, can be p-type metal-oxide-semiconductor field-effect transistors (MOSFETs), this is merely an example. As another example, they can be n-type MOSFETs. When the first transistor ST1, second transistor ST2, third transistor ST3, fourth transistor ST4, fifth transistor ST5, and sixth transistor ST6, as well as the driving transistor DT, can be appropriately modified to suit the characteristics of n-type MOSFETs. Figure 5 The timing diagram.

[0091] The first driving voltage from the first supply voltage line VDDL, the second driving voltage from the second supply voltage line VSSL, and the initialization voltage Vini from the initialization voltage line VIL can be determined based on the characteristics of the driving transistor DT, the characteristics of the light-emitting element EL, etc. For example, the voltage difference between the initialization voltage Vini and the data voltage supplied to the first electrode of the driving transistor DT can be set to be smaller than the threshold voltage of the driving transistor DT.

[0092] Figure 5 The diagram shows the application of... Figure 4 The waveforms of the signals from the (k-1)th scan line, the kth scan line, the (k+1)th scan line, and the kth transmission line.

[0093] Reference Figure 5 The (k-1)th scan signal SCANk-1 applied to the (k-1)th scan line SLk-1 can be used to turn the third transistor ST3 on and off. The kth scan signal SCANk applied to the kth scan line SLk can be used to turn each of the first transistor ST1 and the second transistor ST2 on and off. The (k+1)th scan signal SCANk+1 applied to the (k+1)th scan line SLk+1 can be used to turn the fourth transistor ST4 on and off. The kth transmit signal EMk can be used to control the fifth transistor ST5 and the sixth transistor ST6.

[0094] The (k-1)th scan signal SCANk-1, the kth scan signal SCANk, the (k+1)th scan signal SCANk+1, and the kth transmit signal EMk can be generated in each frame period. A frame period can be divided into a first period t1 to a fourth period t4. During the first period t1, the gate electrode of the driving transistor DT can be initialized. During the second period t2, the data voltage can be supplied to the gate electrode of the driving transistor DT, and the threshold voltage of the driving transistor DT can be sampled. During the third period t3, the anode electrode of the light-emitting element EL can be initialized. During the fourth period t4, the light-emitting element EL can emit light.

[0095] The (k-1)th scan signal SCANk-1, the kth scan signal SCANk, and the (k+1)th scan signal SCANk+1 can be sequentially output as the gate on-state voltage Von during the first time period t1, the second time period t2, and the third time period t3. For example, the (k-1)th scan signal SCANk-1 can have the gate on-state voltage Von during the first time period t1 and the gate off-state voltage Voff during the other time periods. The kth scan signal SCANk can have the gate on-state voltage Von during the second time period t2 and the gate off-state voltage Voff during the other time periods. The (k+1)th scan signal SCANk+1 can have the gate on-state voltage Von during the third time period t3 and the gate off-state voltage Voff during the other time periods. Although in Figure 5 In the graph shown, the period during which the (k-1)th scan signal SCANk-1 has a gate on-voltage Von can be shorter than the first period t1, but this period can be substantially equal to the first period t1. Although in Figure 5 In the curve shown, the period during which the k-th scan signal SCANk has a gate on-voltage Von can be shorter than the second period t2, but this period can be substantially equal to the second period t2. Additionally, although in Figure 5 In the curve shown, the period during which the (k+1)th scan signal SCANk+1 can have a gate on-voltage Von can be shorter than the third period t3, but this period can be substantially equal to the third period t3.

[0096] The k-th transmitted signal EMk can have a gate on-voltage Von during the fourth time period t4, and can have a gate off-voltage Voff during other time periods.

[0097] exist Figure 5 In the graph shown, each of the first time period t1, the second time period t2, and the third time period t3 can be a horizontal time period. A horizontal time period refers to the period during which data voltage can be supplied to each sub-pixel SP connected to the scan line of the display panel 100; therefore, a horizontal time period can be defined as a horizontal line scan period. The data voltage can be supplied to the data line DL synchronously with the gate on-state voltage Von of each scan signal.

[0098] The gate on-state voltage Von can correspond to the on-state voltage that enables each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 to conduct. The gate off-state voltage Voff can correspond to the off-state voltage that enables each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 to cut off.

[0099] Figures 6 to 9 The following is shown for explaining in Figure 5 A schematic diagram of the method for driving the equivalent circuit of the first sub-pixel during the first to fourth time periods. Figure 10 The diagram shows a waveform of the driving current flowing in the light-emitting elements of the first to third sub-pixels when the first to third sub-pixels include the same first capacitor. Figure 11 A waveform diagram showing the driving current flowing in the light-emitting elements in the first to third sub-pixels is shown when the second sub-pixel includes a first capacitor with a capacitance larger than that of the first capacitor of the first sub-pixel and the first capacitor of the third sub-pixel.

[0100] In the following text, we will combine Figures 5 to 9 This describes the operation of subpixel SP during the first time period t1 to the fourth time period t4.

[0101] First, during the first time period t1, the (k-1)th scan signal SCANk-1 with a gate on-voltage Von can be supplied to the (k-1)th scan line SLk-1. For example... Figure 6 As shown, during the first time period t1, the third transistor ST3 can be turned on by the (k-1)th scan signal SCANk-1 having a gate on-state voltage Von. With the third transistor ST3 turned on, the gate electrode of the driving transistor DT can be initialized to the initialization voltage Vini of the initialization voltage line VIL.

[0102] Secondly, during the second time period t2, the k-th scan signal SCANk with gate on-state voltage Von can be supplied to the k-th scan line SLk. For example... Figure 7 As shown, during the second time period t2, each of the first transistor ST1 and the second transistor ST2 can be turned on by the k-th scan signal SCANk having a gate turn-on voltage Von.

[0103] When the second transistor ST2 is turned on, the gate electrode and the second electrode of the driving transistor DT can be connected to each other, allowing the driving transistor DT to function as a diode. With the first transistor ST1 turned on, the data voltage Vdata can be supplied to the first electrode of the driving transistor DT. At this time, since the voltage difference (Vsg = Vdata - Vini) between the gate electrode and the first electrode of the driving transistor DT can be greater than the threshold voltage Vth, the driving transistor DT can form a current path until the voltage difference Vsg reaches the threshold voltage Vth. Therefore, the voltage between the gate electrode and the second electrode of the driving transistor DT can increase during the second time period t2 to the voltage difference (Vdata - Vth) between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT. A voltage equal to the voltage difference (Vdata - Vth) can be stored in each of the first capacitor C1 and the second capacitor C2.

[0104] Third, during the third time period t3, the (k+1)th scan signal SCANk+1 with a gate on-state voltage Von can be supplied to the (k+1)th scan line SLk+1. For example... Figure 8 As shown, during the third time period t3, the fourth transistor ST4 can be turned on by the (k+1)th scan signal SCANk+1 with a gate on-state voltage Von. With the fourth transistor ST4 turned on, the anode electrode of the light-emitting element EL can be initialized to the initialization voltage Vini of the initialization voltage line VIL.

[0105] Fourth, during the fourth time period t4, the k-th transmit signal EMk with a gate on-state voltage Von can be supplied to the k-th transmit line Ek. For example... Figure 9 As shown, during the fourth time period t4, each of the fifth transistor ST5 and the sixth transistor ST6 can be turned on by the kth transmit signal EMk having a gate turn-on voltage Von.

[0106] With the fifth transistor ST5 turned on, the first electrode of the driving transistor DT can be connected to the first supply voltage line VDDL. With the sixth transistor ST6 turned on, the second electrode of the driving transistor DT can be connected to the anode electrode of the light-emitting element EL.

[0107] With the fifth transistor ST5 and the sixth transistor ST6 turned on, the flowing drive current Ids can be supplied to the light-emitting element EL according to the voltage at the gate electrode of the drive transistor DT. The drive current Ids can be defined as shown in Equation 2 below:

[0108] [Equation 2]

[0109] Ids=k'×(ELVDD-(Vdata-Vth)-Vth) 2

[0110] Where k' represents a scaling factor determined by the structure and physical properties of the driving transistor DT, Vth represents the threshold voltage of the driving transistor DT, ELVDD represents the first driving voltage from the first supply voltage line VDDL, and Vdata represents the data voltage. The gate voltage of the driving transistor DT can be equal to Vdata - Vth, and the voltage at the first electrode of the driving transistor DT can be equal to ELVDD. By summarizing Equation 2, the following Equation 3 can be derived.

[0111] [Equation 3]

[0112] Ids = k′ × (ELVDD - Vdata) 2

[0113] Therefore, as shown in Equation 3, the drive current Ids may not depend on the threshold voltage Vth of the drive transistor DT. In other words, the threshold voltage Vth of the drive transistor DT can be compensated.

[0114] Incidentally, such as Figure 9 As shown, the drive current Ids can be supplied not only to the light-emitting element EL but also to the parasitic capacitance Cel. However, when the light-emitting element EL emits low-brightness light, the drive current Ids will be small, thus potentially requiring a long time to charge the parasitic capacitance Cel. For example, in... Figure 10 In the case shown, where it takes a long time to charge the parasitic capacitance Cel, the emission of the light-emitting element EL may be delayed in some sub-pixels SP.

[0115] A subpixel SP may include a first subpixel that emits light of a first color, a second subpixel that emits light of a second color, and a third subpixel that emits light of a third color. In the following description, for ease of illustration, the first subpixel is a red subpixel that emits red light, the second subpixel is a green subpixel that emits green light, and the third subpixel is a blue subpixel that emits blue light.

[0116] The first sub-pixel, the second sub-pixel, and the third sub-pixel can be defined as a single pixel used to represent a black-and-white / grayscale image. In some implementations, a single pixel may include a first sub-pixel, two second sub-pixels, and a third sub-pixel.

[0117] When a pixel represents black and then gray, the driving current Ids of the second sub-pixel emitting green light can be smaller than the driving current Ids of the first sub-pixel emitting red light. Furthermore, the driving current Ids of the second sub-pixel emitting green light can be smaller than the driving current Ids of the third sub-pixel emitting blue light. Additionally, the parasitic capacitance Cel of the second sub-pixel can be larger than the parasitic capacitance Cel of both the first and third sub-pixels.

[0118] Therefore, the time spent charging the parasitic capacitance Cel with the driving current Ids in the second sub-pixel is longer than the time spent charging the parasitic capacitance Cel with the driving current Ids in the first sub-pixel. Furthermore, the time spent charging the parasitic capacitance Cel with the driving current Ids in the second sub-pixel is longer than the time spent charging the parasitic capacitance Cel with the driving current Ids in the third sub-pixel. Therefore, as... Figure 10 As shown, the time point T31 when the driving current I_G starts flowing in the light-emitting element EL in the second sub-pixel is later than the time point T21 when the driving current I_R starts flowing in the light-emitting element EL in the first sub-pixel. Furthermore, the time point T31 when the driving current I_G starts flowing in the light-emitting element EL in the second sub-pixel is later than the time point T11 when the driving current I_B starts flowing in the light-emitting element EL in the third sub-pixel.

[0119] Because the point at which the driving current I_G begins flowing in the light-emitting element EL in the second sub-pixel, T31, is later than the points at which the driving current begins flowing in each of the first and third sub-pixels, T21 and T11, the pixel will be unable to represent gray and will represent another color. For example, due to the lack of green, the pixel will represent purple.

[0120] To overcome such problems, such as Figure 9 As shown, when the fifth transistor ST5 and the sixth transistor ST6 are turned on, the charging current Ic can flow further to the parasitic capacitance Cel through the voltage (Vdata-Vth) stored in the first capacitor C1. The capacitance of the first capacitor C1 of the second sub-pixel, which takes a longer time to charge the parasitic capacitance Cel with the driving current Ids, can be larger than the capacitances of the first capacitor C1 of the first sub-pixel and the first capacitor C1 of the third sub-pixel. As a result, the charging current Ic flowing to the parasitic capacitance Cel in the second sub-pixel can be larger than the charging current Ic flowing to the parasitic capacitance Cel in the first sub-pixel and the parasitic capacitance Cel in the third sub-pixel. Therefore, it is possible to reduce the time spent charging the parasitic capacitance Cel in the second sub-pixel. Figure 11As shown, it is possible to reduce the time difference between the point in time T32 when the driving current I_G begins to flow in the light-emitting element EL in the second sub-pixel and the point in time T22 when the driving current I_R begins to flow in the light-emitting element EL in the first sub-pixel. Furthermore, it is possible to reduce the time difference between the point in time T32 when the driving current I_G begins to flow in the light-emitting element EL in the second sub-pixel and the point in time T12 when the driving current I_B begins to flow in the light-emitting element EL in the third sub-pixel. As a result, the problem of pixels failing to display the desired color due to the time difference between the points in time when the driving currents Ids begin to flow in the light-emitting elements EL in different sub-pixels can be overcome.

[0121] Figures 12 to 14 A plan view showing the first to third sub-pixels according to the disclosed embodiments is shown.

[0122] Reference Figures 12 to 14 Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a driving transistor DT, a first transistor ST1 to a sixth transistor ST6, a first capacitor C1, and a second capacitor C2.

[0123] The driving transistor DT may include an active layer DT_ACT, a gate electrode DT_G, a first electrode DT_S, and a second electrode DT_D. The active layer DT_ACT of the driving transistor DT may be stacked with the gate electrode DT_G of the driving transistor DT. The gate electrode DT_G of the driving transistor DT may include a first gate electrode DT_G1 and a second gate electrode DT_G2. The second gate electrode DT_G2 may be disposed on the first gate electrode DT_G1, and the first gate electrode DT_G1 and the second gate electrode DT_G2 may be connected to each other through a first contact hole CNT1. The first gate electrode DT_G1 may be stacked with the active layer DT_ACT of the driving transistor DT, and the first gate electrode DT_G1 may be connected to the second electrode D2-1 of the second-1 transistor ST2-1 through a second contact hole CNT2. The first electrode DT_S of the driving transistor DT may be connected to the first electrode S1 of the first transistor ST1. The second electrode DT_D of the driving transistor DT may be connected to the first electrode S2-2 of the second-2 transistor ST2-2 and the first electrode S6 of the sixth transistor ST6.

[0124] The first transistor ST1 may include an active layer ACT1, a gate electrode G1, a first electrode S1, and a second electrode D1. The gate electrode G1 of the first transistor ST1 may be a portion of the k-th scan line SLk, where k may be a positive integer equal to or greater than 2. The gate electrode G1 may be the portion of the k-th scan line SLk that overlaps with the active layer ACT1 of the first transistor ST1. The first electrode S1 of the first transistor ST1 may be connected to the first electrode DT_S of the driving transistor DT. The second electrode D1 of the first transistor ST1 may be connected to the j-th data line DLj through a third contact hole CNT3.

[0125] The second transistor ST2 can be implemented as a dual transistor. The second transistor ST2 may include a second-first transistor ST2-1 and a second-second transistor ST2-2.

[0126] Transistor ST2-1 (2-1) may include an active layer ACT2-1, a gate electrode G2-1, a first electrode S2-1, and a second electrode D2-1. The gate electrode G2-1 of transistor ST2-1 may be a portion of the k-th scan line SLk. The gate electrode G2-1 may be a portion of the k-th scan line SLk that overlaps with the active layer ACT2-1 of transistor ST2-1. The first electrode S2-1 of transistor ST2-1 may be connected to the second electrode D2-2 of transistor ST2-2 (2-2). The second electrode D2-1 of transistor ST2-1 may be connected to the first gate electrode DT_G1 of the driving transistor DT through the second contact hole CNT2.

[0127] Transistor ST2-2 (2-2) may include an active layer ACT2-2, a gate electrode G2-2, a first electrode S2-2, and a second electrode D2-2. The gate electrode G2-2 of transistor ST2-2 may be a portion of the k-th scan line SLk. The gate electrode G2-2 may be the portion of the k-th scan line SLk superimposed on the active layer ACT2-2 of transistor ST2-2. The first electrode S2-2 of transistor ST2-2 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D2-2 of transistor ST2-2 may be connected to the first electrode S2-1 of transistor ST2-1 (2-1).

[0128] The third transistor ST3 can be implemented as a dual transistor. The third transistor ST3 may include the third-first transistor ST3-1 and the third-second transistor ST3-2.

[0129] Transistor ST3-1 (3-1) may include an active layer ACT3-1, a gate electrode G3-1, a first electrode S3-1, and a second electrode D3-1. The gate electrode G3-1 of transistor ST3-1 may be a portion of the (k-1)th scan line SLk-1. The gate electrode G3-1 may be a portion of the (k-1)th scan line SLk-1 that overlaps with the active layer ACT3-1 of transistor ST3-1. The first electrode S3-1 of transistor ST3-1 may be connected to the first gate electrode DT_G1 of the driving transistor DT via the second contact hole CNT2. The second electrode D3-1 of transistor ST3-1 may be connected to the first electrode S3-2 of transistor ST3-2 (3-2).

[0130] Transistor ST3-2 (3-2) may include an active layer ACT3-2, a gate electrode G3-2, a first electrode S3-2, and a second electrode D3-2. The gate electrode G3-2 of transistor ST3-2 may be a portion of the (k-1)th scan line SLk-1. The gate electrode G3-2 may be the portion of the (k-1)th scan line SLk-1 that overlaps with the active layer ACT3-2 of transistor ST3-2. The first electrode S3-2 of transistor ST3-2 may be connected to the first gate electrode DT_G1 of the driving transistor DT through the second contact hole CNT2. The second electrode D3-2 of transistor ST3-2 may be connected to the initialization connection electrode VIE through the fourth contact hole CNT4.

[0131] The fourth transistor ST4 may include an active layer ACT4, a gate electrode G4, a first electrode S4, and a second electrode D4. The gate electrode G4 of the fourth transistor ST4 may be a portion of the (k+1)th scan line SLk+1. The gate electrode G4 may be the portion of the (k+1)th scan line SLk+1 that overlaps with the active layer ACT4 of the fourth transistor ST4. The first electrode S4 of the fourth transistor ST4 can be connected to the anode connection electrode ANDE through the sixth contact hole CNT6. The light-emitting element EL (i.e., Figure 15 The anode electrode of the light-emitting element 170 shown (i.e., Figure 15 The first electrode 171 shown can be connected to the anode connection electrode ANDE via the anode contact hole AND_CNT. The second electrode D4 of the fourth transistor ST4 can be connected to the initialization connection electrode VIE via the fourth contact hole CNT4. The initialization voltage line VIL can be connected to the initialization connection electrode VIE via the fifth contact hole CNT5. The initialization connection electrode VIE can be connected to the second electrode D3-2 of the third-second transistor ST3-2 and the second electrode D4 of the fourth transistor ST4 via the fourth contact hole CNT4. The initialization connection electrode VIE can be configured such that it intersects with the (k-1)th scan line SLk-1.

[0132] The fifth transistor ST5 may include an active layer ACT5, a gate electrode G5, a first electrode S5, and a second electrode D5. The gate electrode G5 of the fifth transistor ST5 may be a portion of the k-th emitter line Ek. The gate electrode G5 may be a portion of the k-th emitter line Ek that overlaps with the active layer ACT5 of the fifth transistor ST5. The first electrode S5 of the fifth transistor ST5 can be connected to the second sub-supply voltage line VDDL2 via the seventh contact hole CNT7. The second electrode D5 of the fifth transistor ST5 can be connected to the first electrode DT_S of the driving transistor DT.

[0133] The sixth transistor ST6 may include an active layer ACT6, a gate electrode G6, a first electrode S6, and a second electrode D6. The gate electrode G6 of the sixth transistor ST6 may be a portion of the k-th emitter line Ek. The gate electrode G6 may be a portion of the k-th emitter line Ek superimposed on the active layer ACT6 of the sixth transistor ST6. The first electrode S6 of the sixth transistor ST6 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D6 of the sixth transistor ST6 may be connected to the anode electrode of the light-emitting element EL through the sixth contact hole CNT6.

[0134] When still referring to Figures 15 to 16 In this configuration, the first electrode CE11 of the first capacitor C1 can be part of the second electrode DT_D of the driving transistor DT, and the second electrode CE12 of the first capacitor C1 can be a first sub-supply voltage line VDDL1 superimposed on the second electrode DT_D of the driving transistor DT. The first sub-supply voltage line VDDL1 can be connected to the second sub-supply voltage line VDDL2 through the eighth contact hole CNT8. The second sub-supply voltage line VDDL2 can be configured to be parallel to the j-th data line DLj, and the first sub-supply voltage line VDDL1 can be configured to be parallel to the k-th scan line SLk. The first supply voltage line VDDL can include the first sub-supply voltage line VDDL1 and the second sub-supply voltage line VDDL2 electrically connected to each other.

[0135] The first electrode CE21 of the second capacitor C2 can be substantially the same as the first gate electrode DT_G1 of the driving transistor DT. The second electrode CE22 of the second capacitor C2 can be the first sub-supply voltage line VDDL1 superimposed on the gate electrode DT_G of the driving transistor DT.

[0136] The area of ​​the second capacitor C2 can be larger than that of the first capacitor C1. That is, since the second capacitor C2 maintains the voltage at the gate electrode DT_G of the driving transistor DT for one frame period, the capacitance of the second capacitor C2 can be larger than that of the first capacitor C1.

[0137] The capacitance of the first capacitor C1 can be proportional to the area of ​​the second electrode DT_D of the driving transistor DT stacked with the first sub-supply voltage line VDDL1. In other words, the capacitance of the first capacitor C1 can increase proportionally as the area of ​​the second electrode DT_D of the driving transistor DT stacked with the first sub-supply voltage line VDDL1 increases. The proportional increase in capacitance can also be applied to the area of ​​the second electrode DT_D of the driving transistor DT facing the first sub-supply voltage line VDDL1. Thus, the capacitance of the first capacitor C1 can be selectively determined to correspond to the amount of overlap between the second electrode DT_D of the driving transistor DT and the first sub-supply voltage line VDDL1 (specifically, the first capacitor C1 can be the second electrode CE12 of the first sub-supply voltage line VDDL1).

[0138] like Figure 12 and Figure 13 As shown, the area where the second electrode DT_D of the driving transistor DT in the second sub-pixel SP2 is superimposed on the first sub-supply voltage line VDDL1 can be larger than the area where the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1 is superimposed on the first sub-supply voltage line VDDL1. Additionally, as... Figure 13 and Figure 14 As shown, the area where the second electrode DT_D of the driving transistor DT in the second sub-pixel SP2 overlaps with the first sub-supply voltage line VDDL1 can be larger than the area where the second electrode DT_D of the driving transistor DT in the third sub-pixel SP3 overlaps with the first sub-supply voltage line VDDL1. Furthermore, the area where the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1 overlaps with the first sub-supply voltage line VDDL1 can be substantially the same as the area where the second electrode DT_D of the driving transistor DT in the third sub-pixel SP3 overlaps with the first sub-supply voltage line VDDL1. Therefore, the capacitance of the first capacitor C1 of the second sub-pixel SP2 can be larger than the capacitance of the first capacitor C1 of the first sub-pixel SP1 and the capacitance of the first capacitor C1 of the third sub-pixel SP3. The capacitances of the first capacitor C1 of the first sub-pixel SP1 and the third sub-pixel SP3 can be equal to each other.

[0139] according to Figures 12 to 14In the embodiment shown, the capacitance of the first capacitor C1 of the second sub-pixel SP2 can be larger than the capacitance of the first capacitor C1 of the first sub-pixel SP1 and the first capacitor C1 of the third sub-pixel SP3. Charging the parasitic capacitance Cel in the second sub-pixel SP2 using the driving current Ids takes a longer time. Therefore, the charging current Ic flowing to the parasitic capacitance Cel in the second sub-pixel SP2 can be larger than the charging current Ic flowing to the parasitic capacitance Cel in the first sub-pixel SP1 and the third sub-pixel SP3. This reduces the time spent charging the parasitic capacitance Cel in the second sub-pixel SP2. Therefore, it is possible to overcome the failure of a pixel to display the desired color due to the difference in the timing between when the driving current Ids begins to flow in the light-emitting element EL in the sub-pixel. Thus, it is possible to prevent or suppress the degradation of the image quality viewed by the user.

[0140] Figure 15 It shows along Figure 12 A sectional view taken by line I-I'. Figure 16 It shows along Figure 12 Line II-II' and Figure 13 The sectional view taken from line III-III'.

[0141] Along Figure 14 The sectional view taken by line IV-IV' can be compared with Figure 16 As shown along Figure 12 The sectional view taken along line II-II' is essentially the same; therefore, it is not shown along... Figure 14 A sectional view taken from line IV-IV'.

[0142] Reference Figure 15 and Figure 16 The thin-film transistor layer (TFTL), the light-emitting element layer (EML), and the encapsulation layer (TFE) can be sequentially formed on the first substrate (SUB1).

[0143] The thin-film transistor layer (TFTL) may include a buffer film (BF), an active layer (ACT), a first gate layer (GTL1), a second gate layer (GTL2), a data metal layer (DTL), a gate insulating layer (130), a first interlayer dielectric layer (141), a second interlayer dielectric layer (142), a protective layer (150), and a planarization layer (160).

[0144] A buffer film (BF) can be formed on the surface of the first substrate SUB1 to protect the thin-film transistors and organic emitting layer 172 of the light-emitting element layer EML from moisture that may penetrate through the first substrate SUB1. The buffer film BF can be formed from inorganic layers stacked alternately on top of each other. For example, the buffer film BF can be composed of multiple layers in which one or more inorganic layers of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are stacked alternately on top of each other. The buffer film BF can be removed.

[0145] The active layer ACT can be formed on the first substrate SUB1 or the buffer film BF. The active layer ACT can include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. A light-shielding layer can be formed below the active layer ACT to block external light incident on the active layer ACT.

[0146] In cases where the active layer ACT can be made of polycrystalline silicon by doping ions into the active layer ACT, the active layer ACT can be conductive. Therefore, the active layer ACT can include not only the active layer DT_ACT of the driving transistor DT and the active layers ACT1 to ACT6 of the first switching transistor ST1 to the sixth switching transistor ST6, but also the source electrodes DT_S, S1, S2-1, S2-2, S3-1, S3-2, S4, S5 and S6 and the drain electrodes DT_D, D1, D2-1, D2-2, D3-1, D3-2, D4, D5 and D6.

[0147] The gate insulating layer 130 may be formed on the active layer ACT. The gate insulating layer 130 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0148] The first gate layer GTL1 can be formed on the gate insulating layer 130. The first gate layer GTL1 can include not only the first gate electrode DT_G1 of the driving transistor DT and the gate electrodes G1 to G6 of the first switching transistor ST1 to the sixth switching transistor ST6, but also scan lines SLk-1, SLk and SLk+1 and emitter line Ek. The first gate layer GTL1 can be composed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof.

[0149] The first interlayer dielectric layer 141 may be formed on the first gate layer GTL1. The first interlayer dielectric layer 141 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The first interlayer dielectric layer 141 may include multiple inorganic layers.

[0150] The second gate layer GTL2 can be formed on the first interlayer dielectric layer 141. The second gate layer GTL2 may include an initialization voltage line VIL and a first sub-supply voltage line VDDL1. The second gate layer GTL2 may be composed of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

[0151] The second interlayer dielectric layer 142 may be formed on the second gate layer GTL2. The second interlayer dielectric layer 142 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The second interlayer dielectric layer 142 may include multiple inorganic layers.

[0152] The data metal layer (DTL) can be formed on the second interlayer dielectric layer 142. The data metal layer (DTL) may include a j-th data line DLj, a second sub-supply voltage line VDDL2, a second gate electrode DT_G2 of the driving transistor DT, an anode connection electrode ANDE, and an initialization connection electrode VIE. The data metal layer (DTL) may be composed of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0153] Planarization layer 160 may be formed on data metal layer DTL to provide a flat surface for the horizontal difference between active layer ACT, first gate layer GTL1, second gate layer GTL2 and data metal layer DTL. Planarization layer 160 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0154] The protective layer 150 may also be formed between the data metal layer DTL and the planarization layer 160. The protective layer 150 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0155] Although Figure 15 In the example shown, the driving transistor DT and the first transistors ST1 to ST6 are implemented as top-gate transistors with their gate electrodes located above the active layer, but the disclosure is not limited to this. That is, the driving transistor DT and the first transistors ST1 to ST6 can be implemented as bottom-gate transistors with their gate electrodes located below the active layer, or as dual-gate transistors with their gate electrodes located above and below the active layer.

[0156] The first contact hole CNT1 can be a hole that penetrates the first interlayer dielectric layer 141 and the second interlayer dielectric layer 142, such as Figure 15As shown, the first gate electrode DT_G1 of the driving transistor DT is exposed via the first contact hole CNT1. The second gate electrode DT_G2 of the driving transistor DT can be connected to the first gate electrode DT_G1 of the driving transistor DT through the first contact hole CNT1.

[0157] The second contact hole CNT2 can be formed to pass through the gate insulating layer 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142, exposing the second electrode D2-1 of the second-1 transistor ST2-1 via the second contact hole CNT2. The first gate electrode DT_G1 of the driving transistor DT can be connected to the second electrode D2-1 of the second-1 transistor ST2-1 through the second contact hole CNT2.

[0158] The third contact hole CNT3 can be formed to pass through the gate insulating layer 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142, and the second electrode D1 of the first transistor ST1 can be exposed through the third contact hole CNT3. The j-th data line DLj can be connected to the second electrode D1 of the first transistor ST1 through the third contact hole CNT3.

[0159] The fourth contact hole CNT4 can be formed to pass through the gate insulating layer 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142. The second electrode D3-2 of the third-second transistor ST3-2 and the second electrode D4 of the fourth transistor ST4 can be exposed through the fourth contact hole CNT4. The initialization connection electrode VIE can be connected to the second electrode D3-2 of the third-second transistor ST3-2 and the second electrode D4 of the fourth transistor ST4 through the fourth contact hole CNT4.

[0160] The fifth contact hole CNT5 can be formed to pass through the second interlayer dielectric layer 142, and the initialization voltage line VIL can be exposed through the fifth contact hole CNT5. The initialization connection electrode VIE can be connected to the initialization voltage line VIL through the fifth contact hole CNT5.

[0161] The sixth contact hole CNT6 can be formed to pass through the gate insulating layer 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142, and the second electrode D6 of the sixth transistor ST6 can be exposed through the sixth contact hole CNT6. The anode connection electrode ANDE can be connected to the second electrode D6 of the sixth transistor ST6 through the sixth contact hole CNT6.

[0162] The seventh contact hole CNT7 can be formed to pass through the gate insulating layer 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142, exposing the first electrode S5 of the fifth transistor ST5 via the seventh contact hole CNT7. The second sub-supply voltage line VDDL2 can be connected to the first electrode S5 of the fifth transistor ST5 through the seventh contact hole CNT7.

[0163] The eighth contact hole CNT8 can be formed to pass through the second interlayer dielectric layer 142, and the first sub-supply voltage line VDDL1 can be exposed through the eighth contact hole CNT8. The second sub-supply voltage line VDDL2 can be connected to the first sub-supply voltage line VDDL1 through the eighth contact hole CNT8.

[0164] The anode contact hole AND_CNT can be formed to pass through the protective layer 150 and the planarization layer 160, and the anode connection electrode ANDE can be exposed through the anode contact hole AND_CNT.

[0165] The light-emitting element layer (EML) can be formed on the thin-film transistor layer (TFTL). The EML may include a light-emitting element 170 and a diaphragm layer 180.

[0166] The light-emitting element 170 and the embankment layer 180 can be formed on the planarization layer 160. Each light-emitting element 170 may include a first electrode 171, an organic emitting layer 172, and a second electrode 173.

[0167] The first electrode 171 can be formed on the planarization layer 160. The first electrode 171 can be connected to the anode connection electrode ANDE through the anode contact hole AND_CNT that penetrates the protective layer 150 and the planarization layer 160.

[0168] In a top-emitting organic light-emitting diode (OLED) in which light is emitted from the organic emitting layer 172 toward the second electrode 173, the first electrode 171 may be made of a metallic material with high reflectivity (such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO)). The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0169] A dam layer 180 may be formed on the planarization layer 160 to separate the first electrode 171, thereby defining the emission region EA of each of the sub-pixels SP1, SP2, and SP3. The dam layer 180 may be formed to cover the edge of the first electrode 171. The dam layer 180 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0170] In the emission region EA of each of the sub-pixels SP1, SP2 and SP3, the first electrode 171, the organic emission layer 172 and the second electrode 173 can be stacked one on top of the other in this order, such that holes from the first electrode 171 and electrons from the second electrode 173 can combine with each other in the organic emission layer 172 to emit light.

[0171] An organic emitting layer 172 can be formed on the first electrode 171 and the dam layer 180. The organic emitting layer 172 can include organic materials and emit light of a certain color. For example, the organic emitting layer 172 can include a hole transport layer, an organic material layer, and an electron transport layer. The organic emitting layer 172 of the first sub-pixel SP1 can emit light of a first color, the organic emitting layer 172 of the second sub-pixel SP2 can emit light of a second color, and the organic emitting layer 172 of the third sub-pixel SP3 can emit light of a third color. As another example, the organic emitting layers 172 of sub-pixels SP1, SP2, and SP3 can emit white light. In this case, the first sub-pixel SP1 can be superimposed with a color filter layer of the first color, the second sub-pixel SP2 can be superimposed with a color filter layer of the second color, and the third sub-pixel SP3 can be superimposed with a color filter layer of the third color. Here, the first color can be red, the second color can be green, and the third color can be blue.

[0172] The second electrode 173 can be formed on the organic emission layer 172. The second electrode 173 can be formed to cover the organic emission layer 172. The second electrode 173 can be a common layer formed across sub-pixels SP1, SP2, and SP3. A capping layer can be formed on the second electrode 173.

[0173] In a top-emitting organic light-emitting diode (OLED), the second electrode 173 can be formed of a transparent conductive material (TCP) that transmits light, such as ITO and IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 173 can be formed of a semi-transmissive conductive material, the light extraction efficiency can be improved by using a microcavity.

[0174] The encapsulation layer TFE can be formed on, for example, the light-emitting element layer (EML). The encapsulation layer TFE may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer (EML). Additionally, the encapsulation layer TFE may include at least one organic layer to protect the light-emitting element layer (EML) from foreign matter such as dust.

[0175] As another example, the second substrate can be disposed on the light-emitting element layer EML instead of the encapsulation layer TFE, such that the space between the light-emitting element layer EML and the second substrate can be empty or filled with a filler film. The filler film can be an epoxy filler film or a silicon filler film.

[0176] like Figure 15 and Figure 16As shown, in the second sub-pixel SP2, the length L2 of the first sub-supply voltage line VDDL1 overlapping with the second electrode DT_D of the driving transistor DT can be larger than the length L1 of the first sub-supply voltage line VDDL1 overlapping with the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1. In this document, the length of the overlap between the first sub-supply voltage line and the second electrode of the driving transistor refers to the length of the portion of the first sub-supply voltage line overlapping with the second electrode of the driving transistor. In the third sub-pixel SP3, the length of the overlap between the first sub-supply voltage line VDDL1 and the second electrode DT_D of the driving transistor DT can be substantially the same as the length L1 of the overlap between the first sub-supply voltage line VDDL1 and the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1.

[0177] Therefore, the area where the second electrode DT_D of the driving transistor DT in the second sub-pixel SP2 overlaps with the first sub-supply voltage line VDDL1 can be larger than the area where the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1 overlaps with the first sub-supply voltage line VDDL1. Furthermore, the area where the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1 overlaps with the first sub-supply voltage line VDDL1 can be substantially the same as the area where the second electrode DT_D of the driving transistor DT in the third sub-pixel SP3 overlaps with the first sub-supply voltage line VDDL1. Therefore, the capacitance of the first capacitor C1 of the second sub-pixel SP2 can be larger than the capacitance of the first capacitor C1 of the first sub-pixel SP1 and the capacitance of the first capacitor C1 of the third sub-pixel SP3. The capacitance of the first capacitor C1 of the first sub-pixel SP1 and the capacitance of the first capacitor C1 of the third sub-pixel SP3 can be equal to each other.

[0178] according to Figure 15 and Figure 16 In the embodiment shown, the capacitance of the first capacitor C1 of the second sub-pixel SP2 can be larger than the capacitance of the first capacitor C1 of the first sub-pixel SP1 and the first capacitor C1 of the third sub-pixel SP3. Charging the parasitic capacitance Cel in the second sub-pixel SP2 using the driving current Ids takes a longer time. Therefore, the charging current Ic flowing in the parasitic capacitance Cel of the second sub-pixel SP2 can be larger than the charging current Ic flowing in the parasitic capacitance Cel of the first sub-pixel SP1 and the parasitic capacitance Cel of the third sub-pixel SP3. Therefore, the time spent charging the parasitic capacitance Cel of the second sub-pixel SP2 can be reduced. Therefore, it is possible to avoid pixel failure to display the desired color due to differences in the timing between when the driving current Ids begins to flow in the light-emitting element EL in the sub-pixel. Therefore, it is possible to prevent or suppress the degradation of the image quality viewed by the user.

[0179] Figures 17 to 19 A plan view showing the first to third sub-pixels according to the disclosed embodiments is shown.

[0180] Besides the area where the second electrode DT_D of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 each have different driving transistor DT, which can be superimposed with the first sub-supply voltage line VDDL1, Figures 17 to 19 The embodiments shown can be compared with Figures 12 to 14 The embodiments shown are essentially the same.

[0181] Reference Figures 17 to 19 In the second sub-pixel SP2, the area where the second electrode DT_D of the driving transistor DT is superimposed on the first sub-supply voltage line VDDL1 can be larger than the area where the second electrode DT_D of the driving transistor DT is superimposed on the first sub-pixel SP1. Therefore, the capacitance of the first capacitor C1 of the second sub-pixel SP2 can be larger than the capacitance of the first capacitor C1 of the first sub-pixel SP1.

[0182] Furthermore, the area where the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1 is superimposed on the first sub-supply voltage line VDDL1 can be larger than the area where the second electrode DT_D of the driving transistor DT in the third sub-pixel SP3 is superimposed on the first sub-supply voltage line VDDL1. Therefore, the capacitance of the first capacitor C1 of the first sub-pixel SP1 can be larger than the capacitance of the first capacitor C1 of the third sub-pixel SP3.

[0183] like Figure 10As shown, the time spent charging the parasitic capacitance Cel using the driving current Ids is the longest in the second sub-pixel SP2, the second longest in the first sub-pixel SP1, and the shortest in the third sub-pixel SP3. Therefore, the capacitance of the first capacitor C1 in the second sub-pixel SP2 can be the largest, the capacitance of the first capacitor C1 in the first sub-pixel SP1 can be the second largest, and the capacitance of the first capacitor C1 in the third sub-pixel SP3 can be the smallest. Consequently, the charging current Ic flowing to the parasitic capacitance Cel in the second sub-pixel SP2 can be the largest, the charging current Ic flowing to the parasitic capacitance Cel in the first sub-pixel SP1 can be the second largest, and the charging current Ic flowing to the parasitic capacitance Cel in the third sub-pixel SP3 can be the smallest. As a result, the time spent charging the parasitic capacitance Cel can be reduced the most in the second sub-pixel SP2, and the time spent charging the parasitic capacitance Cel can be reduced the second most in the first sub-pixel SP1. Therefore, it is possible to overcome the problem that pixels cannot represent the desired color due to the difference in the timing of the start of the driving current Ids in the light-emitting element EL in the sub-pixel. Therefore, it is possible to prevent or suppress the degradation of the quality of the images viewed by the user.

[0184] Figure 20 It shows along Figure 17 A sectional view taken by line V-V'.

[0185] Along Figure 18 The schematic cross-sectional view taken by line VI-VI' can be compared with Figure 16 As shown along Figure 13 The schematic cross-sectional view taken along line III-III' is essentially the same; therefore, it is not necessary to show the view along line III-III'. Figure 18 A schematic cross-sectional view taken along line VI-VI'. Figure 19 The schematic cross-sectional view taken by line VII-VII' can be compared with Figure 16 As shown along Figure 12 The schematic cross-sectional view taken along line II-II' is essentially the same; therefore, it is not necessary to show the view along line II-II'. Figure 19 A schematic cross-sectional view taken along line VII-VII'. Figures 17 to 19 The schematic cross-sectional view taken by line I-I' can be compared with Figure 15 As shown along Figure 12 The schematic cross-sectional view taken along line I-I' is essentially the same; therefore, it is not necessary to show the view along... Figures 17 to 19 A schematic cross-sectional view taken from line I-I'.

[0186] Reference Figure 16 and Figure 20 , Figure 20 It can be along Figure 17A schematic cross-sectional view taken by line V-V' and can be compared with Figure 16 Along shown in Figure 12 The cross-sectional views taken from line II-II' are essentially the same. In the second sub-pixel SP2, the length L2 of the first sub-supply voltage line VDDL1 overlapping with the second electrode DT_D of the driving transistor DT can be larger than the length L1' of the first sub-supply voltage line VDDL1 overlapping with the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1. Similarly, the length L1' of the first sub-supply voltage line VDDL1 overlapping with the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1 can be larger than the length L of the first sub-supply voltage line VDDL1 overlapping with the second electrode DT_D of the driving transistor DT in the third sub-pixel SP3.

[0187] Therefore, the area where the second electrode DT_D of the driving transistor DT in the second sub-pixel SP2 is superimposed on the first sub-supply voltage line VDDL1 can be larger than the area where the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1 is superimposed on the first sub-supply voltage line VDDL1. Therefore, the capacitance of the first capacitor C1 of the second sub-pixel SP2 can be larger than the capacitance of the first capacitor C1 of the first sub-pixel SP1.

[0188] Furthermore, the area where the second electrode DT_D of the driving transistor DT in the first sub-pixel SP1 is superimposed on the first sub-supply voltage line VDDL1 can be larger than the area where the second electrode DT_D of the driving transistor DT in the third sub-pixel SP3 is superimposed on the first sub-supply voltage line VDDL1. Therefore, the capacitance of the first capacitor C1 of the first sub-pixel SP1 can be larger than the capacitance of the first capacitor C1 of the third sub-pixel SP3.

[0189] according to Figure 20In the embodiment shown, the time spent charging the parasitic capacitance Cel using the driving current Ids is the longest in the second sub-pixel SP2, the second longest in the first sub-pixel SP1, and the shortest in the third sub-pixel SP3. Therefore, the capacitance of the first capacitor C1 in the second sub-pixel SP2 can be the largest, the capacitance of the first capacitor C1 in the first sub-pixel SP1 can be the second largest, and the capacitance of the first capacitor C1 in the third sub-pixel SP3 can be the smallest. Consequently, the charging current Ic flowing to the parasitic capacitance Cel in the second sub-pixel SP2 can be the largest, the charging current Ic flowing to the parasitic capacitance Cel in the first sub-pixel SP1 can be the second largest, and the charging current Ic flowing to the parasitic capacitance Cel in the third sub-pixel SP3 can be the smallest. As a result, the time spent charging the parasitic capacitance Cel can be reduced the most in the second sub-pixel SP2 and the second most in the first sub-pixel SP1. Therefore, it is possible to overcome the problem that the pixel cannot represent the desired color due to the difference in the timing of the start of the driving current Ids in the light-emitting element EL in the sub-pixel. Therefore, it is possible to prevent or suppress the degradation of the quality of the images viewed by the user.

[0190] While exemplary embodiments have been described above, they are not intended to describe all possible forms. Rather, the language used in this specification is descriptive rather than restrictive, and it is understood that various changes may be made without departing from the spirit and scope of the disclosure. Furthermore, features of various embodiments may be combined to further form undisclosed embodiments.

Claims

1. A light-emitting display device, the light-emitting display device comprising: The first sub-pixel emits light of the first color; as well as The second sub-pixel emits light of the second color. Each of the first sub-pixel and the second sub-pixel includes: a driving transistor, including a first electrode, a second electrode, and a gate electrode, and configured to control the current flowing from the first electrode to the second electrode according to a data voltage applied to the gate electrode; a light-emitting element connected to the second electrode of the driving transistor; and a first capacitor disposed between a first sub-supply voltage line and the second electrode of the driving transistor, wherein a first supply voltage is applied to the first sub-supply voltage line, and the first sub-supply voltage line is configured to overlap with the second electrode of the driving transistor. Wherein, the capacitance of the first capacitor of the first sub-pixel and the capacitance of the first capacitor of the second sub-pixel are selectively determined to correspond to the amount of overlap between the first sub-supply voltage line of the first sub-pixel and the second electrode of the driving transistor in the second sub-pixel, respectively, and Wherein, the capacitance of the first capacitor of the first sub-pixel is less than the capacitance of the first capacitor of the second sub-pixel.

2. The light-emitting display device according to claim 1, wherein, In the first sub-pixel, the area where the first sub-supply voltage line overlaps with the second electrode of the driving transistor is smaller than the area where the first sub-supply voltage line overlaps with the second electrode of the driving transistor in the second sub-pixel.

3. The light-emitting display device according to claim 1, wherein, In the first sub-pixel, the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor is smaller than the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor in the second sub-pixel.

4. The light-emitting display device according to claim 1, further comprising: The scan line extends in the first direction; as well as The data cable extends in a second direction that intersects the first direction. The first sub-supply voltage line extends in the first direction.

5. The light-emitting display device according to claim 4, further comprising: The second sub-supply voltage line is electrically connected to the first sub-supply voltage line. The second sub-supply voltage line extends in the second direction.

6. The light-emitting display device according to claim 1, wherein, Each of the first sub-pixel and the second sub-pixel further includes a second capacitor disposed between the first sub-supply voltage line and the gate electrode of the driving transistor, and In each of the first sub-pixel and the second sub-pixel, the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.

7. The light-emitting display device according to claim 1, further comprising: The third sub-pixel emits light of the third color. The third sub-pixel includes a driving transistor, a light-emitting element, a first sub-supply voltage line, and a first capacitor. Wherein, the capacitance of the first capacitor of the third sub-pixel is smaller than the capacitance of the first capacitor of the second sub-pixel.

8. The light-emitting display device according to claim 7, wherein, In the third sub-pixel, the area where the first sub-supply voltage line overlaps with the second electrode of the driving transistor is smaller than the area where the first sub-supply voltage line overlaps with the second electrode of the driving transistor in the second sub-pixel.

9. The light-emitting display device according to claim 7, wherein, In the third sub-pixel, the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor is smaller than the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor in the second sub-pixel.

10. The light-emitting display device according to claim 7, wherein, The capacitance of the first capacitor of the third sub-pixel is equal to the capacitance of the first capacitor of the first sub-pixel.

11. The light-emitting display device according to claim 10, wherein, In the third sub-pixel, the area where the first sub-supply voltage line overlaps with the second electrode of the driving transistor is equal to the area where the first sub-supply voltage line overlaps with the second electrode of the driving transistor in the first sub-pixel.

12. The light-emitting display device according to claim 10, wherein, In the third sub-pixel, the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor is equal to the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor in the first sub-pixel.

13. The light-emitting display device according to claim 7, wherein, The capacitance of the first capacitor of the third sub-pixel is smaller than the capacitance of the first capacitor of the first sub-pixel.

14. The light-emitting display device according to claim 13, wherein, In the third sub-pixel, the area where the first sub-supply voltage line overlaps with the second electrode of the driving transistor is smaller than the area where the first sub-pixel overlaps with the second electrode of the driving transistor.

15. The light-emitting display device according to claim 13, wherein, In the third sub-pixel, the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor is smaller than the length of the first sub-supply voltage line overlapping with the second electrode of the driving transistor in the first sub-pixel.

16. The light-emitting display device according to claim 1, further comprising: At least one insulating layer is disposed between the second electrode of the driving transistor and the first sub-supply voltage line.

17. The light-emitting display device according to claim 16, wherein, The at least one insulating layer includes: A gate insulating layer is disposed on the second electrode of the driving transistor; and An interlayer dielectric layer is disposed on the gate electrode of the driving transistor.

18. The light-emitting display device according to claim 17, wherein, The gate electrode of the driving transistor is disposed on the gate insulating layer.

19. The light-emitting display device according to claim 17, wherein, The first sub-supply voltage line is disposed on the interlayer dielectric layer.

20. The light-emitting display device according to claim 17, wherein, The second electrode of the driving transistor is covered by the gate insulating layer.

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