Processor, instruction execution device and method

Abstract

The present invention discloses a method for executing a data storage instruction in a processor, comprising the steps of: splitting the data storage instruction into an address pseudo-instruction and a data pseudo-instruction, wherein the address pseudo-instruction relates to the address operand of the data storage instruction, and the data pseudo-instruction relates to the data operand of the data storage instruction; executing the address pseudo-instruction to calculate the data storage address corresponding to the address operand; executing the data pseudo-instruction to obtain the data content corresponding to the data operand; and storing the obtained data content in the data storage address calculated in the data storage area. The present invention also discloses a corresponding instruction execution device, a processor including the execution device, and a system on chip.

Description

Technical Field

[0001] The present invention relates to the field of processors, and in particular to the field of instruction execution in processors. Background Art

[0002] The basic work of the processor is to execute the stored instruction sequence, that is, the program. The essence of program execution is a process of continuously fetching instructions, analyzing instructions, and executing instructions. Instructions are fetched from the memory where the program is stored, decoded and executed, and the results of instruction execution are saved. This cycle repeats until a shutdown instruction is encountered. The processor can execute instructions in a pipeline manner. Pipeline conflicts that occur during pipeline execution of instructions are often an important factor affecting processor performance.

[0003] Data conflicts in pipeline conflicts often occur between two instructions with data dependencies, especially common in storage and load instructions. A typical application scenario is memory copy, that is, the program needs to move data from one address range to another address range, and a large number of memory load / store operations are required for the two addresses at the same time. The data that each storage instruction needs to write depends on the data moved by the previous load instruction. Load instructions sometimes take a long time to read data, which causes the storage instruction to be unable to perform memory write operations due to the inability to obtain data, thereby affecting the execution efficiency of the storage instruction and the entire program flow.

[0004] Therefore, a new processor instruction execution scheme is needed to effectively solve the execution efficiency problems caused by data conflicts. Summary of the invention

[0005] To this end, the present invention provides a new processor and an instruction execution method therein, in an effort to solve or at least alleviate at least one of the above problems.

[0006] According to one aspect of the present invention, a method for executing a data storage instruction in a processor is provided, comprising the steps of: splitting the data storage instruction into an address pseudo-instruction and a data pseudo-instruction, the address pseudo-instruction involving an address operand of the data storage instruction, and the data pseudo-instruction involving a data operand of the data storage instruction; executing the address pseudo-instruction to calculate a data storage address corresponding to the address operand; executing the data pseudo-instruction to obtain data content corresponding to the data operand; and storing the obtained data content in the data storage address calculated in the data storage area.

[0007] Optionally, the method according to the present invention also includes the steps of: after calculating the data storage address, storing the address pseudo-instructions and the data storage address; and after obtaining the data content, associating the obtained data content and the stored data storage address according to the correspondence between the address pseudo-instructions and the data pseudo-instructions, so as to store the obtained data content at the calculated data storage address.

[0008] Optionally, the method according to the present invention also includes the steps of: storing address pseudo-instructions and data loading instructions in a load / store transmit queue; and storing data pseudo-instructions in a sub-storage transmit queue different from the load / store transmit queue; wherein the step of executing the address pseudo-instruction to calculate the data storage address includes transmitting the address pseudo-instruction from the load / store transmit queue to the execution unit for execution, and the step of executing the data pseudo-instruction to obtain data content includes transmitting the data pseudo-instruction from the sub-storage transmit queue to the execution unit for execution.

[0009] Optionally, the method according to the present invention further comprises the steps of: acquiring a data storage instruction, and decoding the data storage instruction to determine a data operand and an address operand in the data storage instruction.

[0010] Optionally, in the instruction execution method according to the present invention, the data content includes any one or more of the following: a register value, a calculation result of a calculation unit, and data from the data storage area.

[0011] According to another aspect of the present invention, there is provided an instruction execution device, comprising: an instruction splitting unit, adapted to split a data storage instruction into an address pseudo-instruction and a data pseudo-instruction, the address pseudo-instruction involving an address operand of the data storage instruction, and the data pseudo-instruction involving a data operand of the data storage instruction; an instruction address generating unit, adapted to execute the address pseudo-instruction to calculate a data storage address corresponding to the address operand; a storage data acquisition unit, adapted to execute the data pseudo-instruction to acquire data content corresponding to the data operand; and a memory operation unit, adapted to store the acquired data content at the data storage address calculated in the data storage area.

[0012] According to another aspect of the present invention, a processor is provided, comprising the instruction execution device according to the present invention.

[0013] According to yet another aspect of the present invention, a system on chip is provided, comprising the processor according to the present invention.

[0014] According to the solution of the present invention, by splitting the data storage instruction into an address pseudo-instruction involving the data storage address and a data pseudo-instruction involving the data content, and allowing the address pseudo-instruction and the data loading instruction to be executed similarly, and only when the address pseudo-instruction is executed to obtain the data content, the data storage process is finally performed, so that the existing processing pipeline process will not be blocked due to data correlation. On the other hand, since the processing for the address pseudo-instruction is the same as the processing for the existing instruction, and only the processing logic for the data pseudo-instruction is additionally added, this does not complicate the design of the pipeline. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The above and other purposes, features and advantages of the present disclosure will become more apparent by reading the following detailed description in conjunction with the accompanying drawings. Throughout the present disclosure, the same reference numerals generally refer to the same parts or elements.

[0016] Figure 1 A schematic diagram of a processor 100a according to an embodiment of the present invention is shown;

[0017] Figure 2 A schematic diagram of a processor 100b according to another embodiment of the present invention is shown;

[0018] Figure 3 A schematic diagram showing a method 300 for executing a data storage instruction according to another embodiment of the present invention; and

[0019] Figure 4 FIG. 4 is a schematic diagram of a system on chip 400 according to another embodiment of the present invention. DETAILED DESCRIPTION

[0020] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0021] Figure 1A schematic diagram of a processor 100a according to an embodiment of the present invention is shown. The processor 100a includes an instruction execution device 200 and a processor resource 120. The instruction execution device 200 obtains and executes instructions from an instruction storage space 130 coupled to the processor 100a. When executing instructions, the instruction execution device 200 can interact with the processor resource 120, for example, write some values ​​into a register 122 of the processor resource 120, and obtain content from the register 122 to control the execution of instructions. The instruction execution device 200 can also store some data in the on-chip cache 124 of the processor resource 120 or in the external storage space 140 coupled to the processor 100a during the execution of instructions, or load data from the on-chip cache 124 or the external storage space 140.

[0022] The processor 100a supports a specific instruction set. The instruction set defines a set of instruction types that the processor 100a can execute. The instruction set defines various types of instructions. An instruction generally includes an operation code and an operand. The operation code indicates what operation the instruction performs. The source operand in the operand indicates the source of data when the instruction is executed, and the destination operand indicates the execution result of the instruction. The source operand and the destination operand often involve the use of registers. For example, the source operand can use a value stored in a register, or a value at a storage space location stored in a register. The register associated with the source operand is called a source register. Similarly, the destination operand can use a register to save the execution result, or store the execution result in a storage location indicated by the value in the register. The register associated with the destination operand is called a destination register.

[0023] One type of instruction is a data operation related instruction, which includes a data storage instruction and a data loading instruction.

[0024] The data storage instruction is used to write data to the on-chip cache 124 or the external storage space 140, so the source operand in the data storage instruction includes an address operand related to the storage location of the data to be written and a data operand related to the data content to be written, but no destination operand.

[0025] The data load instruction is used to read data from the on-chip cache 124 or the external storage space 140, so the source operand of the data load instruction includes an address operand related to the storage location of the data to be read, and the destination operand includes a data operand for storing the content of the read data.

[0026] The instruction execution device 200 includes an instruction fetch unit 210. The instruction fetch unit 210 fetches the instruction to be executed from the instruction storage space 130 and sends the fetched instruction to the instruction decoding unit 220. The instruction decoding unit 220 decodes the instruction and determines the instruction type and the operands in the instruction. The instruction decoding unit 220 can therefore determine instructions related to data operations, such as data loading instructions and data storage instructions. The instruction decoding unit 220 can also determine the source operand in the data storage instruction, and further determine the data operand and address operand in the source operand.

[0027] The instruction decoding unit 220 sends the determined data storage instruction to the instruction splitting unit 230. The instruction splitting unit 230 splits the data storage instruction into two parts. In order to be processed in the instruction mode later, the two parts have the form of instructions and can be called pseudo instructions. As mentioned above, the operands of the data storage instruction include operands related to the storage address and operands related to the data content. Therefore, the instruction splitting unit 230 can split the data storage instruction into an address pseudo instruction st.addr related to the storage address (i.e., related to the address operand), and a data pseudo instruction st.data related to the data content (i.e., related to the data operand). The present invention is not limited to the specific forms of the address pseudo instruction and the data pseudo instruction. As long as the address pseudo instruction st_addr contains the address operand part in the data storage instruction, the data pseudo instruction st_data includes the data operation part in the data storage instruction, and st_addr and st_data can be recognized and processed by the subsequent instruction processing part, it is within the protection scope of the present invention.

[0028] The instruction address generation unit 252 receives the address pseudo instruction st_addr split out by the instruction splitting unit 230, and processes the pseudo instruction to calculate the data storage address corresponding to the address operand in the pseudo instruction st_addr. According to one embodiment of the present invention, the instruction address generation unit 252 also obtains the data loading instruction from the instruction decoding unit 220, and calculates the corresponding data loading address for the address operand in the data loading instruction.

[0029] The storage data acquisition unit 254 receives the data pseudo instruction st_data split by the instruction splitting unit 230, and processes the data pseudo instruction st_data to obtain data content corresponding to the data operand.

[0030] The data content can come from multiple data sources. According to one embodiment, the storage data acquisition unit 254 can obtain data from the register of the processor resource 120. According to another embodiment, the storage data acquisition unit 254 can obtain data from other execution units 260. Other execution units 260 include various operation units, such as integer operation units and vector operation units. These operation units perform operation operations to generate data and provide them to the storage data acquisition unit 254. According to another embodiment, the storage data acquisition unit 254 can also obtain data from the on-chip cache 124 or the external storage space 140. The present invention is not limited to the specific form of the data source, and any method that can generate or obtain data by the processor 100a is within the protection scope of the present invention.

[0031] After the storage data acquisition unit 254 acquires the data content according to the data pseudo instruction st_data, the memory operation unit 256 stores the acquired data content at the data storage address calculated by the instruction address generation unit 252. The memory operation unit 256 can write the data to the on-chip cache 124 or the external storage space 140. According to one embodiment, the memory operation unit 256 can first write the data to the on-chip cache 124, and when the space in the cache 124 is insufficient or other conditions are met, the data can be written from the on-chip cache 124 to the external storage space 140 via the bus interface unit 256_1.

[0032] The present invention is not limited to the specific form of the memory operation unit 256, and all methods that can write data content into the on-chip cache and further write it into the external storage space are within the protection scope of the present invention.

[0033] In addition, for data loading instructions, since there is no need to wait for obtaining data content from the storage data acquisition unit 254, after the instruction address generation unit 252 calculates the data storage address for the data loading instruction, the content operation unit 256 can directly read data from the calculated data storage address to complete the execution of the data loading instruction.

[0034] Likewise, the storage data acquisition unit 254 may also acquire data from the on-chip cache 124 or the external storage space 140 via the memory operation unit 256 , so as to acquire data content for the data pseudo instruction st_data.

[0035] According to an embodiment of the present invention, it is considered that the storage data acquisition unit 254 needs a long time to obtain data content from various data sources, especially from the external storage space 140, and at this time the instruction address generation unit 252 has calculated the data storage address for the address pseudo instruction st_addr. To this end, the instruction execution device 200 may also include a storage instruction buffer 258. The storage instruction buffer 250 is coupled to the instruction address generation unit 252. After the instruction address generation unit 252 calculates the data storage address corresponding to the address operand for the address pseudo instruction st_addr, the address pseudo instruction st_addr and the calculated data storage address can be stored in the storage instruction buffer 250.

[0036] After the storage data acquisition unit 254 acquires the data content according to the data pseudo-instruction st_data, the data pseudo-instruction st_data and the corresponding address pseudo-instruction st_addr can be merged in the storage instruction buffer 250. The information merging includes associating the acquired data content and the stored data storage address according to the correspondence between the address pseudo-instruction and the data pseudo-instruction. In other words, through the information merging, the various parts of the data storage instruction split at the instruction splitting unit 230 can be re-merged together, and all the work before the data storage operation has been completed. In this way, after the information merging, the memory operation unit 256 can store the acquired data content at the calculated data storage address.

[0037] In addition, when the processor 100a performs instruction processing in a pipeline manner, it is necessary to schedule the execution of the instruction after the instruction is decoded. For this purpose, the processor 100a also includes an instruction emission unit for scheduling after decoding. For high-performance processors, the parallel operation of instructions plays an indispensable role, so how to efficiently allocate instructions to different execution units is crucial, and the instruction emission unit plays the role of controlling or scheduling instructions.

[0038] According to one embodiment of the present invention, the processor 100a includes a load / store emission unit 242 and a sub-storage emission unit 244. The load / store emission unit 242 is coupled to the instruction splitting unit 230, receives the address pseudo instruction st_addr obtained by the instruction splitting unit 230 splitting the data storage instruction, and stores the instruction in the emission queue, so that the instruction is emitted to the instruction address generation unit 252 for execution when the condition is met. According to one embodiment, the load / store emission unit 242 is also coupled to the instruction decoding unit 220 to obtain the data loading instruction, and stores the data loading instruction and the address pseudo instruction st_addr together in the emission queue, and performs the same subsequent processing.

[0039] The sub-storage emission unit 244 is coupled to the instruction splitting unit 230, receives the data pseudo instruction st_data obtained by the instruction splitting unit 230 splitting the data storage instruction, and stores the instruction in the emission queue so as to emit the instruction to the storage data acquisition unit 254 for execution when conditions are met.

[0040] According to an embodiment of the present invention, after the instruction is scheduled for execution, there may be multiple data pseudo instructions st_data to be executed simultaneously in the storage data acquisition unit 254. The storage data acquisition unit 254 acquires data content for one data pseudo instruction st_data each time, which greatly simplifies the structure of the storage data acquisition unit 254. Since the data storage instructions are split, this simplified structure does not affect the execution efficiency of the data storage instructions.

[0041] according to Figure 1 The structural scheme of the processor 100a given, especially the structural scheme of the instruction processing device 200, uses an instruction splitting unit to split the data and address parts of the data storage instruction into two pseudo-instructions respectively, and processes the address part of the data storage instruction and the data loading instruction together, while the data part can be processed with lower resource overhead through pseudo-instructions. This solves the instruction processing blocking problem caused by data correlation without losing performance.

[0042] Figure 2 FIG. 1 is a schematic diagram of a processor 100 b according to another embodiment of the present invention. Figure 2 The processor 100b shown is Figure 1 Further description of the processor 100a shown, therefore Figure 2 In, with Figure 1 The same or similar parts are denoted by the same reference numerals and will not be described in detail.

[0043] Figure 2 The instruction issuing unit 240 and the instruction executing unit 260 are also included. The instruction issuing unit 240 includes a load / store issuing unit 242 and a sub-store issuing unit 244. For instructions related to data operations, as mentioned above, Figure 1 As described above, the data loading instruction decoded by the instruction decoding unit 220 and the address pseudo instruction st_addr obtained by splitting the data storage instruction by the instruction splitting unit 230 are sent to the load / store emission unit 242 for subsequent processing, and the data pseudo instruction st_data obtained by splitting the data storage instruction by the instruction splitting unit 230 is sent to the sub-storage emission unit 244 for subsequent processing. As for other instructions decoded by the instruction decoding unit 220, they can be sent to other components in the instruction emission unit 240 for processing.

[0044] The instruction execution unit 260 includes the memory execution unit 250 and other execution units 262. The other execution units 262 include floating point operation units, integer operation units, etc., and perform other operations in addition to data storage and loading operations.

[0045] The memory execution unit 250 includes the above reference Figure 1 The instruction address generation unit 252, the storage data acquisition unit 254, the memory operation unit 256 and the storage instruction buffer 258 are described above. Figure 1 The data loading instruction and the data operation instruction are processed.

[0046] Figure 2 The processor 100b shown describes the various components in the instruction processing device 200 in a pipeline manner. These components are divided according to functional logic and can be implemented in different hardware methods according to the functions to be implemented. All specific hardware implementation methods are within the protection scope of the present invention.

[0047] Figure 1 and 2 The processors 100a and 100b shown may be used as part of a processing system. The processing system may include other components, such as various interrupt sources, coprocessors, and storage devices, thereby constructing a fully functional processing system around the processor. According to one embodiment, such a processing system is, for example, a SoC (system on chip).

[0048] Figure 3 A schematic diagram of a method 300 for executing a data storage instruction according to another embodiment of the present invention is shown. Figure 3 The method shown is suitable for Figure 1 and 2 The processor shown in the figure, in particular, the instruction execution device 200 is executed. Figure 3 As shown, the method 300 is adapted to step S310 .

[0049] In step S310, the data storage instruction is split into address pseudo-instructions involving address operands of the data storage instruction and data pseudo-instructions involving data operands of the data storage instruction. As described above, the processor can execute various types of instructions defined in the instruction set it supports. Instructions related to data operations include data storage instructions that write data to the on-chip cache 124 or the external storage space 140 and data loading instructions that read data from the on-chip cache 124 or the external storage space 140. The source operand in the data storage instruction includes an address operand related to the storage location of the data to be written, and the source operand in the data storage instruction also includes a data operand related to the content of the data to be written. By analyzing the data storage instruction, the data storage instruction can be split into the address pseudo-instruction st_addr and the data pseudo-instruction st_data according to a predetermined rule. Step S310 can be referred to above. Figure 1 Or it is executed in the instruction splitting unit 230 described in 2.

[0050] Subsequently, in step S320, the address pseudo instruction st_addr obtained by splitting step S310 is processed to calculate the data storage address corresponding to the address operand. Step S320 can be referred to above. Figure 1 Or it is executed in the instruction address generation unit 252 described in 2.

[0051] In step S330, the data pseudo instruction st_data obtained by splitting in step S310 is processed to obtain the data content corresponding to the data operand. Step S330 can be referred to above. Figure 1 Or it is executed in the storage data acquisition unit 254 shown in 2.

[0052] Optionally, step S330 may obtain data content from multiple data sources. According to one embodiment, data may be obtained from registers of the processor resource 120. According to another embodiment, the result of the operation may be obtained from other execution units as the data content. According to yet another embodiment, data may also be obtained from the on-chip cache 124 or the external storage space 140. The present invention is not limited to the specific form of the data source, and any method by which the processor 100a can generate or obtain data is within the protection scope of the present invention.

[0053] Then, in step S340, the data content acquired in step S330 is stored at the data storage address calculated in step S320. Step S340 can be referred to above. Figure 1 Or it is executed in the memory operation unit 256 described in step 2. After step S340 is completed, the execution of the data storage instruction is completed.

[0054] According to an embodiment of the present invention, it is considered that it takes a long time to obtain data content from various data sources, especially from the external storage space 140 in step S330, and the speed of calculating the data storage address for the address pseudo instruction st_addr in step S320 is very fast. For this reason, it is necessary to store the calculation result of step S320 to wait for the data content to be obtained in step S330. The method 300 also includes step S350. In step S350, the address pseudo instruction st_addr and the data storage address calculated in step S320 are stored. At the same time, in step S350, after the data content is obtained for the data pseudo instruction st_data in step S330, the data pseudo instruction st_data and the corresponding address pseudo instruction st_addr can be merged. The information merging includes associating the obtained data content and the stored data storage address according to the corresponding relationship between the address pseudo instruction and the data pseudo instruction. In other words, through the information merging, the various parts of the data storage instruction split at step S310 can be re-merged together, and all the work before the data storage operation has been completed. In this way, after the information is merged, the acquired data content can be stored at the calculated data storage address in step S340.

[0055] In addition, when the processor processes instructions in a pipeline manner, it is necessary to schedule the execution of instructions after decoding the instructions. For high-performance processors, the parallel operation of instructions plays an indispensable role. Therefore, how to efficiently distribute instructions to different execution units is crucial. The instruction issuance operation plays the role of controlling or scheduling instructions.

[0056] Therefore, the method 300 further includes steps S360 and S370. In step S360, the address pseudo instruction st_addr obtained by splitting in step S310 is stored in a corresponding emission queue, such as a load / store emission queue, so that when the emission condition is met, it is taken out from the emission queue to be emitted to step S320 to calculate the corresponding data storage address. In step S360, the data load instruction is also processed similarly, so that the data load instruction and the address pseudo instruction st_addr are processed in a substantially identical manner.

[0057] In step S370, the data pseudo instruction st_data obtained by splitting in step S310 is stored in a corresponding transmission queue, such as a sub-storage transmission queue, so that when the transmission conditions are met, it is transmitted from the transmission queue to step S330 for execution to obtain data content.

[0058] In addition, before splitting the data storage instruction, the method 300 may further include step S380. In step S380, the instruction is acquired and decoded, so as to determine the data storage instruction of the type related to data operation, and determine the data operand and address operand in the data storage instruction, so as to perform instruction splitting processing in step S310.

[0059] Figure 4 FIG. 4 is a schematic diagram of a system on chip (SoC) 400 according to an embodiment of the present invention. The system on chip 400 includes a reference Figure 1 and 2 The processor 100, various interrupt sources 420, storage space 430 and coprocessor 440, etc. The system on chip 400 can be integrated on a circuit board and constitute a relatively complete processing system. The interrupt source 420 is, for example, various peripheral interfaces, which receive external inputs and output the output of the processor 100 after processing. The storage space 430 can provide an external storage space for the processor 100, which is used to store the code to be executed by the processor 100 and the various output data generated. The coprocessor 440 is a special processor used to perform special processing tasks, such as image operations.

[0060] It should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0061] Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0062] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0063] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0064] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0065] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0066] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative, not restrictive, with respect to the scope of the present invention, which is defined by the appended claims.

Claims

1. A method for executing a data storage instruction in a processor, comprising the steps of: Splitting the data storage instruction into an address pseudo instruction and a data pseudo instruction, wherein the address pseudo instruction relates to an address operand of the data storage instruction and the data pseudo instruction relates to a data operand of the data storage instruction; storing the address pseudo instruction and the data load instruction in a load / store issue queue; as well as storing the data pseudo instruction in a sub-store issue queue different from the load / store issue queue; Executing the address pseudo instruction to calculate a data storage address corresponding to the address operand; Executing the data pseudo instruction to obtain data content corresponding to the data operand; as well as The acquired data content is stored in the data storage address calculated in the data storage area; The step of executing the address pseudo instruction to calculate the data storage address corresponding to the address operand comprises transmitting the address pseudo instruction from the load / store issue queue to the execution unit for execution; and the step of executing the data pseudo instruction to obtain data content corresponding to the data operand comprises transmitting the data pseudo instruction from the sub-storage issue queue to an execution unit for execution; The method further comprises the steps of: The data loading instruction is issued from the load / store issue queue to an instruction address generation unit for execution to calculate a data loading address.

2. The method according to claim 1, further comprising the steps of: After calculating the data storage address, storing the address pseudo instruction and the data storage address; and After acquiring the data content, the acquired data content and the stored data storage address are associated according to the correspondence between the address pseudo instruction and the data pseudo instruction, so as to store the acquired data content at the calculated data storage address.

3. The method according to any one of claims 1 to 2, further comprising the steps of: The data storage instruction is acquired, and the data storage instruction is decoded to determine a data operand and an address operand in the data storage instruction.

4. The method according to claim 3, wherein the data content comprises any one or more of the following: Register values, calculation results of the arithmetic unit, and data from the data storage area.

5. An instruction execution device in a processor, comprising: an instruction splitting unit adapted to split a data storage instruction into an address pseudo instruction and a data pseudo instruction, wherein the address pseudo instruction relates to an address operand of the data storage instruction, and the data pseudo instruction relates to a data operand of the data storage instruction; A load / store issuing unit, coupled to the instruction splitting unit and adapted to receive the address pseudo instruction and store it for issuing and executing; as well as a sub-storage emission unit, coupled to the instruction splitting unit and adapted to receive the data pseudo-instruction and store it for emission execution; an instruction address generating unit, adapted to execute the address pseudo instruction to calculate a data storage address corresponding to the address operand; a storage data acquisition unit adapted to execute the data pseudo instruction to acquire data content corresponding to the data operand; as well as A memory operation unit, adapted to store the acquired data content at a data storage address calculated in the data storage area; wherein the load / store issuing unit is coupled to the instruction address generating unit so as to issue the address pseudo instruction to the instruction address generating unit so as to calculate the data storage address, and The sub-storage issuing unit is coupled to the storage data acquisition unit so as to issue the data pseudo instruction to the storage data acquisition unit so as to acquire data content corresponding to the data operand; The load / store issuing unit is coupled to the instruction decoding unit so as to issue the data loading instruction to the instruction address generating unit so as to calculate the data loading address.

6. The instruction execution device according to claim 5, further comprising: A storage instruction buffer, coupled to the instruction address generation unit, adapted to store the address pseudo instruction and the calculated data storage address; as well as The storage instruction buffer is also suitable for associating the acquired data content and the stored data storage address according to the correspondence between the address pseudo-instruction and the data pseudo-instruction after the storage data acquisition unit acquires the data content, so that the memory operation unit can store the acquired data content at the calculated data storage address.

7. The instruction execution device according to any one of claims 5 to 6, further comprising: an instruction fetch unit, adapted to fetch data operation instructions, the data operation instructions including data loading instructions and the data storage instructions; The instruction decoding unit is adapted to decode the acquired instruction to determine the data storage instruction in the instruction, and determine the data operand and address operand in the data storage instruction so as to send the data storage instruction to the instruction splitting unit. 8 . The instruction execution device according to claim 7 , wherein the storage data acquisition unit is adapted to acquire the data content via the memory operation unit. 9 . The instruction execution device according to claim 7 , further comprising an operation unit, wherein the storage data acquisition unit is adapted to acquire an operation result from the operation unit as the data content. 10 . The instruction execution device according to claim 7 , wherein the storage data acquisition unit is adapted to acquire a register value as the data content.

11. The instruction execution device according to claim 7, wherein the storage data acquisition unit is adapted to acquire data content for one data pseudo instruction each time.

12. A processor, comprising: An instruction execution device as claimed in any one of claims 5 to 11.

13. A processor, comprising: an instruction fetch unit adapted to fetch instructions to be executed; an instruction decoding unit adapted to decode the acquired instruction to determine the type and operand of the instruction, the instruction comprising a data load instruction of a data load type and a data storage instruction of a data storage type; an instruction splitting unit, adapted to split the data storage instruction into an address pseudo instruction and a data pseudo instruction, wherein the address pseudo instruction relates to an address operand of the data storage instruction and the data pseudo instruction relates to a data operand of the data storage instruction; An instruction issuing unit, adapted to store the decoded instructions for issuing and executing, the instruction issuing unit comprising: A load / store issuing unit, coupled to the instruction decoding unit and the instruction splitting unit, and adapted to receive the decoded data loading instruction and the address pseudo instruction and store them for issuing and executing; and a sub-storage issuing unit, coupled to the instruction splitting unit and adapted to receive the data pseudo-instruction and store it for issuing and executing; and An instruction execution unit, adapted to execute instructions issued from the instruction issuance unit, the instruction execution unit comprising a memory execution unit adapted to perform data loading and storage operations, the memory execution unit comprising: an instruction address generating unit adapted to receive the instruction emitted by the load / store emission unit, and execute the data loading instruction to calculate the data loading address, and execute the address pseudo instruction to calculate the data storage address corresponding to the address operand; a storage data acquisition unit adapted to receive the instruction emitted by the sub-storage emission unit and execute the data pseudo instruction to acquire data content corresponding to the data operand; a storage instruction buffer, coupled to the instruction address generation unit, adapted to store the address pseudo instruction and the calculated data storage address; and adapted to associate the acquired data content with the stored data storage address according to the corresponding relationship between the address pseudo instruction and the data pseudo instruction after the storage data acquisition unit acquires the data content, and The memory operation unit is adapted to store the acquired data content at the data storage address calculated in the data storage area.

14. A system on chip, comprising: A processor as claimed in claim 12 or 13.

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