Display panel and display device including the same

Abstract

A display panel and a display device including the display panel are disclosed. The display panel includes: a substrate; a transistor located on the substrate; a storage capacitor located on the substrate and electrically connected to the transistor; a metal layer located between the substrate and the transistor; a first insulating layer located on the metal layer and having a first contact hole; and a wiring connected to the metal layer through the first contact hole, wherein the first insulating layer has a first hole spaced apart from the transistor.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0036198, filed with the Korean Intellectual Property Office on Mar. 28, 2019, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Aspects of the present invention relate to a display panel having a transmissive region and a display device including the display panel. BACKGROUND ART

[0003] Recently, the application fields of display devices have become more diversified. As display devices have become thinner and lighter, their range of use has gradually expanded.

[0004] As the area occupied by the display region of a display device increases, functions that can be combined with or associated with the display device are being added. As a way of adding various functions while increasing the display region, research is being conducted on display devices in which various components can be arranged in the display region. SUMMARY OF THE INVENTION

[0005] Aspects of some of the embodiments relate to a display panel and a display device including the display panel, the display panel including a region in which various suitable types of components can be arranged inside the display region. However, it should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limiting the disclosure.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0007] According to some embodiments, there is provided a display panel including: a substrate; a transistor disposed on the substrate; a storage capacitor disposed on the substrate and electrically connected to the transistor; a metal layer disposed between the substrate and the transistor; a first insulating layer disposed on the metal layer and having a first contact hole; and a wiring connected to the metal layer through the first contact hole, wherein the first insulating layer has a first hole spaced apart from the transistor.

[0008] In some embodiments, the first insulating layer includes a plurality of sub-layers.

[0009] In some embodiments, the number of layers defining the first contact hole is the same as the number of layers defining the first hole.

[0010] In some embodiments, the material change of the side surface of the first contact hole in the depth direction of the first contact hole is the same as the material change of the side surface of the first hole in the depth direction of the first hole.

[0011] In some embodiments, the display panel further includes: a second insulating layer, located on the first insulating layer and having a second hole that overlaps with the first hole.

[0012] In some embodiments, the second insulating layer further has a second contact hole for connecting the source electrode or the drain electrode of the transistor to the semiconductor layer of the transistor.

[0013] In some embodiments, the number of layers defining the second contact hole is the same as the number of layers defining the second hole.

[0014] In some embodiments, the material change of the side surface of the second contact hole in the depth direction of the second contact hole is the same as the material change of the side surface of the second hole in the depth direction of the second hole.

[0015] In some embodiments, the width of the second hole is different from the width of the first hole.

[0016] In some embodiments, the metal layer has the same voltage level as the gate electrode of the transistor.

[0017] In some embodiments, the display panel further includes: a driving voltage line, electrically connected to the transistor and the storage capacitor, wherein the metal layer has the same voltage level as the driving voltage line.

[0018] According to some embodiments, there is provided a display device, the display device including: a substrate; a transistor and a storage capacitor, located on the substrate; a metal layer, located between the substrate and the transistor; a first insulating layer, located on the metal layer and having a first contact hole; a wiring, connected to the metal layer through the first contact hole; and a component, arranged under the substrate, wherein the first insulating layer has a first hole spaced apart from the transistor, and wherein the component corresponds to the first hole.

[0019] In some embodiments, the number of layers defining the first contact hole is the same as the number of layers defining the first hole.

[0020] In some embodiments, the material change of the side surface of the first contact hole in the depth direction of the first contact hole is the same as the material change of the side surface of the first hole in the depth direction of the first hole.

[0021] In some embodiments, the display device further includes: a second insulating layer, located on the first insulating layer and having a second hole that overlaps with the first hole.

[0022] In some embodiments, the second insulating layer further has a second contact hole for connecting the source electrode or the drain electrode of the transistor to the semiconductor layer of the transistor.

[0023] In some embodiments, the number of layers defining the second contact hole is the same as the number of layers defining the second hole.

[0024] In some embodiments, the material change of the side surface of the second contact hole in the depth direction of the second contact hole is the same as the material change of the side surface of the second hole in the depth direction of the second hole.

[0025] In some embodiments, the width of the second hole is different from the width of the first hole.

[0026] In some embodiments, the metal layer has the same voltage level as the voltage level of the gate electrode of the transistor.

[0027] In some embodiments, the display device further includes: a driving voltage line electrically connected to the transistor and the storage capacitor, wherein the metal layer has the same voltage level as the voltage level of the driving voltage line.

[0028] In some embodiments, the substrate includes: a first region in which a first display element is located; a second region in which a second display element is located; and a third region in which a first hole is located, wherein the transistor, the storage capacitor, and the metal layer are located in the second region, and wherein the transistor and the storage capacitor are electrically connected to the second display element.

[0029] In some embodiments, the component corresponds to the second region and the third region, and the metal layer overlaps a part of the component.

[0030] In some embodiments, the component includes an electronic element that emits and / or receives light.

[0031] In some embodiments, the display device further includes: a second component corresponding to the second region and different from the component.

[0032] These and / or other aspects will become apparent and easier to understand by the following description of embodiments in conjunction with the accompanying drawings. Description of the Drawings

[0033] These and / or other aspects will become apparent and easier to understand by the following description of embodiments in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a cross-sectional view of a process of manufacturing a display panel according to an exemplary embodiment;

[0035] Figure 2 is a cross-sectional view of a process of manufacturing a display panel according to an exemplary embodiment;

[0036] Figure 3 is a cross-sectional view of a process of manufacturing a display panel according to an exemplary embodiment;

[0037] Figure 4It is a cross-sectional view of a process for manufacturing a display panel according to an exemplary embodiment;

[0038] Figures 5A to 5D It is a cross-sectional view of a process for manufacturing a display panel according to an exemplary embodiment;

[0039] Figure 6 It is a cross-sectional view of a process for manufacturing a display panel according to an exemplary embodiment;

[0040] Figure 7 It is a cross-sectional view of a process for manufacturing a display panel according to an exemplary embodiment;

[0041] Figure 8 It is a cross-sectional view of a process for manufacturing a display panel according to an exemplary embodiment;

[0042] Figure 9 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0043] Figure 10 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0044] Figure 11 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0045] Figure 12 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0046] Figure 13 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0047] Figure 14 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0048] Figure 15 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0049] Figure 16 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0050] Figure 17 It is a cross-sectional view of a display panel according to another exemplary embodiment;

[0051] Figure 18 It is a perspective view of a display device according to an exemplary embodiment;

[0052] Figure 19 It is a cross-sectional view of a display device according to an exemplary embodiment;

[0053] Figure 20 It is a plan view of a display panel according to an exemplary embodiment;

[0054] Figure 21 is an equivalent circuit diagram of one pixel of a display panel according to an exemplary embodiment;

[0055] Figure 22 is a plan view of a first component region, a second component region, and their vicinity of a display panel according to an exemplary embodiment;

[0056] Figure 23 is a cross-sectional view of a display panel according to an exemplary embodiment;

[0057] Figure 24 is a cross-sectional view of a display panel according to another embodiment; and

[0058] Figure 25 is a cross-sectional view of a display panel according to another exemplary embodiment. Detailed Description

[0059] Now, embodiments will be described in detail with reference to the drawings, in which examples of the embodiments are shown, where the same reference numerals always refer to the same elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments are described below only by referring to the drawings to explain the aspects of the present description.

[0060] Since the disclosure allows for various changes and many embodiments, exemplary embodiments will be shown in the drawings and described in detail in the written description. When referring to the embodiments described with reference to the drawings, the effects and features of the disclosure and the methods for achieving them will be apparent. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein.

[0061] Hereinafter, the disclosure will be described more fully with reference to the drawings, in which exemplary embodiments of the disclosure are shown. When described with reference to the drawings, the same reference numerals in the drawings denote the same or corresponding elements, and their repeated description will be omitted.

[0062] For ease of explanation, the dimensions of the elements in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0063] When an embodiment can be implemented differently, the specific process order may be performed in a different order than described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order.

[0064] Figures 1 to 8 is a cross-sectional view of a process for manufacturing a display panel according to an embodiment.

[0065] Refer toFigure 1 The substrate 100 may include a first region A1, a second region A2, and a third region A3. The substrate 100 includes a transparent material. For example, the substrate 100 may include a glass material or a polymer resin.

[0066] A metal layer ML is formed in the second region A2 of the substrate 100. The metal layer ML may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, etc. The metal layer ML may include a single layer or multiple layers containing the above materials. In an embodiment, the metal layer ML may include a layer containing Mo.

[0067] A buffer layer 201 may be formed on the substrate 100 on which the metal layer ML is formed. The buffer layer 201 may include an inorganic insulating material such as silicon nitride (SiN x , x>0), silicon oxynitride (SiON), and silicon oxide (SiO x , x>0). The buffer layer 201 may include a single layer or multiple layers containing the above inorganic insulating materials. The buffer layer 201 may be formed on the substrate 100 to cover the entire surfaces of the first region A1, the second region A2, and the third region A3.

[0068] Then, a first semiconductor layer Act1 and a second semiconductor layer Act2 are respectively formed in the first region A1 and the second region A2. The first semiconductor layer Act1 and the second semiconductor layer Act2 may include polysilicon. In another embodiment, the first semiconductor layer Act1 and the second semiconductor layer Act2 may include amorphous silicon. In another embodiment, the first semiconductor layer Act1 and the second semiconductor layer Act2 may include an oxide semiconductor containing In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, and / or Zn, etc. For example, the first semiconductor layer Act1 and the second semiconductor layer Act2 may include an oxide semiconductor such as indium gallium zinc oxide (IGZO), tin zinc oxide (ZTO), and indium zinc oxide (ZIO).

[0069] The second semiconductor layer Act2 may be stacked on the metal layer ML. In an embodiment, the width of the second semiconductor layer Act2 may be smaller than the width of the metal layer ML. Thus, when viewed in a direction perpendicular to the substrate 100, the entire surface of the second semiconductor layer Act2 may be stacked on the metal layer ML.

[0070] The first semiconductor layer Act1 and the second semiconductor layer Act2 may be covered by a gate insulating layer 203. The gate insulating layer 203 may include an inorganic insulating material such as silicon nitride (SiN x , x>0), silicon oxynitride (SiON), and silicon oxide (SiO x, an inorganic insulating material (x > 0). The gate insulating layer 203 may include a single layer or multiple layers containing the above inorganic insulating material. The gate insulating layer 203 may be formed over the substrate 100 to cover the entire surfaces of the first region A1, the second region A2, and the third region A3.

[0071] Refer to Figure 2 , a first contact hole (i.e., a first contact opening) CNT1 and a first hole (i.e., a first opening) H1 are formed. The first contact hole CNT1 and the first hole H1 may be formed to penetrate through the first insulating layer IL1 on the substrate 100 and / or the metal layer ML. For example, the first contact hole CNT1 and the first hole H1 may be formed to penetrate through the buffer layer 201 and the gate insulating layer 203.

[0072] The first contact hole CNT1 may be formed to penetrate through the buffer layer 201 and the gate insulating layer 203 positioned in the second region A2. A part of the metal layer ML disposed in the second region A2 may be exposed through the first contact hole CNT1. The first hole H1 may be formed to penetrate through a part of the buffer layer 201 and the gate insulating layer 203 positioned in the third region A3. A part of the layer (e.g., the substrate 100) positioned under the buffer layer 201 may be exposed through the first hole H1.

[0073] The first contact hole CNT1 may be formed during the same process as the process of forming the first hole H1. The side surface of the first insulating layer IL1 surrounding the first contact hole CNT1 may define the first contact hole CNT1. The side surface of the first insulating layer IL1 surrounding the first hole H1 may define the first hole H1. For example, it can be understood that the side surface of the first insulating layer IL1 surrounding the first contact hole CNT1 is the side surface of the first contact hole CNT1, and the side surface of the first insulating layer IL1 surrounding the first hole H1 is the side surface of the first hole H1.

[0074] The material change of the first insulating layer IL1 in the depth (thickness) direction of the first contact hole CNT1 may be the same as the material change of the first insulating layer IL1 in the depth (thickness) direction of the first hole H1. Similarly, the material change of the side surface of the first contact hole CNT1 in the depth (thickness) direction of the first contact hole CNT1 may be substantially the same as the material change of the side surface of the first hole H1 in the depth (thickness) direction of the first hole H1.

[0075] For example, a case is described where the buffer layer 201 as a sub-layer of the first insulating layer IL1 includes a double layer of a silicon nitride layer and a silicon oxide layer and the gate insulating layer 203 as a sub-layer of the first insulating layer IL1 includes a single layer of a silicon oxide layer. Refer to Figure 2An enlarged view of the second region A2, the material change of the first insulating layer IL1 defining the first contact hole CNT1 in the thickness (depth) direction (e.g., the ar1 direction) can occur in the order of silicon oxide - silicon oxide - silicon nitride. As Figure 2 As shown in the enlarged view of the third region A3 of, since the first hole H1 is formed to pass through the same insulating layer during the same process as the process of forming the first contact hole CNT1, the material change of the first insulating layer IL1 defining the first hole H1 in the thickness (depth) direction (e.g., the ar2 direction) can also occur in the order of silicon oxide - silicon oxide - silicon nitride.

[0076] The first contact hole CNT1 is formed during the same process as the process of forming the first hole H1, and the number of layers of the layer defining the first contact hole CNT1 is the same as the number of layers of the layer defining the first hole H1. In an embodiment, in the case where the buffer layer 201 as a sub - layer of the first insulating layer IL1 includes a double - layer of a silicon nitride layer and a silicon oxide layer and the gate insulating layer 203 as a sub - layer of the first insulating layer IL1 includes a single - layer of a silicon oxide layer, the number of layers defining the first contact hole CNT1 is three, which is equal to the three layers defining the first hole H1. The number of layers defining the first contact hole CNT1 and the first hole H1 can be determined by the number of interfaces between the layers.

[0077] Referring to Figure 3 , a first gate electrode G1 and a second gate electrode G2 are formed on the substrate 100 in which the first contact hole CNT1 and the first hole H1 are formed. The first gate electrode G1 can be positioned above the first semiconductor layer Act1 in the first region A1, and the second gate electrode G2 can be positioned above the second semiconductor layer Act2 in the second region A2.

[0078] Each of the first gate electrode G1 and the second gate electrode G2 can include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, etc. The first gate electrode G1 and the second gate electrode G2 can include a single - layer or multiple - layers containing the above - mentioned materials. In an embodiment, the first gate electrode G1 and the second gate electrode G2 can include the same material as the material of the metal layer ML or a material different from the material of the metal layer ML.

[0079] The wiring GCL can be formed during the process of forming the first gate electrode G1 and the second gate electrode G2. The wiring GCL can include the same material as that of the first gate electrode G1 and the second gate electrode G2. The wiring GCL can be connected to the metal layer ML through the first contact hole CNT1 and can transmit signals (e.g., a predetermined signal), such as a gate signal. In the second region A2, the metal layer ML can be used as a gate electrode. In this case, the metal layer ML can have the same voltage level as that of the second gate electrode G2. For example, the second gate electrode G2 can be used as a top gate electrode, and the metal layer ML can be used as a bottom gate electrode.

[0080] After forming the first gate electrode G1 and the second gate electrode G2, the first semiconductor layer Act1 and the second semiconductor layer Act2 can be doped with impurities by using the first gate electrode G1 and the second gate electrode G2 as self-aligned masks, respectively. The first semiconductor layer Act1 can include a first channel region CR1, a first source region SR1, and a first drain region DR1. The first channel region CR1 can be stacked with the first gate electrode G1, and the first source region SR1 and the first drain region DR1 can be doped with impurities. The second semiconductor layer Act2 can include a second channel region CR2, a second source region SR2, and a second drain region DR2. The second channel region CR2 can be stacked with the second gate electrode G2, and the second source region SR2 and the second drain region DR2 can be doped with impurities.

[0081] Referring to Figure 4 , a first interlayer insulating layer 205 is formed on the substrate 100 on which the first gate electrode G1, the second gate electrode G2, and the wiring GCL are formed. Then, a first electrode layer CE1b and a second electrode layer CE2b are formed, and the first electrode layer CE1b and the second electrode layer CE2b are stacked with the first gate electrode G1 and the second gate electrode G2, respectively.

[0082] The first interlayer insulating layer 205 can include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, and can include a single layer or multiple layers including the above inorganic insulating materials.

[0083] In the first region A1, the first electrode layer CE1b can be stacked with the first gate electrode G1 below it. The first gate electrode G1 and the first electrode layer CE1b can constitute a first storage capacitor Cst1, and the first gate electrode G1 and the first electrode layer CE1b are stacked with each other with the first interlayer insulating layer 205 between the first gate electrode G1 and the first electrode layer CE1b. The first gate electrode G1 can be used as the lower electrode CE1a of the first storage capacitor Cst1, and the first electrode layer CE1b can be used as the upper electrode of the first storage capacitor Cst1.

[0084] In the second region A2, the second electrode layer CE2b may be stacked on the second gate electrode G2 thereunder. The second gate electrode G2 and the second electrode layer CE2b may form the second storage capacitor Cst2. The second gate electrode G2 and the second electrode layer CE2b are stacked on each other with the first interlayer insulating layer 205 therebetween. The second gate electrode G2 may serve as the lower electrode CE2a of the second storage capacitor Cst2, and the second electrode layer CE2b may serve as the upper electrode of the second storage capacitor Cst2.

[0085] The first electrode layer CE1b and the second electrode layer CE2b may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, etc., and may include a single layer or multiple layers containing the above materials.

[0086] Then, the second interlayer insulating layer 207 is formed. The second interlayer insulating layer 207 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may include a single layer or multiple layers containing the above inorganic insulating materials. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may cover the entire surface of the substrate 100. Thus, the first hole H1 in the third region A3 may be covered by the first interlayer insulating layer 205 and the second interlayer insulating layer 207.

[0087] Referring to Figure 5A , a second contact hole (i.e., a second contact opening) CNT2 and a second hole (i.e., a second opening) H2 are formed. The second contact hole CNT2 and the second hole H2 may be formed to penetrate the second insulating layer IL2. The second contact hole CNT2 is formed in the first region A1 and the second region A2. The second hole H2 is formed in the third region A3. The second contact hole CNT2 may be formed to penetrate the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207. The second hole H2 may be formed to penetrate the first interlayer insulating layer 205 and the second interlayer insulating layer 207.

[0088] The second hole H2 may be defined by the side surface of the second insulating layer IL2 surrounding the second hole H2. For example, in the case where the first interlayer insulating layer 205 is a single layer and the second interlayer insulating layer 207 is a single layer (the first interlayer insulating layer 205 and the second interlayer insulating layer 207 are sub-layers of the second insulating layer IL2), the number of layers defining the second hole H2 may be two. The number of layers defining the second hole H2 may be the same as the number of layers between the wiring GCL and the second source electrode SE2 (see Figure 6 ), and the second source electrode SE2 (see Figure 6 ) will be formed during the process described below. The number of layers defining the second hole H2 may be the same as the number of layers between the wiring GCL and the second drain electrode DE2 (seeFigure 6 ) have the same number of layers as that between, and the second drain electrode DE2 (see Figure 6 ) will be formed during the process described below.

[0089] In the first region A1, the first source region SR1 and / or the first drain region DR1 of the first semiconductor layer Act1 can be exposed through the second contact hole CNT2. In the second region A2, the second source region SR2 and / or the second drain region DR2 of the second semiconductor layer Act2 can be exposed through the second contact hole CNT2.

[0090] The second hole H2 formed in the third region A3 is superimposed on the first hole H1. As Figure 5A shown, the width W2 of the second hole H2 can be smaller than the width W1 of the first hole H1. In another embodiment, as Figure 5B shown, the width W2 of the second hole H2 can be larger than the width W1 of the first hole H1. In an embodiment, depending on whether the materials of the gate insulating layer 203 and the first interlayer insulating layer 205 are different from each other and / or the conditions of the process (e.g., etching process) for forming the second hole H2, as Figure 5B shown, the connecting portion of the second hole H2 and the first hole H1 can form a step difference, or as Figure 5C shown, the connecting portion of the second hole H2 and the first hole H1 can form an inclined surface (a gentle inclined surface or an inclined surface with a curvature), or as Figure 5D shown, during the etching process of forming the second hole H2, while removing a part of the side surface of the first insulating layer IL1 that defines the first hole H1, the side surface of the first insulating layer IL1 itself that forms the first hole H1 can have a step difference. In the following drawings, for ease of description, as Figure 5A shown, the case where the width W2 of the second hole H2 is smaller than the width W1 of the first hole H1 is described.

[0091] Referring to Figure 6 , a source electrode and / or a drain electrode are formed on the substrate 100 on which the second contact hole CNT2 and the second hole H2 are formed. Regarding this, in Figure 6 it is shown that the first source electrode SE1 and the first drain electrode DE1 are formed in the first region A1, and the second source electrode SE2 and the second drain electrode DE2 are formed in the second region A2.

[0092] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can include Mo, Al, Cu, and / or Ti, etc., and can include a single layer or multiple layers containing the above materials. In an embodiment, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can include a multi-layer of Ti / Al / Ti.

[0093] Reference Figure 7 , a planarization layer 209 is formed. The planarization layer 209 may cover the first transistor TR1 and the first storage capacitor Cst1 in the first region A1 and the second transistor TR2 and the second storage capacitor Cst2 in the second region A2. The planarization layer 209 may include an organic insulating material. The organic insulating material may include a general polymer, a polymer derivative having a phenolic group, an acrylate polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a parylene polymer, a polyvinyl alcohol polymer, or a blend thereof. In an embodiment, the planarization layer 209 may include polyimide.

[0094] Then, a third contact hole (i.e., a third contact opening) CNT3 is formed in the planarization layer 209. The third contact hole CNT3 may be formed in each of the first region A1 and the second region A2. The planarization layer 209 may include a third hole (i.e., a third opening) H3 positioned in the third region A3. The third hole H3 may be formed during the same process as the process of forming the third contact hole CNT3 or a separate process. The third hole H3 is superimposed on the first hole H1 and the second hole H2.

[0095] Next, a first pixel electrode 221-1 and a second pixel electrode 221-2 are formed in the first region A1 and the second region A2, respectively. The first pixel electrode 221-1 may be electrically connected to the first transistor TR1 through the third contact hole CNT3, and the second pixel electrode 221-2 may be electrically connected to the second transistor TR2 through the third contact hole CNT3.

[0096] The first pixel electrode 221-1 and the second pixel electrode 221-2 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first pixel electrode 221-1 and the second pixel electrode 221-2 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof. In another embodiment, the first pixel electrode 221-1 and the second pixel electrode 221-2 may further include a layer including ITO, IZO, ZnO, and / or In2O3, etc., on / under the reflective layer.

[0097] A pixel defining layer 211 is formed on the first pixel electrode 221-1 and the second pixel electrode 221-2. The pixel defining layer 211 can cover the edges of each of the first pixel electrode 221-1 and the second pixel electrode 221-2 in the first region A1 and the second region A2. The pixel defining layer 211 can include an organic insulating material and / or an inorganic insulating material. The pixel defining layer 211 includes a first opening OP1 and a second opening OP2 that are respectively stacked with the first pixel electrode 221-1 and the second pixel electrode 221-2.

[0098] The pixel defining layer 211 can include a fourth hole (i.e., a fourth opening) H4 positioned in the third region A3. The fourth hole H4 can be formed during the same process as the process of forming the first opening OP1 and the second opening OP2. In some examples, the fourth hole H4 can be formed during a different process.

[0099] A first functional layer 222a is formed on the substrate 100 on which the pixel defining layer 211 is formed. The first functional layer 222a can include a single layer or multiple layers. The first functional layer 222a can include a hole transport layer (HTL) having a single-layer structure. In some embodiments, the first functional layer 222a can include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer 222a can be provided integrally to cover the first region A1 and the second region A2.

[0100] Then, a first emission layer 222b1 is formed in the first region A1, and a second emission layer 222b2 is formed in the second region A2. The first emission layer 222b1 and the second emission layer 222b2 can include a polymer material or a low molecular weight material, and emit red light, green light, blue light, or white light. The first emission layer 222b1 and the second emission layer 222b2 can be patterned to be respectively stacked with the first pixel electrode 221-1 and the second pixel electrode 221-2.

[0101] Next, a second functional layer 222c can be formed. In an embodiment, the second functional layer 222c can be omitted. For example, in a case where the first functional layer 222a and the emission layers (e.g., the first emission layer 222b1 and the second emission layer 222b2) include a polymer material, the second functional layer 222c can be preferably formed. The second functional layer 222c can include a single layer or multiple layers. The second functional layer 222c can include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 222c can be formed integrally to cover the first region A1 and the second region A2.

[0102] Then, a counter electrode 223 is formed. The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include a (semi)transparent layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. In some examples, the counter electrode 223 may further include a layer containing ITO, IZO, ZnO, In2O3, etc. on the (semi)transparent layer including the above materials. The counter electrode 223 may be formed integrally to cover the first region A1 and the second region A2.

[0103] The layer formed in the first region A1 from the first pixel electrode 221-1 to the counter electrode 223 may constitute the first organic light-emitting diode OLED1. The layer formed in the second region A2 from the second pixel electrode 221-2 to the counter electrode 223 may constitute the second organic light-emitting diode OLED2.

[0104] Refer to Figure 8 , the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 may be covered by a packaging substrate 300A. The packaging substrate 300A may include a transparent material. For example, the packaging substrate 300A may include a glass material. In some examples, the packaging substrate 300A may include a polymer resin. The packaging substrate 300A can prevent or substantially prevent external moisture or foreign substances from penetrating into the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2.

[0105] A sealing material such as a sealant may be disposed between the packaging substrate 300A and the substrate 100 on which the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 are formed. The sealing material can block external moisture or foreign substances that can penetrate the space between the substrate 100 and the packaging substrate 300A.

[0106] Before disposing the packaging substrate 300A, a capping layer 250 may be formed on the counter electrode 223. The capping layer 250 may include LiF. In some examples, the capping layer 250 may include an inorganic insulating material such as silicon nitride and / or an organic insulating material. In some examples, the capping layer 250 may be omitted.

[0107] Refer to Figures 1 to 8 The described display panel 10A can display an image (e.g., a predetermined image) through the first organic light-emitting diode OLED1 disposed in the first region A1 and the second organic light-emitting diode OLED2 disposed in the second region A2. The third region A3 may include a transmissive region that can transmit light. For example, in Figure 8In [the figure], light generated below the substrate 100 can travel in the +z direction through the third region A3, and light generated above the encapsulation substrate 300A can travel in the -z direction through the third region A3.

[0108] Figure 9 is a cross-sectional view of a display panel according to another embodiment. Although in Figure 8 it is shown that the display panel 10A may include the encapsulation substrate 300A as an encapsulation member, in another embodiment as shown in Figure 9 the display panel 10B may include the thin film encapsulation layer 300B as an encapsulation member.

[0109] Figure 9 shows the process after the process described with reference to Figure 7 and shows the state in which the cover layer 250 is formed. Referring to Figure 9 a thin film encapsulation layer 300B is formed on the cover layer 250. The thin film encapsulation layer 300B may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Regarding this, Figure 9 it is shown in [the figure] that the thin film encapsulation layer 300B has a structure in which a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 are stacked. In another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order may be modified.

[0110] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one of inorganic insulating materials such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride, and may be formed by chemical vapor deposition (CVD). The organic encapsulation layer 320 may include polymer-based materials. The polymer-based materials may include silicone resins, acrylic resins, epoxy resins, polyimides, and / or polyethylene, etc.

[0111] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be formed integrally to cover the first region A1, the second region A2, and the third region A3. The organic encapsulation layer 320 may be formed integrally to cover the first region A1 and the second region A2. The organic encapsulation layer 320 may not exist in the third region A3. In other words, the organic encapsulation layer 320 may include an opening corresponding to the third region A3. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be in contact with each other in the third region A3. The first inorganic encapsulation layer 310 may contact the top surface of the substrate 100.

[0112] The substrate 100 may include multiple layers. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104.

[0113] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, each of the first base layer 101 and the second base layer 103 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0114] Each of the first barrier layer 102 and the second barrier layer 104 is a barrier layer that prevents or substantially prevents the penetration of external foreign substances, and may include a single layer or multiple layers containing an inorganic insulating material such as silicon nitride (SiN x , x>0) and silicon oxide (SiO x , x>0). In the case where the substrate 100 includes a polymer resin, the flexibility of the substrate 100 can be relatively improved (e.g., increased) compared to the case where the substrate 100 includes a glass material.

[0115] Figure 10 is a cross-sectional view of a display panel 10B' according to another embodiment. As described with reference to Figure 9 , different from a substrate including a glass material, in the substrate 100 including a polymer resin, holes passing through the substrate 100 can be easily formed.

[0116] Referring to Figure 10 , as described with reference to Figure 9 , after forming the thin film encapsulation layer 300B, holes 100H passing through the substrate 100 can be formed. The holes 100H can be formed by processes such as laser, scribing, and polishing. During the process of forming the holes 100H, holes 300BH can also be formed in the thin film encapsulation layer 300B, and the holes 300BH correspond to the third region A3. The holes 100H passing through the substrate 100 and the holes 300BH passing through the thin film encapsulation layer 300B can overlap with each other and overlap with the first hole H1, the second hole H2, the third hole H3, and / or the fourth hole H4.

[0117] Since the display panel 10B' shown in Figure 10 includes holes 10BH passing through the third region A3 of the display panel 10B', the display panel 10B' can have a relatively higher transmittance in the third region A3 than the display panel 10B shown in Figure 9 . Light and / or sound can transmit through the holes 10BH of the display panel 10B' shown in Figure 10 .

[0118] Figure 11is a cross-sectional view of a display panel 10C according to an embodiment. Since Figure 11 the structures of the first region A1 and the second region A2 of the display panel 10C in Figures 1 to 8 are the same as the structures of the first region A1 and the second region A2 of the display panel 10A described with reference to

[0119] With reference to Figure 11 the third region A3, at least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 250 may be positioned in the third region A3. Figure 11 the transmittance of the third region A3 of the display panel 10C in Figure 8 may be less than the transmittance of the third region A3 of the display panel 10A described with reference to Figure 8 In an embodiment, in the case where the third region A3 of the display panel 10A described with reference to Figure 11 is used as a region for transmitting light in the visible light band,

[0120] Figure 12 is a cross-sectional view of a display panel 10D according to an embodiment. Since Figure 12 the structures of the first region A1 and the second region A2 of the display panel 10D in Figure 9 are the same as the structures of the first region A1 and the second region A2 of the display panel 10B described with reference to

[0121] With reference to Figure 12 the third region A3, at least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 250 may be positioned in the third region A3. In addition, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be positioned in the third region A3. Figure 12 the transmittance of the third region A3 of the display panel 10D in Figure 9 may be relatively smaller than the transmittance of the third region A3 of the display panel 10B described with reference to Figure 12 In an embodiment,

[0122] In reference to Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12In the described display panels 10A, 10B, 10B', 10C, and 10D, first holes H1, second holes H2, etc. are formed to improve (e.g., increase) the transmittance of the third region A3. In this case, the first holes H1 can be formed concurrently (e.g., simultaneously) with the first contact holes CNT1 during the process of forming the first contact holes CNT1. The second holes H2 can be formed concurrently (e.g., simultaneously) with the second contact holes CNT2 during the process of forming the second contact holes CNT2. Accordingly, since a separate process for improving (e.g., increasing) the transmittance of the third region A3 is not required, manufacturing costs, time, etc. can be reduced.

[0123] Although in the display panels 10A, 10B, 10B', 10C, and 10D described with reference to Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 the first holes H1 and the first contact holes CNT1 are formed to penetrate the first insulating layer IL1, and the first insulating layer IL1 includes a buffer layer 201 and a gate insulating layer 203, the present disclosure is not limited thereto. In an embodiment, as described below with reference to Figures 13 to 21 the first holes H1 and the first contact holes CNT1 can be formed in a first insulating layer including sub-layers more in number than the sub-layers described with reference to Figure 8 etc.

[0124] Figure 13 is a cross-sectional view of a display panel 10E according to another embodiment.

[0125] Referring to Figure 13 , the first holes H1 and the first contact holes CNT1 can be formed to penetrate the first insulating layer IL1'. The first insulating layer IL1' can include a buffer layer 201, a gate insulating layer 203, and a first interlayer insulating layer 205.

[0126] A wiring GCL' electrically connected to a metal layer ML formed in a second region A2 can be formed during the same process as the process of forming the second electrode layer CE2b. The process of forming the first contact holes CNT1 for connection between the wiring GCL' and the metal layer ML can be performed after forming the first interlayer insulating layer 205. The first holes H1 can be formed concurrently (e.g., simultaneously) with the first contact holes CNT1 during the process of forming the first contact holes CNT1.

[0127] The first contact hole CNT1 can be defined by the side surface of the first insulating layer IL1' surrounding the first contact hole CNT1, and the first hole H1 can be defined by the side surface of the first insulating layer IL1' surrounding the first hole H1. Since the first hole H1 and the first contact hole CNT1 are formed to penetrate the first insulating layer IL1' during the same process, the number of layers defining the first hole H1 can be the same as the number of layers defining the first contact hole CNT1, and / or the material variation of the layer defining the first contact hole CNT1 in the thickness (depth) direction can have the same manner as the material variation of the layer defining the first hole H1 in the thickness (depth) direction. Similarly, the material variation of the side surface of the first contact hole CNT1 in the depth (thickness) direction of the first contact hole CNT1 can be the same as the material variation of the side surface of the first hole H1 in the depth (thickness) direction of the first hole H1.

[0128] The wiring GCL' can apply a voltage (e.g., a predetermined voltage), e.g., a constant voltage (e.g., ELVDD, see Figure 21 ). As a comparative example, in the case where the wiring is in a floating state, external static electricity is introduced through the floating wiring, and thus the second transistor TR2 can be damaged. In the present embodiment, in order to prevent or substantially prevent the introduction of external static electricity, a constant voltage can be applied to the metal layer ML.

[0129] The second hole H2 can be formed concurrently (e.g., simultaneously) with the second contact hole CNT2 during the process of forming the second contact hole CNT2. The second hole H2 can be formed in the second insulating layer IL2'. The second insulating layer IL2' can include a second interlayer insulating layer 207 positioned between the wiring GCL' and the second drain electrode DE2 and / or between the wiring GCL' and the second source electrode SE2. That is, the number of layers defining the second hole H2 can be the same as the number of layers positioned between the wiring GCL' and the second drain electrode DE2 and / or between the wiring GCL' and the second source electrode SE2. In an embodiment, in the case where the second interlayer insulating layer 207 includes a bilayer of a silicon oxide layer and a silicon nitride layer, the number of layers defining the second hole H2 can be two. In this case, the number of layers positioned between the wiring GCL' and the second drain electrode DE2 and / or between the wiring GCL' and the second source electrode SE2 is two. In another embodiment, in the case where the second interlayer insulating layer 207 includes a single layer of a silicon nitride layer, the number of layers defining the second hole H2 can be one, and the number of layers positioned between the wiring GCL' and the second drain electrode DE2 and / or between the wiring GCL' and the second source electrode SE2 is one.

[0130] Although in Figure 13It is shown that the width of the first hole H1 is greater than the width of the second hole H2, but the embodiments are not limited thereto. In another embodiment, as described with reference to Figure 5B , the width of the first hole H1 may be less than the width of the second hole H2. In some examples, the width of the first hole H1 may be the same as the width of the second hole H2.

[0131] Other elements that do not include the features described with reference to Figure 13 are the same as the elements of the embodiment described with reference to Figure 8 .

[0132] Figure 14 and Figure 15 are cross-sectional views of display panels 10F and 10F' according to another embodiment.

[0133] In Figure 14 and Figure 15 of the display panels 10F and 10F' shown, as described with reference to Figure 13 , the first hole H1 and the first contact hole CNT1 may be formed to penetrate the first insulating layer IL1' including the buffer layer 201, the gate insulating layer 203, and the first interlayer insulating layer 205. The second hole H2 may be formed to penetrate the second insulating layer IL2' including the second interlayer insulating layer 207.

[0134] Unlike Figure 13 of the display panel 10E shown, in Figure 14 and Figure 15 of the display panels 10F and 10F' shown, the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 may be covered by the thin film encapsulation layer 300B. In addition, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104. The specific structures of the thin film encapsulation layer 300B and the substrate 100 are the same as the structures described with reference to Figure 9 and the like.

[0135] Unlike Figure 14 of the display panel 10F, Figure 15 of the display panel 10F' may include a hole 100H penetrating the substrate 100 and a hole 300BH penetrating the thin film encapsulation layer 300B in the third region A3.

[0136] Figure 16 is a cross-sectional view of a display panel 10G according to another embodiment.

[0137] In Figure 16 of the display panel 10G shown, as described with reference to Figure 13As described, the first hole H1 and the first contact hole CNT1 may be formed to penetrate a first insulating layer IL1' including a buffer layer 201, a gate insulating layer 203, and a first interlayer insulating layer 205. The second hole H2 may be formed to penetrate a second insulating layer IL2' including a second interlayer insulating layer 207.

[0138] Referring to Figure 16 a third region A3 of the display panel 10G, at least one of a first functional layer 222a, a second functional layer 222c, a counter electrode 223, and a cover layer 250 may be positioned in the third region A3, and its specific structure is the same as that described with reference to Figure 11 described.

[0139] Figure 17 FIG. is a cross-sectional view of a display panel 10H according to another embodiment.

[0140] In Figure 17 the display panel 10H shown in, as described with reference to Figure 13 the first hole H1 and the first contact hole CNT1 may be formed to penetrate a first insulating layer IL1' including a buffer layer 201, a gate insulating layer 203, and a first interlayer insulating layer 205. The second hole H2 may be formed to penetrate a second insulating layer IL2' including a second interlayer insulating layer 207.

[0141] Referring to Figure 17 a third region A3 of the display panel 10H, at least one of a first functional layer 222a, a second functional layer 222c, a counter electrode 223, and a cover layer 250 may be positioned in the third region A3. In addition, a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 may be positioned in the third region A3, and the specific structure including the above-described structure is the same as that described with reference to Figure 12 described.

[0142] Figure 18 FIG. is a perspective view of a display device 1 according to an embodiment.

[0143] Referring to Figure 18 , the display device 1 includes a display area DA surrounding a first component area RA1 and a second component area RA2. The first component area RA1 and the second component area RA2 may have different sizes (areas) and / or different shapes. In some examples, the first component area RA1 and the second component area RA2 may have the same size (area) and / or the same shape.

[0144] The display area DA can display an image (e.g., a predetermined image) by using light emitted from a plurality of pixels arranged in the display area DA. The intermediate area MA can be arranged between the first component area RA1 and the second component area RA2 and the display area DA. The display area DA can be surrounded by the peripheral area PA. The intermediate area MA and the peripheral area PA can be a non-display area in which no pixels are arranged. The intermediate area MA can be completely surrounded by the display area DA, and the display area DA can be completely surrounded by the peripheral area PA.

[0145] Hereinafter, although the display device 1 according to the embodiment is described by using an organic light-emitting display device as an example, the display device 1 of the present disclosure is not limited thereto. In another embodiment, various types of display devices such as an inorganic light-emitting display and a quantum dot light-emitting display can be used.

[0146] Figure 19 is a cross-sectional view of the display device 1 according to the embodiment. Figure 19 can correspond to a cross-section taken along the Figure 18 line XIX-XIX’ of.

[0147] Referring to Figure 19 , the display device 1 can include a display panel 10, an input sensing layer 40, and an optical function layer 50 arranged on the display panel 10. These layers can be covered by a window 60. The display device 1 can include various suitable electronic devices such as a mobile phone, a laptop computer, and a smart watch.

[0148] The display panel 10 can display an image. The display panel 10 includes pixels arranged in the display area DA. Each pixel can include a display element and a pixel circuit connected thereto. The display element can include an organic light-emitting diode. In some examples, the display element can include an inorganic light-emitting diode or a quantum dot light-emitting diode.

[0149] The input sensing layer 40 obtains coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 can include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 can be arranged on the display panel 10. The input sensing layer 40 can sense an external input by using a mutual capacitance method and / or a self-capacitance method.

[0150] The input sensing layer 40 can be directly formed on the display panel 10, or can be formed separately and then bonded to the display panel 10 by using an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 can be continuously formed after the process of forming the display panel 10. In this case, the adhesive layer can not be arranged between the input sensing layer 40 and the display panel 10. Although Figure 19The input sensing layer 40 is shown disposed between the display panel 10 and the optical function layer 50. However, in another embodiment, the input sensing layer 40 may be disposed on the optical function layer 50.

[0151] The optical function layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectance of light (external light) incident from the outside through the window 60 toward the display panel 10. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal-type retarder. The retarder may include a λ / 2 (half-wavelength) retarder and / or a λ / 4 (quarter-wavelength) retarder. The polarizer may include a film-type polarizer or a liquid crystal-type polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal-type polarizer may include liquid crystals arranged in a set or predetermined alignment. Each of the retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or the protective film may be defined as the base layer of the anti-reflection layer.

[0152] In another embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged by considering the colors of light emitted from the pixels of the display panel 10, respectively. In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers, respectively. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may generate destructive interference, and thus the reflectance of external light may be reduced.

[0153] The optical function layer 50 may include a lens layer. The lens layer may improve (e.g., increase) the emission efficiency of light emitted from the display panel 10 or reduce the color deviation of light. The lens layer may include a layer having a concave lens or convex lens shape, and / or include a plurality of layers having different refractive indices, respectively. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or include one of the anti-reflection layer and the lens layer.

[0154] Each of the display panel 10, the input sensing layer 40, and the optical function layer 50 may include an opening corresponding to one of the first component region RA1 and the second component region RA2. Regarding this, in Figure 19 it is shown that the display panel 10, the input sensing layer 40, and the optical function layer 50 respectively include a first component opening 11, a second component opening 41, and a third component opening 51, and the first component opening 11, the second component opening 41, and the third component opening 51 are stacked on top of each other in the first component region RA1. The sizes (e.g., diameters) of the first component opening 11, the second component opening 41, and the third component opening 51 may be the same as or different from each other. In another embodiment, at least one of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening.

[0155] Components for adding various functions to the display device 1 may be located in the first component region RA1 and the second component region RA2. Each of the first component region RA1 and the second component region RA2 may correspond to a sensor region, a camera region, or a speaker region according to the type of component.

[0156] As Figure 19 As shown, the first component 21 disposed in the first component region RA1 may be located inside the first component opening 11, the second component opening 41, and the third component opening 51. In some examples, like the second component 22, the first component 21 may be disposed below the display panel 10.

[0157] The first component 21 and / or the second component 22 may include electronic components. For example, the first component 21 and / or the second component 22 may include electronic components that use light or sound. For example, the electronic component may be a sensor (such as an infrared sensor that emits and / or receives light in the infrared band, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance, or a sensor that identifies fingerprints), a small lamp that outputs light, or a speaker that outputs sound. The electronic component that uses light may use light in various suitable bands such as visible light, infrared light, and ultraviolet light. In an embodiment, the first component region RA1 and / or the second component region RA2 may be understood as a transmissive region through which light and / or sound propagating from the electronic component toward the outside or from the outside toward the electronic component can pass.

[0158] In an embodiment, in a case where the display device 1 is used as a smart watch or a dashboard for a vehicle, the first component 21 may be a member including a pointer of a clock or a pointer indicating predetermined information (such as the speed of a vehicle, etc.). In a case where the display device 1 includes a clock or a pointer of a dashboard for a vehicle, the pointer may be exposed to the outside through a window 60 that may include an opening. In some examples, even in a case where the first component 21 includes a speaker, the window 60 may include an opening.

[0159] As described above, the first component 21 and the second component 22 may include (a plurality of) elements related to the function of the display device 1 or elements including accessories such as increasing the aesthetic feeling of the display device 1. A layer including an optically transparent adhesive, etc. may be located between the window 60 and the optical function layer 50.

[0160] Figure 20 is a plan view of the display panel 10 according to an embodiment.

[0161] Referring to Figure 20 , the display panel 10 may include a first component region RA1, a second component region RA2, a display region DA, an intermediate region MA, and a peripheral region PA. Figure 20It may be a diagram of the substrate 100 of the display panel 10. For example, it can be understood that the substrate 100 includes a first component region RA1, a second component region RA2, a display region DA, an intermediate region MA, and a peripheral region PA.

[0162] The display panel 10 includes a plurality of pixels P arranged in the display region DA. Each pixel P may include a display element such as an organic light-emitting diode. Each pixel P may emit, for example, red light, green light, blue light, or white light through the organic light-emitting diode. In this specification, as described above, it can be understood that the pixel P is a pixel that emits one of red light, green light, blue light, and white light. The first component region RA1 and the second component region RA2 are arranged inside the display region DA, and the intermediate region MA is positioned between the first component region RA1 and the second component region RA2 and the display region DA.

[0163] The intermediate region MA may surround the first component region RA1 and the second component region RA2. The peripheral region PA may surround the display region DA. The intermediate region MA and the peripheral region PA are a type of non-display region in which display elements such as organic light-emitting diodes that emit light are not arranged. Traces and / or power lines for supplying signals to the pixels P may be arranged in the intermediate region MA and the peripheral region PA.

[0164] The first external driving circuit 110, the second external driving circuit 120, the terminal 140, the data driving circuit 150, the first power line 160, and the second power line 170 may be arranged in the peripheral region PA.

[0165] The first external driving circuit 110 may include a scan and control driving circuit. The first external driving circuit 110 may provide a scan signal and an emission control signal to the pixel P through the scan line SL and the emission control line EL. The second external driving circuit 120 may be arranged in parallel with the first external driving circuit 110 and have the display region DA between the first external driving circuit 110 and the second external driving circuit 120. The second external driving circuit 120 may also include a scan and control driving circuit. In another embodiment, the second external driving circuit 120 may be omitted.

[0166] Terminal 140 may be disposed on one side of the peripheral region PA. Terminal 140 may not be covered by an insulating layer and is exposed, and thus is electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits signals or power of the controller to the display panel 10. The control signal generated by the controller may be transmitted to the first external driving circuit 110 and the second external driving circuit 120 through the printed circuit board PCB. The controller may supply a first power ELVDD (also referred to as a first power voltage) and a second power ELVSS (also referred to as a second power voltage, see Figure 21 ) to the first power line 160 and the second power line 170 through the first connection line 161 and the second connection line 171 respectively. The first power ELVDD may be supplied to each pixel P through the driving voltage line PL connected to the first power line 160, and the second power ELVSS may be supplied to the counter electrode of the pixel P connected to the second power line 170.

[0167] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be supplied to each pixel P through the connection line 151 and the data line DL. The connection line 151 is connected to the terminal 140 and the data line DL is connected to the connection line 151. Although it is shown in Figure 20 that the data driving circuit 150 is disposed on the printed circuit board PCB, in another embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power line 160.

[0168] The first power line 160 may include a first sub-line 162 and a second sub-line 163 that extend parallel to the x direction and have the display area DA therebetween. The second power line 170 may have an annular shape that has an open side and partially surrounds the display area DA.

[0169] Figure 21 is an equivalent circuit diagram of one pixel of the display panel according to an embodiment.

[0170] Referring to Figure 21 , each pixel P includes a pixel circuit PC and an organic light-emitting diode OLED as a display element, and the display element is connected to the pixel circuit PC. The pixel circuit PC may include a driving transistor T1, a switching transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light or emit red light, green light, blue light, or white light through the organic light-emitting diode OLED. The driving transistor T1 and the switching transistor T2 may be thin film transistors.

[0171] The switching transistor T2 is connected to the scan line SL and the data line DL. The switching transistor T2 can transfer the data voltage input from the data line DL to the driving transistor T1 in response to the switching voltage input from the scan line SL. The storage capacitor Cst can be connected to the switching transistor T2 and the driving voltage line PL, and can store a voltage corresponding to the difference between the voltage transferred from the switching transistor T2 and the first power supply voltage ELVDD supplied through the driving voltage line PL.

[0172] The driving transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with a brightness (e.g., a predetermined brightness) by using the driving current. The counter electrode (e.g., the cathode) of the organic light-emitting diode OLED can receive the second power supply voltage ELVSS.

[0173] Although it is shown in Figure 21 that the pixel circuit PC includes two transistors and one storage capacitor, the embodiments are not limited thereto. The number of transistors and / or the number of storage capacitors can be variously modified according to the design of the pixel circuit PC.

[0174] Figure 22 is a plan view of the first component region RA1, the second component region RA2, and the vicinity thereof of a display panel according to an exemplary embodiment.

[0175] Referring to Figure 22 , the first component region RA1 and the second component region RA2 can be surrounded by the display region DA. A plurality of pixels P are arranged in the display region DA.

[0176] In an embodiment, the transmittance of the first component region RA1 and the transmittance of the second component region RA2 can be different from each other. For example, the first component region RA1 can have a relatively high transmittance, and the second component region RA2 can have a relatively low transmittance. The pixel Pa can be arranged in the second component region RA2. Hereinafter, in order to distinguish from the pixels P arranged in the display region DA, each pixel Pa arranged in the second component region RA2 is referred to as a second pixel Pa. The second pixel Pa can emit red light, green light, blue light, or white light. The second pixel Pa can be substantially the same as the pixel P in the display region DA. For example, in a case where the pixel P in the display region DA has the same structure as the equivalent circuit diagram structure described with reference to Figure 21 , the second pixel Pa can have the same structure as the structure of the pixel P.

[0177] The scan line SL and the data line DL that respectively transmit a scan signal and a data signal to the pixel P and the second pixel Pa can bypass along the edge of the first component region RA1 in the intermediate region MA. The scan line SL and the data line DL can pass through the second component region RA2.

[0178] The second component region RA2 may include a first sub-region RA2-S1 in which the second pixel Pa is arranged and a second sub-region RA2-S2 in which no pixel is arranged. Among Figure 22 the three second pixels Pa arranged in the first sub-region RA2-S1 shown in can respectively emit red light, green light, and blue light. Since the second sub-region RA2-S2 does not include the second pixel Pa, the second sub-region RA2-S2 can be a transmissive region, and the light emitted from the second component arranged in the second component region RA2 or the light propagating toward the second component can pass through the transmissive region. Although the second sub-region RA2-S2 corresponds to a kind of transmissive region, wirings such as the data line DL can pass through the second sub-region RA2-S2. Therefore, the transmittance of the second sub-region RA2-S2 can be relatively smaller than that of the first component region RA1 through which the data line DL does not pass.

[0179] As described above, the first component region RA1 and the second component region RA2 can have different transmittances. Regarding this, the cross-sectional structures of the first component region RA1 and the second component region RA2 are described.

[0180] First, the cross-sectional structure of the first component region RA1 is described.

[0181] Figure 23 is a cross-sectional view of the display panel 10 according to an embodiment, and may correspond to the cross-section taken along Figure 22 the lines XXIIa-XXIIa' and XXIIb-XXIIb'.

[0182] Referring to Figure 23 the display area DA of, the first pixel circuit PC1 is positioned on the substrate 100 and electrically connected to the first organic light-emitting diode OLED1. The first pixel circuit PC1 and the first organic light-emitting diode OLED1 can constitute the pixel P described with reference to Figure 22 The first pixel circuit PC1 can have the same structure as the pixel circuit PC described with reference to Figure 21 The cross-sectional structures of the driving transistor T1 and the first storage capacitor Cst1 included in the first pixel circuit PC1 can be the same as the cross-sectional structures of the first transistor TR1 and the first storage capacitor Cst1 described with reference to Figures 1 to 8 In the embodiment, the cross-sectional structure of the display area DA can be substantially the same as the cross-sectional structure of the first region A1 described with reference to Figure 8 ​

[0183] Referring to Figure 23 For the first component region RA1 of [[reference]], the insulating layer on the substrate 100 may include holes corresponding to the first component region RA1. For example, the first insulating layer IL1 may include a first hole H1, and the second insulating layer IL2 may include a second hole H2. In addition, the planarization layer 209 may include a third hole H3, and the pixel defining layer 211 may include a fourth hole H4. The first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 may be stacked on top of each other. The specific structures of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 and the process of forming the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 may be the same as those of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 described with reference to Figures 1 to 8 In an embodiment, the cross-sectional structure of the first component region RA1 may be substantially the same as the cross-sectional structure of the third region A3 described with reference to Figure 8 .

[0184] Although it is described with reference to Figure 23 that the cross-sectional structures of the display region DA and the first component region RA1 are substantially the same as the cross-sectional structures of the first region A1 and the third region A3 described with reference to Figure 8 , the embodiment is not limited thereto. In another embodiment, the cross-sectional structures of the display region DA and the first component region RA1 of the display panel 10 may be substantially the same as the cross-sectional structures of the first region A1 and the third region A3 of the display panels 10C, 10E, or 10G described with reference to Figure 11 , Figure 13 or Figure 16 . In a case where it is desired that the first component region RA1 has a relatively high transmittance, preferably, the cross-sectional structures of the display region DA and the first component region RA1 of the display panel 10 are the same as the structures of the first region A1 and the third region A3 of the display panel 10E described with reference to Figure 13 .

[0185] Figure 24 is a cross-sectional view of a display panel according to another embodiment and corresponds to a modified embodiment of Figure 23 . Since Figure 24 the display region DA of Figure 23 is the same as the display region DA of

[0186] Referring to Figure 24 For the first component region RA1 of [[reference]], a sealing material 340 may be disposed between the substrate 100 and the encapsulation substrate 300A. The sealing material 340 may prevent or substantially prevent external moisture from traveling toward the display elements between the substrate 100 and the encapsulation substrate 300A. As Figure 24As shown, in the case where the sealing material 340 surrounds the periphery of the first component region RA1, the base 100 and / or the encapsulation base 300A may respectively include holes 100H and 300AH located in the first component region RA1. In this case, compared with the embodiment described with reference to Figure 23 the transmittance of the first component region RA1 can be improved (e.g., increased) even more.

[0187] Although in Figure 24 it is shown that the first hole H1 is defined in the first insulating layer IL1 including the buffer layer 201 and the gate insulating layer 203, and the second hole H2 is defined in the second insulating layer IL2 including the first interlayer insulating layer 205 and the second interlayer insulating layer 207, the embodiment is not limited thereto. In another embodiment, as described with reference to Figure 13 the first hole H1 located in the first component region RA1 may be defined in the first insulating layer IL1' including the buffer layer 201, the gate insulating layer 203, and the first interlayer insulating layer 205, and the second hole H2 may be defined in the second insulating layer IL2' including the second interlayer insulating layer 207.

[0188] Although Figure 23 and Figure 24 show the case where the encapsulation member includes the encapsulation base 300A, the embodiment is not limited thereto. As Figure 9 、 Figure 10 、 Figure 12 、 Figure 14 、 Figure 15 and Figure 17 shown, the encapsulation member may include a thin film encapsulation layer 300B. The first component region RA1 of the display panel 10 may have the same structure as or a structure derived from that of the third region A3 described with reference to Figure 9 、 Figure 10 、 Figure 12 、 Figure 14 、 Figure 15 and Figure 17 For example, in the case where it is desired that the first component region RA1 has a relatively high transmittance, preferably, the first component region RA1 of the display panel 10 has the same structure as that of the third region A3 described with reference to Figure 10 and / or Figure 15 described.

[0189] Next, the cross-sectional structure of the second component region RA2 is described.

[0190] Figure 25 is a cross-sectional view of a display panel according to an embodiment, and may correspond to the cross-section taken along the lines XXIIc-XXIIc' and XXIIa-XXIIa' of Figure 22 .

[0191] As Figure 23 mentioned in Figure 25 , the cross-sectional structure of the first component region RA1 of Figure 8 may have a structure substantially the same as that of the first region A1 of the display panel 10A shown in Figure 11 or the display panel 10C shown in

[0192] Referring to the first sub-region RA2-S1 of the second component region RA2 of Figure 25 , the second pixel circuit PC2 is positioned on the substrate 100 and electrically connected to the second organic light-emitting diode OLED2. The second pixel circuit PC2 and the second organic light-emitting diode OLED2 may constitute the second pixel Pa described with reference to Figure 22 . The second pixel circuit PC2 may have a structure the same as that of the first pixel circuit PC1. The cross-sectional structures of the driving transistor T1a and the second storage capacitor Cst2 included in the second pixel circuit PC2 may be the same as those of the second transistor TR2 and the second storage capacitor Cst2 shown in Figure 11 respectively. In an embodiment, the cross-sectional structure of the first sub-region RA2-S1 may be substantially the same as that of the second region A2 described with reference to Figure 11 . The metal layer ML is disposed under the second pixel circuit PC2. The metal layer ML may prevent or substantially prevent the second pixel circuit PC2 from being damaged by the light emitted from the second component 22 or prevent or substantially prevent the performance of the second pixel circuit PC2 from deteriorating due to the light emitted from the second component 22. In an embodiment, the metal layer ML may have the same voltage level as that of the driving voltage line PL (see Figure 21 ). In another embodiment, the metal layer ML may have the same voltage level as that of the gate electrode of the thin-film transistor T1a.

[0193] Referring to the second sub-region RA2-S2 of the second component region RA2 of Figure 25 , the insulating layer on the substrate 100 may include holes corresponding to the second component region RA2.

[0194] For example, the first insulating layer IL1 may include a first hole H1, and the second insulating layer IL2 may include a second hole H2. In addition, the planarization layer 209 may include a third hole H3, and the pixel defining layer 211 may include a fourth hole H4. The first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 may be stacked on top of each other. The specific structures of the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 and the process of forming the first hole H1, the second hole H2, the third hole H3, and the fourth hole H4 may be the same as those with reference to Figures 1 to 8Those of the described first hole H1, second hole H2, third hole H3, and fourth hole H4 are the same. In an embodiment, the cross-sectional structure of the second sub-region RA2-S2 may be substantially the same as the cross-sectional structure of the third region A3 described with reference to Figure 11 At least one of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 250 may be formed in the first hole H1 of the second sub-region RA2-S2.

[0195] Although in Figure 25 the cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second component region RA2 are respectively substantially the same as the cross-sectional structures of the second region A2 and the third region A3 described with reference to Figure 11 the embodiments are not limited thereto. In another embodiment, the cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second component region RA2 may be respectively substantially the same as the cross-sectional structures of the second region A2 and the third region A3 of the display panel 10G described with reference to Figure 16 The cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second component region RA2 of the display panel 10 may respectively have structures the same as or derived from the structures of the second region A2 and the third region A3 described with reference to

[0196] Although in Figure 25 it is shown that the encapsulation member includes the encapsulation substrate 300A, the embodiments are not limited thereto. In another embodiment, the encapsulation member may include a thin film encapsulation layer 300B described with reference to Figure 9 etc. The cross-sectional structures of the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second component region RA2 of the display panel 10 may respectively have structures the same as or derived from the structures of the second region A2 and the third region A3 described with reference to Figure 9 、 Figure 10 、 Figure 12 、 Figure 14 、 Figure 15 or Figure 17 For example, in a case where the second component 22 does not require a high transmittance like an infrared sensor, the first sub-region RA2-S1 and the second sub-region RA2-S2 of the second component region RA2 of the display panel 10 may respectively have structures the same as the structures of the second region A2 and the third region A3 described with reference to Figure 9 、 Figure 12 、 Figure 14 or Figure 17 The embodiments may provide a display panel and a display device that can provide various functions while simplifying the process the most.

[0197] The embodiments may provide a display panel and a display device that can provide various functions while simplifying the process the most.

[0198] It will be understood that although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, first component, first region, first layer, or first section discussed herein may be termed a second element, second component, second region, second layer, or second section without departing from the spirit and scope of the inventive concept.

[0199] For ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as “beneath” or “below” or “under” another element or feature will then be oriented “above” the other element or feature. Thus, the example terms “beneath” and “below” can encompass both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being “between” two layers, that layer may be the only layer between the two layers, or there may be one or more intervening layers.

[0200] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the inventive concept. As used herein, unless the context clearly dictates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that the terms “comprises” and / or “comprising,” and variations thereof, when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0201] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, by way of example, XYZ, XYY, YZ, and ZZ.

[0202] In addition, the use of "may" in describing embodiments of the inventive concept refers to "one or more embodiments of the inventive concept". Further, the term "exemplary" is intended to mean an example or illustration.

[0203] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, the element or layer can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or there can be one or more intervening elements or layers. When an element or layer is referred to as being "directly on", "directly connected to", "directly coupled to", or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0204] As used herein, the terms "substantially", "about", and similar terms are used as approximating terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values recognized by one of ordinary skill in the art. Further, the specific quantities or ranges recited in this written specification or claims may also include the inherent deviations of measured or calculated values recognized by one of ordinary skill in the art.

[0205] As used herein, the term "use" and its variations can be considered to be synonymous with the term "utilize" and its variations, respectively.

[0206] The display panel and / or any other related devices or components according to embodiments of the present invention described herein may be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a suitable combination of software, firmware, and hardware. For example, various components of the display panel may be formed on one integrated circuit (IC) chip or on separate IC chips. Additionally, various components of the display panel may be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on the same substrate. Further, various components of the display panel may be components of processes or threads that execute computer program instructions and interact with other system components to perform the various functions described herein on one or more processors in one or more computing devices. The computer program instructions are stored in a memory, which may be implemented in a computing device using standard memory devices (such as, by way of example, random access memory (RAM)). The computer program instructions may also be stored in other non-transitory computer-readable media (such as, by way of example, CD-ROM, flash drive, etc.). Additionally, those skilled in the art should recognize that, without departing from the scope of the exemplary embodiments of the present invention, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0207] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various suitable changes in form and detail may be made therein without departing from the spirit and scope defined by the claims and their equivalents.

Claims

1. A display panel, the display panel comprising: a substrate; a transistor located on the substrate; a storage capacitor located on the substrate and electrically connected to the transistor; a metal layer located between the substrate and the transistor; a first insulating layer located on the metal layer and having a first contact opening; and a wiring connected to the metal layer through the first contact opening, wherein the first insulating layer has a first opening spaced apart from the transistor, and the first opening does not overlap with the metal layer in the thickness direction.

2. The display panel according to claim 1, wherein The first insulating layer includes a plurality of sub-layers.

3. The display panel according to claim 1, wherein, The number of layers defining the first contact opening is the same as the number of layers defining the first opening.

4. The display panel according to claim 1, wherein, The material change of the side surface of the first contact opening in the depth direction of the first contact opening is the same as the material change of the side surface of the first opening in the depth direction of the first opening.

5. The display panel according to claim 1, the display panel further comprising: a second insulating layer located on the first insulating layer and having a second opening overlapping with the first opening.

6. The display panel according to claim 5, wherein, The second insulating layer further has a second contact opening for connection between a source electrode or a drain electrode of the transistor and a semiconductor layer of the transistor.

7. The display panel according to claim 6, wherein, The number of layers defining the second contact opening is the same as the number of layers defining the second opening.

8. The display panel according to claim 6, wherein, The material change of the side surface of the second contact opening in the depth direction of the second contact opening is the same as the material change of the side surface of the second opening in the depth direction of the second opening.

9. The display panel according to claim 5, wherein, The width of the second opening is different from the width of the first opening.

10. The display panel according to claim 1, wherein, The metal layer has a voltage level same as that of a gate electrode of the transistor.

11. The display panel according to claim 10, the display panel further comprising: a driving voltage line electrically connected to the transistor and the storage capacitor, wherein the metal layer has a voltage level same as that of the driving voltage line.

12. A display device, the display device comprising: a substrate; a transistor and a storage capacitor located on the substrate; a metal layer located between the substrate and the transistor; a first insulating layer located on the metal layer and having a first contact opening; a wiring connected to the metal layer through the first contact opening; and a component arranged under the substrate, wherein the first insulating layer has a first opening spaced apart from the transistor, and the first opening does not overlap with the metal layer in the thickness direction, and wherein the component corresponds to the first opening.

13. The display device according to claim 12, wherein, The number of layers defining the first contact opening is the same as the number of layers defining the first opening.

14. The display device according to claim 12, wherein, The material change of the side surface of the first contact opening in the depth direction of the first contact opening is the same as the material change of the side surface of the first opening in the depth direction of the first opening.

15. The display device according to claim 12, the display device further comprising: a second insulating layer located on the first insulating layer and having a second opening overlapping with the first opening.

16. The display device according to claim 15, wherein, The second insulating layer further has a second contact opening for connection between a source electrode or a drain electrode of the transistor and the semiconductor layer of the transistor.

17. The display device according to claim 16, wherein, The number of layers defining the second contact opening is the same as the number of layers defining the second opening.

18. The display device according to claim 16, wherein, The material change of a side surface of the second contact opening in a depth direction of the second contact opening is the same as the material change of a side surface of the second opening in a depth direction of the second opening.

19. The display device according to claim 15, wherein, The width of the second opening is different from the width of the first opening.

20. The display device according to claim 12, wherein, The metal layer has a voltage level that is the same as the voltage level of the gate electrode of the transistor.

21. The display device according to claim 12, wherein the display device further comprises: a driving voltage line electrically connected to the transistor and the storage capacitor, wherein the metal layer has a voltage level that is the same as the voltage level of the driving voltage line.

22. The display device according to claim 12, wherein, The substrate comprises: a first region in which a first display element is located; a second region in which a second display element is located; and a third region in which the first opening is located, wherein the transistor, the storage capacitor, and the metal layer are located in the second region, and wherein the transistor and the storage capacitor are electrically connected to the second display element.

23. The display device according to claim 22, wherein, The component corresponds to the second region and the third region, and wherein the metal layer is stacked with a part of the component.

24. The display device according to claim 23, wherein, The component includes an electronic element that emits and / or receives light.

25. The display device according to claim 22, wherein the display device further comprises: a second component corresponding to the second region and different from the component.

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