Source Driver

Abstract

A source driver includes: a plurality of output buffers configured to output data signals respectively corresponding to a plurality of data lines; and an output controller configured to control the timing at which each of the data signals corresponding to the second image data is transmitted from the output buffer to the data line based on a difference between the first image data and the second image data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0046131, filed on April 19, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a source driver, and to a display device having the source driver. Background Art

[0004] The display device includes a display panel and a panel driver. The display panel includes a plurality of pixels. The panel driver includes a scan driver configured to supply a scan signal to the pixels and a source driver configured to supply a data signal to the pixels.

[0005] The source driver includes output buffers coupled to a plurality of data lines, respectively. A DC power supply is supplied to the output buffer to drive the output buffer. The voltage of the DC power supply may be changed by a pattern, grayscale, etc. of an image to be displayed (e.g., due to a voltage drop). The charge amount or charging rate of the data signal supplied from the output buffer to the data line may be reduced due to a change in the voltage of the DC power supply. Summary of the invention

[0006] The embodiments disclosed herein provide a source driver configured to control the timing of data signals being transmitted to data lines according to changes in image data. The embodiments disclosed herein also provide a display device having the source driver.

[0007] According to one aspect of the present disclosure, a source driver is provided, comprising: a plurality of output buffers configured to output data signals respectively corresponding to a plurality of data lines; and an output controller configured to control the timing at which each of the data signals corresponding to the second image data is transmitted from the output buffer to the data line based on a difference between the first image data and the second image data.

[0008] The first image data may correspond to data signals supplied to pixels in a k-1th pixel row, and the second image data may correspond to data signals supplied to pixels in a kth pixel row, k being a natural number greater than 1.

[0009] The output controller may include: a delay determiner configured to output an output delay signal based on a result obtained by comparing first image data and second image data with a threshold reference; and a delay switch coupled between an output terminal of an output buffer among a plurality of output buffers and a data line among a plurality of data lines and configured to be turned off in response to the output delay signal.

[0010] When a grayscale difference between the first image data and the second image data is smaller than a reference difference, the delay determiner may be configured to output an output delay signal.

[0011] When a grayscale difference between the first image data and the second image data is greater than or equal to a reference difference, the delay switch may be configured to maintain a turned-on state.

[0012] The period during which the delay switch is turned off may be shorter than one horizontal period.

[0013] When the delay switch is turned off, the output buffer corresponding to the delay switch may be configured so that a data line corresponding to the output buffer has an electrical high impedance state.

[0014] When the first image data and the second image data are equal to or greater than a first reference grayscale, the delay determiner may be configured to output an output delay signal.

[0015] The delay determiner may be configured to output an output delay signal when the first image data and the second image data are equal to or less than a second reference grayscale, wherein the second reference grayscale is greater than the first reference grayscale.

[0016] The delay switch may be configured to be turned off during the delay period in response to the output delay signal.

[0017] When one of the first image data and the second image data is less than a first reference grayscale and the other of the first image data and the second image data is greater than a second reference grayscale, the delay switch may be configured to maintain a turned-on state.

[0018] The output controller may further include a precharge switch coupled between one of the plurality of data lines and a power source and configured to be turned on in response to the output delay signal.

[0019] During the delay period in which the delay switch is turned off, the voltage of the power source may be supplied to the data line corresponding to the precharge switch among the plurality of data lines.

[0020] According to another aspect of the present disclosure, there is provided a display device including a display panel, which includes a plurality of pixels, a scan driver configured to supply scan signals to pixels in units of pixel rows, and a source driver configured to supply data signals to the pixels in response to the scan signals, and includes a plurality of output buffers configured to output the data signals to a plurality of data lines, respectively; and an output controller configured to control the timing of each of the data signals corresponding to the current image data being transmitted from the output buffer to the data line based on the difference between the previous image data and the current image data.

[0021] The previous image data may correspond to data signals supplied to pixels in a k-1th pixel row, and the current image data may correspond to data signals supplied to pixels in a kth pixel row, k being a natural number greater than 1.

[0022] The output controller may include: a delay determiner configured to output an output delay signal based on a result obtained by comparing a grayscale difference between previous image data and current image data with a reference difference; and a delay switch coupled between an output terminal of an output buffer among a plurality of output buffers and a data line among a plurality of data lines and configured to be turned off in response to the output delay signal.

[0023] When the grayscale difference is less than the reference difference, the delay determiner may be configured to output an output delay signal.

[0024] When the grayscale difference is greater than or equal to the reference difference, the delay switch may be configured to maintain a turned-on state.

[0025] When the delay switch is turned off, the output buffer corresponding to the delay switch may be configured so that a data line corresponding to the output buffer has an electrically high impedance.

[0026] According to the present disclosure, a source driver and a display device having the source driver can control at least one of the output buffers to have a temporary high impedance state during a delay period based on the change between the image data of the previous pixel row (e.g., the k-1 pixel row) and the image data of the current pixel row (e.g., the k pixel row). Therefore, the equivalent resistance (or load) relative to the first power supply can be reduced so that the voltage fluctuation of the first power supply used to drive the output buffer can be reduced or minimized. Therefore, the voltage level change rate (conversion rate or voltage charging rate) of the data signal (data line voltage) relative to the grayscale change between the pixel rows can be increased, and display defects such as image drag or image distortion can be minimized or reduced. Therefore, the image quality of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a block diagram illustrating a source driver according to an embodiment of the present disclosure.

[0030] Figure 3 The diagram is included in Figure 2 Schematic diagram of an example of an output buffer and a portion of an output controller in a source driver shown in .

[0031] Figure 4 is shown and supplied to Figure 3 Schematic diagram of an example of image data corresponding to a data signal of an output buffer shown in FIG.

[0032] Figure 5 It is a graphic with Figure 4 The image data shown in Figure 3 An example of the operation of the output buffer and the output controller is shown in the waveform diagram.

[0033] Fig. 6A and Figure 6B is based on Figure 5 The waveform diagram shown in Figure 3 A schematic diagram of an example of the operation of a delay switch is shown in FIG.

[0034] Figure 7 The diagram is included in Figure 2 Schematic diagram of an example of an output buffer and a portion of an output controller in a source driver shown in .

[0035] Figure 8 It is a graphic with Figure 4 The image data shown in Figure 7 An example of the operation of the output buffer and the output controller is shown in the waveform diagram. DETAILED DESCRIPTION

[0036] By referring to the detailed description and the accompanying drawings of the embodiments, it is easier to understand the features of the inventive concept and the method for realizing the inventive concept. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the embodiments may be embodied in various forms and should not be construed as being limited to the embodiments illustrated herein. On the contrary, these embodiments are provided as examples so that the disclosure will be thorough and complete, and the aspects and features of the inventive concept will be fully conveyed to those skilled in the art. Therefore, processes, elements and techniques that are unnecessary for a person of ordinary skill in the art to fully understand the aspects and features of the inventive concept may not be described.

[0037] Unless otherwise specified, throughout the drawings and written description, the same reference numerals represent the same elements, and therefore their description will not be repeated. Further, parts not related to the description of the embodiment may not be shown to make the description clear. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

[0038] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations from the illustrated shapes as a result of, for example, manufacturing techniques and / or tolerances are contemplated. Further, for the purpose of describing embodiments according to the concept of the present disclosure, the specific structural or functional descriptions disclosed herein are illustrative only. Therefore, the embodiments disclosed herein should not be interpreted as being limited to specific illustrated shapes of regions, but rather to include shape deviations, for example, caused by manufacturing. For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and / or implant concentration gradients at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may cause some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions illustrated in the drawings are schematic in nature, and their shapes are not intended to illustrate the true shape of the region of the device and are not intended to be limiting. In addition, as will be appreciated by those skilled in the art, the embodiments may be modified in various different ways, all without departing from the spirit and scope of the present disclosure.

[0039] In the detailed description, for the purpose of explanation, several specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

[0040] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited to these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the first element, component, region, layer or section described below may be referred to as a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

[0041] It will be understood that when an element, layer, region or component is referred to as being "on", "connected to" or "coupled to" another element, layer, region or component, it can be directly on, directly connected to or directly coupled to the other element, layer, region or component, or there can be one or more intervening elements, layers, regions or components. However, "direct connection / direct coupling" refers to a component being directly connected or coupled to another component without an intermediate component. At the same time, other expressions describing the relationship between components, such as "between", "immediately between", or "adjacent to" and "closely adjacent" can be similarly understood. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0042] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used herein, the singular form "a" is intended to also include the plural form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include", "have" and "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0043] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to take into account the inherent deviations of measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "approximately" or "approximately" includes the value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the value. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0044] When a certain embodiment can be implemented differently, a specific process can be performed in a different order from the described order. For example, two processes described in succession can be performed substantially simultaneously or in a reverse order from the described order.

[0045] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. Further, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. Further, the various components of these devices can be processes or threads for executing various functions described herein on one or more processors that execute computer program instructions and interact with other system components in one or more computing devices. Computer program instructions are stored in a memory, and the memory can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). Computer program instructions can also be stored in other non-transient computer-readable media (such as, for example, a CD-ROM, a flash drive, etc.). In addition, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the embodiments of the present disclosure.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined herein.

[0047] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0048] Reference Figure 1 , the display device 1000 may include a display panel 100 , a scan driver 200 , a source driver 300 (or a data driver), and a timing controller 400 .

[0049] The display device 1000 may be implemented using a self-luminous display device including a plurality of self-luminous devices. For example, the display device 1000 may be an organic light-emitting display device including an organic light-emitting device, or may be a display device including an inorganic light-emitting device. However, this is merely illustrative, and the display device 1000 may be implemented using a liquid crystal display device, a plasma display device, a quantum dot display device, etc.

[0050] The display panel 100 may include a plurality of scan lines SL and a plurality of data lines DL, and may include a plurality of pixels PX coupled to the scan lines SL and the data lines DL, respectively. In an embodiment, a pixel PX at an i-th row and a j-th column (i and j are natural numbers) may be coupled to a scan line SLi corresponding to an i-th pixel row, and to a data line DLj corresponding to a j-th pixel column.

[0051] The timing controller 400 may generate a first control signal SCS and a second control signal DCS corresponding to an externally supplied synchronization signal. The first control signal SCS may be supplied to the scan driver 200, and the second control signal DCS may be supplied to the source driver 300. In addition, the timing controller 400 may re-adjust the externally supplied input image data RGB into the image data DATA, and may supply the image data DATA to the source driver 300.

[0052] The scanning start signal and the clock signal may be included in the first control signal SCS. The scanning start signal may control the first timing of the scanning signal. The clock signal may be used to shift the scanning start signal.

[0053] A source start pulse and a clock signal may be included in the second control signal DCS. The source start pulse may control the sampling start time of the data. The clock signal may be used to control the sampling operation.

[0054] The scan driver 200 may receive a first control signal SCS from the timing controller 400, and may supply a scan signal to the scan line SL in response to the first control signal SCS. For example, the scan driver 200 may sequentially supply the scan signal to the scan line SL. When the scan signal is sequentially supplied, the pixel PX may be selected in units of horizontal lines (or pixel rows), for example, line by line.

[0055] The scan signal may be set to a turn-on level (eg, a logic high voltage). When the scan signal is supplied, a transistor included in the pixel PX and receiving the scan signal may be set to a turn-on state.

[0056] The source driver 300 may receive a second control signal DCS and image data DATA from the timing controller 400. The source driver 300 may supply a data signal to the data line DL in response to the second control signal DCS. The data signal supplied to the data line DL may be supplied to the pixel PX selected by the scan signal. To this end, the source driver 300 may supply the data signal to the data line DL in synchronization with the scan signal.

[0057] In an embodiment, the source driver 300 may include a plurality of output buffers configured to output data signals corresponding to pixel rows to data lines DL, respectively, and may include an output controller configured to control the timing of data signals corresponding to current image data being transmitted from the output buffers to the data lines DL, respectively, based on the difference between the previous image data and the current image data. The previous image data may correspond to data signals supplied to pixels (e.g., predetermined pixels) included in the previous pixel row (e.g., the k-1 pixel row (k is a natural number greater than 1)). The current image data may correspond to data signals supplied to pixels included in the current pixel row (e.g., the k-1 pixel row). The pixels of the previous pixel row and the pixels of the current pixel row are coupled to the same data line.

[0058] In an embodiment, the display device 1000 may further include an emission driver configured to supply an emission control signal to the pixel PX and a power supply configured to supply a power voltage (eg, a predetermined power voltage) to the pixel PX.

[0059] Figure 2 is a block diagram illustrating a source driver according to an embodiment of the present disclosure.

[0060] Reference Figure 1 and Figure 2 , the source driver 300 may include a shift register 310 , a latch 320 , a digital-to-analog converter (DAC) 330 , a gamma voltage generator 340 , an output buffer 350 , and an output controller 360 .

[0061] In some embodiments, the source driver 300 may be mounted on the display panel 100 in the form of a driving IC. Alternatively, the source driver 300 may be integrated on the display panel 100.

[0062] The shift register 310 may receive a horizontal start signal STH and a data clock signal DCLK from a controller (eg, a predetermined controller). The shift register 310 may generate a sampling signal by shifting the horizontal start signal STH in synchronization with the data clock signal DCLK.

[0063] The latch 320 may latch the image data DATA in response to the sampling signal. The latch 320 may output the latched image data. The latch 320 may sequentially latch the image data DATA in response to the sampling signal supplied from the shift register 310, and may supply the latched image data to the DAC 330.

[0064] The latch 320 has a size corresponding to the number of bits of the image data DATA. In an embodiment, the latch 320 may include m sampling latches (m is a natural number) for storing m digital image data DATA respectively. The sampling latch may have a storage capacity corresponding to the number of bits of the image data DATA, and may sequentially store the digital image data signal in response to a sampling signal.

[0065] In an embodiment, the latch 320 may further include a holding latch. The holding latch may receive and store the image data DATA from the sampling latch substantially simultaneously, and may supply the sampled image data DATA stored in a previous period to the DAC 330 substantially simultaneously.

[0066] In an embodiment, the latch 320 may compare image data with respect to consecutive scan lines (e.g., pixel rows). In another embodiment, a comparison operation may be performed on image data (e.g., DATA1 and DATA2) latched with respect to consecutive scan lines by a delay determiner 364 of the output controller 360. The first image data DATA1 may correspond to a data signal supplied to pixels included in a k-1th pixel row (k is a natural number greater than 1), and the second image data DATA2 may correspond to a data signal supplied to pixels included in a kth pixel row.

[0067] The DAC 330 may convert the latched image data DATA into an analog data signal based on the gamma voltage GV. The converted analog data signal may be supplied to the output buffer 350.

[0068] The gamma voltage generator 340 may generate the gamma voltage GV by using a plurality of gamma reference voltages. For example, the gamma voltage GV may be determined based on a gamma curve (eg, a predetermined gamma curve such as a 2.2 gamma curve, etc.).

[0069] The output buffer 350 may output the data signal output from the DAC 330 to the data lines DL1 to DLm. For example, the output buffer 350 may output the data signal corresponding to the corresponding pixel row to the data lines DL1 to DLm in response to a predetermined clock signal CLK.

[0070] The output controller 360 may individually control the timing at which the data signals corresponding to the second image data DATA2 are transmitted from the output buffer 350 to the data lines DL1 to DLm, respectively. The first image data DATA1 and the second image data DATA2 are latched image data corresponding to pixel rows adjacent to each other. In an embodiment, the output controller 360 may include a delay determiner 364 and a plurality of delay switches 362 (e.g., DSW1 to DSWm) corresponding to each of the output buffers 350.

[0071] The delay switches 362 may be coupled between the output terminals of the output buffer 350 and the data lines DL1 to DLm, respectively. Each of the delay switches 362 may be turned off in response to the output delay signal ODS. The output delay signal ODS may be supplied individually to the delay switches 362 according to changes in image data corresponding to the output delay signal ODS.

[0072] In an embodiment, when the first delay switch DSW1 coupled to the first data line DL1 is turned off, the first output buffer corresponding to the first delay switch DSW1 and the first data line DL1 may be electrically disconnected (open circuited). For example, the first output buffer may have an electrically high impedance (Hi-Z) state. Each of the delay switches 362 may be turned off during a period (e.g., a predetermined period) in response to the output delay signal ODS.

[0073] The delay determiner 364 may compare the first image data DATA1 and the second image data DATA2 with a threshold reference RD (e.g., a predetermined threshold reference), and may output the output delay signal ODS based on the comparison result. For example, when a data signal corresponding to each of the first image data DATA1 and the second image data DATA2 is supplied to the first data line DL1, the first image data DATA1 may be image data corresponding to a pixel of the first data line DL1 coupled to the k-1 pixel row, and the second image data DATA2 may be image data corresponding to a pixel of the first data line DL1 coupled to the k pixel row. That is, the result obtained by comparing the first image data DATA1 and the second image data DATA2 with the threshold reference RD may be understood as a grayscale change between adjacent pixel rows.

[0074] For example, when the grayscale difference between the first image data DATA1 and the second image data DATA2 is less than a reference difference (e.g., a predetermined reference difference), the delay determiner 364 may output the output delay signal ODS corresponding to the corresponding delay switch. On the contrary, when the grayscale difference between the first image data DATA1 and the second image data DATA2 is greater than or equal to the reference difference, the delay determiner 364 does not output the output delay signal ODS to the corresponding delay switch. That is, the corresponding delay switch may maintain a conducting state.

[0075] For example, when the grayscale difference between the first image data DATA1 and the second image data DATA2 is less than grayscale 200, the output delay signal ODS is output. When the grayscale difference between the first image data DATA1 and the second image data DATA2 is greater than or equal to grayscale 200, the output delay signal ODS is not output.

[0076] As described above, when the image data variation (or grayscale difference) between adjacent pixels PX in the extending direction of the data line is relatively small, the output of the data signal supplied to the corresponding pixel can be further delayed compared to the output of the data signal supplied to another pixel located in the same pixel row. Therefore, the present embodiment can improve the charging rate (and conversion rate) of charging the data signal output from the output buffer 350 to a desired voltage level.

[0077] Figure 3 The diagram is included in Figure 2 Schematic diagram of an example of an output buffer and a portion of an output controller in a source driver shown in .

[0078] Reference Figure 2 and Figure 3The first to fourth output buffers 351 to 354 may be coupled to the first to fourth data lines DL1 to DL4, respectively. The first to fourth delay switches DSW1 to DSW4 may be coupled between the first to fourth output buffers 351 to 354 and the first to fourth data lines DL1 to DL4, respectively.

[0079] Each of the first to fourth output buffers 351 to 354 may be a voltage follower type buffer amplifier. The first to fourth output buffers 351 to 354 may receive first to fourth analog data signals obtained by converting digital image data, respectively, and may output first to fourth data signals DV1 to DV4. In addition, the voltage of the first power supply VDD1 may be supplied to the first to fourth output buffers 351 to 354 so as to perform the operations of the first to fourth output buffers 351 to 354. That is, the first power supply VDD1 may be output as a high potential voltage for driving the output buffer 350. In addition, in the drawings, GND is a ground terminal.

[0080] The voltage level of the data signal supplied to the output buffer 350 may vary depending on an image pattern or an image load. Due to the influence of the variation of the data signal, an unexpected fluctuation (or distortion) may occur in the voltage of the first power source VDD1.

[0081] For example, when a voltage drop of the first power source VDD1 occurs, the output of the output buffer 350 may become unstable. For example, the voltage of the first power source VDD1 drops, and the change rate (e.g., conversion rate) of the voltage levels of the first data signal DV1 to the fourth data signal DV4 outputted from the first output buffer 351 to the fourth output buffer 354, respectively, may decrease. Therefore, the first data signal DV1 to the fourth data signal DV4 cannot reach the desired voltage level and may be supplied to the pixel through the first data line DL1 to the fourth data line DL4. Therefore, the image quality may deteriorate.

[0082] The source driver 300 and the display device 1000 having the same according to an embodiment of the present disclosure include an output controller 360 configured to separate output timings of respective output buffers 350 so that the output of the first power source VDD1 can be stabilized.

[0083] The first to fourth delay switches DSW1 to DSW4 may be coupled between the output terminals of the first to fourth output buffers 351 to 354 and the first to fourth data lines DL1 to DL4, respectively. The first to fourth delay switches DSW1 to DSW4 may be turned on or off, respectively, based on the first to fourth output delay signals ODS1 to ODS4. For example, when the first output delay signal ODS1 is output, the first delay switch DSW1 may be turned off, and the first data line DL1 may be electrically disconnected from the first output buffer 351 (or may have a high impedance state).

[0084] Whether the first to fourth output delay signals ODS1 to ODS4 are to be outputted may be determined by the difference (or grayscale change) between the first image data DATA1 and the second image data DATA2. The output controller 360 may determine the output of the first to fourth output delay signals ODS1 to ODS4 based on the difference between the first image data DATA1 and the second image data DATA2.

[0085] Figure 4 is shown and supplied to Figure 3 Schematic diagram of an example of image data corresponding to a data signal of an output buffer shown in FIG. Figure 5 It is a graphic with Figure 4 The output buffer and output controller ( Figure 3 A waveform diagram of an example of the operation of FIG. 1 ).

[0086] Reference Figures 2 to 5 , the delay determiner 364 included in the output controller 360 can determine the first output delay signal ODS1 to the fourth output delay signal ODS4 based on the respective differences between the previous image data DAT1-1, DAT1-2, DAT1-3 and DAT1-4 and the current image data DAT2-1, DAT2-2, DAT2-3 and DAT2-4.

[0087] The previous image data DAT1-1, DAT1-2, DAT1-3, and DAT1-4 may correspond to the first to fourth data signals DV1 to DV4 supplied to the k-th pixel row, respectively. Figure 3 In the delay period DP (see Figure 5 ) are respectively generated from the current image data DAT2-1, DAT2-2, DAT2-3 and DAT2-4.

[0088] In an embodiment, a first reference grayscale RG1 and a second reference grayscale RG2 may be set in the delay determiner 364. The second reference grayscale RG2 may be greater than the first reference grayscale RG1. For example, the first reference grayscale RG1 may be set to grayscale 10, and the second reference grayscale RG2 may be set to grayscale 200.

[0089] The delay determiner 364 may compare the previous image data DAT1-1, DAT1-2, DAT1-3, and DAT1-4 and the current image data DAT2-1, DAT2-2, DAT2-3, and DAT2-4 with the first reference grayscale RG1 and the second reference grayscale RG2, respectively. The first previous image data DAT1-1 and the first current image data DAT2-1 may correspond to the first data signal DV1. The second previous image data DAT1-2 and the second current image data DAT2-2 may correspond to the second data signal DV2. The third previous image data DAT1-3 and the third current image data DAT2-3 may correspond to the third data signal DV3. The fourth previous image data DAT1-4 and the fourth current image data DAT2-4 may correspond to the fourth data signal DV4.

[0090] In an embodiment, when the previous image data and the current image data are equal to or less than the second reference grayscale RG2, the delay determiner 364 may output the output delay signal ODS. Figure 4 As shown in , when the first previous image data DAT1-1 and the first current image data DAT2-1 are equal to or less than the second reference gray RG2, the delay determiner 364 may output the first output delay signal ODS1. Therefore, the first delay switch DSW1 may have an off state during the delay period DP in which the first output delay signal ODS1 is output. Similarly, because the third previous image data DAT1-3 and the third current image data DAT2-3 are equal to or less than the second reference gray RG2, the delay determiner 364 may output the third output delay signal ODS3.

[0091] In an embodiment, when the previous image data and the current image data are equal to or greater than the first reference grayscale RG1, the delay determiner 364 may output the output delay signal ODS. Figure 4 As shown in , because the second previous image data DAT1-2 and the second current image data DAT2-2 are equal to or greater than the first reference grayscale RG1, the delay determiner 364 may output the second output delay signal ODS2. Therefore, the second delay switch DSW2 may have an off state during the delay period DP. In an embodiment, the period during which the second delay switch DSW2 has an off state may be shorter than one horizontal period. For example, the period during which the second delay switch DSW2 has an off state may be about 10ns to about 40ns.

[0092] In an embodiment, when one of the previous image data and the current image data is less than the first reference grayscale RG1 and the other of the previous image data and the current image data is greater than the second reference grayscale RG2, the corresponding delay switch may maintain a conducting state. Figure 4 As shown in , because the fourth previous image data DAT1-4 is less than the first reference grayscale RG1 and the fourth current image data DAT2-4 is greater than the second reference grayscale RG2, the delay determiner 364 does not output the fourth output delay signal ODS4.

[0093] Figure 5 Show according to Figure 4 The output signal of the image data shown in FIG. Figure 5 As shown in FIG. 1 , when the scan signal Sk is supplied to the k-th pixel row, the first to fourth data signals DV1 to DV4 may be written into some pixels in the k-th pixel row through the first to fourth data lines DL1 to DL4 , respectively.

[0094] The transistor of the pixel can be turned on by the logic high level of the scan signal Sk. In addition, the first to fourth delay switches DSW1 to DSW4 can be turned off by the logic low levels of the first to fourth output delay signals ODS1 to ODS4, respectively, and can be turned on by the logic high levels of the first to fourth output delay signals ODS1 to ODS4, respectively. Figure 5 , a case will be described in which the first to third output delay signals ODS1 to ODS3 have a logic low level for turning off the first to third delay switches DSW1 to DSW3 and the fourth output delay signal ODS4 has a logic high level H so that the fourth delay switch DSW4 maintains a turned-on state.

[0095] The clock signal CLK may determine a timing at which a data signal corresponding to each of the pixel rows is output from the output buffer 350 .

[0096] At the first time t1, the clock signal CLK may change from a logic low level to a logic high level. Before the first time t1, the first to fourth data line voltages D1 to D4 supplied to the first to fourth data lines DL1 to DL4 may correspond to image data (eg, DAT1-1 to DAT1-4) of the k-1th pixel row.

[0097] At the first moment t1, the first output buffer 351 to the fourth output buffer 354 can start to output the first data line voltage D1 to the fourth data line voltage D4 corresponding to the image data (e.g., DAT2-1 to DAT2-4) of the k-th pixel row. In this example, only the fourth delay switch DSW4 maintains the on state. Therefore, the fourth data line voltage D4 can change or can start to change to correspond to the fourth current image data DAT2-4. The fourth data line voltage D4 corresponding to a large grayscale change usually uses a relatively long time for the purpose of voltage change. Therefore, the fourth data signal DV4 can be supplied to the fourth data line DL4 from the first moment t1.

[0098] At the first moment t1, the first output delay signal ODS1 to the third output delay signal ODS3 may be supplied to the first delay switch DSW1 to the third delay switch DSW3. The first output delay signal ODS1 to the third output delay signal ODS3 may be supplied during the delay period DP. Because the first data signal DV1 to the third data signal DV3 correspond to a relatively small grayscale change, the first data signal DV1 to the third data signal DV3 have a relatively small voltage change. Therefore, the time suitable for the voltage change is shorter than the time for changing the fourth data line voltage D4. Therefore, during the delay period DP, the first output buffer 351 to the third output buffer 353 may have a high impedance (Hi-z) state from the first data line DL1 to the third data line DL3, respectively.

[0099] However, since the delay period DP is a relatively very short time of about 10 ns to about 40 ns, the existing data voltages supplied to the first to third data lines DL1 to DL3 may be maintained.

[0100] Because the first to third output buffers 351 to 353 have a Hi-z state, the number of data lines DL coupled from the output buffer 350 during the delay period DP is reduced. Therefore, the equivalent resistance (or load) relative to the first power supply VDD1 during the delay period DP can be reduced. Therefore, the voltage drop or voltage fluctuation width of the first power supply VDD1 is minimized or reduced, and the conversion rate of the voltage output from the fourth output buffer 354 can be improved.

[0101] Subsequently, at the second time t2, the first to third output delay signals ODS1 to ODS3 may be changed from a logic low level to a logic high level. Figure 52 illustrates a case where the change timing of the first output delay signal ODS1 to the third output delay signal ODS3 is approximately equal to the change timing of the clock signal CLK, but the change timing of the first output delay signal ODS1 to the third output delay signal ODS3 is not limited thereto. For example, the timing at which the first output delay signal ODS1 to the third output delay signal ODS3 changes from a logic low level to a logic high level may be between the first time t1 and the second time t2, or may be between the second time t2 and the third time t3.

[0102] In an embodiment, the delay period DP may be set differently relative to the data line depending on the change in grayscale. For example, when the change in grayscale becomes smaller, the pulse width of the output delay signal ODS corresponding thereto (e.g., the width of the logic low level period of the output delay signal ODS) may be reduced at an interval (e.g., a predetermined interval).

[0103] At the second time t2, the first to third delay switches DSW1 to DSW3 may be turned on, and the first to third output buffers 351 to 353 may be electrically coupled to the first to third data lines DL1 to DL3, respectively. Since the first to third data line voltages D1 to D3 have a small fluctuation width, the first to third data line voltages D1 to D3 may reach a voltage level corresponding to the first to third current image data DAT2-1 to DAT2-3 before the third time t3.

[0104] Since the voltage charging of the fourth data line voltage D4 starts from or begins at the first time t1, the fourth data line voltage D4 may reach a voltage level (eg, a target voltage) corresponding to the fourth current image data DAT2-4 sufficiently before the third time t3.

[0105] Subsequently, the scan signal Sk corresponding to the kth pixel row can be supplied during the write period WP between the third moment t3 and the fourth moment t4, and the first data line voltage D1 to the fourth data line voltage D4 corresponding to the first current image data DAT2-1 to the fourth current image data DAT2-4 can be supplied to the pixels of the kth pixel row during the write period WP.

[0106] Figures 3 to 5 The configuration and operation shown in FIG. 1 may be applied to (or extended to) all data lines included in the display device 1000 .

[0107] As described above, the source driver 300 and the display device 1000 having the source driver 300 according to the embodiment of the present disclosure can control at least some of the output buffers 350 to have a high impedance state during the delay period DP based on the change between the image data of the previous pixel row and the image data of the current pixel row. Therefore, the equivalent resistance (or load) relative to the first power supply VDD1 is reduced, so that the voltage fluctuation of the first power supply VDD1 for driving the output buffer 350 can be reduced or minimized. Therefore, the voltage level change rate (conversion rate or voltage charging rate) of the data signal (data line voltage) relative to the grayscale change between the pixel rows can be increased, and the image quality of the display device can be improved.

[0108] Fig. 6A and Figure 6B is based on Figure 5 The waveform diagram shown in Figure 3 A schematic diagram of an example of the operation of a delay switch is shown in FIG.

[0109] Reference Figures 3 to 6B , the timing at which the data signal is supplied according to a change (or difference) in image data between a previous pixel row and a current pixel row may be individually controlled for each of the first to fourth data lines DL1 to DL4 .

[0110] The change in grayscale of the image data corresponding to the first to third data lines DL1 to DL3 may be less than a threshold reference (eg, a predetermined threshold reference), and the change in grayscale of the image data corresponding to the fourth data line DL4 may be greater than the threshold reference. Figures 5 to 6B As shown in , the first to third delay switches DSW1 to DSW3 may be turned off during the delay period DP, and may be turned on after the delay period DP. The fourth delay switch DSW4 may maintain a turned-on state even during the delay period DP. During the delay period DP, the first to third output buffers 351 to 353 and the first to third data lines DL1 to DL3 do not serve as a load of the first power supply VDD1.

[0111] Figure 7 The diagram is included in Figure 2 Schematic diagram of an example of an output buffer and a portion of an output controller in a source driver shown in .

[0112] exist Figure 7 In, with reference Figure 3 Components equivalent to the components described herein are denoted by the same reference numerals, and their overlapping or repeated descriptions will be omitted. Figure 7 The output controller shown in Figure 3The output controllers shown in are substantially identical or similar in configuration.

[0113] Reference Figure 2 , Figure 3 and Figure 7 , the output controller 360 may include delay switches DSW1 to DSW4 and a delay determiner 364. The output controller 360 may further include precharge switches PSW1 to PSW4 respectively coupled to the data lines DL1 to DL4.

[0114] In an embodiment, the precharge switches PSW1 to PSW4 may be coupled between the data lines DL1 to DL4 and the second power supply VDD2 (e.g., a predetermined second power supply), respectively. The precharge switches PSW1 to PSW4 may be turned on, respectively, in response to the output delay signals ODS1 to ODS4. For example, the first precharge switch PSW1 may be coupled between the first data line DL1 and the second power supply VDD2. The first precharge switch PSW1 may include a gate electrode supplied with the first output delay signal ODS1.

[0115] exist Figure 7 , an embodiment in which the delay switches DSW1 to DSW4 are implemented using NMOS (n-type metal oxide semiconductor) transistors and the precharge switches PSW1 to PSW4 are implemented using PMOS (p-type metal oxide semiconductor) transistors is illustrated. In the embodiment, the delay switches DSW1 to DSW4 and the precharge switches PSW1 to PSW4 can share gate signals, respectively. That is, when the first delay switch DSW1 is turned on, the first precharge switch PSW1 can be turned off. When the first delay switch DSW1 is turned off, the first precharge switch PSW1 can be turned on.

[0116] However, this is merely illustrative, and gate electrodes of the precharge switches PSW1 to PSW4 may be coupled to signal lines for supplying separate control signals. The precharge switches PSW1 to PSW4 may operate complementarily with the delay switches DSW1 to DSW4 , respectively.

[0117] In some embodiments, the precharge switches PSW1 to PSW4 may be turned on during the delay period DP. When the first precharge switch PSW1 is turned on, the voltage of the second power supply VDD2 may be supplied to the first data line DL1. The voltage of the second power supply VDD2 may be set to a middle level of the entire data voltage range. However, this is merely illustrative, and the voltage of the second power supply VDD2 is not limited thereto.

[0118] During the delay period DP, a voltage (e.g., a predetermined voltage) can be precharged in the data line (e.g., a predetermined data line) by the operation of the precharge switches PSW1 to PSW4. Therefore, after the delay period DP, the voltage of the data line supplied with the data signal can quickly reach the target voltage. Therefore, the problem that the voltage of the data line fails to reach the target voltage due to the temporary high impedance state of the output buffer 350 can be prevented, or its effect can be reduced.

[0119] Figure 8 It is a graphic with Figure 4 The image data shown in Figure 7 An example of the operation of the output buffer and the output controller is shown in the waveform diagram.

[0120] exist Figure 8 In, with reference Figure 5 Components equivalent to the components described are denoted by the same reference numerals, and overlapping or duplicate descriptions thereof will be omitted.

[0121] Reference Figure 4 , Figure 5 , Figure 7 and Figure 8 , when the scan signal Sk is supplied to the k-th pixel row, the first to fourth data signals DV1 to DV4 may be written into some pixels in the k-th pixel row through the first to fourth data lines DL1 to DL4 .

[0122] During the delay period DP, the first to third output delay signals ODS1 to ODS3 may be output, the first to third delay switches DSW1 to DSW3 may be turned off, and the first to third precharge switches PSW1 to PSW3 may be turned on. In addition, the fourth delay switch DSW4 may maintain a turned-on state, and the fourth precharge switch PSW4 may maintain a turned-off state.

[0123] The fourth data line voltage D4 may be charged as the fourth data signal DV4 supplied from the fourth output buffer 354 starting from the first time t1 .

[0124] During the delay period DP, the first to third data lines DL1 to DL3 may be charged by the second power source VDD2. Therefore, each of the first to third data line voltages D1 to D3 may be charged (eg, to a predetermined voltage level).

[0125] Subsequently, at the second time t2, the first to third delay switches DSW1 to DSW3 may be turned on, and the first to third precharge switches PSW1 to PSW3 may be turned off. Therefore, the first to third data line voltages D1 to D3 may be quickly charged to the first to third data signals DV1 to DV3 supplied from the first to third output buffers 351 to 353, respectively. Therefore, the problem that the voltage of the data line fails to reach the target voltage due to the temporary high impedance state of the output buffer 350 may be reduced or prevented.

[0126] Next, at the third time t3 , the first to fourth data line voltages D1 to D4 may correspond to the first to fourth data signals DV1 to DV4 (eg, target voltages), respectively.

[0127] As described above, the source driver 300 and the display device 1000 having the source driver 300 according to the embodiment of the present disclosure can control at least some of the output buffers 350 to have a temporary high impedance state during the delay period DP based on the change between the image data of the previous pixel row and the image data of the current pixel row. Therefore, the equivalent resistance (or load) relative to the first power supply VDD1 is reduced, so that the voltage fluctuation of the first power supply VDD1 for driving the output buffer 350 can be reduced or minimized. Therefore, the voltage level change rate (conversion rate or voltage charging rate) of the data signal (data line voltage) relative to the grayscale change between the pixel rows can be increased, and the image quality of the display device can be improved.

[0128] Embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art to which this application is submitted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims and the functional equivalents to be included therein.

Claims

1. A source driver, comprising: a plurality of output buffers configured to output data signals respectively corresponding to the plurality of data lines; as well as An output controller configured to control the timing of each of the data signals corresponding to the second image data being transmitted from the output buffer to the corresponding data line of the data lines based on a difference between first image data and second image data, wherein the first image data corresponds to a data signal supplied to a first pixel in a first pixel row, and the second image data corresponds to a data signal supplied to a second pixel in a second pixel row different from the first pixel row.

2. The source driver according to claim 1, wherein: The first image data corresponds to data signals supplied to pixels in a k-1th pixel row, and wherein the second image data corresponds to data signals supplied to pixels in a kth pixel row, k being a natural number greater than 1.

3. The source driver according to claim 1, wherein: The output controller comprises: a delay determiner configured to output an output delay signal based on a result obtained by comparing the first image data and the second image data with a threshold reference; and A delay switch is coupled between an output terminal of one of the plurality of output buffers and one of the plurality of data lines and is configured to be turned off in response to the output delay signal.

4. The source driver according to claim 3, wherein: When the grayscale difference between the first image data and the second image data is smaller than a reference difference, the delay determiner is configured to output the output delay signal, and Wherein, when the grayscale difference between the first image data and the second image data is greater than or equal to the reference difference, the delay switch is configured to maintain a conducting state.

5. The source driver according to claim 3, wherein: The period during which the delay switch is turned off is shorter than one horizontal period. 6 . The source driver according to claim 3 , when the delay switch is turned off, the output buffer corresponding to the delay switch is configured so that a data line corresponding to the output buffer has an electrical high impedance state.

7. The source driver according to claim 3, wherein: When the first image data and the second image data are equal to or greater than a first reference grayscale, the delay determiner is configured to output the output delay signal.

8. The source driver according to claim 7, wherein: When the first image data and the second image data are equal to or less than a second reference grayscale, the delay determiner is configured to output the output delay signal, Wherein, the second reference grayscale is greater than the first reference grayscale, and The delay switch is configured to be turned off during a delay period in response to the output delay signal.

9. The source driver according to claim 8, wherein: When one of the first image data and the second image data is less than the first reference grayscale and the other of the first image data and the second image data is greater than the second reference grayscale, the delay switch is configured to maintain a turned-on state.

10. The source driver according to claim 3, wherein: The output controller further includes a precharge switch coupled between one of the plurality of data lines and a power source and configured to be turned on in response to the output delay signal, and During a delay period in which the delay switch is turned off, the voltage of the power supply is supplied to the data line corresponding to the precharge switch among the plurality of data lines.

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