A method for aging transistors and a display device including the transistors.

Abstract

This invention relates to a method for aging a transistor and a display device including the transistor. The display device includes a plurality of pixels. Each of the plurality of pixels includes: a first transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor having a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; and a third transistor having a first gate electrode connected to the first scan line, a second gate electrode, a first electrode connected to the first node, and a second electrode connected to the third node. The second gate electrode may be in a floating state, and the third transistor may be aged to reduce leakage current, thereby improving image generation.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0047416, filed on April 23, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a method for aging a transistor and a display device including the transistor, and more specifically, to aging such a transistor to prevent or mitigate leakage current when the transistor is in a turned-off state. Background Technology

[0004] With the development of information technology, display devices, as the connecting medium between users and information, have become increasingly important. In response, as individual users demand that these devices not only sustain their lives but also pursue leisure and other informational goals, the use of display devices such as liquid crystal displays, organic light-emitting diode displays, and plasma displays has increased.

[0005] When in use, a particular display device can be driven at various driving frequencies. For example, when a display device is driven at a frequency of 60Hz, it can display 60 image frames per second. Conversely, when a display device is driven at a frequency of 30Hz, it can display 30 image frames per second.

[0006] When a display device is driven at a low frequency, each pixel is required to maintain information about each image frame for a relatively long period of time. As a result, leakage current may occur in each pixel, causing the information about the image frame to be lost. Therefore, image degradation or flickering may occur. Summary of the Invention

[0007] The embodiments described herein provide a method for aging a transistor to prevent or mitigate leakage current when the transistor is in a turned-off state, and a display device including the transistor. As a result, transient afterimages that are typically caused by leakage current can also be prevented or mitigated.

[0008] The display device according to an embodiment may include a plurality of pixels. Each of the plurality of pixels may include: a first transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor having a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node; and a third transistor having a first gate electrode connected to the first scan line, a second gate electrode, a first electrode connected to the first node, and a second electrode connected to the third node.

[0009] The second gate electrode can be in a floating state.

[0010] The third transistor may include a semiconductor layer disposed between a first gate electrode and a second gate electrode, and the semiconductor layer may include a source region, a channel region, and a drain region.

[0011] The second gate electrode can be arranged to overlap at least a portion of at least one of the source region, channel region, and drain region.

[0012] The third transistor may further include a gate insulating layer disposed between the first gate electrode and the semiconductor layer, wherein the gate insulating layer has a first region adjacent to the drain region and a second region adjacent to the source region, wherein the electron density in the first region is higher than the electron density in the second region, or the hole density in the first region is higher than the hole density in the second region.

[0013] The second gate electrode can be arranged to overlap with a portion of the semiconductor layer other than the source region.

[0014] The first electrode of the third transistor can be connected to the drain region, and the second electrode of the third transistor can be connected to the source region.

[0015] The first electrode of the third transistor can be connected to the source region, and the second electrode of the third transistor can be connected to the drain region.

[0016] The third transistor may further include a gate insulating layer disposed between the first gate electrode and the semiconductor layer, wherein the gate insulating layer has a first region adjacent to the drain region and a second region adjacent to the source region, wherein the electron density in the first region is higher than the electron density in the second region, or the hole density in the first region is higher than the hole density in the second region.

[0017] The third transistor may include: a first sub-transistor having a sub-gate electrode connected to a first scan line, a first electrode connected to a first node, and a second electrode; and a second sub-transistor having a sub-gate electrode connected to the first scan line, a first electrode connected to the second electrode of the first sub-transistor, and a second electrode connected to a third node.

[0018] The sub-gate electrode of the first sub-transistor can be separated from the first electrode and the second electrode of the first sub-transistor, and the sub-gate electrode of the second sub-transistor can be separated from the first electrode and the second electrode of the second sub-transistor.

[0019] One of the first sub-transistor and the second sub-transistor may include a second gate electrode. The first sub-transistor may include a semiconductor layer located between the sub-gate electrode and the second gate electrode of the first sub-transistor, the semiconductor layer including a source region, a channel region, and a drain region, the second gate electrode being arranged to overlap at least a portion of at least one of the source region, the channel region, and the drain region, and the first sub-transistor may further include a gate insulating layer disposed between the sub-gate electrode and the semiconductor layer of the first sub-transistor, wherein the gate insulating layer may include a first region adjacent to the drain region and a second region adjacent to the source region, and wherein the electron density in the first region is higher than the electron density in the second region, or the hole density in the first region is higher than the hole density in the second region.

[0020] The first sub-transistor may include a semiconductor layer disposed between a sub-gate electrode and a second gate electrode of the first sub-transistor, the semiconductor layer including a source region, a channel region, and a drain region. The second gate electrode may be disposed to overlap at least a portion of the semiconductor layer, excluding the source region.

[0021] At least one of the first sub-transistor and the second sub-transistor may include a second gate electrode.

[0022] The second sub-transistor may include a semiconductor layer disposed between a sub-gate electrode and a second gate electrode of the second sub-transistor, the semiconductor layer including a source region, a channel region, and a drain region. The second gate electrode may be disposed to overlap at least a portion of at least one of the source region, the channel region, and the drain region, and the second sub-transistor may further include a gate insulating layer disposed between the sub-gate electrode and the semiconductor layer of the second sub-transistor, wherein the gate insulating layer has a first region adjacent to the drain region and a second region adjacent to the source region, and wherein the electron density in the first region is higher than the electron density in the second region, or the hole density in the first region is higher than the hole density in the second region.

[0023] The second sub-transistor may include a semiconductor layer disposed between a sub-gate electrode and a second gate electrode of the second sub-transistor, the semiconductor layer including a source region, a channel region, and a drain region. The second gate electrode may be arranged to overlap with a portion of at least one of the drain region and the channel region, and the second gate electrode may not overlap with the source region.

[0024] The first sub-transistor and the second sub-transistor may include a second gate electrode.

[0025] Each of the multiple pixels may further include a light-emitting diode, and a second gate electrode may be connected to the cathode of the light-emitting diode.

[0026] A method for aging a transistor according to an embodiment, the transistor including a first gate electrode, a second gate electrode, and a semiconductor layer disposed between the first gate electrode and the second gate electrode and including a source region, a channel region, and a drain region, all doped with acceptors, includes: applying a voltage higher than the voltage of the drain region to the first gate electrode, and applying a voltage lower than the voltage of the first gate electrode to the second gate electrode.

[0027] The second gate electrode can be arranged to overlap at least a portion of at least one of the source region, channel region, and drain region.

[0028] The second gate electrode can be arranged to overlap with at least a portion of at least one of the drain region and the channel region.

[0029] A method for aging a transistor according to an embodiment, the transistor including a first gate electrode, a second gate electrode, and a semiconductor layer disposed between the first gate electrode and the second gate electrode and including a source region, a channel region, and a drain region, all doped with donors, includes: applying a voltage lower than the voltage of the drain region to the first gate electrode; and applying a voltage higher than the voltage of the first gate electrode to the second gate electrode.

[0030] The second gate electrode can be arranged to overlap at least a portion of at least one of the source region, channel region, and drain region.

[0031] The second gate electrode can be arranged to overlap with at least a portion of at least one of the drain region and the channel region.

[0032] In this paper, a method for aging transistors and a display device including such transistors can reduce leakage current when the transistors are in the off state.

[0033] In this paper, a method for aging transistors and a display device including such transistors are described to mitigate transient afterimages. Attached Figure Description

[0034] The above and other features of the invention will become more apparent from a further detailed description of embodiments of the invention with reference to the accompanying drawings, in which:

[0035] Figure 1 A display device configuration according to an embodiment of the present disclosure is shown;

[0036] Figure 2 Pixels are shown according to embodiments of the present disclosure;

[0037] Figure 3 A method for driving pixels according to an embodiment of the present disclosure is shown;

[0038] Figure 4 An example of pixel leakage current is shown;

[0039] Figure 5 The structure of the fourth transistor is shown;

[0040] Figure 6 This is a schematic diagram used to compare the leakage current of a transistor before and after aging.

[0041] Figure 7 Pixels are shown according to another embodiment of this disclosure;

[0042] Figure 8 The structure of a third transistor according to an embodiment of the present disclosure is shown;

[0043] Figure 9 The structure of a third transistor according to another embodiment of the present disclosure is shown;

[0044] Figures 10 to 13 Pixels are shown according to another embodiment of this disclosure; and

[0045] Figures 14 to 16 The auxiliary power supply line used to mitigate transient afterimages is shown. Detailed Implementation

[0046] Hereinafter, various embodiments of the invention will be described in detail with reference to the accompanying drawings. The invention may be embodied in many different forms and is not limited to the embodiments described herein.

[0047] To clearly illustrate the invention, components not related to the description have been omitted, and throughout the text, the same or similar components are labeled with the same reference numerals.

[0048] For ease of description, the dimensions and thicknesses of the various components shown in the accompanying drawings are arbitrarily illustrated, as the invention is not necessarily limited to those shown in the drawings.

[0049] In this specification, the term “and / or” includes any and all combinations of one or more of the associated listed items. When following a list of elements, expressions such as “at least one of…” modify the entire list of elements, not any individual element in the list. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] Throughout this specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, or "electrically connected" to the other element using one or more intermediate elements inserted between the element and the other element. It will be further understood that when the terms "comprising" and / or "including" are used in this specification, they or they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0051] The terms “overlapping” or “being overlapped” mean that the first object can be on top of or under the second object, and vice versa.

[0052] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe individual elements, these elements should not be limited to these terms. These terms are used to distinguish one element from another, or for the convenience of description and explanation. For example, when “first element” is discussed in the specification, it may be referred to as “second element” or “third element,” and “second element” and “third element” may be referred to in a similar manner without departing from the teaching of this document.

[0053] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0054] Figure 1 This is a schematic diagram illustrating a display device configuration according to an embodiment of the present disclosure.

[0055] Reference Figure 1 The display device 10 according to embodiments of the present disclosure may include a timing controller 11, a data driver 12, a scan driver 13, a light-emitting driver 14, and a pixel unit 15.

[0056] The timing controller 11 can receive grayscale values ​​and control signals for each frame from an external processor. The timing controller 11 can render grayscale values ​​so that they correspond to the specifications of the display device 10. For example, the external processor can provide red, green, and blue grayscale values ​​for each pixel. However, when the pixel unit 15 has a honeycomb structure, pixels may not correspond one-to-one to their respective grayscale values ​​because adjacent pixels share pixels. Therefore, grayscale rendering is necessary. When pixels correspond one-to-one to their respective grayscale values, grayscale rendering may not be necessary. Unrendered or rendered grayscale values ​​can be provided to the data driver 12. Furthermore, the timing controller 11 can provide control signals applicable to each of the data driver 12, scan driver 13, and light-emitting driver 14 for frame display.

[0057] The data driver 12 can use grayscale values ​​and control signals to generate data voltages to be provided to data lines D1, D2, D3, ..., Dn. For example, the data driver 12 can use a clock signal to sample grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data lines D1 to Dn in the pixel row unit (where n can be an integer greater than zero).

[0058] The scan driver 13 can receive clock signals, scan start signals, etc. from the timing controller 11 to generate scan signals to be provided to scan lines S1, S2, S3, ..., and Sm (where m can be an integer greater than zero).

[0059] Scan driver 13 can sequentially provide scan signals with on-level pulses to scan lines S1, S2, S3, ..., Sm. Scan driver 13 can include scan stages configured as shift registers. Scan driver 13 can generate scan signals under the control of a clock signal in a manner that sequentially transmits scan start signals in the form of on-level pulses to the next scan stage.

[0060] The LED driver 14 can receive clock signals, LED stop start signals, etc., from the timing controller 11 to generate LED signals to be provided to LED lines E1, E2, E3, ..., Eo. For example, the LED driver 14 can sequentially provide LED signals with off-level pulses to LED lines E1 to Eo (where o can be a positive integer). For example, each LED stage in the LED driver 14 can be configured as a shift register and can generate LED signals under the control of a clock signal by sequentially transmitting an on-level pulse in the form of an LED stop start signal to the next LED stage.

[0061] Pixel unit 15 includes pixels. Each pixel PXij can be connected to a corresponding data line, scan line, and light-emitting line. Furthermore, pixel PXij can be connected to a first power line, a second power line, and an auxiliary power line (where i and j can be natural numbers). Pixel PXij can refer to a pixel in which the scan transistor is connected to the i-th scan line and the j-th data line.

[0062] Figure 2 Pixels are shown according to an embodiment of this disclosure.

[0063] Reference Figure 2 The pixel PXij includes transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst and a light-emitting diode LD.

[0064] In the following description, circuit configurations of P-type transistors will be presented as examples. However, those skilled in the art will be able to design circuit configurations of N-type transistors by distinguishing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art will be able to design circuit configurations combining P-type and N-type transistors. P-type transistors are collectively referred to as transistors in which the amount of current flowing increases as the voltage difference between the gate and source electrodes increases in the negative direction. N-type transistors are collectively referred to as transistors in which the amount of current flowing increases as the voltage difference between the gate and source electrodes increases in the positive direction. Transistors can be configured in various forms such as thin-film transistors (TFTs), field-effect transistors (FETs), and bipolar junction transistors (BJTs).

[0065] The first transistor T1 may have a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be referred to as a driving transistor.

[0066] The second transistor T2 may have a gate electrode connected to the i-th scan line Si, a first electrode connected to the data line Dj, and a second electrode connected to the second node N2. The second transistor T2 may be referred to as a scan transistor.

[0067] The third transistor T3 may have a gate electrode connected to the i-th scan line Si, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be referred to as a diode-connected transistor.

[0068] The fourth transistor T4 may have a gate electrode connected to the (i-1)th scan line S(i-1), a first electrode connected to the first node N1, and a second electrode connected to the initialization line INTL. In another embodiment, the gate electrode of the fourth transistor T4 may be connected to another scan line. The fourth transistor T4 may be referred to as a gate initialization transistor.

[0069] The fifth transistor T5 may have a gate electrode connected to the i-th light-emitting line Ei, a first electrode connected to the first power supply line ELVDDL, and a second electrode connected to the second node N2. The fifth transistor T5 may be referred to as a light-emitting transistor. In another embodiment, the gate electrode of the fifth transistor T5 may be connected to another light-emitting line.

[0070] The sixth transistor T6 may have a gate electrode connected to the i-th light-emitting line Ei, a first electrode connected to the third node N3, and a second electrode connected to the anode of the light-emitting diode LD. The sixth transistor T6 may be referred to as a light-emitting transistor. In another embodiment, the gate electrode of the sixth transistor T6 may be connected to another light-emitting line.

[0071] The seventh transistor T7 may have a gate electrode connected to the i-th scan line Si, a first electrode connected to the initialization line INTL, and a second electrode connected to the anode of the light-emitting diode LD. The seventh transistor T7 may be referred to as an anode initialization transistor. In another embodiment, the gate electrode of the seventh transistor T7 may be connected to another scan line.

[0072] The first electrode of the storage capacitor Cst can be connected to the first power line ELVDDL, and the second electrode can be connected to the first node N1.

[0073] The anode of the light-emitting diode (LD) can be connected to the second electrode of the sixth transistor T6, and the cathode can be connected to the second power supply line ELVSSL. The LD can include organic light-emitting diodes, inorganic light-emitting diodes, quantum dot light-emitting diodes, etc.

[0074] A first power supply voltage can be applied to a first power supply line ELVDDL, a second power supply voltage can be applied to a second power supply line ELVSSL, and an initialization voltage can be applied to an initialization line INTL. For example, the first power supply voltage can be greater than the second power supply voltage. Alternatively, the initialization voltage can be equal to or greater than the second power supply voltage.

[0075] Figure 3 This is a schematic diagram illustrating a method for driving pixels according to embodiments of the present disclosure.

[0076] First, the data voltage DATA(i-1)j for the (i-1)th pixel is applied to the data line Dj, and the on-level (low level) scan signal is applied to the (i-1)th scan line S(i-1).

[0077] At this time, because the off-level (high-level) scan signal is applied to the i-th scan line Si, the second transistor T2 is turned off, and the data voltage DATA(i-1)j is prevented from being introduced into the pixel PXij.

[0078] At this time, because the fourth transistor T4 is turned on, the first node N1 is connected to the initialization line INTL, and the voltage of the first node N1 is initialized. Because the off-level light emission signal is applied to the light emission line Ei, transistors T5 and T6 are turned off, preventing the light-emitting diode LD from emitting light according to the initialization voltage.

[0079] The data voltage DATAij for the i-th pixel PXij is applied to the data line Dj, and a scan signal at the on level is applied to the i-th scan line Si. Therefore, transistors T2, T1, and T3 are turned on, and the data line Dj and the first node N1 are electrically connected. Thus, a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DATAij is applied to the second electrode of the storage capacitor Cst (i.e., the first node N1), and the storage capacitor Cst maintains a voltage corresponding to the difference between the first power supply voltage and the compensation voltage. This period can be referred to as the threshold voltage compensation period.

[0080] Because the seventh transistor T7 is turned on, the anode of the light-emitting diode LD is connected to the initialization line INTL, and the light-emitting diode LD is initialized with a charge amount corresponding to the voltage difference between the initialization voltage and the second power supply voltage.

[0081] When a conduction-level light-emitting signal is applied to the light-emitting line Ei, transistors T5 and T6 can be turned on. Therefore, the drive current path is formed as the path of the first power line ELVDDL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light-emitting diode LD, and the second power line ELVSSL.

[0082] The amount of drive current flowing through the first and second electrodes of the first transistor T1 is controlled according to the voltage maintained in the storage capacitor Cst. The light-emitting diode LD emits light at a brightness corresponding to the amount of drive current. The light-emitting diode LD emits light until a light-emitting signal at the off level is applied to the light-emitting line Ei.

[0083] Figure 4 An example of leakage current in a pixel is shown.

[0084] Ideally, when a high-level (off level) scan signal is applied to the gate electrodes of the third transistor T3 and the fourth transistor T4, the current flowing through the third transistor T3 and the fourth transistor T4 should be zero or very small.

[0085] However, leakage current LC1 can be generated by turning off the third transistor T3 during the light-emitting period of the LED LD. Furthermore, leakage current LC2 can be generated by turning off the fourth transistor T4 outside the initialization period of the first node N1. As described above, when leakage current is generated, information about the image frame may not be maintained, and therefore, the image may degrade or experience flickering.

[0086] Figure 5 The structure of the fourth transistor is shown.

[0087] Reference Figure 5 The fourth transistor T4 may include a gate electrode GE4, a source electrode SE4, a drain electrode DE4, and a semiconductor layer ACT4. The semiconductor layer ACT4 may include a source region SA4, a channel region CA4, and a drain region DA4. The source electrode SE4 may be connected to the source region SA4, and the drain electrode DE4 may be connected to the drain region DA4.

[0088] The substrate SUB can be formed from various materials such as glass, polymers, and metals. The substrate SUB can be selected from rigid and flexible substrates depending on the application. When the substrate SUB is configured to include polymeric organic materials, it can be formed from polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene terephthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. Alternatively, the substrate SUB can be formed from fiberglass reinforced plastic (FRP).

[0089] The barrier layer (BAR) can be located on the substrate (SUB). Additionally, the buffer layer (BUF) can be located on the barrier layer (BAR). Furthermore, the semiconductor layer (ACT4) can be located on the buffer layer (BUF).

[0090] The barrier layer (BAR) and buffer layer (BUF) can be selectively included layers to prevent impurity diffusion or moisture transport from the substrate SUB to the semiconductor layer ACT4. The barrier layer (BAR) and buffer layer (BUF) can be insulating layers. For example, the barrier layer (BAR) and buffer layer (BUF) can be made of silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y (and so on)

[0091] The semiconductor layer ACT4 can be formed from polycrystalline silicon, amorphous silicon, oxide semiconductors, organic semiconductors, inorganic semiconductors, etc. The semiconductor layer ACT4 may include a source region SA4, a channel region CA4, and a drain region DA4.

[0092] As described above, when assuming the fourth transistor T4 is a P-type transistor, each of the source region SA4 and the drain region DA4 can be acceptor-doped. The first electrode of the fourth transistor T4 can be the source electrode SE4, and the second electrode can be the drain electrode DE4.

[0093] On the other hand, assuming the fourth transistor T4 is an N-type transistor, each of the source region SA4 and the drain region DA4 can be donor-doped. The first electrode of the fourth transistor T4 can be the drain electrode DE4, and the second electrode can be the source electrode SE4.

[0094] In the following text, it is assumed that the fourth transistor T4 is a P-type transistor.

[0095] The gate insulating layer GI can be located on the semiconductor layer ACT4. For example, the gate insulating layer GI can be made of silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y The region of the gate insulating layer GI adjacent to the drain region DA4 can have a higher electron density than the region of the gate insulating layer GI adjacent to the source region SA4. For example, a charge trapping region CTA4 can exist in the region of the gate insulating layer GI adjacent to the drain region DA4. Electrons trapped and fixed in position within the lattice of the gate insulating layer GI can be retained in the charge trapping region CTA4.

[0096] The gate electrode GE4 can be a conductor. For example, the gate electrode GE4 can be formed using gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), platinum (Pt), etc.

[0097] The insulating layer IL can be located on the gate electrode GE4 and the gate insulating layer GI. For example, the insulating layer IL can be made of silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y (and so on)

[0098] The source electrode SE4 and drain electrode DE4 can be located on the insulating layer IL. The source electrode SE4 can be connected to the source region SA4 through the contact holes of the insulating layer IL and the gate insulating layer GI. The drain electrode DE4 can be connected to the drain region DA4 through the contact holes of the insulating layer IL and the gate insulating layer GI. The source electrode SE4 and drain electrode DE4 can be formed using gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), platinum (Pt), etc.

[0099] Each of the aforementioned layers and electrodes can be configured as a single layer or multiple layers.

[0100] Hereinafter, a method for aging transistors according to embodiments of the present disclosure will be described.

[0101] When the transistors of a display device, such as display device 10, are used continuously, the characteristics of the transistors may change rapidly or not rapidly during a certain initial period.

[0102] The aging process of a transistor can be a process used to prevent changes in the characteristics of the transistor, even if the user uses the display device 10 continuously. The aging process can include applying stress to the transistor when manufacturing the display device 10, which includes the transistor.

[0103] The method for aging the fourth transistor T4 according to an embodiment of the present disclosure can be performed by applying a bias voltage higher than the bias voltage of the drain electrode DE4 to the gate electrode GE4 of the fourth transistor T4. Therefore, electrons are trapped in the lattice of the gate insulating layer GI, and thus, a charge trapping region CTA4 can be formed.

[0104] Figure 6 This is a schematic diagram used to compare the leakage current of a transistor before and after aging.

[0105] Reference Figure 6 The graph shows the gate-source voltage Vgs versus the leakage current Id of the transistor.

[0106] Referring to the curve AFA when the aging process is performed and the curve BFA when the aging process is not performed, it can be confirmed that the leakage current is reduced when the aging process is performed.

[0107] Ideally, when a high-level voltage is applied to the gate electrode of a P-type transistor, the transistor is turned off, preventing leakage current from being generated. However, due to gate-induced leakage (“GIDL”) phenomenon, leakage current may still be generated even when a high-level voltage is applied to the gate electrode.

[0108] The primary cause of the GIDL phenomenon is tunneling based on the electric field generated between the gate and drain electrodes. (See again...) Figure 5 The fourth transistor T4 according to an embodiment of the present disclosure has a structure in which an electric field generated by a charge trapping region CTA4 compensates for a portion of the electric field between the gate electrode and the drain electrode, and thus the GIDL phenomenon can be mitigated.

[0109] Reference Figure 5 and Figure 6The aging process described herein is primarily applicable to P-type transistors, but the aging process described herein can be similarly applied to N-type transistors.

[0110] For example, the aging process can be performed by applying a bias voltage lower than the bias voltage of the drain electrode DE4 to the gate electrode GE4 of the N-type fourth transistor T4. Therefore, holes can be trapped in the lattice of the gate insulating layer GI, and thus, a charge trapping region CTA4 can be formed. Consequently, the region of the gate insulating layer GI adjacent to the drain region DA4 can have a higher hole density than the region of the gate insulating layer GI adjacent to the source region SA4.

[0111] Reference Figure 4 Since the gate electrode of the fourth transistor T4 is connected to the (i-1)th scan line S(i-1) and the drain electrode of the fourth transistor T4 is connected to the initialization line INTL, the voltage suitable for the aging process can be conveniently applied to the gate electrode and drain electrode of the fourth transistor T4.

[0112] However, voltage cannot be directly applied to the drain electrode of the third transistor T3, and therefore, it is difficult to perform aging on the third transistor T3.

[0113] Figure 7 A pixel is shown according to another embodiment of this disclosure.

[0114] exist Figure 7 In the pixel PXija, with Figure 2 Compared to the pixel PXij, the configuration of the third transistor T3a has been changed.

[0115] Reference Figure 7 The third transistor T3a may include a second gate electrode. The electrical node of the second gate electrode may be different from that of the first gate electrode. The second gate electrode may be connected to an auxiliary power line BMLL. The auxiliary power line BMLL and the second gate electrode connected to the auxiliary power line BMLL may always be in a floating state. For example, the auxiliary power line BMLL may not be configured to be powered. In other words, when the user uses the display device 10, the auxiliary power line BMLL may not be powered because an aging process has occurred before it is used by the user.

[0116] According to embodiments of this disclosure, the auxiliary power line BMLL can therefore be used during the aging process of the third transistor T3a. For example, during the aging process, the auxiliary power line BMLL can be connected to an auxiliary power supply, and after the aging process, the auxiliary power line BMLL can be disconnected from the auxiliary power supply.

[0117] Figure 8 The structure of a third transistor according to an embodiment of the present disclosure is shown.

[0118] Reference Figure 8 The third transistor T3a may include a first gate electrode GE3, a source electrode SE3, a drain electrode DE3, and a semiconductor layer ACT3. The semiconductor layer ACT3 may include a source region SA3, a channel region CA3, and a drain region DA3. The source electrode SE3 may be connected to the source region SA3, and the drain electrode DE3 may be connected to the drain region DA3.

[0119] The barrier layer (BAR) can be located on the substrate (SUB).

[0120] The second gate electrode BE can be located on the barrier layer BAR. The second gate electrode BE can be a conductor. The second gate electrode BE can be formed using gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), platinum (Pt), etc.

[0121] exist Figure 8 In some embodiments, at least a portion of the second gate electrode BE may overlap with the source region SA3, the channel region CA3, and the drain region DA3. For example, the second gate electrode BE may overlap with the source region SA3, the channel region CA3, and the drain region DA3.

[0122] The buffer layer BUF can be located on the barrier layer BAR and the second gate electrode BE. Furthermore, the semiconductor layer ACT3 can be located on the buffer layer BUF. The semiconductor layer ACT3 can be located between the first gate electrode GE3 and the second gate electrode BE.

[0123] The semiconductor layer ACT3 can be formed from polycrystalline silicon, amorphous silicon, oxide semiconductors, organic semiconductors, inorganic semiconductors, etc. The semiconductor layer ACT3 may include a source region SA3, a channel region CA3, and a drain region DA3.

[0124] As described above, when assuming the third transistor T3a is a P-type transistor, each of the source region SA3 and the drain region DA3 can be acceptor-doped. Therefore, the first electrode of the third transistor T3a can be the drain electrode DE3, and the second electrode can be the source electrode SE3.

[0125] On the other hand, assuming the third transistor T3a is an N-type transistor, each of the source region SA3 and the drain region DA3 can be donor-doped. Therefore, the first electrode of the third transistor T3a can be the source electrode SE3, and the second electrode can be the drain electrode DE3.

[0126] In the following text, it is assumed that the third transistor T3a is a P-type transistor.

[0127] The gate insulating layer GI can be located on the semiconductor layer ACT3. The gate insulating layer GI can be located between the first gate electrode GE3 and the semiconductor layer ACT3.

[0128] The region of the gate insulating layer GI adjacent to the drain region DA3 can have a higher electron density than the region of the gate insulating layer GI adjacent to the source region SA3. For example, a charge trapping region CTA3 can exist in the region of the gate insulating layer GI adjacent to the drain region DA3. Electrons trapped and fixed in position within the lattice of the gate insulating layer GI can be retained in the charge trapping region CTA3.

[0129] The insulating layer IL can be located on the first gate electrode GE3 and the gate insulating layer GI.

[0130] The source electrode SE3 and drain electrode DE3 can be located on the insulating layer IL. The source electrode SE3 can be connected to the source region SA3 through the contact holes of the insulating layer IL and the gate insulating layer GI. The drain electrode DE3 can be connected to the drain region DA3 through the contact holes of the insulating layer IL and the gate insulating layer GI.

[0131] Each of the aforementioned layers and electrodes can be configured as a single layer or multiple layers.

[0132] Hereinafter, a method for aging a third transistor T3a according to an embodiment of the present disclosure will be described.

[0133] The method for aging the third transistor T3a according to an embodiment of this disclosure can be performed by applying a bias voltage higher than the bias voltage of the drain electrode DE3 to the first gate electrode GE3. At this time, a voltage lower than the voltage of the first gate electrode GE3 can be applied to the second gate electrode BE. That is, the aforementioned auxiliary power supply can provide a voltage lower than the voltage of the first gate electrode GE3 to the second gate electrode BE through the auxiliary power line BMLL.

[0134] According to embodiments of this disclosure, in cases where it is difficult to directly apply a voltage lower than the voltage of the first gate electrode GE3 to the drain electrode DE3, a voltage lower than the voltage of the first gate electrode GE3 can be directly applied to the second gate electrode BE. Therefore, the electric field between the first gate electrode GE3 and the drain electrode DE3 is enhanced. Thus, electrons can be effectively trapped in the lattice of the gate insulating layer GI based on the charge trapping region CTA3.

[0135] The reduction in leakage current due to the mitigation of the GIDL phenomenon caused by the charge trapping region CTA3, compared with the reference... Figure 6 The descriptions are the same.

[0136] As described, even if the third transistor T3a is configured as a P-type transistor, the same aging process can be performed for the N-type transistor that is the third transistor T3a.

[0137] For example, when the third transistor T3a is configured as an N-type transistor, the source region SA3 and the drain region DA3 can be doped with donors.

[0138] The aging method according to embodiments of this disclosure may include applying a voltage lower than the voltage of the drain region DA3 to the first gate electrode GE3. That is, a voltage lower than the voltage of the drain electrode DE3 may be applied to the first gate electrode GE3. Furthermore, the aging method may include applying a voltage higher than the voltage of the first gate electrode GE3 to the second gate electrode BE. Therefore, holes can be trapped in the lattice of the gate insulating layer GI, and thus a charge trapping region CTA3 can be formed. Therefore, the region of the gate insulating layer GI adjacent to the drain region DA3 may have a higher hole density than the region of the gate insulating layer GI adjacent to the source region SA3.

[0139] Figure 9 The structure of a third transistor according to another embodiment of the present disclosure is shown.

[0140] Figure 9 The third transistor T3a' is different from the second gate electrode BE'. Figure 8 The third transistor T3a.

[0141] At least a portion of the second gate electrode BE' may overlap with the drain region DA3. Alternatively, the second gate electrode BE' may not overlap with the source region SA3.

[0142] As described above, it is required that the charge trapping region CTA3 be formed in the portion of the gate insulating layer GI close to the drain region DA3. Therefore, it is sufficient for the electric field provided by the second gate electrode BE' to be supplied to the drain region DA3.

[0143] Figures 10 to 13 Pixels are shown according to another embodiment of this disclosure.

[0144] exist Figure 10 In pixel PXijb, the configuration of the third transistor T3b can be different. Figure 7 The pixel PXija. Repeated descriptions of the same configuration for pixels PXijb and PXija will be omitted.

[0145] The third transistor T3b may include a first sub-transistor T3b1 and a second sub-transistor T3b2.

[0146] The first sub-transistor T3b1 may have a sub-gate electrode connected to the i-th scan line Si, a first electrode connected to the first node N1, and a second electrode connected to the first electrode of the second sub-transistor T3b2.

[0147] The second sub-transistor T3b2 may have a sub-gate electrode connected to the i-th scan line Si, a first electrode connected to the second electrode of the first sub-transistor T3b1, and a second electrode connected to the third node N3.

[0148] For example, Figure 10 The diagram shows each of the sub-gate electrodes connected to the i-th scan line Si as different from the example shown. Figure 8 The gate electrode GE3 is shown in the diagram. That is, each sub-gate electrode forms a separate connection from the third transistor T3b to the scan line Si.

[0149] The first sub-transistor T3b1 may include a second gate electrode. The second gate electrode may be connected to an auxiliary power supply line BMLL. The structure of the first sub-transistor T3b1 may include... Figure 8 and Figure 9 The structure of the third transistors T3a and T3a'.

[0150] However, the second sub-transistor T3b2 may not include a second gate electrode. The structure of the second sub-transistor T3b2 may include... Figure 5 The structure of the fourth transistor T4.

[0151] To prevent leakage current, the first sub-transistor T3b1 and the second sub-transistor T3b2 can be connected in series. Because the first sub-transistor T3b1 and the second sub-transistor T3b2, which are connected in series, share the same current path, the aging process can be performed only on the first sub-transistor T3b1 to mitigate leakage current.

[0152] exist Figure 11 In pixel PXijb', the configuration of the third transistor T3b' can be different. Figure 7 The configuration of the third transistor T3a in pixel PXija.

[0153] The third transistor T3b' may include the first sub-transistor T3b1' and the second sub-transistor T3b2'.

[0154] The first sub-transistor T3b1' may have a sub-gate electrode connected to the i-th scan line Si, a first electrode connected to the first node N1, and a second electrode connected to the first electrode of the second sub-transistor T3b2'.

[0155] The second sub-transistor T3b2' may have a sub-gate electrode connected to the i-th scan line Si, a first electrode connected to the second electrode of the first sub-transistor T3b1', and a second electrode connected to the third node N3.

[0156] At this point, the first sub-transistor T3b1' may not include the second gate electrode. The structure of the first sub-transistor T3b1' may include... Figure 5The structure of the fourth transistor T4.

[0157] However, the second sub-transistor T3b2' may include a second gate electrode. The second gate electrode may be connected to the auxiliary power line BMLL. The structure of the second sub-transistor T3b2' can follow... Figure 8 and Figure 9 The structure of the third transistors T3a and T3a'.

[0158] To prevent leakage current, the first sub-transistor T3b1' and the second sub-transistor T3b2' can be connected in series. Because the first sub-transistor T3b1' and the second sub-transistor T3b2', which are connected in series, share the same current path, the aging process can be performed only on the second sub-transistor T3b2' to mitigate leakage current.

[0159] exist Figure 12 In pixel PXijb", the configuration of the third transistor T3b can be different. Figure 7 The configuration of the third transistor T3a in pixel PXija.

[0160] The third transistor T3b” may include the first sub-transistor T3b1” and the second sub-transistor T3b2”.

[0161] The first sub-transistor T3b1” may have a sub-gate electrode connected to the i-th scan line Si, a first electrode connected to the first node N1, and a second electrode connected to the first electrode of the second sub-transistor T3b2”.

[0162] The second sub-transistor T3b2” may have a sub-gate electrode connected to the i-th scan line Si, a first electrode connected to the second electrode of the first sub-transistor T3b1”, and a second electrode connected to the third node N3.

[0163] The first sub-transistor T3b1” and the second sub-transistor T3b2” may include a second gate electrode. The second gate electrode may be connected to the auxiliary power line BMLL. The structure of the first sub-transistor T3b1” and the second sub-transistor T3b2” can follow... Figure 8 and Figure 9 The structure of the third transistors T3a and T3a'.

[0164] exist Figure 13 In pixel PXijc, the configuration of the third transistor T3c and the fourth transistor T4c can be different. Figure 7 The configuration of the third transistor T3a and the fourth transistor T4 in the pixel PXija.

[0165] The third transistor T3c may include the first sub-transistor T3c1 and the second sub-transistor T3c2.

[0166] The first sub-transistor T3c1 may have a sub-gate electrode connected to the i-th scan line Si, a first electrode connected to the first node N1, and a second electrode connected to the first electrode of the second sub-transistor T3c2.

[0167] The second sub-transistor T3c2 may have a sub-gate electrode connected to the i-th scan line Si, a first electrode connected to the second electrode of the first sub-transistor T3c1, and a second electrode connected to the third node N3.

[0168] The first sub-transistor T3c1 and the second sub-transistor T3c2 may each include a second gate electrode. The second gate electrode can be connected to the auxiliary power line BMLL. The structure of the first sub-transistor T3c1 and the second sub-transistor T3c2 can follow... Figure 8 and Figure 9 The structure of the third transistors T3a and T3a'.

[0169] Figure 13 The pixel PXijc includes a fourth transistor T4c connected in series to reduce the above reference. Figure 4 The leakage current of LC2 is described in the sub-transistors T4c1 and T4c2.

[0170] Sub-transistor T4c1 may have a gate electrode connected to the (i-1)th scan line S(i-1), a first electrode connected to the first node N1, and a second electrode connected to the first electrode of sub-transistor T4c2.

[0171] Sub-transistor T4c2 may have a gate electrode connected to the (i-1)th scan line S(i-1), a first electrode connected to the second electrode of sub-transistor T4c1, and a second electrode connected to the initialization line INTL.

[0172] Each of the sub-transistors T4c1 and T4c2 can follow Figure 5 The structure of the fourth transistor T4.

[0173] Figures 14 to 16 The auxiliary power supply line used to mitigate transient afterimages is shown.

[0174] The above embodiments are applicable even if the auxiliary power line BMLL of the display device 10 is always kept in a floating state.

[0175] However, in Figures 14 to 16 In one embodiment, transient afterimages can be mitigated by configuring an auxiliary power line BMLL to receive power after the display device 10 has been manufactured and is ready for delivery to the user. That is, in Figures 14 to 16 In some embodiments, the auxiliary power line BMLL may not always remain in a floating state.

[0176] When the curves of the gate-source voltage and leakage current of the first transistor T1 when the data voltage of the current image frame is higher than that of the previous image frame differ from the curves when the data voltage of the current image frame is lower than that of the previous image frame, hysteresis may occur. Therefore, when a strong hysteresis occurs in instances where the same gate-source voltage is applied, the amount of drive current flowing through the first transistor T1 can be varied so that the light-emitting diode LD does not emit light at an appropriate brightness corresponding to the grayscale value.

[0177] When the display device 10 displays a still image, the first transistor of a pixel receives the same gate-source voltage for tens to hundreds of image frame periods. Therefore, when the hysteresis characteristic of the first transistor is maximized in the still image and the display device 10 switches images, the pixel may not emit light appropriately with a brightness corresponding to the grayscale value. When the afterimage persists, its continuity can be considered a transient afterimage. This transient afterimage can last for several seconds and can be perceived by the user of the display device within a corresponding amount of time.

[0178] To address and prevent these transient afterimages, numerous techniques can be implemented. For example, and referring to… Figures 14 to 16 In one embodiment, the absolute value of the threshold voltage of the third transistor can be reduced by applying a voltage lower than the voltage of the first gate electrode to the second gate electrode of the third transistor. Therefore, the switching speed of the third transistor is increased, thereby advancing the turn-on time of the third transistor and mitigating the degree and / or presence of transient afterimages.

[0179] Reference Figure 14 The auxiliary power line BMLL and the second power line ELVSSL can be connected via switch SW.

[0180] The switch SW can be turned off during the aging process of the display device 10. Therefore, an appropriate voltage for aging can be applied to the auxiliary power line BMLL. In another embodiment, the switch SW can be turned on when a second power supply voltage is appropriately applied to the auxiliary power line BMLL during the aging process of the display device 10.

[0181] The switch SW can also be turned on when driving the display device 10. Therefore, the second power supply line ELVSSL can be connected to the auxiliary power supply line BMLL. Typically, because the second power supply voltage applied to the pixel is the lowest voltage, a voltage lower than the voltage of the first gate electrode can be applied to the second gate electrode of the third transistor. According to an embodiment, the switch SW may not always be turned on when driving the display device 10, but its timing can be appropriately set to resolve transient afterimages.

[0182] Reference Figure 15The auxiliary power line BMLL and the second power line ELVSSL can be directly connected to each other. That is, the second gate electrode can be connected to the cathode of the light-emitting diode (LD) (see...). Figure 7 ).

[0183] Therefore, a second power supply voltage lower than that of the first gate electrode can be applied to the second gate electrode not only during the aging process but also during the driving of the display device 10. Thus, leakage current reduction and transient afterimage reduction can be achieved simultaneously.

[0184] Reference Figure 16 The auxiliary power supply APP can be connected to the auxiliary power supply line BMLL, and the second power supply PP2 can be connected to the second power supply line ELVSSL.

[0185] The auxiliary power supply APP can provide the voltage corresponding to the above embodiment to the auxiliary power line BMLL during the aging process and during operation.

[0186] The second power supply PP2 can provide a second power supply voltage corresponding to the above embodiment to the second power supply line ELVSSL during the aging process and during driving.

[0187] exist Figure 16 In this embodiment, the auxiliary power line BMLL and the second power line ELVSSL are separated from each other, and therefore, voltage control can be easily performed.

[0188] exist Figures 14 to 16 In this context, it is assumed that the third transistor is configured as a P-type transistor.

[0189] In another embodiment, when the third transistor is configured as an N-type transistor, in Figures 14 to 16 In one embodiment, the absolute value of the threshold voltage can be reduced by applying a voltage higher than the voltage of the first gate electrode to the second gate electrode of the third transistor.

[0190] therefore, Figures 14 to 16 The second power line, ELVSSL, can be replaced with the first power line, ELVDDL. Furthermore, Figure 16 The second power supply PP2 can be replaced with the first power supply.

[0191] The foregoing description is provided to illustrate and describe the invention. Furthermore, the foregoing description simply illustrates and describes embodiments of the present disclosure, which can be applied to various other combinations, modifications, and environments as set forth above, and can be changed or modified within the scope of the invention.

Claims

1. A display device, comprising: Multiple pixels; Each of the plurality of pixels includes: A first transistor, the first transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor has a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to a second node; and A third transistor has a first gate electrode connected to the first scan line, a second gate electrode, a first electrode connected to the first node, and a second electrode connected to the third node. A voltage higher than the voltage of the second electrode of the third transistor is applied to the first gate electrode, and a voltage lower than the voltage of the first gate electrode is applied to the second gate electrode.

2. The display device according to claim 1, wherein, The second gate electrode is in a floating state.

3. The display device according to claim 1, wherein, The third transistor includes a semiconductor layer disposed between the first gate electrode and the second gate electrode, and The semiconductor layer includes a source region, a channel region, and a drain region.

4. The display device according to claim 3, wherein, The second gate electrode is arranged to overlap with at least a portion of at least one of the source region, the channel region, and the drain region. The third transistor further includes a gate insulating layer disposed between the first gate electrode and the semiconductor layer. The gate insulating layer has a first region adjacent to the drain region and a second region adjacent to the source region. Wherein, the electron density in the first region is higher than the electron density in the second region, or the hole density in the first region is higher than the hole density in the second region.

5. The display device according to claim 3, wherein, The second gate electrode is arranged to overlap with a portion of the semiconductor layer other than the source region of the semiconductor layer.

6. The display device according to claim 5, wherein, The third transistor further includes a gate insulating layer disposed between the first gate electrode and the semiconductor layer, and The gate insulating layer has a first region adjacent to the drain region and a second region adjacent to the source region. Wherein, the electron density in the first region is higher than the electron density in the second region, or the hole density in the first region is higher than the hole density in the second region.

7. The display device according to claim 1, wherein, The third transistor includes: A first sub-transistor, the first sub-transistor having a sub-gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode; and The second sub-transistor has a sub-gate electrode connected to the first scan line, a first electrode connected to the second electrode of the first sub-transistor, and a second electrode connected to the third node. Wherein, at least one of the first sub-transistor and the second sub-transistor includes the second gate electrode.

8. The display device according to claim 7, wherein, The first sub-transistor includes a semiconductor layer disposed between the sub-gate electrode and the second gate electrode of the first sub-transistor. The semiconductor layer includes a source region, a channel region, and a drain region. The second gate electrode is arranged to overlap at least a portion of at least one of the source region, the channel region, and the drain region, and The first sub-transistor further includes a gate insulating layer disposed between the sub-gate electrode and the semiconductor layer of the first sub-transistor. The gate insulating layer has a first region adjacent to the drain region and a second region adjacent to the source region. Wherein, the electron density in the first region is higher than the electron density in the second region, or the hole density in the first region is higher than the hole density in the second region.

9. The display device according to claim 7, wherein, The first sub-transistor includes a semiconductor layer disposed between the sub-gate electrode and the second gate electrode of the first sub-transistor. The semiconductor layer includes a source region, a channel region, and a drain region. The second gate electrode is arranged to overlap with at least a portion of the semiconductor layer other than the source region.

10. The display device according to claim 7, wherein, The second sub-transistor includes a semiconductor layer disposed between the sub-gate electrode and the second gate electrode of the second sub-transistor. The semiconductor layer includes a source region, a channel region, and a drain region. The second gate electrode overlaps with at least a portion of at least one of the source region, the channel region, and the drain region, and The second sub-transistor further includes a gate insulating layer disposed between the sub-gate electrode and the semiconductor layer of the second sub-transistor. The gate insulating layer has a first region adjacent to the drain region and a second region adjacent to the source region. Wherein, the electron density in the first region is higher than the electron density in the second region, or the hole density in the first region is higher than the hole density in the second region.

11. The display device according to claim 7, wherein, The second sub-transistor includes a semiconductor layer disposed between the sub-gate electrode and the second gate electrode of the second sub-transistor. The semiconductor layer includes a source region, a channel region, and a drain region. The second gate electrode is arranged to overlap with a portion of the semiconductor layer other than the source region.

12. The display device according to claim 1, wherein, Each of the plurality of pixels further includes a light-emitting diode, and The second gate electrode is connected to the cathode of the light-emitting diode.

13. A method for aging a transistor, the transistor comprising a first gate electrode, a second gate electrode, and a semiconductor layer disposed between the first gate electrode and the second gate electrode and comprising a source region doped with acceptor doping, a channel region, and a drain region doped with acceptor doping, the method comprising: A voltage higher than the voltage of the drain region is applied to the first gate electrode; as well as A voltage lower than that of the first gate electrode is applied to the second gate electrode.

14. The method according to claim 13, wherein, The second gate electrode overlaps with at least a portion of at least one of the source region, the channel region, and the drain region.

15. A display device, comprising: Multiple pixels; Each of the plurality of pixels includes: A first transistor, the first transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor has a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to a second node; and A third transistor has a first gate electrode connected to the first scan line, a second gate electrode, a first electrode connected to the first node, and a second electrode connected to the third node. A voltage lower than the voltage of the second electrode of the third transistor is applied to the first gate electrode, and a voltage higher than the voltage of the first gate electrode is applied to the second gate electrode.

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