Display device

Abstract

A display device is provided. The display device includes: a substrate layer including a display region and a non-display region; a circuit element layer disposed on the substrate layer; a display element layer disposed on the circuit element layer; a plurality of signal pads disposed on the substrate layer, wherein the plurality of signal pads are spaced apart from each other by a predetermined interval and are electrically connected to the circuit element layer; and an input sensing layer including a conductive layer and an input insulating layer, wherein the conductive layer is disposed on the display element layer, and the input insulating layer covers a part of each of the signal pads and the conductive layer. Each of the signal pads includes a first pad portion and a second pad portion, wherein the first pad portion is stacked with the input insulating layer, and the second pad portion is not stacked with the input insulating layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0052827, filed on May 7, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Exemplary embodiments of the inventive concept relate to a display device, and more particularly, to a display device including an input sensing layer. Background Art

[0003] Various display devices are being developed for use in multimedia devices such as televisions, mobile phones, desktop computers, navigation devices, and game consoles. The display device may include a display module, a polarizing layer disposed on the display panel, and a window. The display module may display an image and sense an external input. The display module may include a display panel for displaying an image and an input sensing layer for sensing an external input. Summary of the Invention

[0004] According to an exemplary embodiment of the inventive concept, a display device includes: a substrate layer including a display area and a non-display area adjacent to the display area; a circuit element layer disposed on the substrate layer; a display element layer stacked with the display area and disposed on the circuit element layer; a plurality of signal pads stacked with the non-display area and disposed on the substrate layer, wherein the plurality of signal pads are spaced apart from each other by a predetermined interval in a first direction and electrically connected to the circuit element layer; and an input sensing layer including a conductive layer and an input insulating layer, wherein the conductive layer is disposed on the display element layer, and the input insulating layer covers a part of each of the signal pads and the conductive layer. Each of the signal pads includes a first pad portion and a second pad portion, wherein the first pad portion is stacked with the input insulating layer, and the second pad portion is not stacked with the input insulating layer.

[0005] In an exemplary embodiment of the inventive concept, the first pad portion and the second pad portion are alternately arranged in a second direction substantially perpendicular to the first direction.

[0006] In an exemplary embodiment of the inventive concept, the signal pads include a first signal pad and a second signal pad adjacent to the first signal pad, and the first pad portion of the first signal pad is aligned with the second pad portion of the second signal pad in the first direction, and the second pad portion of the first signal pad is aligned with the first pad portion of the second signal pad in the first direction.

[0007] In an exemplary embodiment of the inventive concept, the first pad portion is a plurality of first pad portions of each of the signal pads, and the second pad portion is a plurality of second pad portions of each of the signal pads, wherein the plurality of first pad portions and the plurality of second pad portions are alternately arranged in the second direction.

[0008] In an exemplary embodiment of the inventive concept, the input insulating layer completely overlaps the first pad portion.

[0009] In an exemplary embodiment of the inventive concept, the display device further includes: a circuit board including a plurality of connection pads respectively electrically connected to the signal pads, wherein a second pad portion of each of the signal pads is electrically connected to a corresponding one of the connection pads.

[0010] In an exemplary embodiment of the inventive concept, the input insulating layer includes: a pad opening exposing the second pad portion, and the display device further includes: an anisotropic conductive film disposed between the signal pad and the connection pad, wherein the anisotropic conductive film electrically connects the second pad portion of each of the signal pads to the corresponding connection pad through the pad opening.

[0011] In an exemplary embodiment of the inventive concept, each of the signal pads includes: a first pad electrode electrically connected to the display element layer and disposed on the substrate layer; a first pad insulating layer covering the first pad electrode and disposed on the substrate layer, wherein a plurality of pad contact holes are formed in the first pad insulating layer; and a second pad electrode disposed on the first pad insulating layer and electrically connected to the first pad electrode through the plurality of pad contact holes, wherein the second pad electrode of each of the signal pads forms the first pad portion and the second pad portion.

[0012] In an exemplary embodiment of the inventive concept, a portion of the second pad electrode corresponding to the first pad portion is completely covered by the input insulating layer.

[0013] In an exemplary embodiment of the inventive concept, the pad contact holes are spaced apart from each other and are arranged in a second direction substantially perpendicular to the first direction.

[0014] In an exemplary embodiment of the inventive concept, a first pad contact hole among the plurality of pad contact holes and a second pad contact hole adjacent to the first pad contact hole among the plurality of pad contact holes respectively overlap the first pad portion and the second pad portion.

[0015] In an exemplary embodiment of the inventive concept, the first pad contact hole and the second pad contact hole among the plurality of pad contact holes form a first contact hole portion, and a third pad contact hole and a fourth pad contact hole among the plurality of pad contact holes form a second contact hole portion, the first contact hole portion overlaps the first pad portion, and the second contact hole portion overlaps the second pad portion.

[0016] In an exemplary embodiment of the inventive concept, the conductive layer includes a first conductive pattern and a second conductive pattern, and the input insulating layer includes: a first input insulating layer covering the first conductive pattern disposed on the display element layer; and a second input insulating layer covering the second conductive pattern disposed on the first input insulating layer, wherein the second input insulating layer covers the first pad portion.

[0017] In an exemplary embodiment of the inventive concept, the input insulating layer further includes: a sub-input insulating layer disposed between the display element layer and the first input insulating layer.

[0018] In an exemplary embodiment of the inventive concept, each of the signal pads further includes: a second pad insulating layer disposed on the first pad insulating layer; and a plurality of pad contact holes passing through the first pad insulating layer and the second pad insulating layer.

[0019] In an exemplary embodiment of the inventive concept, the second pad insulating layer and the sub-input insulating layer are connected to each other and disposed on the same layer.

[0020] In an exemplary embodiment of the inventive concept, the second input insulating layer includes an organic material, and each of the first pad insulating layer and the second pad insulating layer includes an inorganic material.

[0021] In an exemplary embodiment of the inventive concept, the second conductive pattern and the second pad electrode are respectively disposed on the first input insulating layer and the first pad insulating layer through the same process.

[0022] In an exemplary embodiment of the inventive concept, the circuit element layer includes: a signal line electrically connected to the display element layer and one end of the signal line contacting the first pad electrode.

[0023] In an exemplary embodiment of the inventive concept, a first length from the top surface of the substrate layer to the top surface of the input insulating layer is greater than a second length from the top surface of the substrate layer to the top surface of the second pad portion of each of the signal pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0025] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept;

[0026] Figure 2 is an exploded perspective view of a display device according to an exemplary embodiment of the inventive concept;

[0027] Figure 3 is a cross-sectional view of a display module according to an exemplary embodiment of the inventive concept;

[0028] Figure 4 is a plan view of a display panel according to an exemplary embodiment of the inventive concept;

[0029] Figure 5A is an enlarged cross-sectional view of a display area of a display panel according to an exemplary embodiment of the inventive concept;

[0030] Figure 5B is an enlarged cross-sectional view of an encapsulation layer according to an exemplary embodiment of the inventive concept;

[0031] Figure 6A is a cross-sectional view of an input sensing layer according to an exemplary embodiment of the inventive concept;

[0032] Figure 6B is a plan view of an input sensing layer according to an exemplary embodiment of the inventive concept;

[0033] Figure 6C and Figure 6D is a partial cross-sectional view of an input sensing layer according to an exemplary embodiment of the inventive concept;

[0034] Figure 7A is according to an exemplary embodiment of the inventive concept Figure 4 of a pad region;

[0035] Figure 7B is a plan view of a pad according to an exemplary embodiment of the inventive concept;

[0036] Figure 8 is a cross-sectional view taken along line I-I' according to an exemplary embodiment of the inventive concept Figure 7A ;

[0037] Figure 9 is a cross-sectional view taken along line II-II' according to an exemplary embodiment of the inventive concept Figure 7A ;

[0038] Figure 10 is a cross-sectional view taken along line III-III' according to an exemplary embodiment of the inventive concept Figure 7A ;

[0039] Figure 11 is according to an exemplary embodiment of the inventive concept Figure 4 of a pad region; and

[0040] Figure 12 is a plan view of a pad according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0041] In this specification, it will be understood that when one component (or region, layer, part) is referred to as being "on," "connected to," or "coupled to" another component, the component (or region, layer, part) can be directly disposed on / connected to / coupled to the other component, or an intermediate third component may also be present.

[0042] It will be understood that throughout the specification, like reference numerals refer to like elements. Further, in the drawings, the thickness, ratios, and dimensions of layers, regions, and components may be exaggerated for clarity of illustration.

[0043] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It will be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one component from another. For example, in one embodiment, an element referred to as the first element may be referred to as the second element in another embodiment without departing from the spirit and scope of the inventive concept. Unless stated to the contrary, the singular forms of the terms may include the plural forms.

[0045] In addition, for ease of description, spatial relative terms such as "under", "below", "lower", "above", and "upper" may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the drawings. It will be understood that the spatial relative terms are intended to encompass different orientations in addition to the orientation depicted in the drawings during use or operation of the device. For example, if the device in the drawings is flipped, an element described as "under" or "below" other elements or features will then be positioned "above" the other elements or features. Thus, in an example, the terms "under" and "below" may include both the upper and lower (below) orientations. The device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0046] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the drawings.

[0047] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept. Figure 2 is an exploded perspective view of a display device according to an exemplary embodiment of the inventive concept.

[0048] Referring to Figure 1 , the display device DD may display an image IM through a display surface DD-IS. According to an exemplary embodiment of the inventive concept, although the display device DD includes a flat display surface DD-IS, the inventive concept is not limited thereto. The display device DD may include a curved display surface. For example, the curved display surface may include a plurality of display regions facing different directions. In addition, the display device DD may include a bendable display surface, and the display surface may be bendable in different directions.

[0049] According to an exemplary embodiment of the inventive concept, the display device DD may be provided as a flexible display device. However, the present embodiment of the inventive concept is not limited thereto. For example, the display device DD according to an exemplary embodiment of the inventive concept may be provided as a rigid display device.

[0050] In addition, an electronic module, a camera module, a power module, etc. mounted on the main board may be provided on the bracket / case together with the display device DD to constitute a mobile terminal. The display device DD according to an exemplary embodiment of the inventive concept may be applied to large electronic devices (such as, a television and a monitor) and small and medium-sized electronic devices (such as, a tablet PC, a navigation unit for a vehicle, a game console, and a smart watch).

[0051] The display surface DD-IS may be parallel to the surface defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DD-IS (for example, the thickness direction of the display device DD) is indicated by the third direction DR3. In the present specification, "when viewed on a plane or a planar region" may mean the case when viewed in the third direction DR3. The front surface (or, for example, the top surface) and the rear surface (or, for example, the bottom surface) of each of the components or units to be described below are distinguished by the third direction DR3. However, the first direction DR1, the second direction DR2, and the third direction DR3 shown in the present embodiment may be examples, and the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to the opposite directions.

[0052] As Figure 1 shown, the display surface DD-IS includes a display area DD-DA in which an image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA may be an area in which the image IM is not displayed. Application icons and a clock window are shown as examples of the image IM in Figure 1 this.

[0053] In addition, the display area DD-DA has a rectangular shape, and the non-display area DD-NDA at least partially surrounds the display area DD-DA. However, the exemplary embodiment of the inventive concept is not limited thereto. For example, the display area DD-DA and the non-display area DD-NDA may be designed relatively in shape. For example, the non-display area DD-NDA may be provided to be adjacent to only one side of the display area DD-DA, or the non-display area DD-NDA may be omitted.

[0054] Referring to Figure 2 this, the display device DD may include a window WM, a display module DM, a circuit board FB, and a housing member BC.

[0055] The window WM may be disposed on the display module DM to transmit an image IM provided from the display module DM through the transmissive area TA. For example, the window WM may be disposed above the display module DM. The window WM includes a transmissive area TA and a non-transmissive area NTA. The transmissive area TA may have a shape corresponding to the shape of the display area DD-DA shown in Figure 1 . For example, the image IM displayed in the display area DD-DA of the display device DD may be visible from the outside through the transmissive area TA of the window WM.

[0056] The non-transmissive area NTA may have a shape corresponding to the shape of the non-display area DD-NDA. The non-transmissive area NTA may be an area having a light transmittance smaller than that of the transmissive area TA. However, the inventive concept is not limited thereto, and the non-transmissive area NTA may be omitted.

[0057] For example, the window WM may be made of glass, sapphire, or plastic. In addition, although the window WM is provided as a single layer, the window WM may include multiple layers. The window WM may include a substrate layer and at least one printed layer that overlaps the non-transmissive area NTA and is disposed on the rear surface of the substrate layer. The printed layer may have a predetermined color. For example, the printed layer may have black or a color other than black.

[0058] The display module DM is disposed between the window WM and the accommodation member BC. The display module DM includes a display panel DP and an input sensing layer ISL.

[0059] The display panel DP generates an image and transmits the generated image to the window WM. According to an exemplary embodiment of the inventive concept, the display panel DP may be an organic light emitting display panel, a liquid crystal display panel, or a quantum dot light emitting display panel, but the inventive concept is not limited thereto. For example, the organic light emitting display panel includes organic light emitting elements. The liquid crystal display panel includes liquid crystal molecules. The quantum dot light emitting display panel includes quantum dots and quantum rods.

[0060] Hereinafter, the organic light emitting display panel will be described as an example of the display panel DP according to an exemplary embodiment of the inventive concept. However, the inventive concept is not limited thereto, and according to the exemplary embodiment, the inventive concept may be applied to various display panels.

[0061] The input sensing layer ISL may be disposed between the window WM and the display panel DP. The input sensing layer ISL senses an input applied from the outside. The input applied from the outside may be provided in various ways. For example, the external input includes various types of external inputs such as a part of a user's body, a stylus, light, heat, or pressure. In addition, an input through contact with a part of the human body (such as a user's hand) and adjacent or neighboring spatial touch (e.g., hovering) may also be a form of input.

[0062] The input sensing layer ISL may be disposed on the display panel DP. For example, the input sensing layer ISL may be directly disposed on the display panel DP. In this specification, "component A is directly disposed on component B" may mean that an adhesive member is not disposed between component A and component B. In the present embodiment, the input sensing layer ISL may be manufactured together with the display panel DP through a continuous process. However, the inventive concept is not limited thereto. For example, the input sensing layer ISL may be provided as a separate panel and then bonded to the display panel DP through an adhesive layer. For another example, the input sensing layer ISL may be omitted.

[0063] The circuit board FB may be connected to one end of the display panel DP to transmit a driving signal to the display panel DP. According to an exemplary embodiment of the inventive concept, the circuit board FB may be a flexible circuit board. The driving signal may be a signal through which an image IM is displayed on the display panel DP. In addition, a driving circuit board that provides the driving signal may be connected to one end of the circuit board FB. The circuit board FB may be disposed between the display panel DP and the driving circuit board to transmit the driving signal provided from the driving circuit board to the display panel DP.

[0064] Although Figure 2 only the structure in which the circuit board FB is connected to the display panel DP is shown, the present embodiment of the inventive concept is not limited thereto. For example, the display device DD may further include a touch circuit board connected to the input sensing layer ISL. The touch circuit board may provide a touch driving signal to the input sensing layer ISL. In addition, the bonding method of connecting the circuit board FB to the display panel DP according to an exemplary embodiment of the inventive concept may be substantially the same as the bonding method of connecting the touch circuit board to the input sensing layer ISL.

[0065] The accommodation member BC may be bonded to the window WM. The accommodation member BC may be disposed on the rear surface of the display module DM and bonded to the window WM to provide an internal space. The accommodation member BC may include a material having relatively high rigidity. For example, the accommodation member BC may include a plurality of frames and / or plates made of glass, plastic, and / or metal. The accommodation member BC may stably protect the components accommodated in the internal space of the display device DD from external impacts.

[0066] In addition, although the accommodation member BC includes a material having high rigidity, the present embodiment of the inventive concept is not limited thereto. The accommodation member BC may include a flexible material. The display device DD according to an exemplary embodiment of the inventive concept may have a foldable or bendable property. As a result, the components provided in the display device DD may also have a flexible property.

[0067] Figure 3A cross-sectional view of a display module according to an exemplary embodiment of the inventive concept.

[0068] Referring to Figure 3 , the display panel DP includes a substrate layer BL, a circuit element layer DP-CL disposed on the substrate layer BL, a display element layer DP-OLED, and a encapsulation layer TFL.

[0069] The substrate layer BL may include at least one plastic film. The substrate layer BL may include a plastic substrate, a glass substrate, a metal substrate, or an organic composite substrate / inorganic composite substrate as a flexible substrate. Referring to Figure 1 The described display area DD-DA and non-display area DD-NDA may correspond to the display area DP-DA and non-display area DP-NDA disposed on the substrate layer BL, respectively. Hereinafter, the substrate layer BL may be described as a display substrate.

[0070] The circuit element layer DP-CL includes circuit elements and at least one intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements include signal lines and driving circuits of pixels, etc.

[0071] The display element layer DP-OLED may include a plurality of organic light-emitting diodes. The display element layer DP-OLED may further include an organic layer such as a pixel defining layer. According to an exemplary embodiment of the inventive concept, when the display panel DP is provided as a liquid crystal display panel, the display element layer DP-OLED may be provided as a liquid crystal layer.

[0072] The encapsulation layer TFL seals the display element layer DP-OLED. For example, the encapsulation layer TFL may be a thin film encapsulation layer. The encapsulation layer TFL may protect the display element layer DP-OLED from foreign substances (such as moisture, oxygen, and dust particles). Referring to Figure 3 , although the encapsulation layer TFL overlaps each of the display area DP-DA and non-display area DP-NDA, the present embodiment of the inventive concept is not limited thereto. For example, the encapsulation layer TFL may not overlap the non-display area DP-NDA.

[0073] Figure 4 A plan view of a display panel according to an exemplary embodiment of the inventive concept.

[0074] Referring to Figure 4 , the display panel DP may include a driving circuit GDC, a plurality of signal lines SGL, a plurality of signal pads (a "pad" is also referred to as a "bond pad", "pad"), DP-PD and ISL-PD, and a plurality of pixels PX.

[0075] The driving circuit GDC may include a scan driving circuit. The scan driving circuit generates a plurality of scan signals (hereinafter referred to as scan signals). The scan signals are sequentially output to a plurality of scan lines GL (hereinafter referred to as scan lines) which will be described later. The scan driving circuit may also output other control signals to the driving circuits of each of the pixels PX.

[0076] The scan driving circuit may include a plurality of thin film transistors manufactured by the same process as the driving circuit of the pixel PX (e.g., low temperature polycrystalline silicon (LTPS) process or low temperature polycrystalline oxide (LTPO) process).

[0077] The signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. The scan lines GL are respectively connected to the corresponding pixels PX in the pixel PX, and the data lines DL are respectively connected to the corresponding pixels PX in the pixel PX. The power line PL is connected to the pixel PX. The control signal line CSL may supply a control signal to the scan driving circuit.

[0078] In the present embodiment, the signal line SGL may further include an auxiliary line SSL. The auxiliary line SSL may be a signal line connected to the input sensing layer ISL (e.g., see Figure 2 ). In an exemplary embodiment of the inventive concept, the auxiliary line SSL may be omitted.

[0079] The signal line SGL may include a plurality of portions provided on different layers. Figure 4 An example is shown in which the data line DL includes four portions P1 to P4 and the auxiliary line SSL includes two portions P10 to P20. The four portions P1 to P4 may be connected to each other through contact holes CNT, and the two portions P10 and P20 may be connected to each other through contact holes CNT. The first portion P10 of the auxiliary line SSL is connected to the signal line of the input sensing layer ISL to be described below through a contact hole CNT (e.g., see Figure 6B ).

[0080] The first signal pad DP-PD of the signal pads DP-PD and ISL-PD is connected to the data line DL, the power line PL, and the control signal line CSL. The second signal pad ISL-PD of the signal pads DP-PD and ISL-PD is connected to the auxiliary line SSL. The first signal pad DP-PD and the second signal pad ISL-PD are arranged adjacent to each other in a pad region NDA-PA provided on a part of the non-display region DP-NDA. The pad region NDA-PA may be adjacent to the edge DP-E of the display panel DP. The signal pads DP-PD and ISL-PD may be formed by the same process without distinguishing the layer structure or constituent materials from each other. However, the inventive concept is not limited thereto. For example, the signal pads DP-PD and ISL-PD may be formed by separate processes.

[0081] Each of the signal pads DP-PD and ISL-PD may be exposed to an external space to be coupled to a connection pad PCB-P of a printed circuit board (PCB), which will be described later. In this case, when an external conductive foreign object is between two adjacent signal pads (DP-PD and / or ISL-PD) and within a relatively short distance between the two adjacent signal pads (DP-PD and / or ISL-PD), a short circuit may occur between the two adjacent signal pads (DP-PD and / or ISL-PD).

[0082] According to an exemplary embodiment of the inventive concept, a short circuit between two adjacent ones of the signal pads DP-PD and ISL-PD may be prevented by an insulating layer covering a part of each of the signal pads DP-PD and ISL-PD.

[0083] For example, each of the signal pads DP-PD and ISL-PD may be divided into a first pad portion and a second pad portion. For example, the first pad portion of each of the signal pads DP-PD and ISL-PD may be covered by the insulating layer, and the second pad portion of each of the signal pads DP-PD and ISL-PD may be exposed to the outside through a pad opening provided in the insulating layer. The display panel DP and the printed circuit board PCB may be electrically connected to each other through the second pad portion of each of the signal pads DP-PD and ISL-PD exposed through the pad opening.

[0084] For example, the insulating layer may have a thickness greater than that of the second pad portion of each of the signal pads DP-PD and ISL-PD. On a plane, the second pad portion of each of the signal pads DP-PD and ISL-PD may be surrounded by the insulating layer, and thus, an external conductive foreign object may not contact the signal pads DP-PD and ISL-PD due to the insulating layer. This will be described in more detail later with reference to Figure 7A More specifically.

[0085] The display area DP-DA may be an area in which pixels PX are disposed. A plurality of electronic components may be disposed in the display area DP-DA. The electronic components include an organic light-emitting diode (OLED) disposed in each of the pixels PX and a pixel driving circuit connected to the organic light-emitting diode OLED. The driving circuit GDC, signal lines SGL, signal pads DP-PD and ISL-PD, and the pixel driving circuit may be included in Figure 3 the circuit element layer DP-CL shown in.

[0086] For example, the pixel PX may include a first transistor T1, a second transistor T2, a capacitor CP, and an organic light-emitting diode OLED. The pixel driving circuit may include a switching transistor and a driving transistor, but the inventive concept is not limited to reference toFigure 4 The described embodiment. The first transistor T1 is connected to the scan line GL and the data line DL. The organic light-emitting diode OLED receives the power voltage provided from the power line PL.

[0087] In Figure 4 it, a circuit board PCB electrically connected to the display panel DP is additionally shown. For example, the circuit board PCB may be a rigid circuit board or a flexible circuit board.

[0088] The timing control circuit TC that controls the operation of the display panel DP may be provided on the circuit board PCB. In addition, the input sensing circuit ISL-C that controls the input sensing layer ISL may be provided on the circuit board PCB. Each of the timing control circuit TC and the input sensing circuit ISL-C may be mounted on the circuit board PCB in the form of an integrated chip.

[0089] The timing control circuit TC and the input sensing circuit ISL-C according to an exemplary embodiment of the inventive concept may be mounted on the circuit board PCB in the form of one integrated chip. The circuit board PCB may include connection pads PCB-P electrically connected to the signal pads DP-PD and ISL-PD. The circuit board PCB may further include signal lines connecting the connection pads PCB-P to the timing control circuit TC and / or the input sensing circuit ISL-C. In addition, in Figure 4 the connection pads PCB-P shown may be output pads electrically connected to the display panel DP, and the circuit board PCB may further include input pads.

[0090] The signal pads DP-PD and ISL-PD of the display panel DP and the connection pads PCB-P of the circuit board PCB may be electrically connected to each other through a conductive material such as an anisotropic conductive film ACF. In an exemplary embodiment of the inventive concept, the anisotropic conductive film ACF may include conductive balls.

[0091] In addition, in Figure 4 at least a portion of the display panel DP shown may be bent. For example, a portion of the non-display area DP-NDA may be bent along a bending axis parallel to the first direction DR1. The bending axis may overlap with the third portion P3 of the data line DL and the first portion P10 of the auxiliary line SSL.

[0092] Figure 5A is an enlarged cross-sectional view of a display area of a display panel according to an exemplary embodiment of the inventive concept. Figure 5B is an enlarged cross-sectional view of a encapsulation layer according to an exemplary embodiment of the inventive concept.

[0093] Referring to Figure 5A, the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers can be formed by methods such as coating and deposition. Thereafter, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned in a photolithographic manner. The semiconductor patterns, conductive patterns, and signal lines provided in the circuit element layer DP-CL and the display element layer DP-OLED can be formed in the manner described above.

[0094] The substrate layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. The substrate layer BL may have a multi-layer structure. For example, the substrate layer BL may have a three-layer structure of a synthetic resin layer, an adhesive layer, and a synthetic resin layer. For example, the synthetic resin layer may be a polyimide resin layer, and the material is not limited thereto. The synthetic resin layer may include at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, silicone resins, polyamide resins, and perylene resins. In addition, the synthetic resin layer may include a glass substrate, a metal substrate, or an organic composite substrate / inorganic composite substrate.

[0095] At least one inorganic layer may be provided on the top surface of the substrate layer BL. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be provided as a multi-layer. The multi-layer inorganic layer may constitute a barrier layer and / or a buffer layer. In this embodiment, the display panel DP may include a buffer layer BFL.

[0096] The buffer layer BFL can improve the adhesion between the substrate layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately laminated.

[0097] The semiconductor pattern is provided on the buffer layer BFL. For example, the semiconductor pattern may include polysilicon. However, the inventive concept is not limited thereto. For example, the semiconductor pattern may include amorphous silicon or metal oxide.

[0098] Figure 5A A part of the semiconductor pattern is shown. For example, the semiconductor pattern may also be provided in other regions of the pixel PX on a plane. The semiconductor pattern may be arranged in a predetermined layout above the pixel PX. The semiconductor pattern has different electrical properties based on whether the semiconductor pattern is doped. The semiconductor pattern may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant. The N-type transistor includes a doped region doped with an N-type dopant.

[0099] The doped region may have a conductivity greater than that of the undoped region and may substantially serve as an electrode or a signal line. The undoped region may substantially correspond to the channel region of the transistor. For example, a part of the semiconductor pattern may be the channel region of the transistor, another part may be the source region or the drain region of the transistor, and still another part may be a connection electrode or a connection signal line.

[0100] As Figure 5A shown, the source region S1, the channel region A1, and the drain region D1 of the first transistor T1 may be formed of a semiconductor pattern, and the source region S2, the channel region A2, and the drain region D2 of the second transistor T2 may be formed of a semiconductor pattern. The source region S1 and the drain region D1 extend from the channel region A1 in opposite directions from each other, and the source region S2 and the drain region D2 extend from the channel region A2 in opposite directions from each other. Figure 5A A part of the connection signal line SCL formed of a semiconductor pattern is shown. The connection signal line SCL may be connected to the drain region D2 of the second transistor T2 in a plane.

[0101] The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 is stacked with a plurality of pixels PX (for example, see Figure 4 ) and covers the semiconductor pattern. For example, the first insulating layer 10 may include an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 may include a single-layer silicon oxide layer. The insulating layer of the circuit element layer DP-CL to be described later and the first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the materials described above.

[0102] The gates G1 and G2 are disposed on the first insulating layer 10. Each of the gates G1 and G2 may be a part of a metal pattern. The gates G1 and G2 are respectively stacked with the channel regions A1 and A2. In the process of doping the semiconductor pattern, the gates G1 and G2 may serve as masks.

[0103] The second insulating layer 20 covering the gates G1 and G2 is disposed on the first insulating layer 10. The second insulating layer 20 is stacked with the pixels PX (for example, see Figure 4 ). The second insulating layer 20 may include an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. In the present embodiment, the second insulating layer 20 may include a single-layer silicon oxide layer.

[0104] The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may be stacked with the gate G2 of the second transistor T2. The upper electrode UE may be part of a metal pattern. A part of the gate G2 and the upper electrode UE stacked with the said part of the gate G2 may form a capacitor CP (for example, see Figure 4 ). However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the upper electrode UE may be omitted.

[0105] A third insulating layer 30 covering the upper electrode UE is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be a single-layer silicon oxide layer. A first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal line SCL through a contact hole CNT-1 penetrating through the first insulating layer 10 to the third insulating layer 30.

[0106] A fourth insulating layer 40 covering the first connection electrode CNE1 is disposed on the third insulating layer 30. For example, the fourth insulating layer 40 may be a single-layer silicon oxide layer. A fifth insulating layer 50 is disposed on the fourth insulating layer 40. For example, the fifth insulating layer 50 may be an organic layer. A second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating through the fourth insulating layer 40 and the fifth insulating layer 50.

[0107] A sixth insulating layer 60 covering the second connection electrode CNE2 is disposed on the fifth insulating layer 50. For example, the sixth insulating layer 60 may be an inorganic layer. A first electrode AE is disposed on the sixth insulating layer 60. The first electrode AE is connected to the second connection electrode CNE2 through a contact hole CNT-3 penetrating through the sixth insulating layer 60. An opening OP is provided in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a part of the first electrode AE.

[0108] As Figure 5A shown, the display area DP-DA may include an emission area PXA and a non-emission area NPXA adjacent to the emission area PXA. The non-emission area NPXA may at least partially surround the emission area PXA. In this embodiment, the emission area PXA may correspond to the area of the first electrode AE exposed by the opening OP.

[0109] The hole control layer HCL can be disposed in the emission region PXA and the non-emission region NPXA. For example, the hole control layer HCL can be commonly disposed in the entire emission region PXA and the non-emission region NPXA. The hole control layer HCL can include a hole transport layer and can also include a hole injection layer. The emission layer EML is disposed on the hole control layer HCL. The emission layer EML can be disposed in a region of the hole control layer HCL corresponding to the opening OP. For example, each emission layer EML can be formed in each pixel PX and can be separated from the other emission layers EML of other pixels PX.

[0110] The electron control layer ECL is disposed on the emission layer EML. The electron control layer ECL can include an electron transport layer and can also include an electron injection layer. The hole control layer HCL and the electron control layer ECL can be formed on a plurality of pixels PX by using an opening mask. For example, the hole control layer HCL and the electron control layer ECL can be commonly formed on the pixel PX. The second electrode CE is disposed on the electron control layer ECL. For example, the second electrode CE is provided as a single body and is commonly disposed on a plurality of pixels PX (e.g., see Figure 4 ).

[0111] As Figure 5A and Figure 5B shown, the encapsulation layer TFL is disposed on the second electrode CE. The encapsulation layer TFL can include a plurality of thin films. According to this embodiment, the encapsulation layer TFL can include a cover layer CPL and a thin film encapsulation layer TFE. The thin film encapsulation layer TFE can include a first inorganic layer IOL1, an organic layer IOL2, and a second inorganic layer IOL3.

[0112] The cover layer CPL is disposed on the second electrode CE. For example, the cover layer CPL can be in contact with the second electrode CE. The cover layer CPL can include an organic material. The first inorganic layer IOL1 is disposed on the cover layer CPL. For example, the first inorganic layer IOL1 can be in contact with the cover layer CPL. The organic layer IOL2 is disposed on the first inorganic layer IOL1. For example, the organic layer IOL2 can be in contact with the first inorganic layer IOL1. The second inorganic layer IOL3 is disposed on the organic layer IOL2. For example, the second inorganic layer IOL3 can be in contact with the organic layer IOL2.

[0113] The cover layer CPL can protect the second electrode CE from subsequent processes (e.g., sputtering process) and improve the emission efficiency of the organic light-emitting diode OLED. The cover layer CPL can have a refractive index greater than that of the first inorganic layer IOL1.

[0114] The first inorganic layer IOL1 and the second inorganic layer IOL3 can protect the display element layer DP-OLED from oxygen / moisture, and the organic layer IOL2 can protect the display element layer DP-OLED from foreign substances such as dust particles. Each of the first inorganic layer IOL1 and the second inorganic layer IOL3 can be one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. According to an exemplary embodiment of the inventive concept, each of the first inorganic layer IOL1 and the second inorganic layer IOL3 can include a titanium oxide layer and / or an aluminum oxide layer, etc. The organic layer IOL2 can include an acrylic organic layer, but the inventive concept is not limited thereto.

[0115] According to an exemplary embodiment of the inventive concept, an inorganic layer (e.g., a lithium fluoride (LiF) layer) can be disposed between the cover layer CPL and the first inorganic layer IOL1. The LiF layer can improve the emission efficiency of the organic light-emitting diode OLED.

[0116] Figure 6A is a cross-sectional view of an input sensing layer according to an exemplary embodiment of the inventive concept. Figure 6B is a plan view of an input sensing layer according to an exemplary embodiment of the inventive concept. Figure 6C and Figure 6D is a partial cross-sectional view of an input sensing layer according to an exemplary embodiment of the inventive concept.

[0117] Referring to Figure 6A , the input sensing layer ISL can include a sub-input insulating layer ISL-IL1, a first conductive layer ISL-CL1, a first input insulating layer ISL-IL2, a second conductive layer ISL-CL2, and a second input insulating layer ISL-IL3. The sub-input insulating layer ISL-IL1 is disposed on the encapsulation layer TFL. For example, the sub-input insulating layer ISL-IL1 can be directly disposed on the encapsulation layer TFL. In an exemplary embodiment of the inventive concept, the sub-input insulating layer ISL-IL1 can be omitted.

[0118] Each of the first conductive layer ISL-CL1 and the second conductive layer ISL-CL2 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3. The conductive layer having a multi-layer structure (e.g., ISL-CL1 and / or ISL-CL2) may include at least one transparent conductive layer and at least one metal layer. For example, the conductive layer having a multi-layer structure (e.g., ISL-CL1 and / or ISL-CL2) may include metal layers containing different metals from each other. However, the inventive concept is not limited thereto, and the multi-layer structure may include a plurality of different transparent conductive layers or a plurality of different metal layers. The transparent conductive layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The metal layer may be formed of molybdenum, silver, titanium, copper, aluminum, and their alloys. For example, each of the first conductive layer ISL-CL1 and the second conductive layer ISL-CL2 may have a three-layer metal structure (e.g., a three-layer structure of titanium / aluminum / titanium). A metal having relatively high durability and low reflectivity may be applied to the outer layer of the metal structure, and a metal having high conductivity may be applied to the inner layer of the metal structure.

[0119] Each of the first conductive layer ISL-CL1 and the second conductive layer ISL-CL2 may include a plurality of patterns. Hereinafter, an example in which the first conductive layer ISL-CL1 includes a first conductive pattern and the second conductive layer ISL-CL2 includes a second conductive pattern will be described. Each of the first conductive pattern and the second conductive pattern may include a sensing electrode and a signal line connected to the sensing electrode.

[0120] For example, the first conductive pattern may be disposed on the sub-input insulating layer ISL-IL1. The first input insulating layer ISL-IL2 may cover the first conductive pattern and be disposed on the sub-input insulating layer ISL-IL1. The second conductive pattern may be disposed on the first input insulating layer ISL-IL2. The second input insulating layer ISL-IL3 may cover the second conductive pattern and be disposed on the first input insulating layer ISL-IL2. The second input insulating layer ISL-IL3 may be the uppermost insulating layer of the input sensing layer ISL.

[0121] According to an exemplary embodiment of the inventive concept, the second input insulating layer ISL-IL3 may be the same layer as the insulating layer covering each of the reference Figure 4 described first pad portions of the signal pads DP-PD and ISL-PD. For example, the second input insulating layer ISL-IL3 and the insulating layer covering each of the second pad portions of the signal pads DP-PD and ISL-PD may be connected to each other and formed simultaneously at the same time by the same process. However, the inventive concept is not limited thereto, and the second input insulating layer ISL-IL3 and the insulating layer may be formed at different times.

[0122] In the following, an example will be described in which the second input insulating layer ISL-IL3 is stacked on and covers each of the display region DP-DA and the non-display region DP-NDA, and covers each of the second conductive pattern and the signal pads DP-PD and ISL-PD of the second pad portion.

[0123] Each of the sub-input insulating layers ISL-IL1 to the second input insulating layer ISL-IL3 may include an inorganic layer or an organic layer. In this embodiment, each of the sub-input insulating layer ISL-IL1 and the first input insulating layer ISL-IL2 may be an inorganic layer. The inorganic layer may include at least one of, for example, alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The second input insulating layer ISL-IL3 may include an organic layer. The organic layer may include at least one of, for example, acrylic resin, methacrylic resin, polyisoprene resin, ethylene resin, epoxy resin, polyurethane resin, cellulose resin, silicone resin, polyimide resin, polyamide resin, and perylene resin.

[0124] As Figure 6B shown, the input sensing layer ISL includes a first electrode group EG1, a second electrode group EG2, and a signal line group connected to the electrode groups EG1 and EG2. In this embodiment, an example in which the input sensing layer ISL includes two signal line groups SG1 and SG2 is described. The input sensing layer ISL may include a sensing region ISL-DA and a line region ISL-NDA corresponding to the display region DP-DA and the non-display region DP-NDA of the display panel DP, respectively. The sensing region ISL-DA may be a region in which the first electrode group EG1 and the second electrode group EG2 are provided. The first signal line group SG1 and the second signal line group SG2 are provided in the line region ISL-NDA.

[0125] In this embodiment, the input sensing layer ISL may be a capacitive touch sensor. One of the first electrode group EG1 and the second electrode group EG2 may receive a driving signal, and the other may output a change in capacitance between the first electrode group EG1 and the second electrode group EG2 as a sensing signal. A driving portion may be divided for driving. Here, the input sensing layer ISL may be driven in the first driving portion as described above and driven in the second driving portion in a manner opposite to the driving manner described above.

[0126] The first electrode group EG1 includes a plurality of first sensing electrodes IE1-1 to IE1-10. An example in which the first electrode group EG1 includes ten first sensing electrodes IE1-1 to IE1-10 is shown. The first sensing electrodes IE1-1 to IE1-10 may be arranged in the second direction DR2. Each of the first sensing electrodes IE1-1 to IE1-10 may extend along the first direction DR1. The second electrode group EG2 includes a plurality of second sensing electrodes IE2-1 to IE2-8. An example in which the second electrode group EG2 includes eight second sensing electrodes IE2-1 to IE2-8 is shown. The second sensing electrodes IE2-1 to IE2-8 may be arranged in the first direction DR1. Each of the second sensing electrodes IE2-1 to IE2-8 may extend along the second direction DR2. For example, each of the second sensing electrodes IE2-1 to IE2-8 has a length longer than that of the first sensing electrodes IE1-1 to IE1-10. However, the inventive concept is not limited thereto.

[0127] The first signal line group SG1 may include signal lines having the same number as the first sensing electrodes IE1-1 to IE1-10. The signal lines of the first signal line group SG1 may be connected to at least one of both ends of each of the first sensing electrodes IE1-1 to IE1-10. The second signal line group SG2 may include signal lines having the same number as the second sensing electrodes IE2-1 to IE2-8. The signal lines of the second signal line group SG2 may be connected to at least one of both ends of each of the second sensing electrodes IE2-1 to IE2-8.

[0128] The signal lines of the first signal line group SG1 may be connected to a part of the auxiliary line SSL (for example, see Figure 4 ) provided on one side of the pad area NDA-PA through the contact holes CNT. The signal lines of the second signal line group SG2 may be connected to a part of the auxiliary line SSL (for example, see Figure 4 ) provided on the other side of the pad area NDA-PA through the contact holes CNT.

[0129] The contact holes CNT penetrate through the insulating layer provided between the signal lines of the first signal line group SG1 and the auxiliary line SSL. The contact holes CNT may penetrate through some of the first insulating layer 10 to the sixth insulating layer 60 and through the sub-input insulating layer ISL-IL1 and the first input insulating layer ISL-IL2 of the input sensing layer ISL.

[0130] Each of the first sensing electrodes IE1-1 to IE1-10 includes a plurality of first sensing parts SP1 and a plurality of first connection parts CP1. Each of the second sensing electrodes IE2-1 to IE2-8 includes a plurality of second sensing parts SP2 and a plurality of second connection parts CP2.

[0131] Figure 6C It is a cross-sectional view taken along the Figure 6B line X-X'. Figure 6C An example in which the first connection part CP1 and the second connection part CP2 cross each other is shown. In the present embodiment, the first connection part CP1 may correspond to a bridge pattern. In an exemplary embodiment of the inventive concept, the second connection part CP2 may be a bridge pattern.

[0132] As Figure 6B and Figure 6C shown in, a plurality of first connection parts CP1 may be formed of a first conductive layer ISL-CL1, and a plurality of first sensing parts SP1, a plurality of second sensing parts SP2, and a plurality of second connection parts CP2 may be formed of a second conductive layer ISL-CL2. The first sensing part SP1 and the first connection part CP1 may be connected to each other through a contact hole CNT-IL2 penetrating through the first input insulating layer ISL-IL2.

[0133] In the present embodiment, although the plurality of first connection parts CP1 and the plurality of second connection parts CP2 cross each other, the present embodiment of the inventive concept is not limited thereto. For example, each of the first connection parts CP1 may be deformed into a "∧"-shaped curve and / or a "∨"-shaped curve such that the first connection part CP1 does not overlap with the second connection part CP2. For example, the first connection part CP1 may be bent in the second direction DR2. However, the inventive concept is not limited thereto. The first connection part CP1 having a "∧"-shaped curve and / or a "∨"-shaped curve may overlap with the second sensing part SP2 on a plane.

[0134] According to an exemplary embodiment of the inventive concept, the signal lines of the first signal line group SG1 and the second signal line group SG2 include at least one of a part disposed on the same layer as the first sensing electrodes IE1-1 to IE1-10 and a part disposed on the same layer as the second sensing electrodes IE2-1 to IE2-8.

[0135] Figure 6D It is a cross-sectional view taken along the Figure 6B line XI-XI'. As an example, the tenth signal line SG1-10 of the first signal line group SG1 is shown. The first signal line group SG1 may include at least a part disposed on the same layer as the second sensing electrodes IE2-1 to IE2-8. The signal lines of the first signal line group SG1 and the second signal line group SG2 further include a part formed of the first conductive layer ISL-CL1 (for example, see Figure 6A ).

[0136] Figure 7A is a plan view of a Figure 4 pad region according to an exemplary embodiment of the inventive concept. Figure 7BIt is a plan view of a pad according to an exemplary embodiment of the inventive concept. Figure 8 It is along the line of an exemplary embodiment of the inventive concept Figure 7A Cross-sectional view taken along line I-I'. Figure 9 It is along the line of an exemplary embodiment of the inventive concept Figure 7A Cross-sectional view taken along line II-II'. Figure 10 It is along the line of an exemplary embodiment of the inventive concept Figure 7A Cross-sectional view taken along line III-III'.

[0137] As an example, Figure 7A shows the signal pads DP-PD and ISL-PD disposed on the pad region NDA-PA shown in Figure 4 Four signal pads (first signal pad PD1 to fourth signal pad PD4) among them and Figure 4 Four data lines (first data line DL1 to fourth data line DL4) among the data lines DL shown in. The first signal pad PD1 to the fourth signal pad PD4 may be electrically connected to the first data line DL1 to the fourth data line DL4, respectively. In addition, as an example, Figure 7B shows Figure 7A The second signal pad PD2 among the first signal pad PD1 to the fourth signal pad PD4 shown in.

[0138] As briefly described above with reference to Figure 4 At least a part of each of the signal pads DP-PD and ISL-PD according to the inventive concept may be covered by the second input insulating layer ISL-IL3. Hereinafter, the structures of the signal pads DP-PD and ISL-PD covered by the second input insulating layer ISL-IL3 will be described in more detail.

[0139] Referring to Figure 7A and Figure 7B The first signal pad PD1 to the fourth signal pad PD4 may extend in the second direction DR2 and may be arranged to be spaced apart from each other by a predetermined interval in the first direction DR1.

[0140] According to an exemplary embodiment of the inventive concept, each of the first signal pad PD1 to the fourth signal pad PD4 includes a first pad portion P1 that overlaps with the second input insulating layer ISL-IL3 and a second pad portion P2 that does not overlap with the second input insulating layer ISL-IL3. For example, the second input insulating layer ISL-IL3 may overlap with the entire first pad portion P1. However, the inventive concept is not limited thereto. For example, the second input insulating layer ISL-IL3 may overlap with a part of the first pad portion P1.

[0141] The pad opening PD-OP may be formed in the second input insulating layer ISL-IL3, and the second pad portions P2 of each of the first signal pad PD1 to the fourth signal pad PD4 are exposed to the external space through the pad opening PD-OP. As Figure 7A shown, although the pad opening PD-OP overlaps with the second pad portion P2, the present embodiment of the inventive concept is not limited thereto. For example, in addition to the second pad portion P2, the pad opening PD-OP may also overlap with a portion between two adjacent signal pads.

[0142] An anisotropic conductive film ACF (for example, see Figure 4 ) may be disposed on the pad opening PD-OP. The second pad portions P2 of each of the first signal pad PD1 to the fourth signal pad PD4 may be electrically connected to the corresponding connection pads PCB-P in the connection pad PCB-P through the anisotropic conductive film ACF disposed on the pad opening PD-OP.

[0143] According to an exemplary embodiment of the inventive concept, the first pad portions P1 and the second pad portions P2 of each of the first signal pad PD1 to the fourth signal pad PD4 may be alternately arranged in the second direction DR2, and the first pad portions P1 and the second pad portions P2 may be repeatedly provided. For example, the arrangement structures of the first pad portions P1 and the second pad portions P2 of two adjacent signal pads among the first signal pad PD1 to the fourth signal pad PD4 may be different from each other.

[0144] For example, in the case of the first signal pad PD1, the first pad portion P1 closest to the first data line DL1 is connected to the first data line DL1, and the second pad portion P2 arranged in the second direction DR2 is connected to the first pad portion P1. For example, the first signal pad PD1 may have a structure in which the first pad portion P1 and the second pad portion P2 are alternately and repeatedly provided in the second direction DR2.

[0145] In the case of the second signal pad PD2 closest to the first signal pad PD1, the second pad portion P2 closest to the second data line DL2 is connected to the second data line DL2, and the first pad portion P1 arranged in the second direction DR2 is connected to the second pad portion P2. For example, the second signal pad PD2 may have a structure in which the second pad portion P2 and the first pad portion P1 are alternately and repeatedly provided in the second direction DR2.

[0146] In the case of the third signal pad PD3 closest to the second signal pad PD2, the third signal pad PD3 may have a structure substantially the same as that of the first signal pad PD1. For example, the third signal pad PD3 may have a structure in which the first pad portion P1 and the second pad portion P2 are alternately and repeatedly provided in the second direction DR2.

[0147] In the case of the fourth signal pad PD4 being closest to the third signal pad PD3, the fourth signal pad PD4 may have a structure substantially the same as that of the second signal pad PD2. For example, the fourth signal pad PD4 may have a structure in which the second pad portion P2 and the first pad portion P1 are alternately and repeatedly arranged in the second direction DR2.

[0148] For example, each of the odd signal pads in the first direction DR1 provided on the pad region NDA-PA may have the same structure as each of the first signal pad PD1 and the third signal pad PD3, and each of the even signal pads in the first direction DR1 provided on the pad region NDA-PA may have the same structure as each of the second signal pad PD2 and the fourth signal pad PD4.

[0149] In addition, the first pad portion P1 of the first signal pad PD1 and the second pad portion P2 of the second signal pad PD2 adjacent to each other in the first direction DR1 may be aligned with each other in the first direction DR1, and the second pad portion P2 of the first signal pad PD1 and the first pad portion P1 of the second signal pad PD2 may be aligned with each other in the first direction DR1.

[0150] Therefore, even if an external conductive foreign object may be provided between two adjacent first signal pads PD1 and second signal pads PD2, a short circuit between the first signal pad PD1 and the second signal pad PD2 can be prevented.

[0151] For example, even if an external conductive foreign object may contact the second pad portion P2 of the second signal pad PD2, the first pad portion P1 of each of the first signal pad PD1 and the third signal pad PD3 aligned with the second pad portion P2 of the second signal pad PD2 in the first direction DR1 may be covered by the second input insulating layer ISL-IL3. As a result, a short circuit between the second signal pad PD2 and the first signal pad PD1 or between the second signal pad PD2 and the third signal pad PD3 can be prevented.

[0152] In addition, it may be assumed that an external conductive foreign object contacting the second pad portion P2 of the second signal pad PD2 overlaps with the second pad portion P2 of any one of the first signal pad PD1 and the third signal pad PD3. Even in this case, the contact between the external conductive foreign object and the second pad portion P2 of any one of the first signal pad PD1 and the third signal pad PD3 can be prevented by the thickness of the second input insulating layer ISL-IL3. Since the external conductive foreign object is disposed on the second input insulating layer ISL-IL3, contact between the second pad portion P2 having a thickness smaller than the thickness of the second input insulating layer ISL-IL3 of any one of the first signal pad PD1 and the third signal pad PD3 and the external conductive foreign object can be prevented. As a result, a short circuit between the second signal pad PD2 and the first signal pad PD1 or between the second signal pad PD2 and the third signal pad PD3 can be prevented.

[0153] According to an exemplary embodiment of the inventive concept, a plurality of pad contact holes CNT-H for electrically connecting to a data line DL may be formed in each of the first signal pad PD1 to the fourth signal pad PD4. For example, the pad contact holes CNT-H may be arranged to be spaced apart from each other by a predetermined interval in a second direction DR2.

[0154] According to an exemplary embodiment of the inventive concept, each of the first pad portion P1 and the second pad portion P2 may overlap with a corresponding one of the pad contact holes CNT-H. For example, two adjacent ones of the pad contact holes CNT-H may overlap with each of the first pad portion P1 and the second pad portion P2, respectively.

[0155] Hereinafter, reference will be made to Figures 8 to 10 describe in detail the cross-sectional structure of the first signal pad PD1 to the fourth signal pad PD4. Figure 8 The first pad portion PD1-P1 of the first signal pad PD1 and the second pad portion PD2-P2 of the second signal pad PD2 according to an exemplary embodiment of the inventive concept are shown, and Figure 9 the second pad portion PD1-P2 of the first signal pad PD1 and the first pad portion PD2-P1 of the second signal pad PD2 according to an exemplary embodiment of the inventive concept are shown.

[0156] Referring to Figure 5A and Figure 8 , each of the first signal pad PD1 to the fourth signal pad PD4 includes a first pad electrode CN1, a first sub-electrode EN1, a second sub-electrode EN2, and a second pad electrode CN2.

[0157] The first pad electrode CN1 is disposed on the second insulating layer 20. The first pad electrode CN1 of the first signal pad PD1 and the first pad electrode CN1 of the second signal pad PD2 may be respectively connected to Figure 7AOne end of the first data line DL1 and one end of the second data line DL2 shown in the figure. According to an exemplary embodiment of the inventive concept, when forming Figure 5A the upper electrode UE, the first pad electrode CN1 may be formed simultaneously. However, the inventive concept is not limited thereto. For example, the first pad electrode CN1 may be formed at a time different from the formation time of the upper electrode UE.

[0158] The third insulating layer 30 may cover the first pad electrode CN1 and be disposed on the second insulating layer 20. The first sub-electrode EN1 may be stacked on the first pad electrode CN1 and be disposed on the third insulating layer 30. The second sub-electrode EN2 may be disposed on the fourth insulating layer 40. For example, the second sub-electrode EN2 may be connected to the first sub-electrode EN1 through a first sub-contact hole CNT-A formed in the fourth insulating layer 40.

[0159] The sixth insulating layer 60 may cover the second sub-electrode EN2 and be disposed on the fourth insulating layer 40. According to an exemplary embodiment of the inventive concept, the fifth insulating layer 50 may be omitted in the pad region NDA-PA. For example, the fifth insulating layer 50 may not overlap with the pad region NDA-PA. The sub-input insulating layer ISL-IL1 may be disposed on the sixth insulating layer 60. Hereinafter, when describing the pad region NDA-PA (see Figure 4 ), the sixth insulating layer 60 will be described as the first pad insulating layer, and the sub-input insulating layer ISL-IL1 will be described as the second pad insulating layer.

[0160] The second pad electrode CN2 may be disposed on the second pad insulating layer ISL-IL1. The second pad electrode CN2 may be connected to the second sub-electrode EN2 through a pad contact hole CNT-H passing through the first pad insulating layer 60 and the second pad insulating layer ISL-IL1.

[0161] According to an exemplary embodiment of the inventive concept, the first pad insulating layer 60 may include holes, and the second pad insulating layer ISL-IL1 may be disposed in the holes of the first pad insulating layer 60. For example, the second pad insulating layer ISL-IL1 may cover the side surfaces of the holes of the first pad insulating layer 60, and the pad contact hole CNT-H may be formed in the second pad insulating layer ISL-IL1 and may correspond to the holes of the first pad insulating layer 60.

[0162] According to an exemplary embodiment of the inventive concept, the first pad portions P1 and the second pad portions P2 of each of the first signal pad PD1 to the fourth signal pad PD4 may be provided by the second pad electrode CN2. For example, the first pad portions P1 and the second pad portions P2 may be disposed on the first pad insulating layer 60 or the second pad insulating layer ISL-IL1 to be divided by the second pad electrode CN2 exposed to the external space.

[0163] In addition, a second pad electrode CN2 according to an exemplary embodiment of the inventive concept may be formed by the same process as the second conductive pattern described with reference to Figure 6C In the present specification, although the first pad insulating layer 60 and the second pad insulating layer ISL-IL1 are disposed in the pad region NDA-PA of the display panel DP, the present embodiment of the inventive concept is not limited thereto. For example, the second pad insulating layer ISL-IL1 may be omitted. In this case, the second pad electrode CN2 may be disposed on the first pad insulating layer 60 and connected to the second sub-electrode EN2 through a pad contact hole CNT-H formed in the first pad insulating layer 60.

[0164] According to an exemplary embodiment of the inventive concept, a second input insulating layer ISL-IL3 may cover the second pad electrode CN2 of the first signal pad PD1 and be disposed on the second pad insulating layer ISL-IL1. For example, the second input insulating layer ISL-IL3 may completely cover the second pad electrode CN2 of the first pad portion PD1-P1 of the first signal pad PD1. As an additional example, the second input insulating layer ISL-IL3 may have a thickness DH in a third direction DR3. As

[0165] shown, a second pad portion PD2-P2 of the second signal pad PD2 that does not overlap with the second input insulating layer ISL-IL3 may be exposed to an external space. For example, the second pad portion PD2-P2 may be disposed on a pad opening PD-OP formed in the second input insulating layer ISL-IL3. Figure 8 For example, a first length (e.g., height) from the top surface of the base layer BL to the top surface of the second input insulating layer ISL-IL3 may be greater than a second length from the top surface of the base layer BL to the top surface of the second pad portion PD2-P2 of the second signal pad PD2 (e.g., the top surface of the second pad electrode CN2 of the second pad portion PD2-P2).

[0166]

[0167] Figure 9 Referring to Figure 9 , the first sub-electrode EN1 may be electrically connected to the first pad electrode CN1 through a second sub-contact hole CNT-B formed in the third insulating layer 30. Accordingly, an external driving signal received through the second pad electrode CN2 may be transmitted to the data line DL.

[0168] For example, the second pad electrode CN2 corresponding to the second pad portion P2 may receive a driving signal through a connection pad PCB-P of the circuit board PCB (e.g., see Figure 4 ). The driving signal transmitted to the second pad electrode CN2 may pass through the first sub-contact hole CNT-A (e.g., see Figure 8)It is transmitted to the first pad electrode CN1 via the connection between the second sub-electrode EN2 and the first sub-electrode EN1. Since one end of the data line DL is in contact with the first pad electrode CN1, the driving signal can be transmitted from the first pad electrode CN1 to the data line DL.

[0169] Referring to Figure 10 , the first pad electrode CN1 may extend in the second direction DR2 and be disposed in the first pad portion P1 and the second pad portion P2. For example, the first pad electrode CN1 may completely cover the first pad portion P1 and the second pad portion P2 and may be continuous from the first pad portion P1 to the second pad portion P2. Similarly, the second pad electrode CN2 may be stacked with the first pad portion P1 and the second pad portion P2 and be disposed on the sub-input insulating layer ISL-IL1. For example, the second pad electrode CN2 may be completely stacked with the first pad portion P1 and the second pad portion P2.

[0170] In addition, the first pad portions P1 and the second pad portions P2 of each of the first signal pads PD1 to the fourth signal pads PD4 according to an exemplary embodiment of the inventive concept may be alternately and repeatedly disposed in the second direction DR2. Accordingly, each of the first signal pads PD1 to the fourth signal pads PD4 may be connected to a corresponding connection pad in the connection pads PCB-P of the circuit board PCB and at least two or more connection regions.

[0171] Figure 11 is a plan view of a pad region according to an exemplary embodiment of the inventive concept Figure 4 of. Figure 12 is a plan view of a pad according to an exemplary embodiment of the inventive concept.

[0172] Except for the number of pad contact holes CNT-H stacked with the second input insulating layer ISL-IL3, Figure 11 the pad region NDA-PA of Figure 7A may be substantially the same as the pad region NDA-PA of

[0173] Referring to Figure 11 and Figure 12 , the second input insulating layer ISL-IL3 is stacked with the first pad portion P1 of each of the first signal pads PD1 to the fourth signal pads PD4 and is not stacked with the second pad portion P2. For example, the second pad portion P2 of each of the first signal pads PD1 to the fourth signal pads PD4 may be exposed to the external space through a pad opening PD-OPa formed in the second input insulating layer ISL-IL3.

[0174] According to an exemplary embodiment of the inventive concept, each of the first pad portion P1 and the second pad portion P2 may be stacked with at least two pad contact holes CNT-H. The pad contact holes CNT-H may be contact holes formed in the first pad insulating layer 60 described with reference to Figure 8 In the present specification, two or more pad contact holes CNT-H stacked with the first pad portion P1 may be described as a first contact hole portion, and two or more pad contact holes CNT-H stacked with the second pad portion P2 may be described as a second contact hole portion.

[0175] As described above, the second pad portion P2 of each of the first signal pad PD1 to the fourth signal pad PD4 according to an exemplary embodiment of the inventive concept may be exposed to the external space through a pad opening PD-OPa formed in the second input insulating layer ISL-IL3. For example, in a plane, Figure 11 the pad opening PD-OPa has a surface area larger than the surface area of Figure 7A the pad opening PD-OP.

[0176] Although the pad opening formed in the second input insulating layer ISL-IL3 has been described with reference to Figure 7A and Figure 11 the shape of the pad opening formed in the second input insulating layer ISL-IL3 may be variously modified.

[0177] According to an exemplary embodiment of the inventive concept, two adjacent signal pads among the signal pads may be prevented from short-circuiting through an insulating layer covering a part of each of the signal pads. Short-circuiting between the signal pads may be prevented to improve the overall driving reliability of the display device.

[0178] Although the inventive concept has been described with reference to the exemplary embodiments of the inventive concept, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the inventive concept.

Claims

1. A display device, the display device comprising: A substrate layer, including a display area and a non-display area adjacent to the display area; A circuit element layer, disposed on the substrate layer; A display element layer, stacked with the display area and disposed on the circuit element layer; A plurality of signal pads, stacked with the non-display area and disposed on the substrate layer, wherein the plurality of signal pads are spaced apart from each other by a predetermined interval in a first direction and are electrically connected to the circuit element layer; and An input sensing layer, including a conductive layer and an input insulating layer, wherein the conductive layer is disposed on the display element layer, and the input insulating layer covers a part of each of the plurality of signal pads and the conductive layer, Wherein each of the plurality of signal pads includes a first pad portion and a second pad portion, wherein the first pad portion is stacked with the input insulating layer, and the second pad portion is not stacked with the input insulating layer, and Wherein the plurality of signal pads include a first signal pad and a second signal pad adjacent to the first signal pad, and the first pad portion of the first signal pad is aligned with the second pad portion of the second signal pad in the first direction.

2. The display device according to claim 1, wherein, The first pad portion and the second pad portion are alternately arranged in a second direction perpendicular to the first direction.

3. The display device according to claim 2, wherein, The second pad portion of the first signal pad is aligned with the first pad portion of the second signal pad in the first direction.

4. The display device according to claim 2, wherein the display device further comprises: A circuit board, including a plurality of connection pads respectively electrically connected to the plurality of signal pads, Wherein the second pad portion of each of the plurality of signal pads is electrically connected to a corresponding connection pad among the plurality of connection pads.

5. The display device according to claim 4, wherein, The input insulating layer includes: a pad opening exposing the second pad portion, and The display device further includes: an anisotropic conductive film disposed between the plurality of signal pads and the plurality of connection pads, wherein the anisotropic conductive film electrically connects the second pad portion of each of the plurality of signal pads to the corresponding connection pad through the pad opening.

6. The display device according to claim 1, wherein, Each of the plurality of signal pads includes: A first pad electrode, electrically connected to the display element layer and disposed on the substrate layer; A first pad insulating layer, covering the first pad electrode and disposed on the substrate layer, wherein a plurality of pad contact holes are formed in the first pad insulating layer; and A second pad electrode, disposed on the first pad insulating layer and electrically connected to the first pad electrode through the plurality of pad contact holes, Wherein the second pad electrode of each of the plurality of signal pads forms the first pad portion and the second pad portion.

7. The display device according to claim 6, wherein, The plurality of pad contact holes are spaced apart from each other and arranged in a second direction perpendicular to the first direction.

8. The display device according to claim 7, wherein, A first pad contact hole among the plurality of pad contact holes and a second pad contact hole adjacent to the first pad contact hole among the plurality of pad contact holes are respectively stacked with the first pad portion and the second pad portion.

9. The display device according to claim 7, wherein, The first pad contact hole and the second pad contact hole among the plurality of pad contact holes form a first contact hole portion, and a third pad contact hole and a fourth pad contact hole among the plurality of pad contact holes form a second contact hole portion, and The first contact hole portion is stacked with the first pad portion, and the second contact hole portion is stacked with the second pad portion.

10. The display device according to claim 1, wherein, A first length from the top surface of the base layer to the top surface of the input insulating layer is greater than a second length from the top surface of the base layer to the top surface of the second pad portion of each of the plurality of signal pads.

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