Display device

Abstract

A display device is disclosed. The display device includes: a substrate, a pixel and a transmissive region are located on the substrate, the pixel includes a display element; a plurality of wirings, located on the substrate, the wirings are located on one side of the transmissive region; a pixel electrode and an emission layer, both are included in the pixel; a counter electrode, located on the emission layer and includes an opening corresponding to the transmissive region; and a first metal layer, stacked with the wiring, the first metal layer is located below the wiring, wherein a side surface of the first metal layer has an inverted conical shape with respect to a top surface of the substrate.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0055834, filed with the Korean Intellectual Property Office on May 13, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of one or more embodiments relate to a display device. Background Art

[0003] Recently, the uses of display devices have become more diverse. In addition, as display devices have become thinner and lighter, their range of use has gradually expanded.

[0004] Since display devices are used for various purposes, there can be various methods for designing the shape of a display device. In addition, functions that can be combined with or related to the display device can be added.

[0005] The above information disclosed in this background section is only for enhancing the understanding of the background, and thus the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0006] Aspects of one or more embodiments include a display device including a sensor region inside a display region, and sensors are disposed in the sensor region. However, it should be understood that the example embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation of the disclosure.

[0007] Additional aspects will be partially set forth in the description below, and will be partially more apparent from the description, or may be learned by practice of the presented example embodiments.

[0008] According to one or more example embodiments, a display device includes: a substrate on which a pixel and a transmissive region are disposed, the pixel including a display element; wirings located on the substrate and disposed on one side of the transmissive region; a pixel electrode and an emission layer both included in the pixel; a counter electrode disposed on the emission layer and including an opening corresponding to the transmissive region; and a first metal layer stacked with the wirings and located below the wirings, wherein a side surface of the first metal layer has an inverted conical shape with respect to a top surface of the substrate.

[0009] According to some example embodiments, the display device may further include: a buffer layer disposed on the substrate, wherein the pixel may include a thin film transistor disposed on the buffer layer, and the first metal layer may be disposed between the substrate and the buffer layer.

[0010] According to some example embodiments, the substrate may include a first matrix layer, a first inorganic layer, a second matrix layer, and a second inorganic layer that are sequentially stacked.

[0011] According to some example embodiments, the first metal layer may be disposed under the first matrix layer, between the first matrix layer and the first inorganic layer, between the first inorganic layer and the second matrix layer, between the second matrix layer and the second inorganic layer, or on the second inorganic layer.

[0012] According to some example embodiments, the display device may further include: a first additional metal layer, stacked with the first metal layer and an insulating layer is located between the first additional metal layer and the first metal layer, wherein the first additional metal layer may be disposed under the first matrix layer, between the first matrix layer and the first inorganic layer, between the first inorganic layer and the second matrix layer, between the second matrix layer and the second inorganic layer, or on the second inorganic layer.

[0013] According to some example embodiments, the wiring may include a first wiring and a second wiring that do not overlap with each other, and the first metal layer may include a first sub-metal layer and a second sub-metal layer, the first sub-metal layer overlapping with the first wiring, and the second sub-metal layer overlapping with the second wiring.

[0014] According to some example embodiments, the display device may further include: a second metal layer, disposed under the pixel.

[0015] According to some example embodiments, the side surface of the second metal layer may have an inverted conical shape.

[0016] According to some example embodiments, the display device may further include: a functional layer, disposed between the pixel electrode and the emission layer, or between the emission layer and the counter electrode, wherein a material the same as that of the functional layer may be disposed in the transmission region.

[0017] According to some example embodiments, the display device may further include: an inorganic insulating layer, disposed on the substrate, wherein the inorganic insulating layer may include a first hole corresponding to the transmission region, and the counter electrode may be disposed on the sidewall of the first hole.

[0018] According to one or more example embodiments, a display device includes: a substrate including a display region and a sensor region, the display region including main pixels, and the sensor region including auxiliary pixels and a transmission region; a first pixel electrode and a first emission layer, included in the main pixels; a second pixel electrode and a second emission layer, included in the auxiliary pixels; a counter electrode, disposed integrally across the display region and the sensor region; wiring, disposed on one side of the transmission region; and a first metal layer, overlapping with the wiring, the first metal layer being located under the wiring.

[0019] According to some example embodiments, a side surface of the first metal layer may have an inverted conical shape with respect to a top surface of the substrate.

[0020] According to some example embodiments, the display device may further include: an inorganic insulating layer disposed on the substrate, wherein the inorganic insulating layer may include a first hole corresponding to the transmissive region, and the counter electrode may be disposed on a sidewall of the first hole.

[0021] According to some example embodiments, an area of an opening of the counter electrode may be smaller than an area of the first hole.

[0022] According to some example embodiments, the display device may further include: a functional layer disposed integrally in the display region and the sensor region and disposed between the first pixel electrode and the counter electrode, wherein the functional layer may include an opening corresponding to the transmissive region, and the opening of the counter electrode and the opening of the functional layer may overlap each other and form a transmissive hole.

[0023] According to some example embodiments, the display device may further include: a buffer layer disposed on the substrate, wherein the main pixel may include a thin film transistor disposed on the buffer layer, and the first metal layer may be disposed between the substrate and the buffer layer.

[0024] According to some example embodiments, the substrate may include a first base layer, a first inorganic layer, a second base layer, and a second inorganic layer sequentially stacked.

[0025] According to some example embodiments, the first metal layer may be disposed under the first base layer, between the first base layer and the first inorganic layer, between the first inorganic layer and the second base layer, between the second base layer and the second inorganic layer, or on the second inorganic layer.

[0026] According to some example embodiments, the display device may further include: a third metal layer disposed under the main pixel.

[0027] According to some example embodiments, the display device may further include: a component disposed on a bottom surface of the substrate corresponding to the sensor region. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] These and / or other aspects will become more apparent and easier to understand from the following description of example embodiments with reference to the accompanying drawings, in which:

[0029] Figure 1 is a perspective view of a display device according to some example embodiments;

[0030] Figure 2 is a cross-sectional view of a display device according to some example embodiments;

[0031] Figure 3is a plan view of a display panel according to some example embodiments;

[0032] Figure 4A is an equivalent circuit diagram of a pixel driven by an active matrix, the pixel being arranged in a display area of a display device;

[0033] Figure 4B is an equivalent circuit diagram of a pixel driven by an active matrix, the pixel being arranged in a display area of a display device;

[0034] Figure 5 is a plan view of a part of a display device according to some example embodiments;

[0035] Figure 6 is a cross-sectional view of a display device according to some example embodiments;

[0036] Figures 7A to 7C is a cross-sectional view of a method of manufacturing a display device according to some example embodiments;

[0037] Figure 8 is a cross-sectional view of a display device according to some example embodiments;

[0038] Figure 9 is a cross-sectional view of a display device according to some example embodiments;

[0039] Figure 10 is a cross-sectional view of a display device according to some example embodiments; and

[0040] Figure 11 is a cross-sectional view of a display device according to some example embodiments. Detailed Description

[0041] Aspects of some embodiments will now be described in more detail, examples of some embodiments being shown in the accompanying drawings, in which like reference numerals always refer to like elements. In this regard, the example embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the example embodiments are described below only by referring to the drawings to explain aspects of the present specification. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. When an expression such as "at least one of..." is after a list of elements, it modifies the entire list of elements and not individual elements in the list.

[0042] In the following, aspects in accordance with some example embodiments of the disclosure will be described more fully with reference to the accompanying drawings, in which example embodiments of the disclosure are shown. When described with reference to the accompanying drawings, like reference numerals in the drawings denote like or corresponding elements, and their repeated description will be omitted.

[0043] It will be understood that although terms such as “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0044] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0045] It will also be understood that the terms “comprises / comprising” and / or its variants used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0046] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, the layer, region, or component can be formed directly or indirectly on the other layer, region, or component. That is, for example, there can be intermediate layers, regions, or components.

[0047] For ease of explanation, the dimensions of elements in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0048] When a certain embodiment can be implemented differently, the specific process order can be performed in a different order than described. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0049] It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, the layer, region, or component can be “directly connected” to the other layer, region, or component, or can be “indirectly connected” to the other layer, region, or component with other layers, regions, or components therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “connected or electrically connected” to another layer, region, or component, the layer, region, or component can be “directly connected or electrically connected” to the other layer, region, or component, or can be “indirectly connected or electrically connected” to the other layer, region, or component with other layers, regions, or components therebetween.

[0050] Figure 1 is a perspective view of a display device 1 according to some example embodiments.

[0051] Reference Figure 1 , the display device 1 includes a display area DA and a non-display area NDA. The display area DA displays an image, and the non-display area NDA does not display an image. The display device 1 can display an image by using light emitted from a plurality of main pixels Pm arranged in the display area DA.

[0052] The display device 1 includes a sensor area SA. As described below with reference to Figure 2 , the sensor area SA may include an area in which components such as sensors using infrared light, visible light, or sound are arranged below it. The sensor area SA may include a transmissive area TA that can transmit light and / or sound output from the components to the outside or traveling from the outside toward the components. According to some example embodiments, when infrared light passes through the sensor area SA, the light transmittance may be 10% or greater, or for example 20% or greater, 25% or greater, 50% or greater, 85% or greater, or 90% or greater.

[0053] According to some example embodiments, a plurality of auxiliary pixels Pa may be arranged in the sensor area SA. The display device 1 can display an image (e.g., a predetermined image) by using light emitted from the auxiliary pixels Pa. The image displayed through the sensor area SA is an auxiliary image and may have a lower resolution than the image displayed on the display area DA. That is, since the sensor area SA includes the transmissive area TA that can transmit light and / or sound, the number of auxiliary pixels Pa that can be arranged per unit area may be less than the number of main pixels Pm that can be arranged per unit area in the display area DA.

[0054] The sensor area SA may be at least partially surrounded by the display area DA. According to some example embodiments, as shown in Figure 1 , the sensor area SA may be completely surrounded by the display area DA.

[0055] Although the display device according to some example embodiments is described as an organic light-emitting display device, the display device according to the embodiments of the present disclosure is not limited thereto. According to some example embodiments, the display device according to the embodiments of the present disclosure may be various display devices, for example, an inorganic light-emitting display device and a quantum dot light-emitting display device.

[0056] Although in Figure 1 the sensor area SA is shown to be arranged on one side (upper right side) of the display area DA having a quadrilateral shape, the embodiments are not limited thereto. The shape of the display area DA may include a circle, an ellipse, or a polygon such as a triangle or a pentagon. The position and number of the sensor area SA can be variously changed.

[0057] Figure 2is a cross-sectional view of a display device 1 according to some exemplary embodiments and may correspond to a cross-section taken along Figure 1 line A-A' of

[0058] Referring to Figure 2 , the display device 1 may include a display panel 10 including display elements and components 20 corresponding to a sensor area SA.

[0059] The display panel 10 may include a substrate 100, a display element layer 200, and a thin film encapsulation layer 300. The display element layer 200 is disposed on the substrate 100, and the thin film encapsulation layer 300 seals the display element layer 200 as a sealing member. In addition, the display panel 10 may further include a lower protective film 175 disposed under the substrate 100.

[0060] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer containing a polymer resin and an inorganic layer.

[0061] The display element layer 200 may include a circuit layer, an organic light-emitting diode OLED as a display element, and insulating layers IL and IL' between the circuit layer and the organic light-emitting diode OLED. The circuit layer includes thin film transistors TFT and TFT'.

[0062] Main pixels Pm may be disposed in a display area DA. The main pixels Pm include main thin film transistors TFT and organic light-emitting diodes OLED connected thereto. Auxiliary pixels Pa and wirings WL may be disposed in the sensor area SA. The auxiliary pixels Pa include auxiliary thin film transistors TFT' and organic light-emitting diodes OLED connected thereto.

[0063] In addition, a transmission area TA may be disposed in the sensor area SA. The auxiliary thin film transistors TFT' and display elements are not disposed in the transmission area TA. It can be understood that the transmission area TA is an area that transmits light / signals emitted from the components 20 or incident on the components 20.

[0064] The component 20 may be positioned in the sensor area SA. The component 20 may include electronic components using light or sound. For example, the component 20 may be a sensor such as an infrared sensor that emits and / or receives light, a sensor that outputs and senses light or sound to measure distance or identify fingerprints, a small lamp that outputs light, or a speaker that outputs sound. The electronic components using light may use light in various bands such as visible light, infrared light, and ultraviolet light. The components 20 arranged in the sensor area SA may be provided as a plurality of components. For example, as the component 20, a light emitting element and a light receiving element may be provided together in the sensor area SA. Optionally, a light emitter and a light receiver may be provided as one component 20 at the same time.

[0065] According to some example embodiments, the first metal layer BSM1 and / or the second metal layer BSM2 may be arranged in the sensor area SA. The first metal layer BSM1 may correspond to a plurality of wirings WL arranged in the sensor area SA, and the second metal layer BSM2 may correspond to the auxiliary pixel Pa. In addition, the third metal layer BSM3 may be arranged in the display area DA. The third metal layer BSM3 may correspond to the main pixel Pm.

[0066] The first metal layer BSM1 and the second metal layer BSM2 may be respectively arranged under the wiring WL and the auxiliary thin film transistor TFT'. The first metal layer BSM1 and the second metal layer BSM2 may prevent or reduce external light from reaching the wiring WL and the auxiliary pixel Pa including the auxiliary thin film transistor TFT'. For example, light emitted from the component 20 reaching the wiring WL and the auxiliary pixel Pa may be prevented or reduced. In addition, laser light reaching the wiring WL and the auxiliary pixel Pa during the process of forming the transmissive area TA may be prevented or reduced.

[0067] Similarly, the third metal layer BSM3 may be arranged under the main thin film transistor TFT, and may prevent or reduce external light from reaching the main thin film transistor TFT.

[0068] According to some example embodiments, a constant voltage or signal may be applied to the first to third metal layers BSM1, BSM2, and BSM3 to prevent the pixel circuit from being damaged by electrostatic discharge.

[0069] The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Regarding this, Figure 2 The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 and the organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 are shown.

[0070] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one of inorganic insulating materials, and the inorganic insulating materials include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride. The organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0071] The lower protective film 175 may be attached to the rear side of the substrate 100 to support and protect the substrate 100. The lower protective film 175 may include an opening 175OP corresponding to the sensor area SA. Since the lower protective film 175 includes the opening 175OP, the light transmittance of the sensor area SA can be improved. The lower protective film 175 may include PET or PI.

[0072] The area of the sensor area SA may be larger than the area where the components 20 are arranged. Therefore, the area of the opening 175OP of the lower protective film 175 may not be the same as the area of the sensor area SA. For example, the area of the opening 175OP may be smaller than the area of the sensor area SA.

[0073] According to some example embodiments, an input sensing member, an anti-reflection member, and a transparent window may be further arranged on the display panel 10. The input sensing member senses a touch input, and the anti-reflection member includes a polarizer and a retarder or a color filter and a black matrix.

[0074] Although this embodiment shows the thin film encapsulation layer 300 being used as an encapsulation member for sealing the display element layer 200, the embodiment is not limited thereto. For example, as a member for sealing the display element layer 200, a sealing substrate may be used, and the sealing substrate is attached to the substrate 100 through a sealant or a glass frit.

[0075] Figure 3 is a plan view of the display panel 10 according to some example embodiments.

[0076] Referring to Figure 3 , the display panel 10 is arranged in the display area DA and includes a plurality of main pixels Pm. Each of the main pixels Pm may include a display element such as an organic light emitting diode. Each main pixel Pm may emit, for example, red light, green light, blue light, or white light through the organic light emitting diode. In this specification, it can be understood that the main pixel Pm is a pixel that emits light of one color among red, green, blue, and white as described above. The display area DA may be covered by the encapsulation member described with reference to Figure 2 and is thus protected from external air or moisture.

[0077] The sensor area SA may be disposed inside the display area DA. A plurality of auxiliary pixels Pa are disposed in the sensor area SA. Each of the auxiliary pixels Pa may include a display element such as an organic light-emitting diode. Each auxiliary pixel Pa may emit, for example, red light, green light, blue light, or white light through the organic light-emitting diode. According to some example embodiments, it may be understood that the auxiliary pixel Pa is a pixel that emits light of one color among red, green, blue, and white as described above. The transmissive area TA may be disposed in the sensor area SA, and the transmissive area TA is disposed between the auxiliary pixels Pa.

[0078] According to some example embodiments, the pixel circuit of the main pixel Pm may be the same as the pixel circuit of the auxiliary pixel Pa. However, the embodiments are not limited thereto. The pixel circuit included in the main pixel Pm may be different from the pixel circuit included in the auxiliary pixel Pa.

[0079] Since the sensor area SA includes the transmissive area TA, the resolution of the sensor area SA may be less than the resolution of the display area DA. For example, the resolution of the sensor area SA may be about 1 / 2 of the resolution of the display area DA. According to some example embodiments, the resolution of the display area DA may be 400 ppi or greater, and the resolution of the sensor area SA may be 200 ppi or greater.

[0080] Each of the main pixel Pm and the auxiliary pixel Pa may be electrically connected to a peripheral circuit disposed in the non-display area NDA. The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the data driving circuit 150, the first power line 160, and the second power line 170 may be disposed in the non-display area NDA.

[0081] The first scan driving circuit 110 may provide a scan signal to each of the main pixel Pm and the auxiliary pixel Pa through the scan line SL. The first scan driving circuit 110 may provide an emission control signal to each of the main pixel Pm and the auxiliary pixel Pa through the emission control line EL. The second scan driving circuit 120 may be disposed in parallel with the first scan driving circuit 110, and the display area DA is located between the second scan driving circuit 120 and the first scan driving circuit 110. Some of the main pixel Pm and the auxiliary pixel Pa disposed in the display area DA and the sensor area SA may be electrically connected to the first scan driving circuit 110, and the remaining main pixel Pm and auxiliary pixel Pa may be connected to the second scan driving circuit 120. According to some example embodiments, the second scan driving circuit 120 may be omitted.

[0082] Terminal 140 may be disposed on one side of the substrate 100. Terminal 140 may be exposed by not being covered with an insulating layer, and thus is electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits signals or power of a controller (not shown) to the display panel 10. The control signal generated by the controller may be transmitted to each of the first scan driving circuit 110 and the second scan driving circuit 120 through the printed circuit board PCB. The controller may supply the first power voltage ELVDD and the second power voltage ELVSS (see Figure 4A and Figure 4B described below) to the first power line 160 and the second power line 170 respectively through the first connection line 161 and the second connection line 171. The first power voltage ELVDD may be supplied to each of the main pixel Pm and the auxiliary pixel Pa through the driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS (also referred to as a common voltage) may be supplied to the counter electrode connected to the second power line 170 of each of the main pixel Pm and the auxiliary pixel Pa.

[0083] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be supplied to each of the main pixel Pm and the auxiliary pixel Pa through the connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151. Although the data driving circuit 150 is shown disposed on the printed circuit board PCB in Figure 3 , the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power line 160.

[0084] The first power line 160 may include a first sub-line 162 and a second sub-line 163 which extend parallel to each other in the x direction and the display area DA is located between the first sub-line 162 and the second sub-line 163. The second power line 170 has an annular shape with an open side and may partially surround the display area DA.

[0085] Figure 4A and Figure 4B are equivalent circuit diagrams of the main pixel Pm and / or the auxiliary pixel Pa that may be included in the display panel 10 according to an embodiment.

[0086] Referring to Figure 4A , each of the main pixel Pm and the auxiliary pixel Pa includes a pixel circuit PC and an organic light emitting diode OLED. The pixel circuit PC is connected to the scan line SL and the data line DL, and the organic light emitting diode OLED is connected to the pixel circuit PC.

[0087] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is connected to a scan line SL and a data line DL, and transmits a data signal Dm to the driving thin-film transistor T1 in response to a scan signal Sn input through the scan line SL, and the data signal Dm is input through the data line DL.

[0088] The storage capacitor Cst is connected to the switching thin-film transistor T2 and a driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching thin-film transistor T2 and the first power supply voltage ELVDD (or driving voltage) supplied through the driving voltage line PL.

[0089] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with a predetermined brightness by using the driving current.

[0090] Although Figure 4A a case where the pixel circuit PC includes two thin-film transistors and one storage capacitor is described, the embodiments are not limited thereto. As Figure 4B shown, the pixel circuit PC can include seven thin-film transistors and one storage capacitor.

[0091] Referring to Figure 4B , each of the main pixel Pm and the auxiliary pixel Pa includes a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC can include a plurality of thin-film transistors and a plurality of storage capacitors. The thin-film transistors and the storage capacitors can be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

[0092] Although in Figure 4B each of the main pixel Pm and the auxiliary pixel Pa is shown connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL, the embodiments are not limited thereto. According to some example embodiments, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL can be shared by adjacent pixels.

[0093] The plurality of thin-film transistors can include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0094] The signal lines include a scan line SL, a previous scan line SL-1, an emission control line EL, and a data line DL. The scan line SL transmits a scan signal Sn. The previous scan line SL-1 transmits a previous scan signal Sn-1 to a first initialization thin-film transistor T4 and a second initialization thin-film transistor T7. The emission control line EL transmits an emission control signal En to an operation control thin-film transistor T5 and an emission control thin-film transistor T6. And the data line DL intersects with the scan line SL and transmits a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to a driving thin-film transistor T1, and the initialization voltage line VL transmits an initialization voltage Vint for initializing the driving thin-film transistor T1 and the pixel electrode of the organic light-emitting diode OLED.

[0095] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin-film transistor T1 is connected to the driving voltage line PL through the operation control thin-film transistor T5. The driving drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode OLED through the emission control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm according to the switching operation of the switching thin-film transistor T2, and supplies a driving current I OLED to the organic light-emitting diode OLED.

[0096] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL. The switching source electrode S2 of the switching thin-film transistor T2 is connected to the data line DL. The switching drain electrode D2 of the switching thin-film transistor T2 is connected to the driving source electrode S1 of the driving thin-film transistor T1 and is simultaneously connected to the driving voltage line PL through the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL, and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin-film transistor T1.

[0097] The compensating gate electrode G3 of the compensating thin-film transistor T3 is connected to the scan line SL. The compensating source electrode S3 of the compensating thin-film transistor T3 is connected to the driving drain electrode D1 of the driving thin-film transistor T1 and is simultaneously connected to the pixel electrode of the organic light-emitting diode OLED through the emission control thin-film transistor T6. The compensating drain electrode D3 of the compensating thin-film transistor T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensating thin-film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and diode-connects the driving thin-film transistor T1 by electrically connecting the driving gate electrode G1 to the driving drain electrode D1.

[0098] The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL. And the first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the drive gate electrode G1 of the drive thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and performs an initialization operation of transmitting the initialization voltage Vint to the drive gate electrode G1 of the drive thin film transistor T1, thereby initializing the voltage of the drive gate electrode G1 of the drive thin film transistor T1.

[0099] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL. The operation control source electrode S5 of the operation control thin film transistor T5 is connected to the drive voltage line PL. And the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the drive source electrode S1 of the drive thin film transistor T1 and the switch drain electrode D2 of the switch thin film transistor T2.

[0100] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3. And the emission control drain electrode D6 of the emission control thin film transistor T6 is connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0101] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL to allow the drive voltage ELVDD to be transmitted to the organic light emitting diode OLED, thus allowing the drive current I OLED to flow through the organic light emitting diode OLED.

[0102] The second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED. And the second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and initializes the pixel electrode of the organic light emitting diode OLED.

[0103] Although Figure 4B The case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1 is shown, but the embodiments are not limited thereto. According to some example embodiments, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 and be driven in response to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the subsequent scan line) and be driven in response to the signal transmitted through the separate signal line.

[0104] The second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the voltage line for transmitting the common voltage ELVSS. Thus, the organic light emitting diode OLED can receive the driving current I from the driving thin film transistor T1 OLED and emit light, thereby displaying an image.

[0105] Although in Figure 4B it is shown that both the compensation thin film transistor T3 and the first initialization thin film transistor T4 have dual gate electrodes, both the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

[0106] According to some example embodiments, the pixel circuit PC of the main pixel Pm may be the same as the pixel circuit PC of the auxiliary pixel Pa. However, the embodiments are not limited thereto. The pixel circuit PC of the main pixel Pm may be different from the pixel circuit PC of the auxiliary pixel Pa. For example, the main pixel Pm may adopt Figure 4B the pixel circuit PC, and the auxiliary pixel Pa may adopt Figure 4A the pixel circuit PC. Various modifications can be made.

[0107] Figure 5 is Figure 3 a plan view of a part of the sensor area SA of Figure 6 is along Figure 3 the line I-I' of Figure 5A cross-sectional view of the display device 1 taken along line II-II'.

[0108] Referring to Figure 5 , according to an embodiment, the auxiliary pixels Pa and the transmission regions TA are arranged in the sensor region SA of the display device 1. The auxiliary pixels Pa may be continuously arranged to form a pixel group Pg. The pixel group Pg may include at least one auxiliary pixel Pa. In Figure 5 , a pixel group Pg including four auxiliary pixels Pa arranged in two columns is shown. However, the embodiment is not limited thereto. The number and arrangement of the auxiliary pixels Pa included in one pixel group Pg may be variously modified. For example, one pixel group Pg may include three auxiliary pixels Pa arranged side by side in one column.

[0109] The transmission region TA is a region that does not include display elements and thus has a high light transmittance. The transmission region TA may be provided as a plurality of transmission regions TA in the sensor region SA. The transmission regions TA and the pixel group Pg may be alternately arranged in the first direction (x direction) and / or the second direction (y direction). Alternatively, the transmission region TA may surround the pixel group Pg. Alternatively, the auxiliary pixels Pa may surround the transmission region TA.

[0110] The sensor region SA includes a wiring WL that connects the auxiliary pixels Pa and extends in the second direction (y direction) and a wiring (not shown) that extends in the first direction (x direction) crossing the second direction (y direction).

[0111] According to some exemplary embodiments, at least some of the wirings WL may detour around the transmission region TA. The transmission region TA may be provided to ensure light transmittance. The wiring WL may include the data line DL, the driving voltage line PL, the initialization voltage line VL, the previous scan line SL-1, the scan line SL, and the emission control line EL described as an example with reference to Figure 4A and / or Figure 4B .

[0112] Therefore, at least some of the wirings WL may be arranged on one side of the transmission region TA. According to some exemplary embodiments, a first metal layer BSM1 is introduced under the wiring WL arranged on one side of the transmission region TA. In a plan view, the first metal layer BSM1 may be arranged between the transmission region TA and the auxiliary pixel Pa. This is to protect the wiring WL during the process. This will be described in more detail below.

[0113] According to some exemplary embodiments, the first metal layer BSM1 may be provided in an island shape, and one first metal layer BSM1 may correspond to a plurality of wirings WL. That is, one first metal layer BSM1 may be stacked with a plurality of wirings WL. Thus, external light can be prevented from reaching the wiring WL.

[0114] According to some example embodiments, the first metal layer BSM1 may be connected to one of the wirings WL through a contact hole. Since the first metal layer BSM1 receives the voltage or signal of the wiring WL, the possibility of electrostatic discharge occurrence can be significantly reduced. According to some example embodiments, the first metal layer BSM1 may be connected to the scan line SL through a contact hole. Therefore, since the first metal layer BSM1 can be used as a part of the scan line SL, the resistance value of the wiring for transmitting the scan signal can be reduced. This means that when the first metal layer BSM1 is connected to the scan line SL, the RC delay can be reduced.

[0115] According to some example embodiments, the second metal layer BSM2 may be disposed under the auxiliary pixel Pa. The second metal layer BSM2 can prevent external light from reaching the auxiliary thin film transistor TFT' included in the auxiliary pixel Pa, thereby protecting the auxiliary thin film transistor TFT' and stabilizing the characteristics of the auxiliary thin film transistor TFT'.

[0116] According to some example embodiments, the second metal layer BSM2 may be set in an island shape, and one second metal layer BSM2 may correspond to a plurality of auxiliary pixels Pa. For example, one second metal layer BSM2 may be completely superimposed on one pixel group Pg.

[0117] According to some example embodiments, the first metal layer BSM1 and the second metal layer BSM2 may be separated from each other and may receive different voltages or signals. According to some example embodiments, the second metal layer BSM2 may be connected to the driving voltage line PL through a contact hole. Since the second metal layer BSM2 is not floating and is connected to the driving voltage line PL, the possibility of electrostatic discharge occurrence can be significantly reduced.

[0118] Referring to Figure 6 , according to some example embodiments, the display device 1 includes a display area DA and a sensor area SA. Main pixels Pm are arranged in the display area DA, and auxiliary pixels Pa and a transmissive area TA are arranged in the sensor area SA. A plurality of wirings WL are arranged on one side of the transmissive area TA and are located between the transmissive area TA and the auxiliary pixels Pa.

[0119] The main pixel Pm may include a main thin film transistor TFT, a main storage capacitor Cst, and a main organic light emitting diode OLED. The auxiliary pixel Pa may include an auxiliary thin film transistor TFT', an auxiliary storage capacitor Cst', and an auxiliary organic light emitting diode OLED'. The transmissive area TA may include a transmissive hole TAH corresponding to the transmissive area TA.

[0120] A first metal layer BSM1 is disposed below a wiring WL disposed on one side of a transmissive region TA, and the first metal layer BSM1 is stacked with the wiring WL. According to some example embodiments, a side surface of the first metal layer BSM1 may have an inverted conical shape with respect to a top surface of the substrate 100.

[0121] In addition, a second metal layer BSM2 may be disposed below an auxiliary thin film transistor TFT' of an auxiliary pixel Pa, and the second metal layer BSM2 is stacked with the auxiliary thin film transistor TFT'. A third metal layer BSM3 may be disposed below a main thin film transistor TFT of a main pixel Pm, and the third metal layer BSM3 is stacked with the main thin film transistor TFT. A side surface of the second metal layer BSM2 and / or the third metal layer BSM3 may have an inverted conical shape with respect to a top surface of the substrate 100.

[0122] Hereinafter, a structure of elements of a display device in which elements according to some example embodiments are stacked is described.

[0123] The substrate 100 may include a polymer resin. The substrate 100 may include a matrix layer including a polymer resin and an inorganic layer. For example, the substrate 100 may include a first matrix layer 101, a first inorganic layer 102, a second matrix layer 103, and a second inorganic layer 104 stacked in sequence.

[0124] Both the first matrix layer 101 and the second matrix layer 103 may include a polymer resin. For example, the first matrix layer 101 and the second matrix layer 103 may include a polymer resin such as polyether sulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0125] Both the first inorganic layer 102 and the second inorganic layer 104 may be barrier layers that prevent penetration of foreign substances, and may include a single layer or multiple layers including an inorganic material such as silicon nitride (SiN x ) and / or silicon oxide (SiO x ).

[0126] A buffer layer 111 may be positioned on the substrate 100, may reduce or prevent penetration of foreign substances, moisture, or external air from below the substrate 100, and provides a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite material, and may include a single layer or multiple layer structure of an inorganic material and an organic material.

[0127] According to some example embodiments, the first to third metal layers BSM1, BSM2, and BSM3 may be disposed between the substrate 100 and the buffer layer 111, that is, between the second inorganic layer 104 and the buffer layer 111. According to some example embodiments, the first to third metal layers BSM1, BSM2, and BSM3 may be disposed below the second inorganic layer 104. For example, the first to third metal layers BSM1, BSM2, and BSM3 may be disposed between the second base layer 103 and the second inorganic layer 104. According to some example embodiments, at least one of the first to third metal layers BSM1, BSM2, and BSM3 may be disposed on a different layer.

[0128] The first metal layer BSM1 may be disposed below the wiring WL disposed between the transmissive region TA and the auxiliary pixel Pa to prevent the wiring WL from being damaged during the process.

[0129] The second metal layer BSM2 may be disposed below the auxiliary pixel Pa to prevent the auxiliary thin film transistor TFT' disposed in the auxiliary pixel Pa from being damaged or to prevent the characteristics of the auxiliary thin film transistor TFT' from deteriorating.

[0130] The third metal layer BSM3 may be disposed below the main pixel Pm to prevent the main thin film transistor TFT disposed in the main pixel Pm from being damaged or to prevent the characteristics of the main thin film transistor TFT from deteriorating.

[0131] The first to third metal layers BSM1, BSM2, and BSM3 may be connected to the wirings WL and GCL disposed on different layers. The first to third metal layers BSM1, BSM2, and BSM3 may receive a constant voltage or a signal from the wirings WL and GCL. For example, the first to third metal layers BSM1, BSM2, and BSM3 may receive a driving voltage ELVDD or a scan signal. Since the first to third metal layers BSM1, BSM2, and BSM3 may receive a constant voltage or a scan signal, the possibility of electrostatic discharge occurrence may be significantly reduced. However, the embodiments are not limited thereto. All of the first to third metal layers BSM1, BSM2, and BSM3 may not receive an electrical signal. In addition, at least one of the first to third metal layers BSM1, BSM2, and BSM3 may be electrically floated and the remaining metal layers of the first to third metal layers BSM1, BSM2, and BSM3 may receive an electrical signal. Various modifications may be made.

[0132] The first to third metal layers BSM1, BSM2, and BSM3 may include at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu. The first to third metal layers BSM1, BSM2, and BSM3 may include a single layer or multiple layers containing the above materials.

[0133] Although the drawings show all of the first to third metal layers BSM1, BSM2, and BSM3, according to an embodiment, at least one of the first to third metal layers BSM1, BSM2, and BSM3 may be omitted.

[0134] In addition, the side surfaces of the first to third metal layers BSM1, BSM2, and BSM3 are shown to have an inverted conical shape. That is, the width of the first to third metal layers BSM1, BSM2, and BSM3 in the first direction (x direction) may increase away from the top surface of the substrate 100. However, the embodiment is not limited thereto. Only the side surface of the first metal layer BSM1 may have an inverted conical shape, and the side surface of each of the second metal layer BSM2 and the third metal layer BSM3 may have a positive conical shape. Alternatively, only the side surfaces of the first metal layer BSM1 and the second metal layer BSM2 may have an inverted conical shape.

[0135] The side surface of the first metal layer BSM1 may have an inverted conical shape to prevent the laser from reaching the wiring WL during the process of forming the transmission hole TAH. This will be described below.

[0136] The main thin film transistor TFT and the auxiliary thin film transistor TFT' may be disposed on the buffer layer 111. The main thin film transistor TFT includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The auxiliary thin film transistor TFT' includes a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main thin film transistor TFT may be connected to the main organic light emitting diode OLED in the display area DA to drive the main organic light emitting diode OLED. The auxiliary thin film transistor TFT' may be connected to the auxiliary organic light emitting diode OLED' in the sensor area SA to drive the auxiliary organic light emitting diode OLED'.

[0137] The first semiconductor layer A1 and the second semiconductor layer A2 may be disposed on the buffer layer 111 and may include polysilicon. According to some example embodiments, the first semiconductor layer A1 and the second semiconductor layer A2 may include amorphous silicon. According to some example embodiments, the first semiconductor layer A1 and the second semiconductor layer A2 may include an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, and Zn. Both the first semiconductor layer A1 and the second semiconductor layer A2 may include a channel region, a source region, and a drain region, and the source region and the drain region are doped with impurities.

[0138] The first semiconductor layer A1 may be stacked with the third metal layer BSM3, and the buffer layer 111 is located between the first semiconductor layer A1 and the third metal layer BSM3. According to some example embodiments, the width of the first semiconductor layer A1 may be less than the width of the third metal layer BSM3. Thus, when projected in a direction perpendicular to the substrate 100, the first semiconductor layer A1 may be completely stacked with the third metal layer BSM3.

[0139] The second semiconductor layer A2 may be stacked with the second metal layer BSM2, and the buffer layer 111 is located between the second semiconductor layer A2 and the second metal layer BSM2. According to some example embodiments, the width of the second semiconductor layer A2 may be less than the width of the second metal layer BSM2. Thus, when projected in a direction perpendicular to the substrate 100, the second semiconductor layer A2 may be completely stacked with the second metal layer BSM2.

[0140] The first gate insulating layer 112 may cover the first semiconductor layer A1 and the second semiconductor layer A2. The first gate insulating layer 112 may include an inorganic insulating material such as SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO2. The first gate insulating layer 112 may include a single layer or multiple layers including the above inorganic insulating materials.

[0141] The first gate electrode G1 and the second gate electrode G2 are disposed on the first gate insulating layer 112, and the first gate electrode G1 and the second gate electrode G2 are respectively stacked with the first semiconductor layer A1 and the second semiconductor layer A2. The first gate electrode G1 and the second gate electrode G2 may include a single layer or multiple layers including at least one of Mo, Al, Cu, and Ti. For example, both the first gate electrode G1 and the second gate electrode G2 may include a single Mo layer.

[0142] The second gate insulating layer 113 may cover the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may include an inorganic insulating material such as SiO2, SiN x, an inorganic insulating material such as SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO2. The second gate insulating layer 113 may include a single layer or multiple layers containing the above inorganic insulating materials.

[0143] The first top electrode CE2 of the main storage capacitor Cst and the second top electrode CE2' of the auxiliary storage capacitor Cst' may be disposed on the second gate insulating layer 113.

[0144] In the display area DA, the first top electrode CE2 may be stacked with the first gate electrode G1 below it. The first gate electrode G1 and the first top electrode CE2 may form the main storage capacitor Cst. The first gate electrode G1 and the first top electrode CE2 are stacked with each other and the second gate insulating layer 113 is located between the first gate electrode G1 and the first top electrode CE2. The first gate electrode G1 may be used as the first bottom electrode CE1 of the main storage capacitor Cst.

[0145] In the sensor area SA, the second top electrode CE2' may be stacked with the second gate electrode G2 below it. The second gate electrode G2 and the second top electrode CE2' may form the auxiliary storage capacitor Cst'. The second gate electrode G2 and the second top electrode CE2' are stacked with each other and the second gate insulating layer 113 is located between the second gate electrode G2 and the second top electrode CE2'. The second gate electrode G2 may be used as the second bottom electrode CE1' of the auxiliary storage capacitor Cst'.

[0146] Both the first top electrode CE2 and the second top electrode CE2' may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W and / or Cu, and may include a single layer or multiple layers containing the above materials.

[0147] The interlayer insulating layer 115 may cover the first top electrode CE2 and the second top electrode CE2'. The interlayer insulating layer 115 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc peroxide (ZnO2).

[0148] When the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IL, the inorganic insulating layer IL may include a first hole H1 corresponding to the transmission region TA. The first hole H1 may expose the buffer layer 111 or the top surface of the substrate 100. The first hole H1 may include a first opening of the first gate insulating layer 112, a second opening of the second gate insulating layer 113, and a third opening of the interlayer insulating layer 115, all of which correspond to the transmission region TA, and the first opening, the second opening, and the third opening are stacked on top of each other. The first opening to the third opening may be formed separately by separate processes or simultaneously by the same process. Optionally, the first opening and the second opening may be formed simultaneously, and the third opening may be formed separately. Various modifications can be made. When the first opening to the third opening are formed by separate processes, a step difference may be formed on the side surface of the first hole H1.

[0149] Instead of the first hole H1 exposing the buffer layer 111, the inorganic insulating layer IL may include a groove. For example, the first gate insulating layer 112 in the inorganic insulating layer IL may be continuously arranged corresponding to the transmission region TA, and the second gate insulating layer 113 and the interlayer insulating layer 115 may respectively include a second opening and a third opening corresponding to the transmission region TA.

[0150] Optionally, the first gate insulating layer 112 and the second gate insulating layer 113 may be continuously arranged corresponding to the transmission region TA, and the interlayer insulating layer 115 may include a third opening corresponding to the transmission region TA. Various modifications can be made.

[0151] According to some example embodiments, the inorganic insulating layer IL may not include the first hole H1 corresponding to the transmission region TA. Since the inorganic insulating layer IL may transmit light that can be transmitted / received by the component 20 (see Figure 2 ), the inorganic insulating layer IL may not include a hole corresponding to the transmission region TA.

[0152] The source electrodes S1 and S2 and the drain electrodes D1 and D2 may be arranged on the interlayer insulating layer 115. The source electrodes S1 and S2 and the drain electrodes D1 and D2 may include a conductive material containing Mo, Al, Cu, and Ti, and may include a single layer or multiple layers containing the above materials. For example, the source electrodes S1 and S2 and the drain electrodes D1 and D2 may each have a multilayer structure of Ti / Al / Ti.

[0153] The planarization layer 117 may cover the source electrodes S1 and S2 and the drain electrodes D1 and D2. The planarization layer 117 may have a flat top surface such that the first pixel electrode 221 and the second pixel electrode 221' thereon are formed flat.

[0154] The planarization layer 117 may include a single layer or multiple layers including an organic material or an inorganic material. The planarization layer 117 may include common polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, parylene polymers, vinyl alcohol polymers, and blends thereof. In addition, the planarization layer 117 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc peroxide (ZnO2). After forming the planarization layer 117, chemical mechanical polishing may be performed to provide a flat top surface to the planarization layer 117.

[0155] The planarization layer 117 may include a second hole H2 corresponding to the transmission region TA. The second hole H2 may be stacked with the first hole H1. Although the bottom width W2 of the second hole H2 is shown to be greater than the bottom width W1 of the first hole H1 in the drawings, the embodiments are not limited thereto. For example, the planarization layer 117 may cover the edge of the first hole H1 of the inorganic insulating layer IL, and the width of the second hole H2 may be smaller than the width of the first hole H1.

[0156] There is an opening in the planarization layer 117 that exposes one of the first source electrode S1 and the first drain electrode D1 of the main thin film transistor TFT. The first pixel electrode 221 may be electrically connected to the main thin film transistor TFT by contacting the first source electrode S1 or the first drain electrode D1 through the opening in the planarization layer 117.

[0157] In addition, the planarization layer 117 includes an opening that exposes one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin film transistor TFT'. The second pixel electrode 221' may be electrically connected to the auxiliary thin film transistor TFT' by contacting the second source electrode S2 or the second drain electrode D2 through the opening.

[0158] The first pixel electrode 221 and the second pixel electrode 221' may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to some example embodiments, both the first pixel electrode 221 and the second pixel electrode 221' may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof. According to some example embodiments, the first pixel electrode 221 and the second pixel electrode 221' may further include a layer containing ITO, IZO, ZnO, or In2O3 on / under the reflective layer. According to some example embodiments, the first pixel electrode 221 and the second pixel electrode 221' may have a stacked structure of ITO / Ag / ITO.

[0159] The pixel defining layer 119 may cover the edges of each of the first pixel electrode 221 and the second pixel electrode 221'. The pixel defining layer 119 includes a first opening OP1 and a second opening OP2, and the first opening OP1 and the second opening OP2 are respectively stacked with the first pixel electrode 221 and the second pixel electrode 221' and define the emission region of the pixel. The pixel defining layer 119 may prevent the occurrence of arcs or the like at the edges of the pixel electrodes (i.e., the first pixel electrode 221 and the second pixel electrode 221') by increasing the distance between the edges of the first pixel electrode 221 and the second pixel electrode 221' and the counter electrode 223 above the first pixel electrode 221 and the second pixel electrode 221'. The pixel defining layer 119 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin. The pixel defining layer 119 may be formed by a method such as spin coating.

[0160] The pixel defining layer 119 may include a third hole H3 positioned in the transmissive region TA. The third hole H3 may be stacked with the first hole H1 and the second hole H2. Since the first hole H1, the second hole H2, and the third hole H3 are formed, the light transmittance of the transmissive region TA can be improved. The counter electrode 223 described below may be disposed on the inner walls of the first hole H1, the second hole H2, and the third hole H3.

[0161] The wiring WL is disposed between the transmissive region TA and the auxiliary pixel Pa, and the wiring WL winds around the transmissive region TA. The wiring WL may include wirings WLa, WLb, and WLc disposed on different layers. For example, the wiring WL may include a first wiring WLa, a second wiring WLb, and a third wiring WLc. The first wiring WLa is disposed on the layer on which the gate electrodes G1 and G2 are disposed, the second wiring WLb is disposed on the layer on which the first top electrode CE2 and the second top electrode CE2' are disposed, and the third wiring WLc is disposed on the layer on which the source electrodes S1 and S2 are disposed.

[0162] The wiring WL may be stacked with the first metal layer BSM1, and the buffer layer 111 is located between the wiring WL and the first metal layer BSM1. According to some example embodiments, one first metal layer BSM1 may correspond to multiple wirings WL. Thus, in a direction perpendicular to the substrate 100, multiple wirings WL may be completely stacked with the first metal layer BSM1.

[0163] The first functional layer 222a covers the pixel defining layer 119. The first functional layer 222a may include a single layer or multiple layers. The first functional layer 222a may include a hole transport layer (HTL) having a single-layer structure. Optionally, the first functional layer 222a may include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer 222a may be provided integrally to correspond to the main pixels Pm and the auxiliary pixels Pa included in the display area DA and the sensor area SA.

[0164] The first emission layer 222b and the second emission layer 222b' are disposed on the first functional layer 222a, and the first emission layer 222b and the second emission layer 222b' respectively correspond to the first pixel electrode 221 and the second pixel electrode 221'. The first emission layer 222b and the second emission layer 222b' may include a polymer material or a low molecular weight material, and may emit red light, green light, blue light, or white light.

[0165] The second functional layer 222c may be formed on the first emission layer 222b and the second emission layer 222b'. The second functional layer 222c may include a single layer or multiple layers. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 222c may be provided integrally to correspond to the main pixels Pm and the auxiliary pixels Pa included in the display area DA and the sensor area SA. The first functional layer 222a and / or the second functional layer 222c may be omitted.

[0166] The counter electrode 223 is disposed on the second functional layer 222c. The counter electrode 223 may include a conductive material having a small work function. For example, the counter electrode 223 may include a (semi)transparent layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Optionally, the counter electrode 223 may further include a layer containing ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer containing the above materials. The counter electrode 223 may be provided integrally to correspond to the main pixels Pm and the auxiliary pixels Pa included in the display area DA and the sensor area SA.

[0167] Layers within the range from the first pixel electrode 221 to the counter electrode 223 in the display area DA can form the main organic light-emitting diode OLED. Layers within the range from the second pixel electrode 221' to the counter electrode 223 in the sensor area SA can form the auxiliary organic light-emitting diode OLED'.

[0168] The capping layer 250 can be formed on the counter electrode 223. The capping layer 250 can include LiF. Optionally, the capping layer 250 can include an organic insulating material and / or an inorganic insulating material such as silicon nitride. According to some example embodiments, the capping layer 250 can be omitted.

[0169] According to some example embodiments, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 250 can each include a transmissive hole TAH corresponding to the transmissive area TA. That is, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 250 can each include an opening corresponding to the transmissive area TA. According to some example embodiments, the widths of the openings forming the transmissive hole TAH can be substantially the same. For example, the width of the opening of the counter electrode 223 can be substantially the same as the width of the transmissive hole TAH.

[0170] In addition, according to some example embodiments, the first functional layer 222a, the second functional layer 222c, and the capping layer 250 can be omitted. In this case, the opening of the counter electrode 223 can be used as the transmissive hole TAH.

[0171] That the transmissive hole TAH corresponds to the transmissive area TA can mean that the transmissive hole TAH is superimposed on the transmissive area TA. In this case, the area of the transmissive hole TAH can be smaller than the area of the first hole H1 formed in the inorganic insulating layer IL. For this reason, Figure 6 it is shown that the width Wt of the transmissive hole TAH is smaller than the bottom width W1 of the first hole H1. Here, the areas of the transmissive hole TAH and the first hole H1 can be defined as the narrowest areas of the openings.

[0172] According to some example embodiments, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 250 can be disposed on the side surfaces of the first hole H1, the second hole H2, and the third hole H3. According to some example embodiments, the inclination of the side surfaces of the first hole H1, the second hole H2, and the third hole H3 with respect to the top surface of the substrate 100 can be gentler than the inclination of the side surfaces of the transmissive hole TAH with respect to the top surface of the substrate 100.

[0173] Since forming the transmissive hole TAH in the transmissive area TA means removing components such as the counter electrode 223, the light transmittance of the transmissive area TA can be significantly improved.

[0174] The main organic light-emitting diode OLED and the auxiliary organic light-emitting diode OLED' can be sealed by a thin film encapsulation layer 300. The thin film encapsulation layer 300 can be disposed on the cover layer 250. The thin film encapsulation layer 300 can prevent external moisture or foreign substances from penetrating into the main organic light-emitting diode OLED and the auxiliary organic light-emitting diode OLED'.

[0175] The thin film encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, in Figure 6 it is shown that the thin film encapsulation layer 300 has a structure in which a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 are stacked. According to some example embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order can be modified.

[0176] Both the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include at least one inorganic insulating material including alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and can be formed by chemical vapor deposition (CVD). The organic encapsulation layer 320 can include a polymer-based material. The polymer-based material can include a silicone-based resin, an acrylic-based resin, an epoxy-based resin, polyimide, and polyethylene.

[0177] The first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 can all be formed integrally to cover the display area DA and the sensor area SA. Accordingly, the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 can be disposed inside the transmission hole TAH.

[0178] According to some example embodiments, the organic encapsulation layer 320 can be formed integrally to cover the display area DA and the sensor area SA, and can be absent in the transmission area TA. In other words, the organic encapsulation layer 320 can include an opening corresponding to the transmission area TA. In this case, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be in contact with each other inside the transmission hole TAH.

[0179] Figures 7A to 7C are cross-sectional views sequentially showing a method of manufacturing the display device 1 according to an embodiment. Specifically, Figures 7A to 7C shows a method of forming the transmission hole TAH.

[0180] Referring to Figure 7A a sacrificial metal layer ML is formed inside a first hole H1 of the inorganic insulating layer IL.

[0181] The sacrificial metal layer ML may include metals such as Ag, Al, Pt, Pd, Au, Ni, Mo, and Ti. In addition, the sacrificial metal layer ML may further include a layer containing ITO, IZO, ZnO, or In2O3 on / under the metal material. According to some exemplary embodiments, the sacrificial metal layer ML may be formed simultaneously with the pixel electrodes (i.e., the first pixel electrode 221 and the second pixel electrode 221') and may include the same material as the first pixel electrode 221 and the second pixel electrode 221'.

[0182] The first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 250 are sequentially formed on the sacrificial metal layer ML, and the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 250 are all formed integrally in the display area DA and the sensor area SA.

[0183] Next, referring to Figure 7B , laser light is irradiated from the bottom surface of the substrate 100 onto the sacrificial metal layer ML disposed in the transmission region TA. That is, the laser light may travel in the z direction from the bottom surface of the substrate 100 and may be irradiated onto the bottom surface of the sacrificial metal layer ML. The laser light may have an infrared wavelength. In the case where the laser light is infrared light, since the transmittance of the substrate 100 and the buffer layer 111 is 80% to 90% or more, the laser light can effectively reach the sacrificial metal layer ML.

[0184] Since the sacrificial metal layer ML includes an opaque metal, the sacrificial metal layer ML can absorb the laser light. Therefore, thermal expansion occurs in the sacrificial metal layer ML, and the sacrificial metal layer ML on which the laser light has been irradiated can be peeled off from the substrate 100 or the buffer layer 111.

[0185] Since a part of the sacrificial metal layer ML is peeled off, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 250 disposed on the sacrificial metal layer ML can be removed together with the sacrificial metal layer ML. Therefore, as shown in Figure 7C , a transmission hole TAH can be formed, and the transmission hole TAH includes openings of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cover layer 250.

[0186] When laser light is irradiated from above the substrate 100 in the (-)z direction to form the transmission hole TAH and the inorganic material layer, the organic material layer, the counter electrode, etc. disposed in the transmission region TA are removed, the laser processing surface may be secondarily damaged due to particles generated during the removal process. In contrast, since this embodiment uses peeling by thermal expansion of the sacrificial metal layer ML, the problem of damage caused by particles does not occur or can be reduced.

[0187] According to some example embodiments, a first metal layer BSM1 may be introduced to protect the wiring WL disposed on one side of the transmission region TA from the laser. During the process of irradiating the sacrificial metal layer ML with the laser, the optical path of a part of the laser is directed to the wiring WL.

[0188] According to some example embodiments, since the first metal layer BSM1 is introduced under the wiring WL to overlap with the wiring WL, the first metal layer BSM1 can prevent the laser from reaching the wiring WL.

[0189] In addition, according to some example embodiments, the side surface of the first metal layer BSM1 has an inverted conical shape. For example, as Figure 7B shown, the angle θ formed by the top surface of the substrate 100 and the side surface of the first metal layer BSM1 may be about 70° to about 80°. Therefore, the optical path LP of the laser directed to the wiring WL can be reflected by the side surface having an inverted conical shape. This means that although the width of the first metal layer BSM1 is not large enough, the laser can be prevented from reaching the wiring WL disposed above it. Therefore, the space occupied by the first metal layer BSM1 can be reduced.

[0190] Figure 8 is a cross-sectional view of a part of a display device according to another embodiment. In Figure 8 since the same reference numerals as those in Figure 6 denote the same elements, some repeated descriptions thereof may be omitted.

[0191] Referring to Figure 8 , the main pixels Pm are disposed in the display area DA, and the auxiliary pixels Pa and the transmission region TA are disposed in the sensor area SA. In addition, a plurality of wirings WL are disposed on one side of the transmission region TA and are located between the transmission region TA and the auxiliary pixels Pa.

[0192] The main pixel Pm may include a main thin film transistor TFT, a main storage capacitor Cst, and a main organic light emitting diode OLED. The auxiliary pixel Pa may include an auxiliary thin film transistor TFT', an auxiliary storage capacitor Cst', and an auxiliary organic light emitting diode OLED'. The transmission region TA may include a transmission hole TAH corresponding to the transmission region TA.

[0193] A first metal layer BSM1 is disposed under the wiring WL disposed on one side of the transmission region TA to overlap with the wiring WL. According to some example embodiments, the side surface of the first metal layer BSM1 may have an inverted conical shape with respect to the top surface of the substrate 100.

[0194] In addition, the second metal layer BSM2 may be disposed under the auxiliary thin film transistor TFT' of the auxiliary pixel Pa to overlap with the auxiliary thin film transistor TFT'. The third metal layer BSM3 may be disposed under the main thin film transistor TFT of the main pixel Pm to overlap with the main thin film transistor TFT. The side surfaces of the second metal layer BSM2 and / or the third metal layer BSM3 may have an inverted conical shape with respect to the top surface of the substrate 100.

[0195] The substrate 100 may include a stacked first base layer 101, a first inorganic layer 102, a second base layer 103, and a second inorganic layer 104.

[0196] According to some exemplary embodiments, the first metal layer BSM1 may be disposed between the first inorganic layer 102 and the second base layer 103. That is, the first metal layer BSM1 may be disposed on the first inorganic layer 102, and the second base layer 103 may cover the first metal layer BSM1. In this case, the second base layer 103 includes an organic material layer. The top surface of the second base layer 103 may be flat due to its characteristics. In addition, the layer disposed above the second base layer 103 may be less affected by the bending caused by the arrangement of the first metal layer BSM1.

[0197] Since the first metal layer BSM1 can be introduced to minimize the damage to the wiring WL due to the irradiation of the laser when forming the transmission hole TAH, the first metal layer BSM1 may be disposed under the wiring WL, and the position of the first metal layer BSM1 is not limited by the drawings.

[0198] For example, different from the position shown in the drawings, the first metal layer BSM1 may be disposed under the first base layer 101, between the first base layer 101 and the first inorganic layer 102, or between the second base layer 103 and the second inorganic layer 104. Various modifications can be made.

[0199] Although the second metal layer BSM2 and the third metal layer BSM3 are shown in the drawings as being disposed on the layer on which the first metal layer BSM1 is disposed, the embodiments are not limited thereto. The second metal layer BSM2 and / or the third metal layer BSM3 may be disposed on the respective layers under the buffer layer 111 and may not be disposed on the layer on which the first metal layer BSM1 is disposed.

[0200] In addition, the second metal layer BSM2 and the third metal layer BSM3 may be omitted.

[0201] Figure 9 is a cross-sectional view of a part of a display device according to another embodiment. In Figure 9 since Figure 6Like reference numerals in the accompanying drawings denote like elements, and thus some repeated descriptions thereof may be omitted.

[0202] Referring to Figure 9 , main pixels Pm are arranged in a display area DA, and auxiliary pixels Pa and a transmissive area TA are arranged in a sensor area SA. In addition, a plurality of wirings WL are arranged on one side of the transmissive area TA and are located between the transmissive area TA and the auxiliary pixels Pa.

[0203] The main pixels Pm may include main thin film transistors TFTs, main storage capacitors Cst, and main organic light emitting diodes OLEDs. The auxiliary pixels Pa may include auxiliary thin film transistors TFT's, auxiliary storage capacitors Cst', and auxiliary organic light emitting diodes OLED'. The transmissive area TA may include a transmissive hole TAH corresponding to the transmissive area TA.

[0204] A first metal layer BSM1 is arranged below the wiring WL arranged on one side of the transmissive area TA so as to overlap with the wiring WL. According to some exemplary embodiments, a side surface of the first metal layer BSM1 may have an inverted conical shape with respect to a top surface of the substrate 100.

[0205] In addition, a second metal layer BSM2 may be arranged below the auxiliary thin film transistor TFT' of the auxiliary pixel Pa so as to overlap with the auxiliary thin film transistor TFT'. A third metal layer BSM3 may be arranged below the main thin film transistor TFT of the main pixel Pm so as to overlap with the main thin film transistor TFT. A side surface of the second metal layer BSM2 and / or the third metal layer BSM3 may have an inverted conical shape with respect to a top surface of the substrate 100.

[0206] The substrate 100 may include a stacked first base layer 101, a first inorganic layer 102, a second base layer 103, and a second inorganic layer 104.

[0207] The display device according to some exemplary embodiments may further include a first additional metal layer BSM1' arranged together with the first metal layer BSM1 and an insulating layer, the insulating layer being located between the first metal layer BSM1 and the first additional metal layer BSM1', and the first additional metal layer BSM1' overlapping with the first metal layer BSM1 and the insulating layer. The first additional metal layer BSM1' may be arranged below the first base layer 101, between the first base layer 101 and the first inorganic layer 102, between the first inorganic layer 102 and the second base layer 103, between the second base layer 103 and the second inorganic layer 104, or on the second inorganic layer 104. Due to the arrangement of the first additional metal layer BSM1', the thermal diffusion of the laser can be more effectively blocked.

[0208] The second additional metal layer BSM2' may be disposed below the second metal layer BSM2, and the third additional metal layer BSM3' may be disposed below the third metal layer BSM3. The first to third additional metal layers BSM1', BSM2', and BSM3' may be electrically floated and may receive a constant voltage or an electrical signal.

[0209] Figure 10 is a cross-sectional view of a part of a display device according to another embodiment. In Figure 10 since the same reference numerals as those in Figure 6 denote the same elements, some repetitive descriptions thereof may be omitted.

[0210] Referring to Figure 10 , the main pixel Pm is disposed in the display area DA, and the auxiliary pixel Pa and the transmissive area TA are disposed in the sensor area SA. In addition, a plurality of wirings WL are disposed on one side of the transmissive area TA and are located between the transmissive area TA and the auxiliary pixel Pa.

[0211] The main pixel Pm may include a main thin film transistor TFT, a main storage capacitor Cst, and a main organic light emitting diode OLED. The auxiliary pixel Pa may include an auxiliary thin film transistor TFT', an auxiliary storage capacitor Cst', and an auxiliary organic light emitting diode OLED'. The transmissive area TA may include a transmissive hole TAH corresponding to the transmissive area TA.

[0212] The wiring WL disposed on one side of the transmissive area TA may include a first wiring WLa and a second wiring WLb that do not overlap each other. In this case, the first metal layer BSM1 may include a first sub-metal layer BSM1a and a second sub-metal layer BSM1b that are separated from each other.

[0213] The first sub-metal layer BSM1a may overlap with the second wiring WLb, and the second sub-metal layer BSM1b may overlap with the first wiring WLa. Side surfaces of the first sub-metal layer BSM1a and the second sub-metal layer BSM1b may have an inverted conical shape with respect to the top surface of the substrate 100.

[0214] Figure 11 is a cross-sectional view of a part of a display device according to another embodiment. In Figure 11 since the same reference numerals as those in Figure 6 denote the same elements, some repetitive descriptions thereof may be omitted.

[0215] Referring to Figure 11, the main pixel Pm is arranged in the display area DA, and the auxiliary pixel Pa and the transmissive area TA are arranged in the sensor area SA. In addition, a plurality of wirings WL are arranged on one side of the transmissive area TA and are located between the transmissive area TA and the auxiliary pixel Pa.

[0216] The main pixel Pm may include a main thin film transistor TFT, a main storage capacitor Cst, and a main organic light emitting diode OLED. The auxiliary pixel Pa may include an auxiliary thin film transistor TFT', an auxiliary storage capacitor Cst', and an auxiliary organic light emitting diode OLED'. The transmissive area TA may include a transmissive hole TAH corresponding to the transmissive area TA.

[0217] A first metal layer BSM1 is arranged below the wiring WL arranged on one side of the transmissive area TA to overlap with the wiring WL. According to some example embodiments, a side surface of the first metal layer BSM1 may have an inverted conical shape with respect to a top surface of the substrate 100.

[0218] In addition, a second metal layer BSM2 may be arranged below the auxiliary thin film transistor TFT' of the auxiliary pixel Pa to overlap with the auxiliary thin film transistor TFT'. A third metal layer BSM3 may be arranged below the main thin film transistor TFT of the main pixel Pm to overlap with the main thin film transistor TFT. A side surface of the second metal layer BSM2 and / or the third metal layer BSM3 may have an inverted conical shape with respect to a top surface of the substrate 100.

[0219] According to some example embodiments, the first functional layer 222a and / or the second functional layer 222c may be arranged in an area of the transmissive hole TAH. That is, the first functional layer 222a and / or the second functional layer 222c may extend from the display area DA and the sensor area SA to correspond to the transmissive hole TAH.

[0220] Such a structure can be achieved without using a sacrificial metal layer ML (see Figure 7A ) when forming the transmissive hole TAH or by arranging a sacrificial metal layer ML on the first functional layer 222a and / or the second functional layer 222c.

[0221] When irradiating a laser from a bottom surface of the substrate 100, since an area of the sacrificial metal layer ML or the counter electrode 223 irradiated with the laser is peeled off, the transmissive hole TAH is formed while removing a layer thereon.

[0222] Therefore, when the sacrificial metal layer ML is not arranged below the first functional layer 222a and / or the second functional layer 222c, the first functional layer 222a and / or the second functional layer 222c corresponding to the transmissive hole TAH may exist.

[0223] In a display device according to some example embodiments, since a pixel region and a transmissive region having an increased light transmittance are disposed in a sensor region corresponding to a component such as a sensor, an environment in which the component can operate thereunder can be ensured, while an image can be displayed in a region overlapping with the component.

[0224] Accordingly, a display device having various functions and improving quality at the same time can be provided. However, these effects are provided as examples, and the effects according to the embodiments are described in detail through the above description.

[0225] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims and their equivalents.

Claims

1. A display device, the display device comprising: a substrate, on which pixels and a transmissive region are located, the pixels including display elements; a plurality of wirings, located on the substrate, the plurality of wirings being located on one side of the transmissive region; a pixel electrode and an emission layer, both included in the pixel; a counter electrode, located on the emission layer and including an opening corresponding to the transmissive region; and a first metal layer, stacked with the plurality of wirings, the first metal layer being located below the plurality of wirings, wherein a side surface of the first metal layer has an inverted conical shape with respect to a top surface of the substrate.

2. The display device according to claim 1, the display device further comprising: a buffer layer, located on the substrate, wherein the pixel includes a thin film transistor on the buffer layer, and the first metal layer is located between the substrate and the buffer layer.

3. The display device according to claim 1, wherein, the substrate includes a first base layer, a first inorganic layer, a second base layer, and a second inorganic layer stacked in sequence.

4. The display device according to claim 3, wherein, the first metal layer is located below the first base layer, between the first base layer and the first inorganic layer, between the first inorganic layer and the second base layer, between the second base layer and the second inorganic layer, or on the second inorganic layer.

5. The display device according to claim 4, the display device further comprising: a first additional metal layer, stacked with the first metal layer and an insulating layer being located between the first additional metal layer and the first metal layer, wherein the first additional metal layer is located below the first base layer, between the first base layer and the first inorganic layer, between the first inorganic layer and the second base layer, between the second base layer and the second inorganic layer, or on the second inorganic layer.

6. The display device according to claim 1, wherein, The plurality of wirings include a first wiring and a second wiring that do not overlap with each other, and the first metal layer includes a first sub-metal layer and a second sub-metal layer, the first sub-metal layer overlapping with the first wiring, and the second sub-metal layer overlapping with the second wiring.

7. The display device according to claim 1, the display device further comprising: a second metal layer, located below the pixel.

8. The display device according to claim 7, wherein, a side surface of the second metal layer has an inverted conical shape.

9. The display device according to claim 1, the display device further comprising: a functional layer, located between the pixel electrode and the emission layer, or between the emission layer and the counter electrode, wherein a material the same as that of the functional layer is located in the transmissive region.

10. The display device according to claim 1, the display device further comprising: an inorganic insulating layer, located on the substrate, wherein the inorganic insulating layer includes a first hole corresponding to the transmissive region, and the counter electrode is located on a side wall of the first hole.

11. A display device, the display device comprising: A substrate, including a display area and a sensor area, the display area including main pixels, and the sensor area including auxiliary pixels and a transmissive area; A first pixel electrode and a first emission layer, included in the main pixels; A second pixel electrode and a second emission layer, included in the auxiliary pixels; A counter electrode, disposed integrally across the display area and the sensor area; A wiring, located on one side of the transmissive area; And A first metal layer, stacked with the wiring, the first metal layer being located below the wiring, wherein, the counter electrode includes an opening corresponding to the transmissive area.

12. The display device according to claim 11, wherein, A side surface of the first metal layer has an inverted conical shape with respect to a top surface of the substrate.

13. The display device according to claim 11, the display device further comprising: An inorganic insulating layer, located on the substrate, wherein, the inorganic insulating layer includes a first hole corresponding to the transmissive area, and The counter electrode is located on a sidewall of the first hole.

14. The display device according to claim 13, wherein, An area of the opening of the counter electrode is smaller than an area of the first hole.

15. The display device according to claim 11, the display device further comprising: A functional layer, disposed integrally in the display area and the sensor area, and disposed between the first pixel electrode and the counter electrode, wherein, the functional layer includes an opening corresponding to the transmissive area, and The opening of the counter electrode and the opening of the functional layer are overlapped with each other and constitute a transmissive hole.

16. The display device according to claim 11, the display device further comprising: A buffer layer, located above the substrate, wherein, the main pixels include thin film transistors on the buffer layer, and The first metal layer is located between the substrate and the buffer layer.

17. The display device according to claim 11, wherein, The substrate includes a first base layer, a first inorganic layer, a second base layer, and a second inorganic layer stacked in sequence.

18. The display device according to claim 17, wherein, The first metal layer is located below the first base layer, between the first base layer and the first inorganic layer, between the first inorganic layer and the second base layer, between the second base layer and the second inorganic layer, or on the second inorganic layer.

19. The display device according to claim 11, the display device further comprising: A third metal layer, located below the main pixels.

20. The display device according to claim 11, the display device further comprising: A component, located on a bottom surface of the substrate corresponding to the sensor area.

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