Display device and method for manufacturing the same

Abstract

A display device and a manufacturing method thereof are disclosed. The display device includes: in a display area, a first transistor including a first gate electrode; a second transistor electrically connected to the first transistor and including a second gate electrode; a light-emitting element; and in a peripheral area surrounding the display area, a power wiring including a first power wiring pattern and a second power wiring pattern spaced apart from each other and a bridging pattern connecting the first power wiring pattern and the second power wiring pattern; a signal wiring; and an insulating layer covering the power wiring and the signal wiring, and a part of the insulating layer is removed to form an organic layer removal area, the bridging pattern is stacked with the organic layer removal area, the power wiring and the signal wiring are stacked with each other in the organic layer removal area, and the signal wiring and the bridging pattern are respectively disposed in the same layer as the first gate electrode and the second gate electrode.

Description

Technical Field

[0001] Exemplary embodiments generally relate to a display device, and more particularly, to an organic light emitting display device and a method of manufacturing an organic light emitting display device. Background Art

[0002] An organic light emitting display device is configured to emit light by itself. Since the organic light emitting display device can reduce its weight and thickness and has characteristics suitable for a flexible display device, the use of the organic light emitting display device is increasing.

[0003] The organic light emitting display device has a display area and a peripheral area. An array of organic light emitting diodes is disposed in the display area. Signal wirings, power wirings, etc. are disposed in the peripheral area for driving the organic light emitting diodes.

[0004] In the organic light emitting display device, effectively designing a wiring structure in the peripheral area reduces a non-display area and protects the organic light emitting display device from moisture penetration.

[0005] The above information disclosed in this background art section is only for understanding the background art of the inventive concept, and thus, it may include information that does not constitute the prior art. Summary of the Invention

[0006] A device constructed according to an exemplary embodiment of the invention can provide a display device having improved reliability. A method according to an exemplary embodiment of the invention can provide a method of manufacturing the display device.

[0007] Additional features of the inventive concept will be set forth in the description below, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0008] According to one or more exemplary embodiments of the invention, a display device includes: a first transistor disposed in a display area, the first transistor including a first active pattern and a first gate electrode; a second transistor electrically connected to the first transistor, the second transistor including a second active pattern and a second gate electrode; a light-emitting element electrically connected to at least one of the first transistor and the second transistor; a power wiring disposed in a peripheral area surrounding the display area, the power wiring including a first power wiring pattern, a second power wiring pattern spaced apart from the first power wiring pattern, and a bridging pattern connecting the first power wiring pattern and the second power wiring pattern; a signal wiring disposed in the peripheral area; and an insulating layer disposed to cover the power wiring and the signal wiring, the insulating layer including an organic layer removal area in which at least a portion of the insulating layer is removed, wherein the bridging pattern overlaps with the organic layer removal area, wherein the power wiring and the signal wiring overlap with each other in the organic layer removal area, and wherein the signal wiring and the first gate electrode are disposed in the same layer, and the bridging pattern and the second gate electrode are disposed in the same layer.

[0009] The display device may further include a gate wiring pattern disposed on the first gate electrode.

[0010] The display device may further include: a first insulating layer covering the first active pattern; a second insulating layer covering the first gate electrode; a third insulating layer covering the gate wiring pattern; a fourth insulating layer covering the second gate electrode and the bridging pattern; and a first source metal pattern disposed on the fourth insulating layer and including a source electrode and a drain electrode, wherein the insulating layer may include a fifth insulating layer covering the first source metal pattern and a pixel defining layer disposed on the fifth insulating layer.

[0011] The display device may further include a dam structure disposed in the organic layer removal area.

[0012] The display device may further include a encapsulation layer covering the light-emitting element.

[0013] The display device may further include a gate insulating pattern and a dummy insulating pattern, the gate insulating pattern being disposed between the second active pattern and the second gate electrode, and the dummy insulating pattern being disposed between the bridging pattern and the third insulating layer.

[0014] The signal wiring may include a first fan-out line and a second fan-out line, the first fan-out line being disposed in the same layer as the first gate electrode, and the second fan-out line being disposed in the same layer as the gate wiring pattern.

[0015] The power wiring is configured to transmit power to the light-emitting element.

[0016] The power wiring may include a first power wiring and a second power wiring. The first power wiring is configured to transmit a first power supply voltage to a light-emitting element, and the second power wiring is configured to transmit a second power supply voltage to the light-emitting element.

[0017] The signal wiring may be configured to transmit a data signal to at least one of a first transistor and a second transistor.

[0018] The first active pattern may include silicon, and the second active pattern may include an oxide semiconductor.

[0019] The contact area of the bridging pattern and the first power wiring pattern extends along the first power wiring pattern.

[0020] According to one or more exemplary embodiments of the invention, a method for manufacturing a display device includes: forming a first active pattern in a display area; forming a first insulating layer covering the first active pattern; forming a first gate metal pattern including a first gate electrode stacked with the first active pattern; forming a second insulating layer covering the first gate metal pattern; forming a second gate metal pattern stacked with the first gate metal pattern; forming a third insulating layer covering the second gate metal pattern; forming a second active pattern on the third insulating layer; forming a third gate metal pattern, the third gate metal pattern including a second gate electrode stacked with the second active pattern and a bridging pattern disposed in a peripheral area surrounding the display area; forming a fourth insulating layer covering the third gate metal pattern; and forming a source metal pattern disposed on the fourth insulating layer, the source metal pattern including a first power wiring pattern and a second power wiring pattern spaced apart from the first power wiring pattern, wherein the first power wiring pattern and the second power wiring pattern are disposed in the peripheral area in contact with the bridging pattern.

[0021] The method may further include: forming a fifth insulating layer covering the source metal pattern; forming a pixel defining layer disposed on the fifth insulating layer; forming a light-emitting element on the fifth insulating layer and the pixel defining layer; and removing at least a part of the fifth insulating layer and the pixel defining layer in the peripheral area to form an organic layer removal area.

[0022] The remaining portions of the fifth insulating layer and the pixel defining layer after forming the organic layer removal area may include a dam structure extending along the peripheral area.

[0023] The organic layer removal area is stacked with the bridging pattern.

[0024] The first gate metal pattern may further include a first fan-out line stacked with the bridging pattern.

[0025] The second gate metal pattern may further include a second fan-out line extending parallel to the first fan-out line and stacked with the bridging pattern.

[0026] The first active pattern may include silicon, and the second active pattern may include an oxide semiconductor.

[0027] The contact area of the bridging pattern and the first power wiring pattern extends along the first power wiring pattern.

[0028] It will be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings illustrate exemplary embodiments of the invention and, together with the description, are used to explain the inventive concept, wherein the drawings are included to provide a further understanding of the invention and are incorporated into and constitute a part of this specification.

[0030] Figure 1 is a plan view showing a display device according to an exemplary embodiment.

[0031] Figure 2 is showing Figure 1 an enlarged plan view of region “A” of

[0032] Figure 3 is a cross-sectional view of a pixel unit of a display area.

[0033] Figure 4 is a cross-sectional view taken along section line I-I' of Figure 2

[0034] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B are cross-sectional views showing a method of manufacturing a display device according to an exemplary embodiment.

[0035] Figure 11 is an enlarged plan view of a peripheral area of a display device according to an exemplary embodiment.

[0036] Figure 12 is a cross-sectional view taken along section line II-II' of Figure 11 DETAILED DESCRIPTION

[0037] ​​In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words and are non-limiting examples of a device or method that employs one or more of the inventive concepts disclosed herein. However, it is apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Further, the various exemplary embodiments may be different, but need not be exclusive. For example, a particular shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0038] Unless otherwise stated, the exemplary embodiments shown are to be understood as providing exemplary features of some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0039] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless stated otherwise, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements. Further, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When an exemplary embodiment may be implemented differently, the specific process order may be performed differently from the order described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the order described. Further, like reference numerals denote like elements.

[0040] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, no intervening elements or layers are present. For this reason, the term “connected” can refer to physical, electrical, and / or fluid connections with or without intervening elements. Further, the D1 axis and the D2 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, y-axis, and z-axis), and can be interpreted in a broader sense. For example, the D1 axis and the D2 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as, by way of example, XYZ, XYY, YZ, and ZZ). As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0041] Although terms such as “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

[0042] Spatial relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “on top of,” “higher,” “side” (e.g., as in “sidewall”), etc. may be used herein for descriptive purposes to describe the relationship of one element to other elements as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as “beneath” or “below” other elements or features will then be oriented “above” the other elements or features. Thus, the exemplary term “beneath” can encompass both an orientation above and below. Further, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. Additionally, when the terms "comprises" and / or "comprising" are used in this specification, it is specified that there are the stated features, integers, steps, operations, elements, components and / or groups thereof, but there is no exclusion of the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and as such, are used to interpret the inherent deviations of measured, calculated and / or provided values that would be recognized by a person of ordinary skill in the art.

[0044] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular regions shown, but will include deviations in shapes due to, for example, manufacturing. In this manner, the regions shown in the figures may be schematic in nature and the shapes of these regions may not reflect the actual shape of the regions of the device, and as such, are not necessarily intended to be limiting.

[0045] As is the convention in the art, some exemplary embodiments are described and illustrated in the figures in terms of functional blocks, units and / or modules. Those skilled in the art will understand that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) that may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units and / or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled using software (e.g., microcode) that performs the various functions discussed herein and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit and / or module may be implemented by dedicated hardware or may be implemented as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs other functions. Additionally, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments may be physically separated into two or more interacting and discrete blocks, units and / or modules. Additionally, without departing from the scope of the inventive concept, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0047] Figure 1 is a plan view showing a display device according to an exemplary embodiment. Figure 2 is showing Figure 1 an enlarged plan view of region “A” of Figure 3 is a cross-sectional view of a pixel unit of a display area. Figure 4 is along Figure 2 a cross-sectional view taken along section line I-I' of

[0048] Referring to Figure 1 , an organic light-emitting display device may include a display area DA and a peripheral area PA surrounding the display area DA. A pixel array including a plurality of pixels PX may be disposed in the display area DA.

[0049] Wiring may be disposed in the display area DA to provide a driving signal or power to the pixels PX. For example, the wiring may include data lines DL for transmitting data signals, gate lines GL for transmitting gate signals (or scan signals), power lines PL for providing power, etc. For example, the data lines DL and the power lines PL may extend along a first direction D1, and the gate lines GL may extend along a second direction D2 intersecting the first direction D1. A pixel unit of the pixel array may include a light-emitting element for generating light and a circuit portion for driving the light-emitting element. In an exemplary embodiment, the light-emitting element may include an organic light-emitting diode, and the circuit portion may include at least two transistors.

[0050] Signal wiring, power wiring, pad electrodes, etc. may be disposed in the peripheral area PA for driving the pixels PX. For example, the signal wiring may include signal lines for transmitting driving signals to drive switching elements of the pixels PX. For example, the driving signals may include data signals, gate signals, etc. The power wiring may supply power to the light-emitting elements of the pixels PX through the power lines PL or electrodes.

[0051] In an exemplary embodiment, a fan-out wiring FL, a first power wiring VDD, a second power wiring VSS, a driver DR, and a driving signal wiring GDL may be disposed in a peripheral area PA. The fan-out wiring FL may transmit a data signal to a data line DL. The first power wiring VDD may supply a first power voltage to a pixel through a power line PL. The second power wiring VSS may supply a second power voltage to a pixel PX. The driver DR may supply a gate signal to a gate line GL. The driving signal wiring GDL may supply a driving signal to the driver DR. For example, the second power wiring VSS may be electrically connected to a second electrode of a light-emitting diode to supply the second power voltage to the light-emitting diode. In addition, additional wirings may be disposed in the peripheral area PA to transmit a light-emitting signal, a touch sensing signal, etc.

[0052] For example, a part of the peripheral area PA may be bent to be disposed at a side surface or a rear surface of the organic light-emitting display device.

[0053] Referring to Figure 1 and Figure 2 , the fan-out wiring FL, the first power wiring VDD, the second power wiring VSS, and the driving signal wiring GDL may extend toward one side of the organic light-emitting display device and may be electrically connected to a driving chip, a printed circuit board, etc. to receive signals and power from the driving chip, the printed circuit board, etc.

[0054] In an exemplary embodiment, the organic light-emitting display device may include an organic layer removal area OA disposed in the peripheral area PA. The organic layer is removed in at least a part of the organic layer removal area OA. Accordingly, moisture may be prevented or suppressed from penetrating from an edge of the organic light-emitting display device through the organic layer into a display area DA. The organic layer removed in the exemplary embodiment may include a via insulating layer, a pixel defining layer, or a combination thereof disposed under an organic light-emitting diode in the organic light-emitting display device.

[0055] In an exemplary embodiment, the organic layer removal area OA may extend along the peripheral area PA to have a shape surrounding the display area DA.

[0056] In the peripheral area PA, power wirings and signal wirings may be partially overlapped with each other. In an exemplary embodiment, in the organic layer removal area OA, at least one of the first power wiring VDD and the second power wiring VSS may be overlapped with the fan-out wiring FL.

[0057] In an exemplary embodiment, at least one of the first power wiring VDD and the second power wiring VSS may extend through a bridging member in the peripheral area PA.

[0058] For example, the first power wiring VDD may include a first power wiring pattern VDD1 and a second power wiring pattern VDD2 spaced apart from each other along a first direction D1. The first power wiring pattern VDD1 and the second power wiring pattern VDD2 may be electrically connected to each other through a first bridging pattern BP1. The second power wiring VSS may include a third power wiring pattern VSS1 and a fourth power wiring pattern VSS2 spaced apart from each other along the first direction D1. The third power wiring pattern VSS1 and the fourth power wiring pattern VSS2 may be electrically connected to each other through a second bridging pattern BP2.

[0059] In an exemplary embodiment, the first power wiring pattern VDD1 and the second power wiring pattern VDD2 may be disposed in the same layer. The first bridging pattern BP1 may be disposed in a different layer from the first power wiring pattern VDD1 and the second power wiring pattern VDD2. The third power wiring pattern VSS1 and the fourth power wiring pattern VSS2 may be disposed in the same layer. The second bridging pattern BP2 may be disposed in a different layer from the third power wiring pattern VSS1 and the fourth power wiring pattern VSS2.

[0060] The fan-out wiring FL may include a plurality of fan-out lines extending along the first direction D1 or along a perspective direction intersecting the first direction D1 in the peripheral area PA.

[0061] The organic layer removal area OA may extend along a second direction D2 in an area overlapping with the power wiring and the signal wiring.

[0062] In an exemplary embodiment, at least a part of the first bridging pattern BP1 and the second bridging pattern BP2 overlaps with the organic layer removal area OA. In addition, at least a part of the first bridging pattern BP1 and the second bridging pattern BP2 may overlap with the fan-out wiring FL. Therefore, the fan-out wiring FL, the bridging pattern, and the power wiring may be disposed in different layers and may overlap with the organic layer removal area OA.

[0063] Figure 3 and Figure 4 Cross-sections of the pixel unit and the organic layer removal area provided with the bridging pattern are respectively shown.

[0064] Referring Figure 3 , the pixel unit disposed in the display area DA includes a driving transistor based on a substrate base 100, a switching transistor for controlling the driving transistor, an organic light-emitting diode 200 electrically connected to the driving transistor, and a packaging layer 300 covering the organic light-emitting diode 200.

[0065] The buffer layer 110 may be disposed on the substrate base 100. The first active pattern AP1 may be disposed on the buffer layer 110. The first gate electrode GE1 may be disposed on the first active pattern AP1. The first insulating layer 120 may be disposed between the first active pattern AP1 and the first gate electrode GE1.

[0066] The gate wiring pattern GP may be disposed on the first gate electrode GE1. The gate wiring pattern GP may include a capacitor electrode for forming a capacitor, a wiring for transmitting a signal, etc. The second insulating layer 130 may be disposed between the first gate electrode GE1 and the gate wiring pattern GP.

[0067] The third insulating layer 140 may be disposed on the gate wiring pattern GP. The second active pattern AP2 may be disposed on the third insulating layer 140. The second gate electrode GE2 may be disposed on the second active pattern AP2. The gate insulating pattern 152 may be disposed between the second active pattern AP2 and the second gate electrode GE2.

[0068] The fourth insulating layer 160 may be disposed on the second gate electrode GE2. The first source metal pattern may be disposed on the fourth insulating layer 160. The first source metal pattern may include a first source electrode SE1 that electrically contacts the first active pattern AP1, a first drain electrode DE1 that electrically contacts the first active pattern AP1, a second source electrode SE2 that electrically contacts the second active pattern AP2, and a second drain electrode DE2 that electrically contacts the second active pattern AP2. The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may respectively pass through the insulating layers disposed therebelow to contact the active patterns.

[0069] The fifth insulating layer 170 may be disposed on the first source metal pattern. The second source metal pattern may be disposed on the fifth insulating layer 170. The second source metal pattern may include a connection electrode CE that electrically connects the first drain electrode DE1 to the organic light-emitting diode 200. In an exemplary embodiment, the second source metal pattern may further include a mesh wiring to prevent or suppress a voltage drop of the power supplied to the organic light-emitting diode 200.

[0070] The sixth insulating layer 180 may be disposed on the second source metal pattern. The organic light-emitting diode 200 may be disposed on the sixth insulating layer 180. The organic light-emitting diode 200 may include a first electrode 210, a light-emitting layer 220, and a second electrode 230. The first electrode 210 electrically contacts the connection electrode CE. The light-emitting layer 220 is disposed on the first electrode 210. The second electrode 230 is disposed on the light-emitting layer 220. At least a part of the light-emitting layer 220 may be disposed in an opening of the pixel defining layer 190 disposed on the sixth insulating layer 180.

[0071] The encapsulation layer 300 may be entirely disposed in the display area DA to cover the organic light-emitting diode 200.

[0072] For example, the encapsulation layer 300 may have a stacked structure of an organic thin film and an inorganic thin film. For example, as Figure 3 shown, the encapsulation layer 300 may include a first inorganic thin film 310, an organic thin film 320 disposed on the first inorganic thin film 310, and a second inorganic thin film 330 disposed on the organic thin film 320. However, the exemplary embodiments are not limited thereto. For example, the encapsulation layer 300 may have a structure including at least two organic thin films and at least three inorganic thin films.

[0073] Referring to Figure 4 , the fan-out wiring FL, the first bridging pattern BP1, and the dam structure DM may be disposed in the organic layer removal area OA.

[0074] The fan-out wiring FL may include a first fan-out line FL1 and a second fan-out line FL2 disposed in different layers.

[0075] For example, the first fan-out line FL1 may be formed of the same layer as the layer of the first gate electrode GE1 to be disposed on the first insulating layer 120. The second fan-out line FL2 may be formed of the same layer as the layer of the gate wiring pattern GP to be disposed on the second insulating layer 130.

[0076] In an exemplary embodiment, the first bridging pattern BP1 may be formed of a second gate electrode GE2 disposed in the display area DA. Thus, the first bridging pattern BP1 may be disposed between the third insulating layer 140 and the fourth insulating layer 160. In an exemplary embodiment, a dummy insulating pattern 154 may be disposed between the first bridging pattern BP1 and the third insulating layer 140. In an exemplary embodiment, the second bridging pattern BP2 may be formed of the same layer as the layer of the first bridging pattern BP1.

[0077] The dam structure DM may be disposed on the fourth insulating layer 160. The dam structure DM may prevent or inhibit monomers from overflowing into the peripheral area PA during the process of forming the organic thin film 320 of the encapsulation layer 300. The dam structure DM may be formed of the same layer as the layer of the fifth insulating layer 170, the sixth insulating layer 180, the pixel defining layer 190, or a combination thereof.

[0078] The dam structure DM may be disposed in the organic layer removal area OA. The dam structure DM may extend along the organic layer removal area OA to have a shape surrounding the display area DA. The dam structure DM is separated from the fifth insulating layer 170, the sixth insulating layer 180, and the pixel defining layer 190 extending from other parts of the peripheral area PA or the display area DA. Thus, the disconnection of the organic layer may be maintained.

[0079] In an exemplary embodiment, a portion of the organic thin film 320 may be disposed in the organic layer removal region OA. However, the organic thin film 320 may be excluded from the "organic layer" of the organic layer removal region OA intended by the exemplary embodiment. In addition, the organic thin film 320 may not extend to the distal end of the display device and may be separated from the organic light-emitting diode 200 by the first inorganic thin film 310. Accordingly, moisture penetration into the organic thin film 320 may be prevented or suppressed.

[0080] In an exemplary embodiment, the dam structure DM may include a plurality of structures. For example, a first dam structure and a second dam structure spaced apart from the first dam structure may be disposed in the organic layer removal region OA. However, the exemplary embodiment is not limited thereto. For example, a single dam structure or at least three dam structures may be disposed in the organic layer removal region OA as needed.

[0081] The first power wiring pattern VDD1 and the second power wiring pattern VDD2 may be disposed on the fourth insulating layer 160. The first power wiring pattern VDD1 may be spaced apart from the second power wiring pattern VDD2 along the first direction D1.

[0082] For example, each of the first power wiring pattern VDD1 and the second power wiring pattern VDD2 may penetrate the fourth insulating layer 160 to contact the first bridging pattern BP1. Accordingly, a driving signal applied to the second power wiring pattern VDD2 through a printed circuit board or a driving chip may be transmitted to the first power wiring pattern VDD1 through the first bridging pattern BP1.

[0083] In an exemplary embodiment, the first power wiring pattern VDD1 and the second power wiring pattern VDD2 may be formed of the same layer as the layer of the source electrode and the drain electrode disposed in the display area DA. Accordingly, the first power wiring pattern VDD1 and the second power wiring pattern VDD2 may be disposed in the same layer as the source electrode and the drain electrode disposed in the display area DA and may be included in the first source metal pattern.

[0084] When the power wiring is continuously formed by the first source metal pattern without the first bridging pattern BP1 in the peripheral area PA, the power wiring may be exposed in the organic layer removal region OA in the process of forming the first electrode 210 of the organic light-emitting diode 200. Accordingly, the power line PL may be damaged or undercut. Accordingly, cracks may occur in the inorganic layer of the encapsulation layer 300 formed on the power wiring in the organic layer removal region OA.

[0085] According to an exemplary embodiment, a power line PL of an organic light emitting display device continues through a bridging pattern in an organic layer removal region OA. The bridging pattern may be formed by a second gate electrode GE2 provided in a display region DA. Accordingly, even if a fifth insulating layer 170, a sixth insulating layer 180, and a pixel defining layer 190 are removed in the organic layer removal region OA, the bridging pattern may be protected by a fourth insulating layer 160. Accordingly, generation of cracks in an inorganic layer in the organic layer removal region OA may be prevented or suppressed.

[0086] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B are cross-sectional views showing a method of manufacturing a display device according to an exemplary embodiment. Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A show a pixel unit in a display region, Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B show an organic layer removal region.

[0087] Referring to Figure 5A , a semiconductor pattern 112 is formed on a substrate base 100.

[0088] The substrate base 100 may include glass, quartz, silicon, a polymer, or the like. For example, the polymer may include polyethylene terephthalate, polyethylene naphthalate, polyether ketone, polycarbonate, polyarylate, polyethersulfone, polyimide, or a combination thereof.

[0089] A buffer layer 110 may be provided between the semiconductor pattern 112 and the substrate base 100. Accordingly, the semiconductor pattern 112 may be formed on the buffer layer 110. The buffer layer 110 may prevent or reduce penetration of impurities, moisture, or external gas from below the substrate base 100, and may planarize the upper surface of the substrate base 100. For example, the buffer layer 110 may include an inorganic material (such as an oxide, a nitride, or the like). In an exemplary embodiment, the buffer layer 110 may have a multilayer structure including a lower layer containing silicon nitride and an upper layer containing silicon oxide.

[0090] For example, the semiconductor pattern 112 may include polysilicon. To form the semiconductor pattern 112, an amorphous silicon layer may be formed on the substrate base 100, and then the amorphous silicon layer may be crystallized to form a polysilicon layer.

[0091] For example, the amorphous silicon layer may be formed by sputtering, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc. The amorphous silicon layer may be crystallized by excimer laser annealing (ELA), sequential lateral solidification (SLS), etc.

[0092] For example, the polysilicon layer may be polished by chemical mechanical polishing (CMP), etc. to planarize the surface of the polysilicon layer. Thereafter, the polysilicon layer may be patterned by photolithography, etc. to form a semiconductor pattern. The semiconductor pattern may be doped with n-type impurities or p-type impurities as needed.

[0093] Thereafter, a first insulating layer 120 is formed to cover the semiconductor pattern 112. The first insulating layer 120 may insulate the channel formed by the semiconductor pattern 112 from the gate electrode formed on the first insulating layer 120.

[0094] For example, the first insulating layer 120 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the first insulating layer 120 may include insulating metal oxides (such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.). For example, the first insulating layer 120 may have a single-layer structure or a multi-layer structure including silicon nitride and / or silicon oxide.

[0095] Thereafter, a first gate metal layer is formed on the first insulating layer 120, and a first photoresist pattern is formed on the first gate metal layer.

[0096] For example, the first gate metal layer may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the first gate metal layer may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers.

[0097] Referring to Figure 5A and Figure 5B , the first photoresist pattern may include a first gate photoresist pattern GPR1 that partially overlaps with the semiconductor pattern 112 and a first fan-out photoresist pattern FPR1 disposed in the peripheral area PA.

[0098] For example, a photoresist composition including an adhesive resin (such as a phenolic resin, an acrylic resin, etc.) can be coated, exposed to light, and developed to form a first photoresist pattern.

[0099] Thereafter, the first gate metal layer is etched by using the first photoresist pattern as a mask to form a first gate metal pattern including a first gate electrode GE1 and a first fan-out line FL1. For example, the first gate metal layer can be etched by a dry etching method using plasma or the like.

[0100] Referring to Figure 6A , impurities are provided to the semiconductor pattern 112 to form a first active pattern AP1.

[0101] In an exemplary embodiment, the impurities can include p-type impurities (such as boron, etc.). However, the exemplary embodiment is not limited thereto. For example, the impurities can include n-type impurities (such as phosphorus, arsenic, etc.). For example, different regions can be doped with n-type impurities having high and low concentrations.

[0102] As a result, the peripheral portion of the semiconductor pattern 112 that does not overlap with the first gate electrode GE1 is doped with impurities to form a first doped region PD1 and a second doped region PD2. In the semiconductor pattern 112, the portion that overlaps with the first gate electrode GE1 is reserved without being doped to define a channel region CH1.

[0103] Therefore, the first doped region PD1, the second doped region PD2, and the channel region CH1 can be continuously provided in the same layer. The pattern including the first doped region PD1, the second doped region PD2, and the channel region CH1 can define a first active pattern AP1.

[0104] The first photoresist pattern including the first gate photoresist pattern GPR1 can be removed before or after the doping process.

[0105] Thereafter, a second insulating layer 130 covering the first gate metal pattern including the first gate electrode GE1 is formed. A second gate metal layer is formed on the second insulating layer 130. A second photoresist pattern is formed on the second gate metal layer.

[0106] For example, the second insulating layer 130 can include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the second insulating layer 130 can include insulating metal oxides (such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.). For example, the second insulating layer 130 can include silicon nitride.

[0107] In an exemplary embodiment, the second gate metal layer may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the second gate metal layer may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers.

[0108] Referring to Figure 6A and Figure 6B , the second photoresist pattern may include a second gate photoresist pattern GPR2 disposed in the display area DA and a second fan-out photoresist pattern FPR2 disposed in the peripheral area PA.

[0109] Thereafter, the second gate metal layer is etched by using the second photoresist pattern as a mask to form a second gate metal pattern including a gate wiring pattern GP and a second fan-out line FL2. For example, the second gate metal layer may be etched by a dry etching method using plasma or the like.

[0110] For example, the gate wiring pattern GP may include a capacitor electrode, an initialization signal wiring for providing an initialization signal, a light emission signal wiring for providing a light emission signal, etc. In an exemplary embodiment, at least a part of the gate wiring pattern GP may overlap with the first gate metal pattern.

[0111] In an exemplary embodiment, the second fan-out line FL2 may be spaced apart from the first fan-out line FL1 in the horizontal direction so as not to overlap with the first fan-out line FL1.

[0112] In an exemplary embodiment, Figure 2 the driving signal wiring GDL shown in

[0113] Referring to Figure 7A and Figure 7B , a third insulating layer 140 is formed to cover the second gate metal pattern including the gate wiring pattern GP. A second active pattern AP2 is formed on the third insulating layer 140.

[0114] For example, the third insulating layer 140 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the third insulating layer 140 may include an insulating metal oxide (such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.). For example, the third insulating layer 140 may include silicon oxide.

[0115] The second active pattern AP2 includes an oxide semiconductor. For example, the second active pattern AP2 may include a binary compound (AB x ) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), a ternary compound (AB x C y ) or a quaternary compound (AB x C y D z ). For example, the second active pattern AP2 may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZr x O y ), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium hafnium oxide (IGHO), tin aluminum zinc oxide (TAZO), indium gallium tin oxide (IGTO), etc.

[0116] Thereafter, an initial insulating layer 150 covering the second active pattern AP2 is formed. A third gate metal layer GL3 is formed on the initial insulating layer 150. A third photoresist pattern is formed on the third gate metal layer GL3.

[0117] For example, the initial insulating layer 150 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the initial insulating layer 150 may include insulating metal oxides (such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.). For example, the initial insulating layer 150 may include silicon oxide.

[0118] For example, the third gate metal layer GL3 may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the third gate metal layer GL3 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers.

[0119] The third photoresist pattern may include a third gate photoresist pattern GPR3 disposed in the display area DA and a bridging photoresist pattern BPR disposed in the peripheral area PA.

[0120] Referring to Figure 8A and Figure 8B , the third gate metal layer GL3 is etched by using the third photoresist pattern as a mask to form a third gate metal pattern including a second gate electrode GE2 and a first bridging pattern BP1. For example, the third gate metal layer GL3 can be etched by a dry etching method such as using plasma. The third gate metal pattern may further include Figure 2 the second bridging pattern BP2 shown in

[0121] The initial insulating layer 150 is etched by using the third gate metal pattern as a mask to form a gate insulating pattern 152 disposed between the second gate electrode GE2 and the second active pattern AP2. Therefore, the gate insulating pattern 152 may have substantially the same shape as the second gate electrode GE2 in a plan view.

[0122] In the process of forming the gate insulating pattern 152, a portion of the initial insulating layer 150 adjacent to the first bridging pattern BP1 may be etched, and a portion of the initial insulating layer 150 disposed below the first bridging pattern BP1 may be retained, thereby forming a dummy insulating pattern 154 disposed between the first bridging pattern BP1 and the third insulating layer 140.

[0123] In the process of forming the gate insulating pattern 152 or by an additional process, a metal element can be reduced to a metal in an exposed portion of the second active pattern AP2, thereby increasing the conductivity of the second active pattern AP2. Therefore, the exposed portion of the second active pattern AP2 can be used as an ohmic contact or a conductor.

[0124] Referring to Figure 9A and Figure 9B , a fourth insulating layer 160 covering the third gate metal pattern is formed. The fourth insulating layer 160 is patterned to form contact holes exposing the first bridging pattern BP1, the second active pattern AP2, and the doped regions PD1 and PD2 of the first active pattern AP1. In an exemplary embodiment, the contact hole exposing the first active pattern AP1 can be formed in a process different from the process of forming the contact hole exposing the second active pattern AP2. The contact hole exposing the first bridging pattern BP1 can be formed in the same process as the contact hole exposing the second active pattern AP2.

[0125] Thereafter, a first source metal layer filling the contact holes is formed. The first source metal layer is patterned to form a first source metal pattern, which includes a first source electrode SE1 in contact with a first doped region PD1 of the first active pattern AP1, a first drain electrode DE1 in contact with the second doped region PD2 and spaced apart from the first source electrode SE1, a second source electrode SE2 in contact with the second active pattern AP2, a second drain electrode DE2 in contact with the second active pattern AP2 and spaced apart from the second source electrode SE2, a first power wiring pattern VDD1 in contact with the first bridging pattern BP1, and a second power wiring pattern VDD2 in contact with the first bridging pattern BP1 and spaced apart from the first power wiring pattern VDD1. The first source metal pattern may further include a third power wiring pattern VSS1 and a fourth power wiring pattern VSS2 as shown in Figure 2 .

[0126] For example, the fourth insulating layer 160 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the fourth insulating layer 160 may include insulating metal oxides (such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.). For example, the fourth insulating layer 160 may have a multilayer structure including a lower layer containing silicon oxide and an upper layer containing silicon nitride.

[0127] For example, the first source metal layer may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the first source metal layer may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy thereof, and may have a single-layer structure or a multilayer structure including different metal layers.

[0128] Referring to Figure 10A and Figure 10B , a fifth insulating layer 170 covering the first source metal pattern is formed. The fifth insulating layer 170 is patterned to form a contact hole exposing the first drain electrode DE1. In an exemplary embodiment, the fifth insulating layer 170 may cover the first power wiring pattern VDD1 and the second power wiring pattern VDD2.

[0129] Thereafter, a second source metal layer filling the contact hole is formed, and then the second source metal layer is patterned to form a second source metal pattern including a connection electrode CE in contact with the first drain electrode DE1.

[0130] Thereafter, a sixth insulating layer 180 covering the connection electrode CE is formed. The sixth insulating layer 180 is patterned to form a contact hole exposing the connection electrode CE.

[0131] Thereafter, a first electrode layer filling the contact hole is formed, and then the first electrode layer is patterned to form a first electrode 210 of the organic light-emitting diode 200.

[0132] For example, the fifth insulating layer 170 and the sixth insulating layer 180 may include an organic insulating material (such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, silicone resin, epoxy resin, etc.). The fifth insulating layer 170 and the sixth insulating layer 180 may have a flat upper surface to planarize the upper surface of the substrate base 100.

[0133] In an exemplary embodiment, the first electrode 210 may serve as an anode. For example, the first electrode 210 may be formed as a transmissive electrode or a reflective electrode according to the emission type of the display device. When the first electrode 210 is a transmissive electrode, the first electrode 210 may include indium tin oxide, indium zinc oxide, zinc oxide tin, indium oxide, zinc oxide, tin oxide, etc. When the first electrode 210 is a reflective electrode, the first electrode 210 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or a combination thereof, and may have a stacked structure further including a material that can be used for a transmissive electrode.

[0134] A pixel defining layer 190 may be formed on the sixth insulating layer 180. The pixel defining layer 190 may include an opening exposing at least a part of the first electrode 210. For example, the pixel defining layer 190 may include an organic insulating material.

[0135] In another exemplary embodiment, the sixth insulating layer 180 and the second source metal pattern including the connection electrode CE may be omitted. Accordingly, the first electrode 210 may be brought into contact with the first drain electrode DE1, and the pixel defining layer 190 may be disposed on the fifth insulating layer 170.

[0136] In an exemplary embodiment, in a part of the peripheral area PA, the fifth insulating layer 170, the sixth insulating layer 180, and the pixel defining layer 190 including an organic material are removed to form an organic layer removal area OA. Accordingly, the fifth insulating layer 170, the sixth insulating layer 180, and the pixel defining layer 190 may include an opening corresponding to the organic layer removal area OA.

[0137] The organic layer removal area OA may overlap at least a part of each of the first bridging pattern BP1, the second bridging pattern BP2, and the fan-out wiring FL.

[0138] In an exemplary embodiment, a part of at least one of the fifth insulating layer 170, the sixth insulating layer 180, and the pixel defining layer 190 may be retained to form a dam structure DM. For the disconnection of the organic layer, the dam structure DM is spaced apart from the fifth insulating layer 170, the sixth insulating layer 180, and the pixel defining layer 190.

[0139] An emission layer 220 is formed on the first electrode 210. The emission layer 220 may include at least one layer of a hole injection layer (HIL), a hole transport layer (HTL), an organic light emitting layer, an electron transport layer (ETL), and an electron injection layer (EIL). For example, the emission layer 220 may include a low molecular weight organic compound or a high molecular weight organic compound.

[0140] In an exemplary embodiment, the emission layer 220 may emit red light, green light, or blue light. In another exemplary embodiment, the emission layer 220 may emit white light. The emission layer 220 that emits white light may have a multilayer structure including a red emission layer, a green emission layer, and a blue emission layer, or may have a single layer structure including a mixture of a red emission material, a green emission material, and a blue emission material.

[0141] For example, the emission layer 220 may be formed by a screen printing method, an inkjet printing method, a deposition method, or the like.

[0142] A second electrode 230 is formed on the emission layer 220. In an exemplary embodiment, the second electrode 230 may serve as a cathode. For example, the second electrode 230 may be formed as a transmissive electrode or a reflective electrode according to the emission type of the display device. For example, the second electrode 230 may include a metal, a metal alloy, a metal nitride, a metal fluoride, a conductive metal oxide, or a combination thereof.

[0143] For example, the second electrode 230 may continuously extend across a plurality of pixels in the display area DA. In an exemplary embodiment, a cover layer and a barrier layer may be formed on the second electrode 230.

[0144] Thereafter, as Figure 3 and Figure 4 shown, a encapsulation layer 300 may be formed on the organic light emitting diode 200. The encapsulation layer 300 may have a stacked structure of a first inorganic thin film 310, a second inorganic thin film 330, and an organic thin film 320. For example, the organic thin film 320 may include a cured polymer resin (such as poly(meth)acrylate, etc.). For example, the cured polymer resin may be formed by a crosslinking reaction of monomers. In the peripheral area PA, the overflow of the organic thin film 320 may be controlled by the dam structure DM.

[0145] For example, the inorganic thin films 310 and 330 may include silicon oxide, silicon nitride, silicon carbide, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0146] As described above, the organic layer other than the dam structure DM is removed in the organic layer removal region OA. Accordingly, the first inorganic thin film 310 of the encapsulation layer 300 may contact the fourth insulating layer 160.

[0147] In an exemplary embodiment, the organic light-emitting display device may have a front emission type in which light is emitted through the second electrode 230. However, the exemplary embodiment is not limited thereto. For example, the organic light-emitting display device may have a back emission type in which light is emitted in the opposite direction.

[0148] In an exemplary embodiment, the organic light-emitting display device includes an oxide-based semiconductor element and a silicon-based semiconductor element. In an exemplary embodiment, the silicon-based semiconductor element may be used as a driving transistor that supplies current to the organic light-emitting diode 200.

[0149] In an exemplary embodiment, the silicon-based semiconductor element may include a first active pattern AP1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0150] In an exemplary embodiment, the oxide-based semiconductor element may be used as a switching transistor to control the driving transistor. For example, the drain electrode of the oxide-based semiconductor element may be electrically connected to the gate electrode of the silicon-based semiconductor element.

[0151] In an exemplary embodiment, the oxide-based semiconductor element may have a top gate structure. For example, the oxide-based semiconductor element may include a second gate electrode GE2, a second active pattern AP2 disposed under the second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0152] The exemplary embodiment is not limited to the illustrated configuration. For example, the pixel unit of the organic light-emitting display device according to the exemplary embodiment may include at least three transistors.

[0153] Furthermore, in another exemplary embodiment, the oxide-based semiconductor element may be used as a driving transistor, and the silicon-based semiconductor element may be used as a switching transistor.

[0154] In an exemplary embodiment, the metal layer forming the bridging pattern is not limited to the gate metal layer for forming the gate electrode of the oxide-based semiconductor element. For example, when the signal line is formed of the same layer as the layer of the gate electrode of the oxide-based semiconductor element, the bridging pattern may be formed of the same layer as the layer of the gate electrode of the silicon-based semiconductor element.

[0155] Figure 11is an enlarged plan view showing a peripheral area of a display device according to an exemplary embodiment. Figure 12 is a cross-sectional view taken along the Figure 11 section line II-II'.

[0156] Figure 11 and Figure 12 The organic light-emitting display device shown in Figure 3 and Figure 4 may have a substantially same configuration as the organic light-emitting display device shown in

[0157] except for the shape of the bridging pattern and the shape of the contact area between the bridging pattern and the power wiring. Thus, any repetitive description may be omitted.

[0157] Referring to Figure 11 and Figure 12 the power wiring and the fan-out wiring FL may be disposed in the peripheral area PA.

[0158] The power wiring and the fan-out wiring FL may be partially overlapped with the organic layer removal area OA. A dam structure DM may be disposed in the organic layer removal area OA.

[0159] In the exemplary embodiment, the power wiring may include a first power wiring VDD and a second power wiring VSS. In the exemplary embodiment, the first power wiring VDD may include a first power wiring pattern VDD1 and a second power wiring pattern VDD2 which are spaced apart from each other along a first direction D1 and are electrically connected to each other through a first bridging pattern BP1. The second power wiring VSS may include a third power wiring pattern VSS1 and a fourth power wiring pattern VSS2 which are spaced apart from each other along the first direction D1 and are electrically connected to each other through a second bridging pattern BP2.

[0160] In the exemplary embodiment, the organic layer removal area OA may extend along a second direction D2 crossing the first direction D1 and may be overlapped with the first bridging pattern BP1 and the second bridging pattern BP2.

[0161] The fan-out wiring FL may include a first fan-out line FL1 and a second fan-out line FL2 disposed in different layers.

[0162] In the exemplary embodiment, the first bridging pattern BP1 and the second bridging pattern BP2 may have a shape extending along the power wiring. For example, the first bridging pattern BP1 may extend in the second direction D2 along the first power wiring VDD in the peripheral area PA. The second bridging pattern BP2 may extend in the second direction D2 along the second power wiring VSS in the peripheral area PA, or may have a shape surrounding the display area DA.

[0163] In an exemplary embodiment, the contact regions of the bridging patterns BP1 and BP2 with the power wiring pattern may extend along the regions where the bridging patterns BP1 and BP2 and the power wiring pattern overlap each other. For example, the contact region CN1 between the first bridging pattern BP1 and the first power wiring pattern VDD1 may extend along the first power wiring VDD in the second direction D2 in the peripheral region PA. The contact region CN2 between the second bridging pattern BP2 and the third power wiring pattern VSS1 may extend along the second power wiring VSS in the second direction D2 in the peripheral region PA, or may have a shape surrounding the display region DA.

[0164] Accordingly, power can be transmitted to the pixel array in the display region through the double wiring of the bridging pattern and the power wiring pattern. Since the overall resistance of the power wiring is reduced, the power consumption of the display device can be decreased, and the driving efficiency can be improved.

[0165] According to an exemplary embodiment, the power wiring extends through the bridging pattern in the organic layer removal region. Accordingly, since the signal wiring and the power wiring overlap each other, the width of the non-display region can be reduced.

[0166] In addition, the bridging pattern may be extended such that the power line can have a double wiring structure. Accordingly, the resistance of the power line can be reduced.

[0167] The exemplary embodiments can be applied to various display devices. For example, the exemplary embodiments can be applied to vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for monitors or for information transmission, medical display devices, and the like.

[0168] According to an exemplary embodiment, the power line of the display device extends through the bridging pattern in the organic layer removal region. The bridging pattern may be formed of a second gate electrode provided in the display region. Accordingly, even if the organic insulating layer located on the bridging pattern is removed in the organic layer removal region, the bridging pattern can be protected by the inorganic insulating layer. Accordingly, generation of cracks in the inorganic layer in the organic layer removal region can be prevented or reduced.

[0169] In addition, the bridging pattern may be extended such that the power line can have a double wiring structure. Accordingly, the resistance of the power line can be reduced, and the reliability of the display device can be improved.

[0170] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but rather to the claims and the broader scope of various obvious modifications and equivalent arrangements that are obvious to those of ordinary skill in the art.

Claims

1. A display device, the display device comprising: A first transistor disposed in a display area, the first transistor including a first active pattern and a first gate electrode; A second transistor electrically connected to the first transistor, the second transistor including a second active pattern and a second gate electrode; A light-emitting element electrically connected to at least one of the first transistor and the second transistor; A power wiring disposed in a peripheral area surrounding the display area, the power wiring including: a first power wiring pattern; a second power wiring pattern spaced apart from the first power wiring pattern; and a bridging pattern connecting the first power wiring pattern and the second power wiring pattern; A signal wiring disposed in the peripheral area; and An insulating layer disposed to cover the power wiring and the signal wiring, the insulating layer including an organic layer removal area, at least a portion of the insulating layer being removed in the organic layer removal area, Wherein the bridging pattern overlaps with the organic layer removal area, Wherein the power wiring and the signal wiring overlap with each other in the organic layer removal area, and Wherein the signal wiring and the first gate electrode are disposed in the same layer, and the bridging pattern and the second gate electrode are disposed in the same layer.

2. The display device according to claim 1, wherein the display device further comprises: A gate wiring pattern disposed on the first gate electrode.

3. The display device according to claim 2, the display device further comprising: A first insulating layer covering the first active pattern; A second insulating layer covering the first gate electrode; A third insulating layer covering the gate wiring pattern; A fourth insulating layer covering the second gate electrode and the bridging pattern; And A first source metal pattern disposed on the fourth insulating layer and including a source electrode and a drain electrode, Wherein the insulating layer includes: a fifth insulating layer covering the first source metal pattern; and a pixel defining layer disposed on the fifth insulating layer.

4. The display device according to claim 3, wherein the display device further comprises: A dam structure disposed in the organic layer removal area.

5. The display device according to claim 1, the display device further comprising a packaging layer covering the light-emitting element.

6. The display device according to claim 3, the display device further comprising: A gate insulating pattern disposed between the second active pattern and the second gate electrode; And A dummy insulating pattern disposed between the bridging pattern and the third insulating layer.

7. The display device according to claim 2, wherein, The signal wiring includes a first fan-out line and a second fan-out line, the first fan-out line and the first gate electrode being disposed in the same layer, and the second fan-out line and the gate wiring pattern being disposed in the same layer.

8. The display device according to claim 1, wherein, The power wiring is configured to transmit power to the light-emitting element.

9. The display device according to claim 8, wherein, The power wiring includes: A first power wiring configured to transmit a first power supply voltage to the light-emitting element; and A second power wiring configured to transmit a second power supply voltage to the light-emitting element.

10. The display device according to claim 1, wherein, The signal wiring is configured to transmit a data signal to at least one of the first transistor and the second transistor.

11. The display device according to claim 1, wherein, The first active pattern includes silicon, and wherein the second active pattern includes an oxide semiconductor.

12. The display device according to claim 1, wherein, The contact area of the bridging pattern and the first power wiring pattern extends along the first power wiring pattern.

13. A method for manufacturing a display device, the method comprising: forming a first active pattern in a display area; forming a first insulating layer covering the first active pattern; forming a first gate metal pattern including a first gate electrode overlapping the first active pattern; forming a second insulating layer covering the first gate metal pattern; forming a second gate metal pattern overlapping the first gate metal pattern; forming a third insulating layer covering the second gate metal pattern; forming a second active pattern on the third insulating layer; forming a third gate metal pattern including: a second gate electrode overlapping the second active pattern; and a bridging pattern disposed in a peripheral area surrounding the display area, the bridging pattern being disposed in the same layer as the second gate electrode; forming a fourth insulating layer covering the third gate metal pattern; and forming a source metal pattern disposed on the fourth insulating layer, the source metal pattern including: a first power wiring pattern; and a second power wiring pattern spaced apart from the first power wiring pattern, wherein the first power wiring pattern and the second power wiring pattern are disposed in contact with the bridging pattern in the peripheral area, and the first power wiring pattern and the second power wiring pattern are connected to each other through the bridging pattern.

14. The method according to claim 13, the method further comprising: forming a fifth insulating layer covering the source metal pattern; forming a pixel defining layer disposed on the fifth insulating layer; forming a light emitting element on the fifth insulating layer and the pixel defining layer; and removing at least a part of the fifth insulating layer and the pixel defining layer in the peripheral area to form an organic layer removal area.

15. The method according to claim 14, wherein The remaining portions of the fifth insulating layer and the pixel defining layer after forming the organic layer removal area include a dam structure extending along the peripheral area.

16. The method according to claim 14, wherein The organic layer removal area overlaps the bridging pattern.

17. The method according to claim 14, wherein The first gate metal pattern further includes a first fan-out line overlapping the bridging pattern.

18. The method according to claim 17, wherein, The second gate metal pattern further includes a second fan-out line extending parallel to the first fan-out line and overlapping the bridging pattern.

19. The method according to claim 13, wherein The first active pattern includes silicon, and wherein the second active pattern includes an oxide semiconductor.

20. The method according to claim 13, wherein The contact area of the bridging pattern and the first power wiring pattern extends along the first power wiring pattern.

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