Fingerprint sensor and display device including the same

Abstract

According to an aspect of the invention, there is provided a fingerprint sensor for a display device and a display device including the fingerprint sensor. The fingerprint sensor includes: a substrate having a first surface and a second surface; a light-transmitting layer including a first layer and a second layer. The first layer includes at least one first conductive layer and is disposed on the first surface of the substrate and has a first opening in the at least one first conductive layer. The second layer includes at least one second conductive layer and is disposed on the first surface of the substrate and has a second opening in the at least one second conductive layer; a light-emitting element layer disposed on the first layer and the second layer and having at least one light-emitting element; and a sensor layer disposed on the second surface of the substrate and having a light sensor, wherein at least a part of the first opening and at least a part of the second opening are at least partially superimposed and have different sizes.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0062650, filed on May 28, 2019, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0002] The invention generally relates to an electronic device, and more particularly, to a fingerprint sensor and a display device including the fingerprint sensor. Background Art

[0003] In recent years, as display devices such as smart phones or tablet PCs have been widely used, biometric authentication methods using a user's fingerprint have also been widely used. To provide a fingerprint sensing function, a fingerprint sensor may be provided in a form embedded in or attached to a display device.

[0004] For example, a fingerprint sensor may form a sensor of a light sensing method. The fingerprint sensor may include a light source, a lens, and a light sensor array. Reflected light within the display device may be noise that interferes with the light sensor array. When such a fingerprint sensor is attached to a display panel together with a remedy for reducing light noise, the thickness and manufacturing cost of the display device increase.

[0005] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus, it may include information that does not constitute the prior art. Summary of the Invention

[0006] A fingerprint sensor and a display device including the fingerprint sensor constructed according to the principles and exemplary embodiments of the invention use a light sensing method capable of reducing the thickness of a module and improving reliability. For example, the module thickness of the display device may be reduced by integrally forming a light transmissive region with a circuit element layer in the fingerprint sensor.

[0007] In addition, a fingerprint sensor and a display device including the fingerprint sensor constructed according to the principles and exemplary embodiments of the invention may prevent or reduce moiré effects that may occur in the fingerprint sensor by adjusting the resolution between an opening portion of a light shielding layer and a light sensor provided in a sensor layer.

[0008] Additional features of the inventive concept will be set forth in the following description, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0009] According to one aspect of the invention, a fingerprint sensor for a display device includes: a substrate having a first surface and a second surface; a light-transmissive layer including a first layer and a second layer, the first layer including at least one first conductive layer and disposed on the first surface of the substrate and having a first opening in the at least one first conductive layer, the second layer including at least one second conductive layer and disposed on the first surface of the substrate and having a second opening in the at least one second conductive layer; a light-emitting element layer disposed on the first layer and the second layer and having at least one light-emitting element; and a sensor layer disposed on the second surface of the substrate and having a light sensor, wherein at least a part of the first opening and at least a part of the second opening are at least partially overlapped and have different sizes.

[0010] The first opening and the second opening may have a width or diameter between about 5 μm and about 20 μm.

[0011] The first opening and the second opening may have a substantially quadrilateral shape, wherein the width in a first direction and the width in a second direction perpendicular to the first direction are the same or different.

[0012] The width of the first opening may be larger than the width of the second opening.

[0013] The first layer may have a first light-shielding layer to block some of the ambient incident light and allow the remaining ambient incident light to transmit through the first opening, and the second layer may have a second light-shielding layer to limit the field of view of the ambient incident light.

[0014] The second layer may include circuit elements to control the light emission of the at least one light-emitting element.

[0015] The second layer may have: a semiconductor layer including an active pattern of the circuit elements; a first gate layer including a gate electrode overlapping the active pattern; and a source-drain layer including a source electrode and a drain electrode connected to the active pattern.

[0016] The second layer may further include a second gate layer disposed between the first gate layer and the source-drain layer and including at least one capacitor electrode.

[0017] The second opening may have a multi-layer opening portion that overlaps each other between the circuit elements disposed in the semiconductor layer, the first gate layer, the second gate layer, and the source-drain layer.

[0018] The distance between the semiconductor layer and the source-drain layer may be about 300 μm or less.

[0019] The first gate layer may include a light emission control line to supply a light emission control signal to a circuit element, the second gate layer may include an initialization power supply line to supply an initialization power supply to the circuit element, and the source-drain layer may include a power supply line to apply power to the circuit element.

[0020] The second opening may include a multi-layer opening adjacent to and overlapping with the active pattern, the light emission control line, the initialization power supply line, and the power supply line.

[0021] The fingerprint sensor may further include: a protective layer disposed between the substrate and the sensor layer; and an adhesive layer disposed between the substrate and the protective layer.

[0022] According to another aspect of the invention, a display device includes: a substrate having a first surface and a second surface; a light-transmitting layer disposed on the first surface of the substrate and including a first opening having a first size; a circuit element layer disposed on the first surface of the substrate and including a plurality of conductive layers and a second opening located in the plurality of conductive layers, the second opening having at least a part overlapping with the first opening and having a second size different from the first size; a light-emitting element layer disposed on the circuit element layer and including at least one light-emitting element; and a sensor layer disposed on the second surface of the substrate and including a light sensor.

[0023] The first opening and the second opening may have a width or diameter between about 5 μm and about 20 μm.

[0024] The first size may have a first width, the second size may have a second width, and the first width is greater than the second width.

[0025] The light-transmitting layer may have: a light-shielding layer that blocks some of the ambient incident light and allows the remaining ambient incident light to pass through the first opening; and a circuit element layer that restricts the field of view of the ambient incident light.

[0026] The circuit element layer may include circuit elements to control the light emission of the at least one light-emitting element.

[0027] The circuit element layer may have: a semiconductor layer including an active pattern of the circuit element; a first gate layer including a gate electrode overlapping with the active pattern; a second gate layer disposed on the first gate layer and including at least one capacitor electrode; and a source-drain layer disposed on the second gate layer and including a source electrode and a drain electrode connected to the active pattern.

[0028] The distance between the semiconductor layer and the source-drain layer may be about 300 μm or less.

[0029] It will be understood that the foregoing general description and the following detailed description are both exemplary and explanatory and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings illustrate exemplary embodiments of the invention and, together with the description, are used to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are part of this specification and form a part of this specification.

[0031] The above and other features of the invention will become more apparent by describing in more detail the exemplary embodiments of the invention with reference to the drawings, in which:

[0032] Figure 1 and Figure 2 are block diagrams showing exemplary embodiments of a display device constructed in accordance with the principles of the invention;

[0033] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E are plan views of exemplary embodiments of a pixel and a light sensor constructed in accordance with the principles of the invention, showing the relative arrangement of the pixel and the light sensor;

[0034] Figure 4A is a cross-sectional view of an exemplary embodiment of a display device constructed in accordance with the principles of the invention;

[0035] Figure 4B is a cross-sectional view of another exemplary embodiment of a display device constructed in accordance with the principles of the invention;

[0036] Figure 5 is a plan view showing an exemplary embodiment of a light-shielding layer constructed in accordance with the principles of the invention;

[0037] Figure 6A , Figure 6B , Figure 6C and Figure 6D are plan views of exemplary embodiments of a pixel, a pinhole, and a light sensor constructed in accordance with the principles of the invention, showing the relative arrangement of the pixel, the pinhole, and the light sensor;

[0038] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B and Figure 12C are cross-sectional views of other exemplary embodiments of a display device constructed in accordance with the principles of the invention;

[0039] Figure 13 is a circuit diagram showing an exemplary embodiment of a representative pixel;

[0040] Figure 14is a circuit diagram showing another exemplary embodiment of a representative pixel;

[0041] Figure 15 is a plan view showing an exemplary embodiment of the layout of the pixel shown in Figure 14 ;

[0042] Figure 16 is a cross-sectional view taken along line I-I’ of Figure 15 ; and

[0043] Figure 17 is a cross-sectional view taken along line II-II’ of Figure 15 . DETAILED DESCRIPTION

[0044] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable terms and are non-limiting examples of a device or method that employs one or more of the inventive concepts disclosed herein. However, it is apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Additionally, the various exemplary embodiments may be different but not necessarily exclusive. For example, without departing from the inventive concept, the specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0045] Unless otherwise specified, the exemplary embodiments shown are understood to provide exemplary features of various details in which the inventive concept may be practiced in practice. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be additionally combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0046] Cross - hatching and / or shading are typically provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless stated otherwise, the presence or absence of cross - hatching or shading does not convey or imply any preference or requirement for a specific material, material properties, dimensions, ratios, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. Additionally, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When an exemplary embodiment can be implemented differently, the specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Also, the same reference numerals denote the same elements.

[0047] When an element or layer is referred to as "on", "disposed on", "connected to", or "coupled to" another element or layer, the element or layer can be directly on the other element or layer, directly connected to or directly coupled to the other element or layer, or there can be intervening elements or intervening layers. However, when an element or layer is referred to as "directly on", "directly disposed on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or intervening layers. For this reason, the term "connected" can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements. Further, the D1 - axis, D2 - axis, and D3 - axis are not limited to the three axes of a rectangular coordinate system (such as the x - axis, y - axis, and z - axis) and can be interpreted in a broader sense. For example, the D1 - axis, D2 - axis, and D3 - axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0048] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of the disclosure, the first element discussed below may be referred to as the second element.

[0049] For purposes of description, spatial relative terms, such as "under", "below", "beneath", "lower", "above", "upper", "on top of", "higher", "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (other) element as shown in the figures. The spatial relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "under" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary term "under" can cover both an upper and a lower orientation. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatial relative descriptors used herein are to be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. Additionally, when the terms "comprises" and / or "comprising" are used in this specification, it is specified that there are the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and are thus used to interpret the inherent deviations of measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0051] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the particular shapes shown in the regions, but will include deviations in shapes due to, for example, manufacturing. In this manner, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shape of the regions of the device, and are thus not necessarily intended to be limiting.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in a general dictionary shall be interpreted to have a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0053] As used herein, the "light-transmitting layer" may be abbreviated as "LTL" and refers to a layer including one or more light-transmitting hole array layers (LTHL) and / or one or more light-blocking layers (PHL) as described herein. Exemplary embodiments of the light-transmitting layer may include a single layer (such as a light-transmitting hole array layer (LTHL) or a circuit element layer (BPL)) or multiple layers (such as BPL, a first substrate (SUB1), and PHL).

[0054] As used herein, when the terms "width" and "diameter" are used with respect to generally circular openings (e.g., a pinhole (PIH), a first light-transmitting hole (LTH1), a second light-transmitting hole (LTH2), and a multi-layer opening portion (MLO)), the terms "width" and "diameter" may be used interchangeably.

[0055] Hereinafter, exemplary embodiments of the invention will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

[0056] Figure 1 and Figure 2 are block diagrams showing exemplary embodiments of a display device constructed according to the principles of the invention. More specifically, Figure 1 and Figure 2 are diagrams schematically showing a display panel and a driving circuit for driving the display panel included in a display device according to an embodiment. For convenience, in Figure 1 and Figure 2 the display panel and the driving circuit are shown separated from each other, but the exemplary embodiments of the invention are not limited thereto. More specifically, all or part of the driving circuit may be integrally implemented on the display panel.

[0057] Referring to Figure 1 and Figure 2 , the display device 10 includes a display panel 110 and a driving circuit 200 for driving the display panel 110.

[0058] The display panel 110 includes a display area AA and a non-display area NA. The display area AA is an area where a plurality of pixels PXL (which may be referred to as sub-pixels) are provided, and may be referred to as an active area. In various embodiments, each of the pixels PXL may include at least one light-emitting element. The display device 10 displays an image on the display area AA by driving the pixels PXL corresponding to externally input image data.

[0059] In various exemplary embodiments of the invention, the display area AA may include a sensing area SA. The sensing area SA may include at least some of the pixels PXL provided in the pixels PXL in the display area AA.

[0060] In an embodiment, as Figure 1 shown, at least a part of the display area AA may be set as the sensing area SA. In another example, as Figure 2 shown, the entire display area AA may be set as the sensing area SA.

[0061] Although Figure 1 an example is shown in which only one sensing area SA is formed on the display area AA, the exemplary embodiments of the invention are not limited thereto. That is, in various embodiments, a plurality of regularly or irregularly arranged sensing areas SA may be formed on the display area AA. In such an embodiment, the plurality of sensing areas SA may have the same or different areas and shapes.

[0062] In addition, although Figure 1 an example is shown in which the sensing area SA is formed in at least a part of the display area AA, the exemplary embodiments of the invention are not limited thereto. That is, in various embodiments, the display area AA and the sensing area SA may be set such that only a part of the display area AA overlaps with the sensing area SA.

[0063] The non-display area NA is an area provided around the display area AA, and may be referred to as a non-active area. In various embodiments, the non-display area NA refers to an area on the display panel 110 other than the display area AA. In an embodiment, the non-display area NA may include a wiring area, a pad (or referred to as a "bond pad" or "landing pad") area, various dummy areas, and the like.

[0064] In various exemplary embodiments of the invention, the display device 10 may further include a plurality of optical sensors PHS disposed in the sensing area SA. In an embodiment, the optical sensor PHS may sense light reflected by a user's finger from a light source and analyze the reflected light to sense the user's fingerprint. Hereinafter, exemplary embodiments of the invention will be described by using an example in which the optical sensor PHS is used for fingerprint sensing purposes, but in various embodiments, the optical sensor PHS may be used for purposes of performing various functions such as a touch sensor or a scanner.

[0065] In various exemplary embodiments of the invention, the optical sensor PHS may be disposed in the sensing area SA. The optical sensor PHS may be stacked with at least a part or all of the pixels PXL disposed in the sensing area SA, or may be disposed around the pixels PXL. For example, at least some or all of the optical sensors PHS may be disposed between the pixels PXL. Various embodiments of the positional relationship between the optical sensor PHS and the pixels PXL will be described in more detail with reference to Figures 3A to 3E More detailed descriptions will be given of various embodiments of the positional relationship between the optical sensor PHS and the pixels PXL.

[0066] In an embodiment in which the optical sensor PHS is disposed adjacent to the pixels PXL, the optical sensor PHS may use a light-emitting element disposed in at least one pixel PXL as a light source, and the at least one pixel PXL is disposed at or around the sensing area SA. In such an embodiment, the optical sensor PHS and the pixels PXL of the sensing area SA (specifically, the light-emitting element disposed in the pixels PXL) may together form a fingerprint sensor used in a light sensing method. As described above, when the fingerprint sensor of the built-in display device uses the pixels PXL as a light source without a separate external light source, the module thickness of the fingerprint sensor and the display device including the fingerprint sensor can be reduced, and the manufacturing cost can be lowered.

[0067] In various embodiments, the optical sensor PHS may be disposed on the rear surface (e.g., the back surface) of the two surfaces of the display panel 110 that faces away from the surface (e.g., the front surface) on which the display image is displayed. However, the exemplary embodiments of the invention are not limited thereto.

[0068] The driving circuit 200 may drive the display panel 110. For example, the driving circuit 200 may output a data signal corresponding to image data to the display panel 110, or may output a driving signal for the optical sensor PHS and receive a sensing signal received from the optical sensor PHS. The driving circuit 200 that receives the sensing signal may use the sensing signal to detect the form of the user's fingerprint.

[0069] In various exemplary embodiments of the invention, the driving circuit 200 may include a panel driver 210 and a fingerprint detector 220. For convenience, in Figure 1 andFigure 2 In this case, the panel driver 210 and the fingerprint detector 220 are separated from each other, but exemplary embodiments of the invention are not limited thereto. For example, at least a part of the fingerprint detector 220 may be integrated with the panel driver 210 or may operate in combination with the panel driver 210.

[0070] The panel driver 210 may sequentially supply data signals corresponding to image data to the pixels PXL while sequentially scanning the pixels PXL in the display area AA. Then, the display panel 110 may display an image corresponding to the image data.

[0071] In an embodiment, the panel driver 210 may supply a driving signal for fingerprint sensing to the pixel PXL. A driving signal may be provided such that the pixel PXL emits light and serves as a light source for the photosensor PHS. In such an embodiment, the driving signal for fingerprint sensing may be provided to the pixels PXL disposed in a specific area within the display panel 110, for example, the pixels PXL disposed in the sensing area SA. In various embodiments, the driving signal for fingerprint sensing may be provided by the fingerprint detector 220.

[0072] The fingerprint detector 220 may transfer a driving signal for driving the photosensor PHS to the photosensor PHS, and may detect a user fingerprint based on the sensing signal received from the photosensor PHS.

[0073] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E are plan views of exemplary embodiments of pixels and photosensors constructed according to the principles of the invention, showing the relative arrangements of the pixels and photosensors. Figures 3A to 3E show different embodiments regarding the relative sizes, resolutions, and positional relationships between at least one pixel PXL and the photosensor PHS disposed in the sensing area SA.

[0074] Referring to Figure 3A , in the sensing area SA, the photosensor PHS may be disposed at the same resolution (density) as the resolution (density) of the pixels PXL. In other words, the same number of photosensors PHS as the number of pixels PXL may be disposed in the sensing area SA. In such an embodiment, the pixels PXL and the photosensors PHS may be arranged to form a 1:1 pair. In Figure 3A embodiments, the pixels PXL and the photosensors PHS are disposed to overlap each other, but in other embodiments, the pixels PXL and the photosensors PHS may be disposed not to overlap each other or only a part of the pixels PXL and the photosensors PHS may overlap each other.

[0075] InFigure 3A In an embodiment, the optical sensor PHS has a size smaller than that of the pixel PXL, but the exemplary embodiments of the invention are not limited thereto. That is, in other embodiments, the optical sensor PHS may have the same size as that of the pixel PXL or may have a size larger than that of the pixel PXL. Such an embodiment is shown in Figure 3C below.

[0076] Referring to Figures 3B to 3E , the optical sensor PHS may be set at a lower resolution than that of the pixel PXL in the sensing area SA. In other words, the number of optical sensors PHS may be smaller than the number of pixels PXL that can be set in the sensing area SA. In Figures 3B to 3E , an example is shown in which one optical sensor PHS is set for every four pixels PXL, but the exemplary embodiments of the invention are not limited thereto.

[0077] In such an embodiment, as shown in Figure 3B and Figure 3E , the optical sensor PHS may have a size smaller than that of the pixel PXL, or as shown in Figure 3C and Figure 3D , the optical sensor PHS may have a size larger than that of the pixel PXL.

[0078] When the optical sensor PHS is set at a lower resolution than that of the pixel PXL, part or all of the optical sensor PHS may be set to overlap with the pixel PXL. That is, as shown in Figure 3B and Figure 3C , the optical sensor PHS may partially overlap with a part of the pixel PXL.

[0079] Optionally, as shown in Figure 3D , the optical sensor PHS may be set between the pixels PXL and partially overlap with the pixel PXL. In such an embodiment, as shown in Figure 3D , the optical sensor PHS may have a size larger than that of the pixel PXL. For example, the optical sensor PHS may have a large enough size to cover at least one pixel PXL.

[0080] Optionally, as shown in Figure 3E , the optical sensor PHS may not overlap with the pixel PXL.

[0081] In various exemplary embodiments of the invention, the relative position between the pixel PXL and the optical sensor PHS is not limited to the above structure. That is, various modifications can be made to the shape, arrangement, relative size, number, resolution, etc. of the pixels PXL and the optical sensor PHS in the sensing area SA. In addition, in various embodiments, the pixels PXL and the optical sensor PHS may be arranged in a manner in which Figures 3A to 3Econfigured in the form of one or more combinations in the embodiments.

[0082] In addition, Figures 3A to 3E An example is shown in which the optical sensors PHS are regularly arranged in the sensing area SA. However, the exemplary embodiments of the invention are not limited thereto. In other embodiments, the optical sensors PHS may be irregularly arranged in the sensing area SA.

[0083] Figure 4A is a cross-sectional view of an exemplary embodiment of a display device according to an embodiment.

[0084] Referring to Figure 4A , a display device 10 according to an exemplary embodiment of the invention may include a display panel 110 and a sensor layer PSL disposed on one surface of the display panel 110. In addition, the display device 10 may include a first substrate SUB1 and a circuit element layer BPL, a light-emitting element layer LDL, a first protective layer PTL1, a first adhesive layer ADL1, and a window WIN sequentially disposed on one surface (e.g., the upper surface) of the first substrate SUB1. In addition, the display device 10 may further include a second adhesive layer ADL2 and a second protective layer PTL2 sequentially disposed on the other surface (e.g., the lower surface) of the first substrate SUB1.

[0085] The first substrate SUB1 may serve as a base substrate for the display panel 110 and may be a substantially transparent transmissive substrate. The first substrate SUB1 may be a rigid substrate including glass or tempered glass or a flexible substrate of a plastic material. However, the material of the first substrate SUB1 is not limited thereto, and the first substrate SUB1 may be made of various materials.

[0086] The first substrate SUB1 may include a display area AA and a non-display area NA as shown in Figure 1 and Figure 2 . In addition, the display area AA may include a plurality of pixel areas PXA in which each pixel PXL is disposed and / or formed.

[0087] The circuit element layer BPL can be disposed on one surface of the first substrate SUB1 and includes at least one conductive layer. For example, the circuit element layer BPL can include a plurality of circuit elements forming a pixel circuit of the pixel PXL and wirings for supplying various electric powers and signals for driving the pixel PXL. In this case, the circuit element layer BPL can include various circuit elements such as at least one transistor and capacitor, and a plurality of conductive layers for constructing wirings connected to various circuit elements. Further, the circuit element layer BPL can include at least one insulating layer disposed between the plurality of conductive layers. Further, the circuit element layer BPL can include a wiring portion that is disposed in the non-display area NA of the first substrate SUB1 and supplies electric power and signals corresponding to the wirings connected to the pixel PXL.

[0088] The light-emitting element layer LDL can be disposed on one surface of the circuit element layer BPL. The light-emitting element layer LDL can include a plurality of light-emitting elements LD connected to the circuit elements and / or wirings of the circuit element layer BPL through contact holes or the like. In an embodiment, at least one of the plurality of light-emitting elements LD can be disposed in each pixel area PXA.

[0089] Each of the pixels PXL can include a circuit element disposed in the circuit element layer BPL and at least one light-emitting element LD in the light-emitting element layer LDL disposed above the circuit element layer BPL. A detailed description of a representative structure of the pixel PXL will be described below.

[0090] The first protective layer PTL1 can be disposed above the light-emitting element layer LDL to cover the display area AA. The first protective layer PTL1 can include a sealing member such as a thin film encapsulation ("TFE") or a sealing substrate, and can further include a protective film or the like in addition to the sealing member.

[0091] The first adhesive layer ADL1 is disposed between the first protective layer PTL1 and the window WIN to bond the first protective layer PTL1 and the window WIN. The first adhesive layer ADL1 can include a transparent adhesive such as an optically clear adhesive ("OCA"), and can include various adhesive materials.

[0092] The window WIN is a protective member disposed at the uppermost end of the module of the display device 10 including the display panel 110, and can be a substantially transparent transmissive substrate. The window WIN can have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The window WIN can include a rigid substrate or a flexible substrate, and the construction material of the window WIN is not particularly limited.

[0093] In various exemplary embodiments of the invention, the display device 10 may further include a polarizing plate and / or a touch sensor layer (touch electrode layer), etc. For example, the display device 10 may further include a polarizing plate and / or a touch sensor layer disposed between the first protective layer PTL1 and the window WIN.

[0094] The second protective layer PTL2 may be disposed on the other surface of the first substrate SUB1. The second protective layer PTL2 may be bonded to the first substrate SUB1 through the second adhesive layer ADL2.

[0095] The second adhesive layer ADL2 may firmly bond (or attach) the first substrate SUB1 and the second protective layer PTL2. The second adhesive layer ADL2 may include a transparent adhesive such as OCA. The second adhesive layer ADL2 may include a pressure-sensitive adhesive (“PSA”) in which the adhesive material functions when pressure for bonding to the bonding surface is applied. When the second adhesive layer ADL2 includes PSA, the second adhesive layer ADL2 may be bonded to the bonding surface only by pressure at room temperature without an additional heating process or UV process.

[0096] In an embodiment, the second adhesive layer ADL2 may include a material that absorbs specific light, or may include a material that blocks specific light. For example, the second adhesive layer ADL2 may include an infrared light absorbing material that absorbs infrared light having a high energy density, or may include an infrared light blocking material that blocks infrared light.

[0097] The infrared light absorbing material may include, for example, inorganic oxides such as antimony tin oxide (“ATO”), indium tin oxide (“ITO”), tungsten oxide, carbon black, etc., and metals such as silver (Ag). In the case of inorganic oxides, the infrared light absorbing material may selectively transmit light in the visible light region and absorb infrared light. In addition, the infrared light absorbing material may include, for example, organic dyes. The organic dyes may be, for example, dyes used in color filters included in the display panel 110.

[0098] For example, the infrared light blocking material may be at least one selected from borate (ester) mixtures, carbonate (ester) mixtures, alumina mixtures, nitrate (ester) mixtures, nitrite (ester) mixtures. For example, the infrared light blocking material may be selected from lithium borate, potassium borate, magnesium borate, calcium borate, strontium borate, barium borate, sodium borate (e.g., Na2B4O x) at least one of ulexite, lithium carbonate, sodium carbonate, potassium carbonate, calcium carbonate (e.g., calcite), dolomite, and magnesite. In addition, the infrared light blocking material may be at least one selected from a nickel dithiol system, a metal coordination compound of dithiol, a cyanine dye, a squalium dye, a croconic acid dye, a diimonium dye, an aminium (organic ammonium) dye, an ammonium (inorganic ammonium) dye, a phthalocyanine dye, naphthalocyanine, an anthraquinone dye, a naphthoquinone dye, a polymer condensation azopyrrole dye (pyrrole azo dye), a polymethine dye, and an acrylate dye.

[0099] When the user's hand is placed on (or located at) the display surface of the display device 10 (e.g., a surface on which an image is displayed), the display device 10 can perform the function of sensing the user's fingerprint through the photosensor PHS described below. When external light is input into the display device 10 while sensing the user's fingerprint, the visible light region of the external light is blocked by the user's hand, but the infrared light will transmit through the user's hand and will be incident on the photosensor PHS. The infrared light incident on the photosensor PHS acts as noise and will reduce the recognition accuracy of the light reflected by the user's hand.

[0100] When the second adhesive layer ADL2 includes an infrared light absorbing material and / or an infrared light blocking material as in the above embodiments, even if the infrared light of the external light transmits through the user's hand, the infrared light is absorbed and / or blocked by the second adhesive layer ADL2, so the infrared light is not incident on the photosensor PHS. Therefore, the fingerprint recognition accuracy can be improved.

[0101] The second protective layer PTL2 can block oxygen and moisture from flowing in from the outside and can be provided in a single layer or multiple layers. The second protective layer PTL2 can be formed into a film to further ensure the flexibility of the display panel 110. The second protective layer PTL2 can be bonded to the sensor layer PSL through another adhesive layer including a transparent adhesive such as OCA.

[0102] In various embodiments, a selective light blocking film may be further provided under the second protective layer PTL2. The selective light blocking film can prevent light from entering the photosensor PHS of the sensor layer PSL by blocking a specific frequency region (e.g., infrared light) of the external light incident on the display device 10. In the above description, the selective light blocking film is further provided under the second protective layer PTL2, but the exemplary embodiments of the invention are not limited thereto. That is, in another embodiment, when the selective light blocking film is provided above the sensor layer PSL, the selective light blocking film can be provided as any layer of the display device 10. In addition, when the display panel 110 includes an infrared light blocking component, the selective light blocking film can be omitted.

[0103] The light-shielding layer PHL can be disposed between the light-emitting element layer LDL and the sensor layer PSL described below. For example, as shown in Figure 4A , the light-shielding layer PHL can be disposed between the first substrate SUB1 and the circuit element layer BPL. The light-shielding layer PHL can include a plurality of pinholes PIH.

[0104] The display panel 110 can be formed to be transparent in the region where the pinholes PIH are provided, so that the reflected light reflected from the fingerprint region of the finger can pass through the pinholes PIH. In addition, in order to reduce the loss of the reflected light necessary for fingerprint sensing, the display panel 110 can be formed such that light within a predetermined angular range of the field of view (“FOV”, or also referred to as “viewing angle”) passes through each pinhole PIH.

[0105] For example, in an area having an area larger than the area of the pinhole PIH and overlapping with the pinhole PIH with the area where each pinhole PIH is provided as the center, the display panel 110 can be formed to be transparent. Hereinafter, the region formed to be transparent so that the reflected light can pass through is referred to as the optical opening region OPA.

[0106] Based on the center of each pinhole PIH, when the field of view angle in the exemplary range is θ, the thickness of the circuit element layer BPL is q, and the width of the optical opening region OPA formed at the boundary surface between the circuit element layer BPL and the light-emitting element layer LDL is 2p, “2p = 2×(q×tanθ)” can be satisfied. In an embodiment, the field of view can be an angle in the range from about 30 degrees to about 60 degrees, for example, about 45 degrees, but is not limited thereto.

[0107] The pinhole PIH can have a width w within a range of a predetermined width w (for example, from about 5 μm to about 20 μm). Considering this, the width of the optical opening region OPA can be 2p + w. In this way, as the distance from the light-shielding layer PHL increases (that is, as each of the distances from the upper and lower portions of the light-shielding layer PHL increases), the width of the optical opening region OPA to be ensured in each layer of the display device 10 can gradually increase.

[0108] The width w (or diameter) of the pinhole PIH can be set to be about 10 times or more of the wavelength of the reflected light, for example, about 4 μm or about 5 μm or more, to prevent diffraction of light. In addition, the width w of the pinhole PIH can be set to a size sufficient to prevent image blurring and sufficient to sense the shape of the fingerprint more clearly. For example, the width w of the pinhole PIH can be set to about 20 μm or less. However, the exemplary embodiments of the invention are not limited thereto, and the width w of the pinhole PIH can vary according to the wavelength band of the reflected light and / or the thickness of each layer of the module.

[0109] The distance between adjacent pinholes PIH (or pitch) can be set by considering the distance between the light-shielding layer PHL and the sensor layer PSL and the wavelength range of the reflected light. For example, when the field of view of the reflected light to be ensured is about 45 degrees, the distance between adjacent pinholes PIH can be set to be twice or more the distance between the light-shielding layer PHL and the sensor layer PSL, and can be set to be equal to or greater than the value obtained by adding a predetermined error range to this distance. In this case, it is possible to prevent the images observed by the respective light sensors PHS from overlapping each other, thereby preventing image blurring.

[0110] The sensor layer PSL is attached to the rear surface (e.g., the back surface) of the display panel 110 so as to overlap at least one area of the display panel 110. The sensor layer PSL can be provided to overlap the display panel 110 at least in the display area AA. The sensor layer PSL can include a plurality of light sensors PHS distributed at a predetermined resolution and / or distance. The distance between the light sensors PHS can be set closely so that the reflected light reflected from an object to be observed (e.g., a specific area of a finger, such as a fingerprint area) can be incident on at least two adjacent light sensors PHS.

[0111] The light sensors PHS of the sensor layer PSL can output an electrical signal corresponding to the reflected light received through the pinhole PIH as a sensing signal. Depending on whether the reflected light is due to the valleys or ridges of the fingerprint formed on the user's finger, the reflected light received by each light sensor PHS can have different optical characteristics (e.g., frequency, wavelength, size, etc.). Therefore, each of the light sensors PHS can output a sensing signal having different electrical characteristics corresponding to the optical characteristics of the reflected light. The sensing signal output by the light sensor PHS can be converted into image data and used for fingerprint recognition of the user.

[0112] As described above, the display device 10 includes a fingerprint sensor including a light-emitting element layer LDL, a sensor layer PSL, and a light-shielding layer PHL. The light-emitting element layer LDL can include a light-emitting element LD that can also be used as a light-sensing method sensor. The sensor layer PSL can include light sensors PHS that receive the light emitted from the light-emitting element layer LDL and reflected from an object (e.g., a fingerprint area of a finger) located above the display device 10. The light-shielding layer PHL can include pinholes PIH provided between the light-emitting element layer LDL and the sensor layer PSL to selectively transmit the reflected light.

[0113] According to an embodiment, the fingerprint sensor may further include an optical opening area OPA formed inside the display panel 110 or the like to reduce the loss of reflected light incident on each pinhole PIH within a predetermined field of view angle range. In addition, the fingerprint sensor may include a light control layer disposed inside the display panel 110 to control the optical path to more easily control the field of view. Various embodiments of the light control layer will be described below with reference to Figures 9 to 12C Describe various embodiments of the light control layer.

[0114] On the other hand, the display device 10 also uses the light-emitting element LD of the pixel PXL as the light source of the fingerprint sensor, but the exemplary embodiments of the invention are not limited thereto. For example, a display device according to another embodiment may have a separate light source for fingerprint sensing.

[0115] A fingerprint sensing method of the display device 10 according to the above embodiment will be briefly described below. During a fingerprint sensing period in which the optical sensor PHS is activated, in a state where a user's finger (e.g., a fingerprint area) touches or is close to the display area AA, the pixels PXL of the display area AA (specifically, the light-emitting elements LD included in the pixels PXL) may emit light. For example, during the fingerprint sensing period, all the pixels PXL of the display area AA may emit light simultaneously or sequentially. Alternatively, among the pixels PXL of the display area AA, only some pixels PXL may be emitted at a predetermined interval, or only some pixels PXL that emit light of a specific color (e.g., light having a short wavelength such as blue light) may be selectively emitted.

[0116] Some of the light emitted from the pixels PXL may be reflected by the user's finger and pass through the optical opening area OPA and the pinholes PIH formed in the respective layers of the display device 10 to be incident on the optical sensor PHS. At this time, the fingerprint shape (fingerprint pattern) of the user may be detected based on the difference in the amount of light and / or the waveform of the reflected light reflected from the ridges and valleys of each fingerprint.

[0117] Figure 4B is a cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention. In Figure 4B In, a detailed description of the structures that are the same as or similar to those in the above Figure 4A embodiment will be omitted to prevent redundancy.

[0118] Referring to Figure 4B , the display panel 110 includes a second protective layer PTL2. The second protective layer PTL2 may include a base layer BSL and a first coating COL1 and a second coating COL2 formed on the lower surface and the upper surface of the base layer BSL, respectively.

[0119] The substrate layer BSL can be formed in the form of a plastic film including at least one organic film. For example, the plastic film can be manufactured by including at least one of thermoplastic polymer resins (such as polycarbonate ("PC"), polyimide ("PI"), polyethersulfone ("PES"), polyarylate ("PAr"), polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), cycloolefin copolymer, epoxy resin), thermosetting polymer resins (such as unsaturated polyester, phenolic resin (PF), silicone, polyurethane), etc.

[0120] In an embodiment, the material of the substrate layer BSL is not limited to the above materials, and the material of the substrate layer BSL can be selected as a suitable material among the materials capable of protecting the layer disposed thereon according to the design conditions of the display panel 110 and the like. According to an embodiment, the substrate layer BSL can also include the same material as the infrared light absorbing material and / or infrared light blocking material included in the second adhesive layer ADL2 of the display device 10.

[0121] Any one of the first coating COL1 and the second coating COL2 can be coated with an infrared light reflecting and blocking material, and the other can be coated with an infrared light absorbing material. For example, the first coating COL1 can be a layer on which a mixture in which an infrared light absorbing material is mixed is applied (or coated), and the second coating COL2 can be a layer on which a mixture in which an infrared light reflecting and blocking material is mixed is applied (or coated). Examples of the infrared light reflecting and blocking material can include titanium oxide (TiO2), magnesium fluoride (MgF2), etc., but the exemplary embodiments of the invention are not limited thereto.

[0122] As described above, when the second protective layer PTL2 includes an infrared light reflecting and / or blocking material and an infrared light absorbing material, even if the infrared light of external light transmits through the user's hand, the infrared light does not enter the sensor layer PSL through the second protective layer PTL2 located above the sensor layer PSL. Therefore, the optical sensor PHS can more accurately identify the user's fingerprint without interference from external light.

[0123] According to an embodiment, infrared light can be blocked by configuring some structures of the display panel 110 (such as the second adhesive layer ADL2 and / or the second protective layer PTL2) to include an infrared light absorbing material and / or an infrared light blocking material without adding a separate component such as an infrared light blocking film. Therefore, the manufacturing cost of the display device 10 can be reduced, and the thickness of the display device 10 can be further reduced.

[0124] Hereinafter, the light shielding layer PHL will be described in more detail.

[0125] Figure 5It is a plan view showing an exemplary embodiment of a light-shielding layer constructed according to the principles of the invention.

[0126] Referring to Figure 5 , the light-shielding layer PHL may include a light-shielding mask LBM and a plurality of pinholes PIH distributed in the light-shielding mask LBM.

[0127] The light-shielding mask LBM may be formed of a light-blocking material and / or a light-absorbing material. For example, the light-shielding mask LBM may be formed of an opaque metal layer (conductive layer) that is locally opened in the region where each pinhole PIH is provided. However, the construction material of the light-shielding mask LBM is not limited to metal, and the light-shielding mask LBM may be formed of various materials capable of blocking light transmission. For example, the light-shielding mask LBM may be formed of currently known black matrix materials.

[0128] The pinhole PIH may be an opening portion dispersed in the light-shielding mask LBM. The pinholes PIH may be dispersed in the light-shielding mask LBM in a regular or irregular pattern to have a certain size and distance.

[0129] In Figure 5 the embodiment, the pinholes PIH are shown as being generally rectangular in shape, but the exemplary embodiments of the invention are not limited thereto. That is, in various embodiments, the pinholes PIH may have various shapes such as generally rectangular, circular, elliptical, and polygonal shapes. However, the exemplary embodiments of the invention are not limited thereto, and the size, shape, number, resolution, and / or arrangement structure of the pinholes PIH may be variously changed.

[0130] The light-shielding layer PHL may be provided between Figures 1 to 4B the light-emitting element layer LDL in the display device 10 in which the light-emitting element LD is provided and the sensor layer PSL in which the photosensor PHS is provided. The light-shielding layer PHL may form an optical system for selectively transmitting only some light and blocking the remaining light.

[0131] The light-shielding layer PHL may form a fingerprint sensor together with the above-described photosensor PHS. In addition, the light-shielding layer PHL may be integrally formed with the circuit element layer BPL of the display panel 110. In this case, the module thickness of the fingerprint sensor and the display device including the fingerprint sensor may be reduced or minimized.

[0132] Figure 6A , Figure 6B , Figure 6C and Figure 6D are plan views of exemplary embodiments of a pixel, a pinhole, and a photosensor constructed according to the principles of the invention, showing the relative settings of the pixel, the pinhole, and the photosensor. Specifically, Figures 6A to 6D shows the setting related to Figures 1 to 4BDifferent embodiments of the relative sizes, resolutions, and / or setting relationships of pixels PXL, pinholes PIH, and photosensors PHS in the sensing area SA.

[0133] Referring to Figure 6A , the sensing area SA may include a number of pinholes PIH and photosensors PHS that is less than the number of pixels PXL. In addition, the pinholes PIH and photosensors PHS may have sizes smaller than the size of the pixels PXL, and may be distributed in the sensing area SA at a resolution lower than the resolution of the pixels PXL.

[0134] On the other hand, although Figure 6A illustrates an embodiment in which the number of pinholes PIH and photosensors PHS is less than the number of pixels PXL, exemplary embodiments of the invention are not limited thereto. That is, in another embodiment, the pinholes PIH and photosensors PHS may be distributed in the sensing area SA in substantially the same number and at the same distance to correspond one-to-one. For example, the pinholes PIH and photosensors PHS may be arranged to be stacked on top of each other in pairs one-to-one. According to an embodiment, the pairs of pinholes PIH and photosensors PHS may be arranged to be stacked on top of any one of the pixels PXL provided in the sensing area SA, but exemplary embodiments of the invention are not limited thereto. For example, the pinholes PIH and photosensors PHS may be alternately arranged not to be stacked on top of each other, or may be arranged not to be stacked on the pixels PXL.

[0135] The pinholes PIH and photosensors PHS may have the same or different sizes. That is, there are no particular limitations on the relative sizes and resolutions of the pinholes PIH and photosensors PHS.

[0136] Referring to Figure 6B , the sensing area SA may include a number of pinholes PIH that is less than the number of pixels PXL and a number of photosensors PHS that is more than the number of pixels PXL. In addition, the pinholes PIH and photosensors PHS may have sizes smaller than the size of the pixels PXL, the pinholes PIH may be distributed in the sensing area SA at a resolution lower than the resolution of the pixels PXL, and the photosensors PHS may be densely distributed in the sensing area SA at a resolution higher than the resolution of the pixels PXL.

[0137] At least a portion of the photosensors PHS may be stacked on top of any one of the pinholes PIH and / or any one of the pixels PXL, but exemplary embodiments are not limited thereto. For example, a portion of the photosensors PHS may be arranged to be stacked on the pinholes PIH and / or the pixels PXL, and other photosensors PHS may be arranged in the gaps between the pixels PXL.

[0138] Referring to Figure 6C and Figure 6D, the optical sensor PHS can be distributed in the sensing area SA to have a size smaller than that of the optical sensor PHS in the embodiment shown in Figure 6B and a resolution higher than that of the optical sensor PHS in the embodiment shown in Figure 6B . For example, a plurality of optical sensors PHS can be superimposed on each pinhole PIH and / or pixel PXL. On the other hand, the pinholes PIH can be distributed in the sensing area SA with a resolution the same as or different from that of the pixels PXL. For example, as shown in Figure 6C , the pinholes PIH can be distributed in the sensing area SA with a resolution the same as that of the pixels PXL, or as shown in Figure 6D , they can be distributed in the sensing area SA with a resolution lower than that of the pixels PXL.

[0139] Figures 6A to 6D shows an embodiment in which the pinholes PIH and the optical sensors PHS are arranged in a regular array in the sensing area SA, but the exemplary embodiments of the invention are not limited thereto. That is, the pinholes PIH and / or the optical sensors PHS can be irregularly dispersed in the sensing area SA, or can be distributed with different densities or arrangement structures according to each region or part of the sensing area SA.

[0140] The positional relationship among the pixels PXL, the pinholes PIH, and the optical sensors PHS is not limited to the embodiment shown in Figures 6A to 6D . For example, the shapes, arrangement types, relative sizes, numbers, resolutions, and / or mutual setting relationships of the pixels PXL, the pinholes PIH, and / or the optical sensors PHS can be variously changed.

[0141] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 12B and Figure 12C are cross-sectional views of other exemplary embodiments of the display device constructed according to the principles of the invention. In Figures 7 to 12C , the detailed description of the structure that is the same as or similar to at least one of the embodiments described above in the description with reference to Figures 1 to 6D will be omitted to prevent redundancy.

[0142] Referring to Figure 7 , the display panel 110 may further include a second substrate SUB2 provided on one surface (for example, the lower surface) of the first substrate SUB1. The second substrate SUB2 may be provided between the first substrate SUB1 and the sensor layer PSL. In such an embodiment, a barrier layer BRL may be provided between the first substrate SUB1 and the second substrate SUB2.

[0143] The second substrate SUB2 may be formed of the same or different material as that of the first substrate SUB1. For example, both the first substrate SUB1 and the second substrate SUB2 may be thin film substrates of polyimide (“PI”) material. Optionally, the first substrate SUB1 and the second substrate SUB2 may be heterogeneous substrates including different materials. The second substrate SUB2 may include at least one of the materials previously referred to as the construction materials of the first substrate SUB1 and may be formed of various other materials.

[0144] The barrier layer BRL may be provided in the form of a single layer or multiple layers. For example, the barrier layer BRL may be formed of a structure in which ten or more inorganic insulating layers are stacked.

[0145] Referring to Figure 8 , the circuit element layer BPL may include a first light transmissive hole array layer LTHL1 provided in the sensing region SA. For example, the first light transmissive hole array layer LTHL1 may include a plurality of first light transmissive holes LTH1 distributed in the circuit element layer BPL. In such an embodiment, the first light transmissive hole array layer LTHL1 may be provided instead of the light shielding layer PHL. That is, the first light transmissive holes LTH1 may serve as pinholes PIH, respectively.

[0146] When the pinholes PIH are formed by using a plurality of first light transmissive holes LTH1 distributed in the circuit element layer BPL as shown in Figure 8 without separately providing the light shielding layer PHL, a separate mask process for forming the light shielding layer PHL may be omitted. In addition, the display device 10 according to the embodiment shown in Figure 8 may prevent an increase in thickness due to the separately provided light shielding layer PHL, thereby reducing the manufacturing cost and increasing the process efficiency.

[0147] In addition, when the pinholes PIH are provided in the circuit element layer BPL as shown in Figure 8 , since the distance between the pinholes PIH and the optical aperture region OPA described with reference to Figure 4A is reduced, the width of the optical aperture region OPA may be reduced. Then, since the size of the pixel region PXA may be reduced, a high-resolution display device 10 may be realized.

[0148] Referring to Figure 9 and Figure 10 , the circuit element layer BPL may include a first light transmissive hole array layer LTHL1 including a plurality of first light transmissive holes LTH1. In addition, a light shielding layer PHL including a plurality of pinholes PIH may be provided between the first substrate SUB1 and the circuit element layer BPL. Each first light transmissive hole LTH1 and each pinhole PIH are arranged such that at least a part of them overlaps.

[0149] In various exemplary embodiments of the invention, the first light transmissive hole LTH1 and the pinhole PIH may have the same or different sizes. For example, as Figure 9 shown, the first light transmissive hole LTH1 may have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH. For example, the pinhole PIH and the first light transmissive hole LTH1 may have widths (or diameters) in the range of about 5 μm to about 20 μm, and the first light transmissive hole LTH1 may have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH.

[0150] In an embodiment, when the pinhole PIH and the first light transmissive hole LTH1 have a substantially rectangular shape, the length of the first side of the pinhole PIH may be about 8.5 μm, and the length of the second side perpendicular to the first side may be about 9.4 μm. Further, in such an embodiment, the length of the first side of the first light transmissive hole LTH1 may be about 4.5 μm, and the length of the second side perpendicular to the first side may be about 5.4 μm. Such values are merely examples, and the exemplary embodiments of the invention are not limited thereto.

[0151] In an embodiment in which the first light transmissive hole LTH1 has a size smaller than that of the pinhole PIH, the first light transmissive hole array layer LTHL1 may function as a light control layer LBL that controls the path of light (e.g., limits the field of view of the reflected light to a predetermined angular range), and the light shielding layer PHL may function as a light blocking layer.

[0152] As Figure 10 shown, the first light transmissive hole LTH1 may have a width (or diameter) larger than the width (or diameter) of the pinhole PIH. In such an embodiment, the first light transmissive hole array layer LTHL1 may function as a light blocking layer, and the light shielding layer PHL may function as a light control layer LBL that controls the path of light.

[0153] Referring to Figure 11 , the circuit element layer BPL may include a first light transmissive hole array layer LTHL1 including a plurality of first light transmissive holes LTH1. Further, a light shielding layer PHL including a plurality of pinholes PIH may be disposed between the first substrate SUB1 and the second substrate SUB2. Each first light transmissive hole LTH1 and each pinhole PIH are arranged such that at least a part of them overlaps.

[0154] In various exemplary embodiments of the invention, the first light transmissive hole LTH1 and the pinhole PIH may have the same or different sizes. For example, the first light transmissive hole LTH1 may have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH. In such an embodiment, the first light transmissive hole array layer LTHL1 may function as a light control layer LBL that controls the path of light, and the light shielding layer PHL may function as a light blocking layer.

[0155] Referring toFigures 12A to 12C , the first substrate SUB1 may have a first surface FS and a second surface SS, and the circuit element layer BPL may include a light-transmitting hole array layer LTHL disposed in the sensing area SA. The light-transmitting hole array layer LTHL may be formed of multiple layers. For example, the light-transmitting hole array layer LTHL includes a first light-transmitting hole array layer LTHL1 including a first light-transmitting hole LTH1 and a second light-transmitting hole array layer LTHL2 including a second light-transmitting hole LTH2. The first light-transmitting hole array layer LTHL1 may be the first layer (e.g., the first conductive layer) of the circuit element layer BPL, and the second light-transmitting hole array layer LTHL2 may be the second layer (e.g., the second conductive layer).

[0156] The first light-transmitting hole LTH1 and the second light-transmitting hole LTH2 may overlap each other. The first light-transmitting hole LTH1 and the second light-transmitting hole LTH2 may have the same or different sizes.

[0157] For example, as Figure 12A shown, the first light-transmitting hole LTH1 and the second light-transmitting hole LTH2 may have substantially the same width (or diameter) and may be arranged to overlap each other. In such an embodiment, the first light-transmitting hole LTH1 and the second light-transmitting hole LTH2 may form a pinhole PIH of a multi-layer structure. For example, the first light-transmitting hole LTH1 may form a first pinhole PIH1 disposed in the first layer of the circuit element layer BPL, and the second light-transmitting hole LTH2 may form a second pinhole PIH2 disposed in the second layer of the circuit element layer BPL. In this case, the first light-transmitting hole array layer LTHL1 including the first light-transmitting hole LTH1 and the second light-transmitting hole array layer LTHL2 including the second light-transmitting hole LTH2 may form a light-shielding layer PHL of a multi-layer structure.

[0158] As Figure 12B shown, the first light-transmitting hole LTH1 may have a size smaller than that of the second light-transmitting hole LTH2. In such an embodiment, the first light-transmitting hole array layer LTHL1 including the first light-transmitting hole LTH1 may perform the function of a light control layer LBL that controls the path of light, and the second light-transmitting hole array layer LTHL2 including the second light-transmitting hole LTH2 may instead perform the function of a light-shielding layer PHL that blocks light.

[0159] As Figure 12C shown, the first light-transmitting hole LTH1 may have a size larger than that of the second light-transmitting hole LTH2. In such an embodiment, the first light-transmitting hole array layer LTHL1 including the first light-transmitting hole LTH1 may instead perform the function of a light-shielding layer PHL that blocks light, and the second light-transmitting hole array layer LTHL2 including the second light-transmitting hole LTH2 may perform the function of a light control layer LBL that controls the path of light.

[0160] Figure 13This is a circuit diagram showing an exemplary embodiment of a representative pixel. In Figure 13 , for ease of description, an active pixel is shown that is connected to the i-th (i is a natural number) scan line Si provided in the i-th horizontal pixel row and the j-th (j is a natural number) data line Dj provided in the j-th vertical pixel column and includes two transistors. However, the structure of the pixel PXL in the exemplary embodiments of the invention is not limited to Figure 13 the structure shown therein.

[0161] Referring to Figure 13 , the pixel PXL may include a first transistor M1, a second transistor M2, a storage capacitor Cst, and a light-emitting element LD.

[0162] The first transistor M1 (driving transistor) is connected between the j-th data line Dj and the first node N1, and the gate electrode of the first transistor M1 is connected to the i-th scan line Si. When a scan signal having a gate-on voltage (e.g., a low voltage) is supplied from the i-th scan line Si, the first transistor M1 is turned on. When the first transistor M1 is turned on, the j-th data line Dj and the first node N1 can be electrically connected to each other.

[0163] The second transistor M2 (switching transistor) is connected between the first power supply ELVDD and the light-emitting element LD, and the gate electrode of the second transistor M2 is connected to the first node N1. The second transistor M2 controls the amount of current supplied from the first power supply ELVDD through the light-emitting element LD to the second power supply ELVSS corresponding to the voltage of the first node N1. In various embodiments, the first power supply ELVDD may be a high-potential pixel power supply, and the second power supply ELVSS may be a low-potential pixel power supply.

[0164] The storage capacitor Cst is connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to the data signal supplied to the first node N1.

[0165] The light-emitting element LD is connected between the second transistor M2 and the second power supply ELVSS. The light-emitting element LD emits light with a brightness corresponding to the current controlled by the second transistor M2. In various embodiments, the light-emitting element LD may be an organic light-emitting diode (“OLED”).

[0166] Figure 14 This is a circuit diagram showing another exemplary embodiment of a representative pixel. In Figure 14In order to facilitate the description, an active pixel is shown that is connected to the i-th (where i is a natural number) scan line Si provided in the i-th horizontal pixel row, the (i - 1)-th scan line Si-1 provided in the (i - 1)-th horizontal pixel row, the (i + 1)-th scan line Si+1 provided in the (i + 1)-th horizontal pixel row, and the j-th (where j is a natural number) data line Dj provided in the j-th vertical pixel column and includes seven transistors. However, the structure of the pixel PXL in the exemplary embodiments of the invention is not limited to Figure 14 the structure shown in

[0167] Referring to Figure 14 , according to another embodiment, the pixel PXL may include a first transistor M1 to a seventh transistor M7, a storage capacitor Cst, and a light-emitting element LD.

[0168] The first electrode of the first transistor M1 may be connected to the first power supply ELVDD through the fifth transistor M5, and the second electrode of the first transistor M1 may be connected to the anode electrode of the light-emitting element LD through the sixth transistor M6. In addition, the gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current flowing from the first power supply ELVDD through the light-emitting element LD to the second power supply ELVSS corresponding to the voltage of the first node N1.

[0169] The second transistor M2 (switching transistor) may be connected between the j-th data line Dj and the first electrode of the first transistor M1. In addition, the gate electrode of the second transistor M2 may be connected to the i-th scan line Si. The second transistor M2 may be turned on when a scan signal is supplied to the i-th scan line Si to electrically connect the j-th data line Dj and the first electrode of the first transistor M1 to each other.

[0170] The third transistor M3 may be connected between the second electrode of the first transistor M1 and the first node N1. In addition, the gate electrode of the third transistor M3 may be connected to the i-th scan line Si. The third transistor M3 may be turned on when a scan signal of a gate conduction voltage is supplied to the i-th scan line Si to electrically connect the second electrode of the first transistor M1 and the first node N1 to each other. Therefore, when the third transistor M3 is turned on, the first transistor M1 may be connected in a diode form.

[0171] The fourth transistor M4 (initialization transistor) may be connected between the first node N1 and the initialization power supply Vint. In addition, the gate electrode of the fourth transistor M4 may be connected to the (i - 1)-th scan line Si-1. The fourth transistor M4 may be turned on when a scan signal is supplied to the (i - 1)-th scan line Si-1 to supply the voltage of the initialization power supply Vint to the first node N1.

[0172] Figure 14An embodiment is shown in which the (i-1)-th scan line Si-1 serves as an initialization control line for initializing the gate node (i.e., the first node N1) of the first transistor M1. However, the exemplary embodiments of the invention are not limited thereto. For example, in another embodiment, another control line such as the (i-2)-th scan line may serve as an initialization control line for initializing the gate node of the first transistor M1.

[0173] The fifth transistor M5 may be connected between the first power supply ELVDD and the first transistor M1. In addition, the gate electrode of the fifth transistor M5 may be connected to the i-th light emission control line Ei. The fifth transistor M5 may be turned off when a light emission control signal of a gate cut-off voltage is supplied to the i-th light emission control line Ei, and may be turned on in other cases.

[0174] The sixth transistor M6 may be connected between the first transistor M1 and the light emitting element LD. In addition, the gate electrode of the sixth transistor M6 may be connected to the i-th light emission control line Ei. The sixth transistor M6 may be turned off when a light emission control signal of a gate cut-off voltage is supplied to the i-th light emission control line Ei, and may be turned on in other cases.

[0175] The seventh transistor M7 may be connected between the initialization power supply Vint and the first electrode (e.g., the anode electrode) of the light emitting element LD. In addition, the gate electrode of the seventh transistor M7 may be connected to the (i + 1)-th scan line Si+1. When a scan signal of a gate conduction voltage (e.g., a low-level voltage) is supplied to the (i + 1)-th scan line Si+1, the seventh transistor may be turned on to supply the voltage of the initialization power supply Vint to the anode electrode of the light emitting element LD. Here, the voltage of the initialization power supply Vint may be set to a voltage lower than the voltage of the data signal. That is, the voltage of the initialization power supply Vint may be set to be equal to or less than the lowest voltage of the data signal.

[0176] Figure 14 A case is shown in which the anode initialization control line to which the gate electrode of the seventh transistor M7 is connected is the (i + 1)-th scan line Si+1. However, the exemplary embodiments of the invention are not limited thereto. For example, in another embodiment, the gate electrode of the seventh transistor M7 may be connected to the i-th scan line Si. In this case, when a scan signal of a gate conduction voltage is supplied to the i-th scan line Si, the voltage of the initialization power supply Vint may be supplied to the anode electrode of the light emitting element LD through the seventh transistor M7.

[0177] The storage capacitor Cst may be connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

[0178] The anode electrode of the light-emitting element LD can be connected to the first transistor M1 through the sixth transistor M6, and the cathode electrode can be connected to the second power supply ELVSS. The light-emitting element LD generates light of a predetermined brightness corresponding to the amount of current supplied from the first transistor M1. The voltage value of the first power supply ELVDD can be set to be higher than the voltage value of the second power supply ELVSS so that current can flow to the light-emitting element LD.

[0179] On the other hand, the structure of the pixel PXL is not limited to Figure 14 the embodiment shown in. For example, pixel circuits of various known structures can be applied to the pixel PXL.

[0180] Figure 15 is a plan view showing an exemplary embodiment of the layout of the pixel shown in Figure 14 . Specifically, Figure 15 shows the layout of the pixel PXL including Figure 1 and Figure 2 among the pixels PXL in the display area AA of Figures 8 to 12C and having the first light-transmitting hole LTH1 shown in. Figure 16 is a cross-sectional view taken along the line I-I’ of Figure 15 . Figure 17 is a cross-sectional view taken along the line II-II’ of Figure 15 . For ease of description, Figures 15 to 17 only shows Figure 4A and Figure 4B the circuit element layer BPL, the light-emitting element layer LDL, and the first protective layer PTL1 in the display device 10 shown in to avoid redundancy.

[0181] In describing the embodiment of Figures 15 to 17 , for convenience, the scan lines of the (i - 1)-th row, the i-th row, and the (i + 1)-th row are referred to as "scan lines Si-1, Si, and Si+1", the light-emission control line of the i-th row is referred to as "light-emission control line Ei", the data line of the j-th column is referred to as "data line Dj", and the power supply line of the j-th column (for example, the power supply line of the j-th column to which the first power supply ELVDD is applied) is referred to as "power supply line PL".

[0182] Referring to Figures 15 to 17 having the above embodiment, the display device 10 may include pixels PXL provided in the display area AA and a wiring portion for supplying driving signals and / or power to the pixels PXL. The wiring portion may include scan lines Si-1, Si, and Si+1, data lines Dj, light-emission control lines Ei, power supply lines PL, and initialization power supply lines IPL.

[0183] The scan lines Si-1, Si, and Si+1 can extend in a first direction DR1 in the display area AA. The scan lines Si-1, Si, and Si+1 can include the (i-1)th scan line Si-1, the ith scan line Si, and the (i+1)th scan line Si+1 arranged in sequence in a second direction DR2 intersecting the first direction DR1. The scan lines Si-1, Si, and Si+1 can receive scan signals. For example, the (i-1)th scan line Si-1 can receive the (i-1)th scan signal, the ith scan line Si can receive the ith scan signal, and the (i+1)th scan line Si+1 can receive the (i+1)th scan signal.

[0184] The emission control line Ei can extend in the first direction DR1 to be parallel to the scan lines Si-1, Si, and Si+1 in the display area AA. The emission control line Ei can receive an emission control signal.

[0185] The data line Dj can extend in the second direction DR2 in the display area AA. That is, the data line Dj can extend in a direction intersecting the control lines Si-1, Si, Si+1, and Ei including the scan lines Si-1, Si, and Si+1 and the emission control line Ei. The data line Dj can receive a data signal.

[0186] The power supply line PL can extend in the second direction DR2 in the display area AA, but is not limited thereto. The power supply line PL can be set to be spaced apart from the data line Dj and can receive a first power supply ELVDD.

[0187] The initialization power supply line IPL can extend in the first direction DR1 in the display area AA, but is not limited thereto. The initialization power supply line IPL can receive an initialization power supply Vint.

[0188] In an embodiment, the pixel PXL can include a first transistor M1 to a seventh transistor M7, a storage capacitor Cst, and a light-emitting element LD.

[0189] The first transistor M1 can include a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0190] In an embodiment, the first gate electrode GE1 can be set to overlap with a first channel CH1 of an active pattern, and at least one insulating layer (such as a gate insulating layer 113) is disposed between the first gate electrode GE1 and the first channel CH1. The first gate electrode GE1 can be connected to a third drain electrode DE3 (including DE3a and DE3b) of a third transistor M3 and a fourth source electrode SE4 (including SE4a and SE4b) of a fourth transistor M4.

[0191] The first gate electrode GE1 can be connected to the third drain electrode DE3 and the fourth source electrode SE4 through the connection wiring CNL. One end of the connection wiring CNL can be connected to the first gate electrode GE1 through the first contact hole CT1, and the other end can be connected to the third drain electrode DE3 and the fourth source electrode SE4 through the second contact hole CT2.

[0192] In an embodiment, the first channel CH1, the first source electrode SE1, and the first drain electrode DE1 can be formed of a semiconductor pattern in which impurities are not doped or impurities are doped. For example, the first source electrode SE1 and the first drain electrode DE1 can be formed of a semiconductor pattern doped with impurities, and the first channel CH1 can be formed of a semiconductor pattern in which impurities are not doped.

[0193] The first channel CH1 has a shape extending in a random direction and can have a shape that bends several times along the extending length direction. When viewed in a plan view, the first channel CH1 can overlap with the first gate electrode GE1. By forming the first channel CH1 to be long, the channel region of the first transistor M1 can be formed to be long. Therefore, the driving range of the gate voltage applied to the first transistor M1 is widened. Therefore, the gray scale of the light emitted from the light emitting element LD can be finely controlled.

[0194] The first source electrode SE1 can be connected to one end of the first channel CH1. The first source electrode SE1 can be connected to the second drain electrode DE2 of the second transistor M2 and the fifth drain electrode DE5 of the fifth transistor M5. In an embodiment, the first drain electrode DE1 can be connected to the other end of the first channel CH1. The first drain electrode DE1 can be connected to the third source electrode SE3 (including SE3a and SE3b) of the third transistor M3 and the sixth source electrode SE6 of the sixth transistor M6.

[0195] The second transistor M2 can include a second gate electrode GE2, a second channel CH2, a second source electrode SE2, and a second drain electrode DE2.

[0196] The second gate electrode GE2 can be arranged to overlap with the second channel CH2, and at least one insulating layer (for example, the gate insulating layer 113) is disposed between the second gate electrode GE2 and the second channel CH2. The second gate electrode GE2 can be connected to the i-th scan line Si.

[0197] The second channel CH2, the second source electrode SE2, and the second drain electrode DE2 can be formed of a semiconductor pattern in which impurities are not doped or impurities are doped. For example, the second source electrode SE2 and the second drain electrode DE2 can be formed of a semiconductor pattern doped with impurities, and the second channel CH2 can be formed of a semiconductor pattern in which impurities are not doped. The second channel CH2 can correspond to the portion overlapping with the second gate electrode GE2.

[0198] One end of the second source electrode SE2 may be connected to the second channel CH2, and the other end of the second source electrode SE2 may be connected to the data line Dj through the sixth contact hole CT6. In an embodiment, one end of the second drain electrode DE2 may be connected to the second channel CH2, and the other end of the second drain electrode DE2 may be connected to the first source electrode SE1 of the first transistor M1 and the fifth drain electrode DE5 of the fifth transistor M5.

[0199] The third transistor M3 may be provided with a double-gate structure to prevent leakage current. That is, the third transistor M3 may include a 3a transistor M3a and a 3b transistor M3b. The 3a transistor M3a may include a 3a gate electrode GE3a, a 3a active pattern, a 3a source electrode SE3a, and a 3a drain electrode DE3a. The 3b transistor M3b may include a 3b gate electrode GE3b, a 3b active pattern, a 3b source electrode SE3b, and a 3b drain electrode DE3b. Hereinafter, the 3a gate electrode GE3a and the 3b gate electrode GE3b are referred to as the third gate electrode GE3, the 3a active pattern and the 3b active pattern are referred to as the third channel CH3, the 3a source electrode SE3a and the 3b source electrode SE3b are referred to as the third source electrode SE3, and the 3a drain electrode DE3a and the 3b drain electrode DE3b are referred to as the third drain electrode DE3.

[0200] The third gate electrode GE3 (including GE3a and GE3b) may be disposed to overlap the third channel CH3, and at least one insulating layer (e.g., the gate insulating layer 113) is disposed between the third gate electrode GE3 and the third channel CH3. The third gate electrode GE3 may be connected to the i-th scan line Si.

[0201] The third channel CH3, the third source electrode SE3, and the third drain electrode DE3 may be formed of a semiconductor pattern in which no impurities are doped or impurities are doped. For example, the third source electrode SE3 and the third drain electrode DE3 may be formed of a semiconductor pattern in which impurities are doped, and the third channel CH3 may be formed of a semiconductor pattern in which no impurities are doped. The third channel CH3 corresponds to the portion overlapping the third gate electrode GE3.

[0202] One end of the third source electrode SE3 may be connected to the third channel CH3 (including CH3a and CH3b), and the other end of the third source electrode SE3 may be connected to the first drain electrode DE1 of the first transistor M1 and the sixth source electrode SE6 of the sixth transistor M6. In an embodiment, one end of the third drain electrode DE3 may be connected to the third channel CH3, and the other end of the third drain electrode DE3 may be connected to the fourth source electrode SE4 of the fourth transistor M4. In addition, the third drain electrode DE3 may be connected to the first gate electrode GE1 of the first transistor M1 through a connection wiring CNL, a second contact hole CT2, and a first contact hole CT1.

[0203] The fourth transistor M4 may be provided with a dual-gate structure to prevent leakage current. That is, the fourth transistor M4 may include a 4a transistor M4a and a 4b transistor M4b. The 4a transistor M4a may include a 4a gate electrode GE4a, a 4a active pattern, a 4a source electrode SE4a, and a 4a drain electrode DE4a. The 4b transistor M4b may include a 4b gate electrode GE4b, a 4b active pattern, a 4b source electrode SE4b, and a 4b drain electrode DE4b. Hereinafter, the 4a gate electrode GE4a and the 4b gate electrode GE4b are referred to as a fourth gate electrode GE4 (including GE4a and GE4b), the 4a active pattern and the 4b active pattern are referred to as a fourth channel CH4 (including CH4a and CH4b), the 4a source electrode SE4a and the 4b source electrode SE4b are referred to as a fourth source electrode SE4, and the 4a drain electrode DE4a and the 4b drain electrode DE4b are referred to as a fourth drain electrode DE4.

[0204] The fourth gate electrode GE4 may be disposed to overlap the fourth channel CH4, and at least one insulating layer (e.g., a gate insulating layer 113) is disposed between the fourth gate electrode GE4 and the fourth channel CH4. The fourth gate electrode GE4 may be connected to an (i-1)th scan line Si-1.

[0205] The fourth channel CH4, the fourth source electrode SE4, and the fourth drain electrode DE4 may be formed of a semiconductor pattern in which no impurity is doped or an impurity is doped. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 may be formed of a semiconductor pattern in which an impurity is doped, and the fourth channel CH4 may be formed of a semiconductor pattern in which no impurity is doped. The fourth channel CH4 corresponds to a portion overlapping the fourth gate electrode GE4.

[0206] One end of the fourth source electrode SE4 may be connected to the fourth channel CH4, and the other end of the fourth source electrode SE4 may be connected to a third drain electrode DE3 of the third transistor M3. In addition, the fourth source electrode SE4 may be connected to a first gate electrode GE1 of the first transistor M1 through a connection wiring CNL, a second contact hole CT2, and a first contact hole CT1. One end of the fourth drain electrode DE4 may be connected to the fourth channel CH4, and the other end of the fourth drain electrode DE4 may be connected to a seventh drain electrode DE7 of the seventh transistor M7. The fourth drain electrode DE4 may be connected to an initialization power line IPL through an auxiliary connection wiring AUX, a ninth contact hole CT9, and an eighth contact hole CT8.

[0207] The fifth transistor M5 may include a fifth gate electrode GE5, a fifth channel CH5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0208] The fifth gate electrode GE5 can be arranged to overlap with the fifth channel CH5, and at least one insulating layer (such as the gate insulating layer 113) is disposed between the fifth gate electrode GE5 and the fifth channel CH5. The fifth gate electrode GE5 can be connected to the emission control line Ei.

[0209] The fifth channel CH5, the fifth source electrode SE5, and the fifth drain electrode DE5 can be formed of a semiconductor pattern that is either undoped with impurities or doped with impurities. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 can be formed of a semiconductor pattern doped with impurities, and the fifth channel CH5 can be formed of a semiconductor pattern undoped with impurities. The fifth channel CH5 corresponds to the portion that overlaps with the fifth gate electrode GE5.

[0210] One end of the fifth source electrode SE5 can be connected to the fifth channel CH5, and the other end of the fifth source electrode SE5 can be connected to the power line PL through the fifth contact hole CT5. In an embodiment, one end of the fifth drain electrode DE5 can be connected to the fifth channel CH5, and the other end of the fifth drain electrode DE5 can be connected to the first source electrode SE1 of the first transistor M1 and the second drain electrode DE2 of the second transistor M2.

[0211] The sixth transistor M6 can include a sixth gate electrode GE6, a sixth channel CH6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0212] The sixth gate electrode GE6 can be arranged to overlap with the sixth channel CH6, and at least one insulating layer (such as the gate insulating layer 113) is disposed between the sixth gate electrode GE6 and the sixth channel CH6. The sixth gate electrode GE6 can be connected to the emission control line Ei.

[0213] The sixth channel CH6, the sixth source electrode SE6, and the sixth drain electrode DE6 are formed of a semiconductor pattern that is either undoped with impurities or doped with impurities. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 can be formed of a semiconductor pattern doped with impurities, and the sixth channel CH6 can be formed of a semiconductor pattern undoped with impurities. The sixth channel CH6 corresponds to the portion that overlaps with the sixth gate electrode GE6.

[0214] One end of the sixth source electrode SE6 can be connected to the sixth channel CH6, and the other end of the sixth source electrode SE6 can be connected to the first drain electrode DE1 of the first transistor M1 and the third source electrode SE3 of the third transistor M3. In an embodiment, one end of the sixth drain electrode DE6 can be connected to the sixth channel CH6, and the other end of the sixth drain electrode DE6 can be connected to the seventh source electrode SE7 of the seventh transistor M7.

[0215] The seventh transistor M7 may include a seventh gate electrode GE7, a seventh channel CH7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0216] The seventh gate electrode GE7 may be disposed to overlap the seventh channel CH7, and at least one insulating layer (e.g., the gate insulating layer 113) may be interposed between the seventh gate electrode GE7 and the seventh channel CH7. The seventh gate electrode GE7 may be connected to the (i + 1)-th scan line Si+1.

[0217] The seventh channel CH7, the seventh source electrode SE7, and the seventh drain electrode DE7 may be formed of a semiconductor pattern in which no impurity is doped or an impurity is doped. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 may be formed of a semiconductor pattern in which an impurity is doped, and the seventh channel CH7 may be formed of a semiconductor pattern in which no impurity is doped. The seventh channel CH7 corresponds to the portion overlapping the seventh gate electrode GE7.

[0218] One end of the seventh source electrode SE7 may be connected to the seventh channel CH7, and the other end of the seventh source electrode SE7 may be connected to the sixth drain electrode DE6 of the sixth transistor M6. In an embodiment, one end of the seventh drain electrode DE7 may be connected to the seventh channel CH7, and the other end of the seventh drain electrode DE7 may be connected to the initialization power line IPL through the auxiliary connection wiring AUX, the ninth contact hole CT9, and the eighth contact hole CT8.

[0219] The storage capacitor Cst may include a first capacitor electrode LE and a second capacitor electrode UE. In an embodiment, the first capacitor electrode LE may be the lower electrode of the storage capacitor Cst and may be integrally formed with the first gate electrode GE1 of the first transistor M1. In an embodiment, the second capacitor electrode UE may be the upper electrode of the storage capacitor Cst and may overlap the first gate electrode GE1. Further, as seen in the plan view, the second capacitor electrode UE may cover at least one region of the first capacitor electrode LE. The capacitance of the storage capacitor Cst may be increased by increasing the overlapping area between the first capacitor electrode LE and the second capacitor electrode UE.

[0220] The second capacitor electrode UE may extend in the first direction DR1. In an embodiment, a voltage having the same level as the level of the first power supply ELVDD may be applied to the second capacitor electrode UE. The second capacitor electrode UE may have an opening portion OPN in the region where the first contact hole CT1 is formed, in which the first gate electrode GE1 and the connection wiring CNL are in contact in the first contact hole CT1.

[0221] The light-emitting element LD may include a first electrode (e.g., an anode electrode) AD, a second electrode (e.g., a cathode electrode) CD, and a light-emitting element layer LDL disposed between the first electrode AD and the second electrode CD. In an embodiment, the first electrode AD and the second electrode CD are disposed to overlap each other in the light-emitting region of the light-emitting element layer LDL, and the light-emitting element layer LDL may be formed in the light-emitting region. That is, the light-emitting region of each pixel PXL may be a region where the first electrode AD, the light-emitting element layer LDL, and the second electrode CD of the light-emitting element LD overlap each other.

[0222] The first electrode AD may be disposed in a predetermined light-emitting region. The first electrode AD may be connected to a seventh source electrode SE7 of a seventh transistor M7 and a sixth drain electrode DE6 of a sixth transistor M6 through a fourth contact hole CT4 and a seventh contact hole CT7. A bridging pattern BRP may be disposed between the fourth contact hole CT4 and the seventh contact hole CT7. The bridging pattern BRP may connect the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD.

[0223] Hereinafter, a stacked structure (cross-sectional structure) of a pixel PXL and a display area AA including the pixel PXL according to an embodiment will be described.

[0224] First, a buffer layer 112 may be disposed on a first surface of a first substrate SUB1.

[0225] An active pattern ACT may be disposed on the buffer layer 112. In an embodiment, the active pattern ACT may include first to seventh channels CH1 to CH7. The first to seventh channels CH1 to CH7 may be formed of a semiconductor material.

[0226] A gate insulating layer 113 may be disposed on the buffer layer 112 on which the first to seventh channels CH1 to CH7 are disposed. In an embodiment, the gate insulating layer 113 may be a gate insulating film disposed between the active patterns ACT1 to ACT7 of transistors M1 to M7 included in the pixel PXL and the gate electrodes GE1 to GE7.

[0227] The gate insulating layer 113 may include at least one inorganic film and / or organic film. For example, the gate insulating layer 113 may be formed of an inorganic film including SiO x , SiN x , etc., but is not limited thereto. For example, the gate insulating layer 113 may include inorganic insulating materials or organic insulating materials such as SiO x , SiN x , SiON, SiOF, or AlO x , and may be a single-layer film or a multi-layer film including at least one of these materials.

[0228] The first conductive layer may be disposed on the gate insulating layer 113. In an embodiment, the first conductive layer may be a first gate layer. The first conductive layer may be provided with control lines Si-1, Si, Si+1, and Ei, and gate electrodes GE1 to GE7. In addition, one electrode of the storage capacitor Cst (e.g., the first capacitor electrode LE) may be disposed on the first conductive layer. Specifically, the (i-1)-th scan line Si-1, the i-th scan line Si, the (i+1)-th scan line Si+1, the light emission control line Ei, and the first gate electrode GE1 to the seventh gate electrode GE7 may be provided. In an embodiment, the first gate electrode GE1 may also be the first capacitor electrode LE of the storage capacitor Cst. That is, the first gate electrode GE1 and the first capacitor electrode LE may be integrally formed.

[0229] The control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE, which is the lower electrode of the storage capacitor Cst disposed on the first conductive layer, may be formed of the same material. For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE of the storage capacitor Cst may be formed of a predetermined first gate metal.

[0230] Examples of materials capable of constructing the first gate metal may include Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, Pb, etc., and various other metals may be used as materials capable of forming the first gate metal. Examples of alloys capable of constructing the first gate metal may include MoTi, AlNiLa, etc., and various other alloys may be used as alloys capable of constructing the first gate metal. Examples of multi-layer films capable of forming the first gate metal may include Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, TiN / Ti / Cu / Ti, etc., and various other conductive materials having a multi-layer film structure may be used as multi-layer films capable of constructing the first gate metal.

[0231] On the other hand, the materials for constructing the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE are not necessarily limited to metals. That is, materials capable of providing sufficient conductivity for smoothly driving the pixel PXL may be used as materials for forming the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE.

[0232] For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE may be formed of a conductive polymer or a conductive metal oxide. Examples of the conductive polymer capable of constructing the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE may include polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, polyphenylene compounds, mixtures thereof, etc. In particular, among the polythiophene compounds, the PEDOT / PSS compound may be used. Examples of the conductive metal oxide capable of constructing the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE may include ITO, IZO, AZO, ITZO, ZnO, SnO2, etc.

[0233] The first interlayer insulating layer 114 may be disposed on the first conductive layer. In an embodiment, the first interlayer insulating layer 114 may be the first interlayer insulating film disposed between the first capacitor electrode LE and the second capacitor electrode UE. In an embodiment, the first interlayer insulating layer 114 may have a thickness limited to a predetermined range to sufficiently ensure the capacitance of the storage capacitor Cst within a limited area.

[0234] The first interlayer insulating layer 114 may include one or more inorganic films and / or organic films. For example, the first interlayer insulating layer 114 may be formed of an inorganic film including SiO x , SiN x , etc., but is not limited thereto. For example, the first interlayer insulating layer 114 may include inorganic insulating materials or organic insulating materials such as SiO x , SiN x , SiON, SiOF, or AlO x , and may be a single-layer film or a multi-layer film including at least one of these materials.

[0235] The second conductive layer may be disposed on the first interlayer insulating layer 114. In an embodiment, the second conductive layer may be the second gate layer.

[0236] The second conductive layer may be provided with the second capacitor electrode UE and the initialization power line IPL. In an embodiment, the second capacitor electrode UE may cover the first capacitor electrode LE. The second capacitor electrode UE is stacked with the first capacitor electrode LE, and the first interlayer insulating layer 114 is disposed between the second capacitor electrode UE and the first capacitor electrode LE to form the storage capacitor Cst together with the first capacitor electrode LE.

[0237] The second capacitor electrode UE and the initialization power line IPL provided in the second conductive layer may be made of the same material. For example, the second capacitor electrode UE and the initialization power line IPL may be formed of a predetermined second gate metal. In an embodiment, the second gate metal may be one of the metal materials given as examples of the first gate metal above, but is not limited thereto. In addition, the construction materials of the second capacitor electrode UE and the initialization power line IPL provided in the second conductive layer do not have to be limited to metals. That is, a material capable of providing sufficient conductivity to drive the pixel PXL smoothly may be used as the material for constructing the second capacitor electrode UE and the initialization power line IPL. For example, the second capacitor electrode UE and the initialization power line IPL provided in the second conductive layer may be made of a conductive polymer or a conductive metal oxide.

[0238] The second interlayer insulating layer 115 may be provided on the second conductive layer. In an embodiment, the second interlayer insulating layer 115 may be a second interlayer insulating film.

[0239] The second interlayer insulating layer 115 may include one or more inorganic films and / or organic films. For example, the second interlayer insulating layer 115 may be made of an inorganic film including SiO x , SiN x , etc., but is not limited thereto. For example, the second interlayer insulating layer 115 may include inorganic insulating materials or organic insulating materials such as SiO x , SiN x , SiON, SiOF or AlO x , and may be a single-layer film or a multi-layer film including at least one of these materials.

[0240] The third conductive layer may be provided on the second interlayer insulating layer 115. In an embodiment, the third conductive layer may be a source-drain layer.

[0241] The third conductive layer may be provided with a data line Dj, a power line PL, a connection wiring CNL, a bridging pattern BRP, and an auxiliary connection wiring AUX.

[0242] The data line Dj may be electrically connected to the second source electrode SE2 through a sixth contact hole CT6 passing through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0243] The power line PL may be connected to the second capacitor electrode UE serving as the upper electrode of the storage capacitor Cst through a third contact hole CT3 passing through the second interlayer insulating layer 115. In addition, the power line PL may be connected to the fifth source electrode SE5 through a fifth contact hole CT5 passing through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0244] The connection wiring CNL can be connected to the first gate electrode GE1 through a first contact hole CT1 that penetrates the first interlayer insulating layer 114 and the second interlayer insulating layer 115. In addition, the connection wiring CNL can be electrically connected to the third drain electrode DE3 and the fourth source electrode SE4 through a second contact hole CT2 that penetrates the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0245] The bridging pattern BRP can be a pattern of a medium set to connect the sixth drain electrode DE6 and the first electrode AD between the sixth drain electrode DE6 and the first electrode AD. The bridging pattern BRP can be electrically connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a fourth contact hole CT4 that penetrates the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0246] The auxiliary connection wiring AUX can be connected to the initialization power line IPL through an eighth contact hole CT8 that penetrates the second interlayer insulating layer 115. In addition, the auxiliary connection wiring AUX can be connected to the seventh drain electrode DE7 through a ninth contact hole CT9 that penetrates the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0247] The data line Dj, the power line PL, the connection wiring CNL, the bridging pattern BRP, and / or the auxiliary connection wiring AUX provided in the third conductive layer can be made of the same material. For example, the data line Dj, the power line PL, the connection wiring CNL, the bridging pattern BRP, and / or the auxiliary connection wiring AUX can be formed of a predetermined source-drain metal.

[0248] The source-drain metal can be one of the metal materials presented as examples of the first gate metal and / or the second gate metal before, but is not limited thereto. In addition, the construction material of the data line Dj, the power line PL, the connection wiring CNL, the bridging pattern BRP, and / or the auxiliary connection wiring AUX provided in the third conductive layer does not have to be limited to metal. That is, a material capable of providing sufficient conductivity to drive the pixel PXL smoothly can be used as the material for constructing the data line Dj, the power line PL, the connection wiring CNL, the bridging pattern BRP, and / or the auxiliary connection wiring AUX. For example, the data line Dj, the power line PL, the connection wiring CNL, the bridging pattern BRP, and / or the auxiliary connection wiring AUX can be made of a conductive polymer or a conductive metal oxide.

[0249] At least two of the first gate metal, the second gate metal, and the source / drain metal may be formed of the same material. For example, even if the first gate metal and the second gate metal are disposed on different layers, the first gate metal and the second gate metal may be formed of the same material. However, the exemplary embodiments of the invention are not limited thereto. For example, in another embodiment, all of the first gate metal, the second gate metal, and the source / drain metal may be formed of different materials.

[0250] In various exemplary embodiments of the invention, when the light incident on each of the active pattern ACT, the first conductive layer, the second conductive layer, and the third conductive layer is reflected by each of the active pattern ACT, the first conductive layer, the second conductive layer, and the third conductive layer, reflected again by the upper layer, and then incident again, in order to prevent such light that is reflected again from being noise, the distances between the active pattern ACT, the first conductive layer, the second conductive layer, and the third conductive layer may be limited. For example, the distance between the active pattern ACT, the first conductive layer or the second conductive layer and the third conductive layer may be limited to about 300 μm or less. The thicknesses of the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115 may be determined based on the distances between the active pattern ACT, the first conductive layer, the second conductive layer, and the third conductive layer, which are limited as described above.

[0251] A protective layer 116 may be disposed on the third conductive layer. In an embodiment, the protective layer 116 may include a passivation film and / or a planarization film. The protective layer 116 may include a seventh contact hole CT7 that exposes a part of the bridging pattern BRP.

[0252] A light-emitting element LD may be disposed on the protective layer 116. The light-emitting element LD may include a first electrode AD, a second electrode CD, and a light-emitting element layer LDL disposed between the first electrode AD and the second electrode CD.

[0253] In an embodiment, the protective layer 116 may have a thickness of about to about (e.g., about ), but the thickness of the protective layer 116 is not limited thereto.

[0254] At least one of the first electrode AD and the second electrode CD may be a transmissive electrode. For example, when the light-emitting element LD is a back-surface light-emitting type organic light-emitting display element, the first electrode AD may be a transmissive electrode and the second electrode CD may be a reflective electrode. On the other hand, when the light-emitting element LD is a front-surface light-emitting type organic light-emitting display element, the first electrode AD may be a reflective electrode and the second electrode CD may be a transmissive electrode. In addition, when the light-emitting element LD is a double-sided light-emitting type organic light-emitting display element, both the first electrode AD and the second electrode CD may be transmissive electrodes. Hereinafter, the case where the light-emitting element LD is a front-surface light-emitting type organic light-emitting display element and the first electrode AD is an anode electrode will be described as an example. In addition, in the illustrated embodiment, the light-emitting element LD is used as a light source, but the exemplary embodiments of the invention are not limited thereto. For example, the light-emitting element LD may be replaced with another type of light-emitting element.

[0255] The first electrode AD may be disposed on the protective layer 116. The first electrode AD may be connected to the bridging pattern BRP through the seventh contact hole CT7 that penetrates the protective layer 116. Since the bridging pattern BRP is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the fourth contact hole CT4, the first electrode AD may be finally connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the bridging pattern BRP.

[0256] The first electrode AD may include a reflective film capable of reflecting light and a transparent conductive film disposed above or below the reflective film. At least one of the transparent conductive film and the reflective film may be connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0257] The reflective film may include a material capable of reflecting light. For example, the reflective film may include at least one of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and their alloys.

[0258] The transparent conductive film may include a transparent conductive oxide. For example, the transparent conductive film may include at least one transparent conductive oxide among indium tin oxide (“ITO”), indium zinc oxide (“IZO”), aluminum zinc oxide (“AZO”), gallium-doped zinc oxide (“GZO”), zinc tin oxide (“ZTO”), gallium tin oxide (“GTO”), and fluorine-doped tin oxide (“FTO”).

[0259] The light-emitting element layer LDL may be disposed on the exposed surface of the first electrode AD. The light-emitting element layer LDL may have a multilayer thin film structure including a light generation layer (“LGL”). For example, the light-emitting element layer LDL may include: a hole injection layer (“HIL”) for injecting holes; a hole transport layer (“HTL”) for increasing the hole recombination chance by suppressing the movement of electrons not combined in the light generation layer and having excellent hole transport ability; a light generation layer for emitting light through the recombination of injected electrons and holes; a hole blocking layer (“HBL”) for suppressing the movement of holes not combined in the light generation layer; an electron transport layer (“ETL”) for smoothly transporting electrons to the light generation layer; and / or an electron injection layer (“EIL”) for injecting electrons.

[0260] The color of the light generated in the light generation layer may be one of red, green, blue, and white, but the exemplary embodiments of the invention are not limited thereto. For example, the color of the light generated in the light generation layer of the light-emitting element layer LDL may be one of magenta, cyan, and yellow.

[0261] The hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may be a common film connected to each other in adjacent light-emitting regions.

[0262] The second electrode CD may be a transmissive reflective film. For example, the second electrode CD may be a thin film metal layer having a thickness sufficient to transmit the light emitted from the light-emitting element layer LDL. For example, the second electrode CD may transmit some of the light emitted from the light-emitting element layer LDL and reflect the remaining part of the light emitted from the light-emitting element layer LDL.

[0263] In an embodiment, the second electrode CD may include a material having a work function lower than that of the transparent conductive film. For example, the second electrode CD may include at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and their alloys.

[0264] Some of the light emitted from the light-emitting element layer LDL may not transmit through the second electrode CD, and the light reflected from the second electrode CD may be reflected again in the reflective film. That is, the light emitted from the light-emitting element layer LDL may resonate between the reflective film and the second electrode CD. The light extraction efficiency of the light-emitting element LD may be improved by the resonance of the light.

[0265] The pixel defining film (or bank layer) 117 for partitioning the light emitting regions of each pixel PXL may be provided on the first substrate SUB1 on which the first electrode AD and the like are provided. The pixel defining film 117 may expose the upper surface of the first electrode AD and may protrude from the first substrate SUB1 along the outer periphery of each light emitting region.

[0266] The light emitting element region or the light emitting element layer LDL may be provided in the light emitting region of each pixel PXL surrounded by the pixel defining film 117, and the second electrode CD may be provided on the light emitting element layer LDL. One of the first electrode AD and the second electrode CD may be an anode electrode and the other may be a cathode electrode. For example, the first electrode AD may be an anode electrode and the second electrode CD may be a cathode electrode.

[0267] The pixel defining film 117 may include an organic insulating material. For example, the pixel defining film 117 may include at least one of polystyrene, polymethyl methacrylate (“PMMA”), polyacrylonitrile (“PAN”), polyamide (“PA”), polyimide (“PI”), polyarylether (“PAE”), heterocyclic polymers, chemical vapor deposition polymers sold under the trade name PARYLENE by Specialty Coating Systems of Indianapolis, Indiana, epoxy resins, benzocyclobutene (“BCB”), siloxane resins, and silane resins.

[0268] The first protective layer PTL1 covering the second electrode CD may be provided as layer 118 on the second electrode CD. The first protective layer PTL1 may be formed of a thin film encapsulation layer. In an embodiment, the thin film encapsulation layer may be replaced with at least one layer of another type of encapsulation film, encapsulation substrate, protective film, etc.

[0269] The thin film encapsulation layer may prevent oxygen and moisture from permeating into the light emitting element LD. To this end, the thin film encapsulation layer may include an inorganic film. The inorganic film may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.

[0270] Each of the circuit elements and wirings provided on the first surface of the first substrate SUB1 from the buffer layer 112 to the protective layer 116 may constitute the circuit element layer BPL of the display device 10 and / or the fingerprint sensor. In addition, the light emitting element LD from the first electrode AD to the second electrode CD provided in each pixel PXL and the thin film encapsulation layer provided between the light emitting elements LD may constitute the light emitting element layer LDL of the display device 10 and / or the fingerprint sensor.

[0271] Further refer to Figures 11 to 13, the pixel PXL may include a first light-transmitting hole LTH1 formed in at least one conductive layer of the circuit element layer BPL. The sensing region SA may include a plurality of pixels PXL including the first light-transmitting hole LTH1.

[0272] The first light-transmitting hole LTH1 may include a multi-layer opening portion MLO formed to overlap with a plurality of conductive layers constituting the circuit element layer BPL. For example, the first light-transmitting hole LTH1 may include a multi-layer opening portion MLO formed to overlap with at least two of a semiconductor layer in which an active pattern ACT of the circuit element layer BPL is provided, a first conductive layer in which gate electrodes GE1 to GE7 are provided, a second conductive layer in which a second capacitor electrode UE and the like are provided, and a third conductive layer in which a power line PL and a bridging pattern BRP and the like are provided.

[0273] According to the above embodiment, a light-transmitting hole array for receiving reflected light can be integrally formed with the light-emitting element layer LDL and the circuit element layer BPL without forming an additional layer in the circuit element layer BPL. Therefore, the module thickness of the display device 10 can be reduced.

[0274] On the other hand, in various exemplary embodiments of the invention, the position and form of the first light-transmitting hole LTH1 are not limited to Figures 15 to 17 the position and form shown therein. That is, in various other embodiments, the first light-transmitting hole LTH1 may be formed in another region (for example, a region including an opening portion OPN formed in the first gate electrode GE1). In such an embodiment, various modifications can be made to the layout structure so that the conductive layer is not provided in the first light-transmitting hole LTH1.

[0275] The size (width or diameter) of the first light-transmitting hole LTH1 may be determined by the size of the multi-layer opening portion MLO. For example, the width w' of the first light-transmitting hole LTH1 may be determined as the minimum width among the widths of the multi-layer opening portion MLO.

[0276] At least a part of the multi-layer opening portion MLO forming the first light-transmitting hole LTH1 may overlap with the pinhole PIH of the light-shielding layer PHL described with reference to Figures 7 to 12C In such an embodiment, the width w' of the first light-transmitting hole LTH1 may be the same as or different from the width w of the pinhole PIH.

[0277] In an embodiment, the width w' of the first light-transmitting hole LTH1 may be smaller than the width w of the pinhole PIH. For example, the pinhole PIH and the first light-transmitting hole LTH1 may have widths in the range of about 5 μm to about 20 μm, and the width w' of the first light-transmitting hole LTH1 may be set to be smaller than the width w of the pinhole PIH.

[0278] In an embodiment, when the pinhole PIH and the first light-transmitting hole LTH1 have a substantially rectangular shape, the length of the first side of the pinhole PIH may be about 8.5 μm, and the length of the second side perpendicular to the first side may be about 9.4 μm. Further, in such an embodiment, the length of the first side of the first light-transmitting hole LTH1 may be about 4.5 μm, and the length of the second side perpendicular to the first side may be about 5.4 μm. Such values are merely examples, and the exemplary embodiments of the invention are not limited thereto.

[0279] In an embodiment in which the first light-transmitting hole LTH1 has a size smaller than that of the pinhole PIH, the first light-transmitting hole array layer LTHL1 may perform the function of a light control layer LBL that controls the path of light (e.g., limits the field of view of reflected light to a predetermined angular range), and the light-shielding layer PHL may perform a light-blocking function.

[0280] However, the exemplary embodiments of the invention are not limited thereto. That is, in another embodiment, the width w' of the first light-transmitting hole LTH1 may be larger than the width w of the pinhole PIH. In such an embodiment, the first light-transmitting hole array layer LTHL1 may perform a light-blocking function, and the light-shielding layer PHL may perform the function of a light control layer LBL that controls the path of light.

[0281] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but rather to the appended claims and the broader scope of various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A fingerprint sensor for a display device, the fingerprint sensor comprising: A substrate having a first surface and a second surface; A light-transmissive layer including a first layer and a second layer, the first layer including at least one first conductive layer and being disposed on the first surface of the substrate and having a first opening in the at least one first conductive layer, the second layer including at least one second conductive layer and being disposed on the first surface of the substrate and having a second opening in the at least one second conductive layer; A light-emitting element layer disposed on the first layer and the second layer and having at least one light-emitting element; And A sensor layer disposed on the second surface of the substrate and having a photosensor, Wherein at least a part of the first opening and at least a part of the second opening are at least partially overlapped and have different sizes, Wherein the second layer includes circuit elements to control the light emission of the at least one light-emitting element, Wherein the second layer includes: a semiconductor layer including an active pattern of the circuit elements; a first gate layer including a gate electrode overlapped with the active pattern and a light-emitting control line for supplying a light emission control signal to the circuit elements; a source-drain layer including a source electrode and a drain electrode connected to the active pattern and a power supply line for applying power to the circuit elements; and a second gate layer disposed between the first gate layer and the source-drain layer and including at least one capacitor electrode and an initialization power supply line for supplying an initialization power supply to the circuit elements.

2. The fingerprint sensor according to claim 1, wherein, The first opening and the second opening have a width or diameter between 5 μm and 20 μm.

3. The fingerprint sensor according to claim 1, wherein, The first opening and the second opening have a quadrilateral shape, wherein the width in a first direction and the width in a second direction perpendicular to the first direction are the same or different.

4. The fingerprint sensor according to claim 1, wherein, The width of the first opening is larger than the width of the second opening.

5. The fingerprint sensor according to claim 4, wherein, The first layer includes a first light-shielding layer to block some of the ambient incident light and allow the remaining ambient incident light to transmit through the first opening, and The second layer includes a second light-shielding layer to limit the field of view of the ambient incident light.

6. The fingerprint sensor according to claim 1, wherein, The second opening includes a multi-layer opening portion that overlaps each other between the circuit elements disposed in the semiconductor layer, the first gate layer, the second gate layer, and the source-drain layer.

7. The fingerprint sensor according to claim 1, wherein, The distance between the semiconductor layer and the source-drain layer is 300 μm or less.

8. The fingerprint sensor according to claim 1, wherein, The second opening includes a multi-layer opening adjacent to and overlapping with the active pattern, the light-emitting control line, the initialization power supply line, and the power supply line.

9. The fingerprint sensor according to claim 1, the fingerprint sensor further comprising: A protective layer disposed between the substrate and the sensor layer; And An adhesive layer disposed between the substrate and the protective layer.

10. A display device, the display device comprising: A substrate having a first surface and a second surface; A light-transmissive layer disposed on the first surface of the substrate and including a first opening having a first size; A circuit element layer is disposed on the first surface of the substrate and includes a plurality of conductive layers and a second opening located in the plurality of conductive layers. The second opening has at least a part that overlaps with the first opening and has a second size different from the first size; A light-emitting element layer is disposed on the circuit element layer and includes at least one light-emitting element; And A sensor layer is disposed on the second surface of the substrate and includes a photosensor, wherein the circuit element layer includes circuit elements to control the light emission of the at least one light-emitting element, wherein the circuit element layer includes: a semiconductor layer including an active pattern of the circuit elements; a first gate layer including a gate electrode overlapping with the active pattern and a light-emission control line for supplying a light-emission control signal to the circuit elements; a second gate layer disposed on the first gate layer and including at least one capacitor electrode and an initialization power supply line for supplying an initialization power supply to the circuit elements; and a source-drain layer disposed on the second gate layer and including a source electrode and a drain electrode connected to the active pattern and a power supply line for applying power to the circuit elements.

11. The display device according to claim 10, wherein, The first opening and the second opening have a width or diameter between 5 μm and 20 μm.

12. The display device according to claim 10, wherein, The first size includes a first width, and the second size includes a second width, and the first width is greater than the second width.

13. The display device according to claim 12, wherein, The light-transmitting layer includes: a light-shielding layer that blocks some of the ambient incident light and allows the remaining ambient incident light to transmit through the first opening; and the circuit element layer that limits the field of view of the ambient incident light.

14. The display device according to claim 10, wherein, The distance between the semiconductor layer and the source-drain layer is 300 μm or less.

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