Processing devices, network nodes, client devices, and methods thereof

Abstract

This application discloses a synchronization signal design scheme, processing device, and system, which can be applied to, for example, new wireless systems. A first cyclic shift and a second cyclic shift are determined at least based on a cell identifier, wherein at least one of the first cyclic shift and the second cyclic shift is associated with the primary synchronization signal sequence. A secondary synchronization signal sequence is generated based on a first binary sequence that has been cyclically shifted by the first cyclic shift and a second binary sequence that has been cyclically shifted by the second cyclic shift. The secondary synchronization signal sequence is used together with the primary synchronization signal sequence for synchronization.

Description

Technical Field

[0001] This invention relates to a processing device and a network node and client device including the processing device. Furthermore, this invention also relates to corresponding methods and computer programs. Background Technology

[0002] Synchronization is fundamental to most telecommunications systems, such as those based on Long Term Evolution (LTE) or LTE-Advanced. For client devices to perform synchronization with the network, each cell in the network must have at least one transmit-receive point (TRP) periodically transmitting a synchronization signal. These synchronization signals are detected by nearby client devices and used by each client device to identify the appropriate cell as its serving cell. Therefore, synchronization allows client devices to acquire connections to TRPs and track connections between them for subsequent data communication.

[0003] In LTE cellular systems, synchronization signals include the primary synchronization signal (PSS) and the secondary synchronization signal (SSS). Both the PSS and SSS are transmitted within each cycle, i.e., every 5 milliseconds (ms), on unique orthogonal frequency division multiplexing (OFDM) symbols. There are 3 PSSs and 168 SSSs, collectively used to carry 3 × 168 = 504 cell identifiers (IDs). ID These 168 SSSs are further scrambled using a PSS sequence index, and this scrambling is used to indicate the timing of the first and second half frames. Different PSS and SSS sequence pairs carry different cell IDs and are transmitted by TRPs in different cells. The client device first obtains coarse time-frequency synchronization by detecting the PSS in the time domain and the index carried in the PSS. The client device obtains the index carried in the SSS by detecting the SSS in the frequency domain. Then through The community identifier N is obtained. ID Specifically, the PSS sequence is constructed based on a Zadoff Chu (ZC) sequence of length 63 with three different root indices, and the SSS sequence is constructed by interleaving and concatenating two m sequences m0 and m1 of length 31 with different cyclic shifts. The two short m-sequences are further scrambled, resulting in 168 SSS sequences associated with each PSS sequence, and the second m-sequence is scrambled based on a cyclic shift of the first m-sequence. This is achieved through indexing. and The unique invertible mapping between cyclic shifts m0 and m1, in the SSS sequence for cell ID N ID Encode it.

[0004] The 3rd Generation Partnership Project (3GPP) is currently working on defining New Radio (NR) access technology. A consensus has been reached that synchronization in NR will use three NR PSS sequences, which are based on m-sequences modulated with binary phase-shift keying (BPSK) with three different cyclic shifts. Furthermore, the number of scrambled NR SSS sequences should be approximately 1000, meaning each PSS sequence corresponds to approximately 333 SSS sequences. Therefore, these three NR PSS sequences can provide approximately 3 × 333 ≈ 1000 cell IDs, which is about twice the number of cell IDs provided in LTE.

[0005] Current LTE SSS designs cascade two short m-sequences. Due to the existence of numerous SSS sequence pairs, and the fact that one of the two short m-sequences has the same cyclic shift, there is a high risk of cross-correlation. This high risk of cross-correlation can lead to a high probability of false cell ID detection, especially during handover processes. Summary of the Invention

[0006] The purpose of this invention is to provide a solution that can mitigate or resolve the drawbacks and problems of traditional solutions.

[0007] The solutions provided in the independent claims can achieve the above or other objectives. Other advantageous embodiments are provided in the dependent claims.

[0008] According to a first aspect of the present invention, a processing apparatus is provided for achieving the above or other objectives, the processing apparatus being configured to generate an auxiliary synchronization signal to be used for synchronization together with a primary synchronization signal sequence, the processing apparatus being configured to:

[0009] At least based on cell ID N ID A first cyclic shift m0 and a second cyclic shift m1 are determined, wherein at least one of the first cyclic shift m0 and the second cyclic shift m1 is associated with the master synchronization signal sequence, the master synchronization signal sequence being based on an index of the master synchronization signal sequence. Confirmed; and

[0010] The auxiliary synchronization signal sequence is generated by modulo-2 summation of the first binary sequence of cyclic shift first cyclic shift m0 and the second binary sequence of cyclic shift second cyclic shift m1, such that if two generated auxiliary synchronization signal sequences associated with the primary synchronization signal sequence are cyclically shifted versions of each other, the two generated auxiliary synchronization signal sequences are discontinuously shifted versions of each other.

[0011] Therefore, the two secondary synchronization signal sequences associated with the primary synchronization signal sequence should be cyclically shifted versions of each other, not consecutively shifted versions. In other words, the generated first and second secondary synchronization signal sequences are both associated with the same primary synchronization signal sequence, wherein the first secondary synchronization signal sequence can be implemented by cyclically shifting the second generated secondary synchronization signal sequence, and / or the second secondary synchronization signal sequence can be implemented by cyclically shifting the first secondary synchronization signal sequence. This applies when the first and second secondary synchronization signal sequences are non-consecutive shifted versions of each other, i.e., the first generated secondary synchronization signal sequence can be implemented by cyclically shifting the second generated secondary synchronization signal sequence by two or more steps, and / or the second generated secondary synchronization signal sequence can be implemented by cyclically shifting the first generated secondary synchronization signal sequence by two or more steps.

[0012] The processing device according to the first aspect offers many advantages over conventional solutions. The advantage of the processing device lies in its ability to generate the secondary synchronization signal (SSS) sequence in a simple and efficient manner, facilitating low complexity and efficient coding of the cell ID.

[0013] By generating a secondary synchronization signal SSS sequence, low cross-correlation between the secondary synchronization signal SSS sequences that take into account frequency offset is provided, thereby improving the reliability of secondary synchronization signal SSS sequence detection in the client equipment and thus reducing cell search time.

[0014] Furthermore, by generating and using the secondary synchronization signal SSS sequence, it becomes possible to use closed-form codec mapping functions to efficiently and with low complexity obtain the sequence index from the cell ID or vice versa. This reduces the complexity of network nodes and client devices and provides a fast and efficient method for determining the cell ID. At the client device, the descrambled received signal can be detected efficiently, for example, by utilizing the fast Walsh-Hadamard transform (FWHT).

[0015] Therefore, the embodiments described herein can efficiently encode the cell ID into the secondary synchronization SSS sequence, which ensures low cross-correlation between SSS sequences even under large residual frequency offsets, and the mapping from cell ID to the first and second cyclic shift values ​​is simple, and vice versa.

[0016] According to the first aspect, in one embodiment of the processing device, the first and second binary sequences are one of the following:

[0017] m-sequence; or

[0018] This results in the generated auxiliary synchronization signal sequence belonging to an m-sequence of a set of Gold sequences.

[0019] The advantage of this implementation is that when the first and second binary sequences used to generate the secondary synchronization signal SSS sequence are m-sequences, especially if they are m-sequences that cause the generated secondary synchronization signal SSS sequence to belong to a set of Gold sequences, low cross-correlation between the generated SSS sequences is guaranteed.

[0020] According to the first aspect, in one embodiment of the processing device, one of the first and second binary sequences used to generate the secondary synchronization signal SSS sequence is the same sequence as the sequence used to generate one or more primary synchronization signals PSS sequences, for example, the same pseudo-random maximum length sequence.

[0021] According to the first aspect, in one embodiment of the processing device, the plurality of master synchronization signal sequences that can be used for synchronization are one of the following:

[0022] A master synchronization signal sequence;

[0023] Two or more master synchronization signal sequences; or

[0024] Three master synchronization signal sequences.

[0025] One advantage of this implementation is its flexibility in generating synchronization signals for a large number of cell IDs. Using a single primary synchronization signal (PSS) sequence reduces the complexity of primary synchronization signal detection. Using two or more, such as three, primary synchronization signal PSS sequences allows a subset of secondary synchronization signal (SSS) sequences to be associated with each primary synchronization signal PSS sequence. Accordingly, after successful primary synchronization signal detection, only a subset of the secondary synchronization signal (SSS) sequences needs to be detected, thereby reducing the complexity of secondary synchronization signal (SSS) detection. Therefore, this implementation is advantageous because it provides a trade-off between the detection complexity of primary and secondary synchronization signals.

[0026] According to the first aspect, in one embodiment of the processing device, the length L of the generated auxiliary synchronization signal sequence is 127; that is, L = 127.

[0027] One advantage of this implementation is that the generation of the secondary synchronization signal (SSS) can be used in many available and future wireless systems.

[0028] According to the first aspect, in one embodiment of the processing device, the processing device is further configured to determine, based on one or more of the following, a cell ID N with respect to at least one cell. ID The associated first cyclic shift m0 and second cyclic shift m1:

[0029] The first cyclic shift m0 and the second cyclic shift m1 are equal; that is, m0 = m1.

[0030] The first cyclic shift m0 and the second cyclic shift m1 are different; that is, m0 ≠ m1.

[0031] The first cyclic shift m0 is greater than the second cyclic shift m1; that is, m0 > m1.

[0032] The first cyclic shift m0 is less than the second cyclic shift m1; that is, m0 < m1.

[0033] Two circular shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1;

[0034] Two cyclic shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, and the first cyclic shift m0 is greater than the second cyclic shift m1; that is, m0 > m1.

[0035] Two cyclic shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, and the first cyclic shift m0 is less than the second cyclic shift m1; that is, m0 < m1.

[0036] Two cyclic shift pairs (m0, m1) and (m'0, m'1) that both satisfy m'0 = m0 + 1 and m'1 = m1 + 1 are associated with different master synchronization signal sequence indices;

[0037] Two cyclic shift pairs (m0, m1) and (m'0, m'1) that both satisfy m'0 = m0 + 1 and m'1 = m1 + 1 are associated with different master synchronization signal sequence indices, and the first cyclic shift m0 is greater than the second cyclic shift m1; that is, m0 > m1; and

[0038] Two cyclic shift pairs (m0, m1) and (m′0, m′1) that both satisfy m′0 = m0 + 1 and m′1 = m1 + 1 are associated with different master synchronization signal sequence indices, and the first cyclic shift m0 is less than the second cyclic shift m1; that is, m0 < m1.

[0039] One advantage of this implementation is its ability to flexibly generate the secondary synchronization signal (SSS) sequence, which is robust against large frequency offsets. It also has the advantage of being able to further encode 5ms timing and / or other additional information into the SSS sequence.

[0040] According to the first aspect, in one embodiment of the processing device, the processing device is further configured to determine the first cyclic shift m0 and the second cyclic shift m1, wherein m0 and m1 satisfy:

[0041]

[0042]

[0043] in,

[0044] g is an integer greater than 1;

[0045] L′ is a positive integer less than or equal to the length L of the auxiliary synchronization signal sequence;

[0046] It is the index of the auxiliary synchronization signal sequence; where

[0047] It is the index of the main synchronization signal sequence; where

[0048] It is the floor function; and

[0049] mod is the modulo operation.

[0050] One advantage of this implementation is its robustness against large frequency offsets. This implementation also fully utilizes all cyclic shifts m1 of the second binary sequence; for example, by setting L′ = L, the candidate cyclic shift m0 of the first binary sequence remains at its minimum for a given total number of cell IDs to be encoded into the secondary synchronization signal SSS sequence. This allows for low-complexity detection of the secondary synchronization signal SSS sequence at the client device, thus offering an advantage. In other words, the client device can first descramble the received signal sequence using the minimum number of cyclic shift assumptions of the first binary sequence, such that after descrambling according to the correct cyclic shift assumptions of the first binary sequence, the remaining received signal sequence is only a second binary sequence with some unknown cyclic shifts, and can be detected using the low-cost Fast Walsh-Hadamard Transform (FWHT) operation.

[0051] According to the first aspect, in one embodiment of the processing device, the processing device is further configured to determine the first cyclic shift m0 and the second cyclic shift m1, wherein m0 and m1 satisfy:

[0052]

[0053]

[0054] in,

[0055] g is an integer greater than 1;

[0056] L′ is a positive integer less than or equal to the length L of the auxiliary synchronization signal sequence;

[0057] It is the index of the auxiliary synchronization signal sequence; where

[0058] It is the index of the main synchronization signal sequence; where

[0059] It is the floor function; and

[0060] mod is the modulo operation.

[0061] One advantage of this implementation is its robustness against large frequency shifts. This implementation also allows for low-cost detection of the secondary synchronization signal SSS sequence at the client device based on descrambling and FWHT operation. Furthermore, this implementation generates a first cyclic shift m0 and a second cyclic shift m1, both satisfying m0 < m1 (or m0 > m1). This allows for further encoding of 5ms timing and / or other additional information into the secondary synchronization signal SSS sequence by simply swapping the values ​​of m0 and m1. Alternatively, if it is deemed useful to subsequently increase the number of assumptions in the secondary synchronization signal SSS sequence, this constitutes a future-proof solution.

[0062] According to the first aspect, in one embodiment of the processing device, the processing device is further configured to determine the first cyclic shift m0 and the second cyclic shift m1, wherein m0 and m1 satisfy:

[0063]

[0064]

[0065] in,

[0066] g is an integer equal to or greater than 1;

[0067] L′ is a positive integer less than or equal to the length L of the auxiliary synchronization signal sequence;

[0068] It is the index of the auxiliary synchronization signal sequence; where

[0069] It is the index of the main synchronization signal sequence; where

[0070] It is the floor function; and

[0071] mod is the modulo operation.

[0072] One advantage of this implementation is its robustness against large frequency offsets. This implementation also allows for low-cost detection of the secondary synchronization signal SSS sequence at the client equipment based on descrambling and FWHT operations. Furthermore, when g=1, this implementation allows the selection of two cyclic shift pairs (m0, m1) and (m'0, m'1) that both satisfy m'0 = m0+1 and m'1 = m1+1, but this associates the corresponding pair of secondary synchronization signal SSS sequences with different primary synchronization signal PSS sequence indices. Therefore, more valid values ​​can be selected for the cyclic shift pair (m0, m1), potentially enabling the encoding of a larger number of cell IDs into the secondary synchronization signal SSS sequence without increasing the SSS sequence length.

[0073] According to the first aspect, in one embodiment of the processing device, the processing device is further configured to determine the first cyclic shift m0 and the second cyclic shift m1, wherein m0 and m1 satisfy:

[0074]

[0075]

[0076] in,

[0077] g is an integer equal to or greater than 1;

[0078] L′ is a positive integer less than or equal to the length L of the auxiliary synchronization signal sequence;

[0079] It is the index of the auxiliary synchronization signal sequence; where

[0080] It is the index of the main synchronization signal sequence; where

[0081] It is the floor function; and

[0082] mod is the modulo operation.

[0083] One advantage of this implementation is its robustness against large frequency offsets. This implementation also allows for low-cost detection of the secondary synchronization signal SSS sequence at the client device based on descrambling and FWHT operation. Furthermore, when g=1, this implementation allows the selection of two cyclic shift pairs (m0, m1) and (m'0, m'1) that both satisfy m'0 = m0+1 and m'1 = m1+1, but associates the corresponding pair of secondary synchronization signal SSS sequences with different primary synchronization signal PSS sequence indices. Therefore, more valid values ​​can be selected for the cyclic shift pair (m0, m1), potentially enabling the encoding of a larger number of cell IDs into the secondary synchronization signal SSS sequence without increasing the SSS sequence length. Additionally, this implementation generates a first cyclic shift m0 and a second cyclic shift m1, both satisfying m0 < m1 (or m0 > m1). This allows for further encoding of 5ms timing and / or other additional information into the secondary synchronization signal SSS sequence by simply swapping the values ​​of m0 and m1. Alternatively, if it is considered useful to subsequently increase the number of hypotheses in the secondary synchronization signal SSS sequence, then a future-oriented solution is proposed.

[0084] According to a second aspect of the present invention, the above or other objectives are achieved through a network node, the network node comprising:

[0085] Processing apparatus for generating a secondary synchronization signal sequence according to the first aspect or any embodiment of the first aspect; and

[0086] A transceiver for transmitting synchronization signals based on a primary synchronization signal sequence and the secondary synchronization signal sequence.

[0087] The network node according to the second aspect offers many advantages over traditional solutions. The advantage of the network node lies in its ability to generate the secondary synchronization signal (SSS) sequence in a simple and efficient manner.

[0088] According to a third aspect of the present invention, the above and other objectives are achieved by a client device, said client device comprising:

[0089] Processing equipment for determining cell ID N based on a first cyclic shift m0 and a second cyclic shift m1. ID The first cyclic shift and the second cyclic shift are determined based on the received primary synchronization signal and the received secondary synchronization signal;

[0090] A transceiver for receiving a secondary synchronization signal using the secondary synchronization signal sequence.

[0091] The processing device is also used to generate an auxiliary synchronization signal according to the first aspect or any embodiment of the first aspect.

[0092] The client device according to the third aspect offers many advantages over traditional solutions. The advantage of the client device is that it can decode the cell ID N from the first cyclic shift m0 and the second cyclic shift m1 in a simple and efficient manner. ID The first and second cyclic shifts are determined from the detected secondary synchronization signal (SSS) sequence. The secondary synchronization signal (SSS) sequence can be detected in a low-complexity manner, and it can also be generated in a simple and effective way.

[0093] According to a fourth aspect of the present invention, the above or other objectives are achieved by a method for determining a secondary synchronization signal sequence to be used for synchronization together with a primary synchronization signal sequence, the method comprising:

[0094] At least based on cell ID N ID A first cyclic shift m0 and a second cyclic shift m1 are determined, wherein at least one of the first cyclic shift m0 and the second cyclic shift m1 is associated with the master synchronization signal sequence, the master synchronization signal sequence being further based on an index of the master synchronization signal sequence. Confirmed; and

[0095] The secondary synchronization signal sequence is generated by modulo-2 summation of the first binary sequence of the first cyclic shift m0 and the second binary sequence of the second cyclic shift m1, such that if two secondary synchronization signal sequences associated with the primary synchronization signal sequence are cyclic shift versions of each other, then the two secondary synchronization signal sequences are discontinuous shift versions of each other.

[0096] According to the method of the fourth aspect, in one embodiment, the first and second binary sequences are one of the following:

[0097] m-sequences; and

[0098] This makes the generated auxiliary synchronization signal sequence belong to an m-sequence of a set of Gold sequences.

[0099] According to the fourth aspect, in one embodiment of the method, the plurality of master synchronization signal sequences that can be used for synchronization are one of the following:

[0100] A master synchronization signal sequence;

[0101] Two or more master synchronization signal sequences; and

[0102] Three master synchronization signal sequences.

[0103] According to the fourth aspect, in one embodiment of the method, the length L of the auxiliary synchronization signal sequence is 127; that is, L = 127.

[0104] According to the fourth aspect, in one embodiment of the method, the method further includes: determining a cell ID N based on one or more of the following. ID The associated first cyclic shift m0 and second cyclic shift m1:

[0105] The first cyclic shift m0 and the second cyclic shift m1 are equal; that is, m0 = m1.

[0106] The first cyclic shift m0 and the second cyclic shift m1 are different; that is, m0 ≠ m1.

[0107] The first cyclic shift m0 is greater than the second cyclic shift m1; that is, m0 > m1.

[0108] The first cyclic shift m0 is less than the second cyclic shift m1; that is, m0 < m1.

[0109] Two circular shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1;

[0110] Two cyclic shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, and the first cyclic shift m0 is greater than the second cyclic shift m1; that is, m0 > m1.

[0111] Two cyclic shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, and the first cyclic shift m0 is less than the second cyclic shift m1; that is, m0 < m1.

[0112] Two cyclic shift pairs (m0, m1) and (m'0, m'1) that both satisfy m'0 = m0 + 1 and m'1 = m1 + 1 are associated with different master synchronization signal sequence indices;

[0113] Two cyclic shift pairs (m0, m1) and (m'0, m'1) that both satisfy m'0 = m0 + 1 and m'1 = m1 + 1 are associated with different master synchronization signal sequence indices, and the first cyclic shift m0 is greater than the second cyclic shift m1; that is, m0 > m1; and

[0114] Two cyclic shift pairs (m0, m1) and (m′0, m′1) that both satisfy m′0 = m0 + 1 and m′1 = m1 + 1 are associated with different master synchronization signal sequence indices, and the first cyclic shift m0 is less than the second cyclic shift m1; that is, m0 < m1.

[0115] According to the fourth aspect, in one embodiment of the method, the method further includes determining the first cyclic shift m0 and the second cyclic shift m1, wherein m0 and m1 satisfy:

[0116]

[0117]

[0118] in,

[0119] g is an integer greater than 1;

[0120] L′ is a positive integer less than or equal to the length L of the auxiliary synchronization signal sequence;

[0121] It is the index of the auxiliary synchronization signal sequence; where

[0122] It is the index of the main synchronization signal sequence; where

[0123] It is the floor function; and

[0124] mod is the modulo operation.

[0125] According to the fourth aspect, in one embodiment of the method, the method further includes determining the first cyclic shift m0 and the second cyclic shift m1, wherein m0 and m1 satisfy:

[0126]

[0127]

[0128] in,

[0129] g is an integer greater than 1;

[0130] L′ is a positive integer less than or equal to the length L of the auxiliary synchronization signal sequence;

[0131] It is the index of the auxiliary synchronization signal sequence; where

[0132] It is the index of the main synchronization signal sequence; where

[0133] It is the floor function; and

[0134] mod is the modulo operation.

[0135] According to the fourth aspect, in one embodiment of the method, the method further includes determining the first cyclic shift m0 and the second cyclic shift m1, wherein m0 and m1 satisfy:

[0136]

[0137]

[0138] in,

[0139] g is an integer equal to or greater than 1;

[0140] L′ is a positive integer less than or equal to the length L of the auxiliary synchronization signal sequence;

[0141] It is the index of the auxiliary synchronization signal sequence; where

[0142] It is the index of the main synchronization signal sequence; where

[0143] It is the floor function; and

[0144] mod is the modulo operation.

[0145] According to the fourth aspect, in one embodiment of the method, the method further includes determining the first cyclic shift m0 and the second cyclic shift m1, wherein m0 and m1 satisfy:

[0146]

[0147]

[0148] in,

[0149] g is an integer equal to or greater than 1;

[0150] L′ is a positive integer less than or equal to the length L of the auxiliary synchronization signal sequence;

[0151] It is the index of the auxiliary synchronization signal sequence; where

[0152] It is the index of the main synchronization signal sequence; where

[0153] It is the floor function; and

[0154] mod is the modulo operation.

[0155] The advantages of the method described in the fourth aspect can be referred to the advantages of the corresponding processing apparatus claims in the first aspect.

[0156] According to a fifth aspect of the present invention, the above or other objectives are achieved by a method for a network node, the method comprising:

[0157] Generate a secondary synchronization signal sequence according to the method of the fourth aspect; and

[0158] Synchronization signals are transmitted based on the primary synchronization signal sequence and the secondary synchronization signal sequence.

[0159] The advantages of the method described in the fifth aspect can be seen in the advantages of the corresponding network node claims in the second aspect.

[0160] According to a sixth aspect of the present invention, the above and other objectives are achieved by a method for a client device, the method comprising:

[0161] Receive auxiliary synchronization signal; and

[0162] Cell ID N is determined based on the first cyclic shift m0 and the second cyclic shift m1. IDThe first cyclic shift and the second cyclic shift are determined based on the received primary synchronization signal and the received secondary synchronization signal.

[0163] Optionally, the method may further include generating a secondary synchronization signal sequence according to the method of the fourth aspect, and receiving a secondary synchronization signal using the generated secondary synchronization signal sequence.

[0164] The advantages of the method described in the sixth aspect can be seen in the advantages of the corresponding client device claims in the third aspect.

[0165] The present invention also relates to a computer program characterized by a code means, which, when run by a processing means, causes the processing means to perform the method according to any aspect of the present invention. Furthermore, the present invention relates to a computer program product comprising a computer-readable medium and the aforementioned computer program, wherein the computer program is contained in the computer-readable medium and includes one or more of the following means: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), flash memory, electrically erasable EPROM (EEPROM), and hard disk drive.

[0166] Other applications and advantages of the present invention will become apparent from the following detailed description. Attached Figure Description

[0167] The accompanying drawings are intended to illustrate and explain various embodiments of the present invention, wherein:

[0168] - Figure 1 A processing apparatus according to an embodiment of the present invention is shown;

[0169] - Figure 2 A method for processing equipment according to an embodiment of the present invention is shown;

[0170] - Figure 3 A network node according to an embodiment of the present invention is shown;

[0171] - Figure 4 A method for a network node according to an embodiment of the present invention is shown;

[0172] - Figure 5 A client device according to an embodiment of the present invention is shown;

[0173] - Figure 6 A method for a client device according to an embodiment of the present invention is shown;

[0174] - Figure 7 A wireless system according to an embodiment of the present invention is shown;

[0175] - Figure 8 A diagram illustrating the determination of a cyclic shift according to an embodiment of the present invention is shown;

[0176] - Figure 9 Another illustration of determining a cyclic shift according to an embodiment of the present invention is shown;

[0177] - Figure 10 Another illustration of determining a cyclic shift according to an embodiment of the present invention is shown;

[0178] - Figure 11 Another illustration of determining a cyclic shift according to an embodiment of the present invention is shown;

[0179] - Figure 12 Another illustration of determining a cyclic shift according to an embodiment of the present invention is shown;

[0180] - Figure 13 Another illustration of determining a cyclic shift according to an embodiment of the present invention is shown. Detailed Implementation

[0181] Figure 1 A processing apparatus 100 according to an embodiment of the present invention is shown. The processing apparatus 100 includes a processor 102 coupled to a memory 104. The processor 102 and the memory 104 are coupled to each other via a communication device 106 known in the art. In one embodiment, the processor 102 may be a dedicated processor for performing the generation of a secondary synchronization signal SSS sequence according to the present invention. In some embodiments, the processor 102 is a processor in a network node or client device and may also have other additional functions.

[0182] Processing device 100 for generating a secondary synchronization signal SSS sequence to be synchronized together with the primary synchronization signal PSS sequence is used, for example, by processor 102, at least based on cell ID N. ID Determine a first cyclic shift m0 and a second cyclic shift m1, wherein at least one of the first cyclic shift m0 and the second cyclic shift m1 is associated with a master synchronization signal PSS sequence, the master synchronization signal PSS sequence being based on an index of the master synchronization signal PSS sequence. Sure.

[0183] The processing device 100 is also used, for example by the processor 102, to generate a secondary synchronization signal SSS sequence based on the modulo-2 summation of a first binary sequence cyclically shifted by a first cyclic shift m0 and a second binary sequence cyclically shifted by a second cyclic shift m1, such that if two generated secondary synchronization signal SSS sequences associated with the primary synchronization signal PSS sequence are cyclically shifted versions of each other, then the two generated secondary synchronization signal SSS sequences are discontinuously shifted versions of each other.

[0184] Figure 2 It shows that it can be done in such a way Figure 1 A flowchart of the corresponding method 200 executed in the processing device 100 shown.

[0185] Method 200 includes a first step 202, based at least on cell ID N. ID A first cyclic shift m0 and a second cyclic shift m1 are determined, wherein at least one of the first cyclic shift m0 and the second cyclic shift m1 is associated with a master synchronization signal sequence, the master synchronization signal sequence being further based on an index of the master synchronization signal sequence. Sure.

[0186] The method further includes a second step 204, generating a secondary synchronization signal SSS sequence based on the modulo-2 summation of the first binary sequence of the first cyclically shifted sequence m0 and the second binary sequence of the second cyclically shifted sequence m1, such that if two generated secondary synchronization signal SSS sequences associated with the primary synchronization signal PSS sequence are cyclically shifted versions of each other, then the two generated secondary synchronization signal SSS sequences are discontinuously shifted versions of each other.

[0187] Figure 3 A network node 300 according to an embodiment of the present invention is shown. Figure 3 In the illustrated embodiment, network node 300 includes processing device 100, transceiver 302, and memory 304. Processing device 100 is coupled to transceiver 302 and memory 304 via a communication device 306 known in the art. Network node 300 also includes an antenna 308 coupled to transceiver 302, meaning that network node 300 is used for wireless communication in a wireless communication system.

[0188] The processing device 100 of network node 300 is used to generate a secondary synchronization signal SSS sequence according to any embodiment of the method 200 described herein. The transceiver 302 of network node 300 is used to transmit synchronization signals based on the primary synchronization signal PSS sequence and the secondary synchronization signal SSS sequence.

[0189] Figure 4 A flowchart of the corresponding method 400 that can be executed in network node 300 is shown, for example. Figure 3The network node 300 is shown. Method 400 includes a first step 402, namely generating a secondary synchronization signal SSS sequence according to any embodiment of the method 200 described herein. The method further includes a second step 404, transmitting a synchronization signal based on the primary synchronization signal PSS sequence and the secondary synchronization signal SSS sequence.

[0190] Figure 5 A client device according to an embodiment of the present invention is shown. Figure 5 In the illustrated embodiment, client device 500 includes processing device 100, transceiver 502, and memory 504. Processing device 100 is coupled to transceiver 502 and memory 504 via a communication device 506 known in the art. Client device 500 also includes an antenna 508 coupled to transceiver 502, meaning that client device 500 is used for wireless communication in a wireless communication system.

[0191] The processing device 100 of the client device 500 is used to generate a secondary synchronization signal SSS sequence according to any embodiment described herein. The transceiver 502 of the client device 500 is used to receive the secondary synchronization signal SSS. For example, the generated secondary synchronization signal SSS sequence is used to receive the secondary synchronization signal SSS. The processing device 100 is also used to determine the cell ID N based on a first cyclic shift m0 and a second cyclic shift m1. ID The first cyclic shift m0 and the second cyclic shift m1 are determined based on the received primary synchronization signal PSS and the received secondary synchronization signal SSS.

[0192] Figure 6 A flowchart of the corresponding method 600 that can be executed in the client device 500 is shown, for example. Figure 5 The client device 500 is shown. Method 600 includes a first step 602, namely, generating a secondary synchronization signal SSS sequence according to any embodiment of the method 200 described herein. The method further includes a second step 604, namely, receiving a secondary synchronization signal SSS using the generated secondary synchronization signal SSS sequence. The method further includes a third step 606, namely, determining cell ID N based on a first cyclic shift m0 and a second cyclic shift m1. ID The first cyclic shift and the second cyclic shift are determined based on the received primary synchronization signal PSS and the received secondary synchronization signal SSS.

[0193] Figure 7A wireless communication system 700 according to an embodiment is illustrated. The wireless communication system 700 includes a network node 300 and a client device 500 for operation within the wireless communication system 700. Both the network node 300 and the client device 500 may include a processing device 100. In the wireless communication system 700, a synchronization signal is transmitted by the network node 300 and received by the client device 500. Based on the synchronization signal, the client device 500 performs synchronization with the network node 300 and obtains the cell ID of the network node 300, as described in this document. The synchronization signal includes a primary synchronization signal (PSS) and a secondary synchronization signal (SSS). The processing device 100 in the network node 300 generates a sequence of secondary synchronization signals (SSS). The client device 500 receives the synchronization signal. The processing device 100 of the client device 500 may also generate a sequence of secondary synchronization signals (SSS) for related operations, etc., within the client device 500, as described in this document.

[0194] For simplicity, Figure 7 The wireless communication system 700 shown only includes one network node 300 and one client device 500. However, without departing from the scope of the invention, the wireless communication system 700 may include any number of network nodes 300 and any number of client devices 500.

[0195] Network node 300 in this document can also be referred to as a wireless network node, access network node, access point, or base station, such as a radio base station (RBS), while in some networks it may be called a transmitter, "gNB," "eNB," "eNodeB," "NodeB," or "B node," depending on the technology and terminology used. Based on transmission power and cell size, wireless network nodes can be different categories, such as macro base stations (eNodeB), home base stations (eNodeB), or pico base stations. A wireless network node can be a station (STA), which is any device containing IEEE 802.11 compliant Media Access Control (MAC) and Physical Layer (PHY) interfaces to the wireless medium (WM). Network node 300 can also be a base station corresponding to a fifth-generation wireless system.

[0196] The client device 500 can be a user device (UE), mobile station, Internet of Things (IoT) device, sensor device, wireless terminal, and / or mobile terminal, capable of wireless communication in a wireless communication system, sometimes also called a cellular wireless system. The UE can also be a wireless-capable mobile phone, cellular phone, tablet computer, or laptop. The UE in this document can be a portable, portable storable, handheld, computer-based, or vehicle-mounted mobile device, capable of voice and / or data communication with another entity, such as a receiver or server, via a wireless access network. The UE can be a station (STA), any device conforming to IEEE 802.11 that includes Media Access Control (MAC) and Physical Layer (PHY) interfaces to the Wireless Medium (WM). The client device 500 can also be used for communication in 3GPP-related fifth-generation wireless technologies such as LTE and LTE-Advanced, WiMAX and its evolution, and new wireless technologies.

[0197] Furthermore, any method according to embodiments of the present invention can be implemented in a computer program having code means that, when executed by a processing means, causes the processing means to perform the steps of the method. The computer program is contained within a computer-readable medium of the computer program product. The computer-readable medium can generally include any memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable PROM (EPROM), flash memory, electrically erasable PROM (EEPROM), or a hard disk drive.

[0198] Furthermore, those skilled in the art will recognize that the processing device 100, network node 300, and client device 500 of this embodiment of the invention include the necessary communication capabilities, such as functions, devices, units, and elements, to execute this solution. Examples of other such devices, units, and functions include: processors, memories, buffers, control logic, encoders, decoders, rate matchers, rate-down matchers, mapping units, multipliers, decision units, selection units, switches, interleavers, deinterleavers, modulators, demodulators, inputs, outputs, antennas, amplifiers, receiving units, transmitting units, DSPs, MSDs, TCM encoders, TCM decoders, power supply units, power feeders, communication interfaces, communication protocols, etc., which are appropriately configured together to execute this solution.

[0199] Specifically, the processor of the device and node of the present invention may include one or more instances of, for example, a central processing unit (CPU), a processing unit, a processing circuit, a processor, an application-specific integrated circuit (ASIC), a microprocessor, or other processing logic that can be compiled and execute instructions. The term "processor" may therefore refer to a processing circuit comprising a plurality of processing circuits, which are any, some, or all of the items listed above. The processing circuits may further perform data processing functions to input, output, and process data, including data buffering and device control functions, such as call processing control, user interface control, etc.

[0200] According to one embodiment, the first and second binary sequences used to generate the auxiliary synchronization signal SSS sequence are pseudo-random maximum length sequences, i.e., m sequences.

[0201] According to one embodiment, the first and second binary sequences used to generate the secondary synchronization signal SSS sequence are pseudo-random maximum-length sequences, i.e., m-sequences. These m-sequences can be based on a set of Gold sequences, thereby ensuring low cross-correlation between the generated SSS sequences. The Gold sequences will be described in more detail below.

[0202] According to one embodiment, one of the first and second binary sequences used to generate the secondary synchronization signal SSS sequence is the same as the binary sequence used to generate one or more primary synchronization signals PSS sequences, for example, the same pseudo-random maximum length sequence.

[0203] As described below, according to various embodiments, different numbers of primary synchronization signal (PSS) sequences can be used for synchronization signals, such as one primary synchronization signal PSS sequence, two or more primary synchronization signal PSS sequences, such as three primary synchronization signal PSS sequences. Therefore, different numbers of primary synchronization signal PSS sequences can be used together to generate the secondary synchronization signal (SSS) sequences described herein, thereby providing flexible synchronization signal generation to accommodate a large number of cell IDs and / or wireless systems.

[0204] According to one embodiment, as shown below, the length of the generated secondary synchronization signal SSS sequence is 127, i.e., L = 127. This is applicable to some available wireless systems and future wireless systems, thereby enabling the embodiments described herein to be implemented in these systems.

[0205] This invention discloses SSS sequences d(k), k = 0, 1, 2, ..., L-1, which can be constructed based on the modulo-2 sum of two binary sequences of length m with different cyclic shifts m0 and m1. According to one embodiment, BPSK modulation is used. For example, the SSS sequence d(k) can be represented as follows:

[0206] d(k)=1-2((s0((k+m0)mod L)+s1((k+m1)mod L))mod 2), k=0, 1, 2,..., L-1 (Equation 1)

[0207] In this example, the SSS sequence d(k) can be generated based on two sequences S0(k) and S1(k) of length L, where S0(k) is cyclically shifted by a first cyclic shift m0, meaning S0(k) has a first cyclic shift m0. S1(k) is cyclically shifted by a second cyclic shift m1, meaning S1(k) has a second cyclic shift m1.

[0208] Two binary sequences, for example, can be selected by carefully choosing a generator polynomial, choosing two m sequences of the same length L such that all generated SSS sequences belong to the same set of Gold sequences, thereby ensuring low cross-correlation between the generated SSS sequences.

[0209] For example, the generator polynomial can be chosen as g0(x) = x 7 +x 4 +1 and g1(x) = x 7 +x+1. This generates a set of Gold sequences of length L = 127, where the absolute inner product of any two sequences is 1, 2 (n+1) / 2 -1 = 15 or 2 (n+1) / 2 +1=17, n=7 is the highest order of g0(x) and g1(x).

[0210] According to one embodiment, one of the first and second binary sequences used to generate the secondary synchronization signal SSS sequence can be selected as the same sequence as the binary sequence used to generate the primary synchronization signal PSS sequence, for example, the same pseudo-random maximum-length sequence. Therefore, the same binary sequence, for example, the same m-sequence, is used to generate the primary synchronization signal PSS sequence, and to generate the first or second binary sequence used to generate the secondary synchronization signal SSS sequence. For example, both the generated primary synchronization signal PSS sequence and the generated secondary synchronization signal SSS sequence can thus belong to the same set of Gold sequences, thereby ensuring low cross-correlation between the generated secondary synchronization signal SSS sequence and the generated primary synchronization signal PSS sequence.

[0211] Cell ID, i.e., N ID satisfy: The cell ID is carried through the sequence indexes of the SSS and PSS. and The cell ID is encoded into, for example, two binary sequences of two m sequences, with a first cyclic shift m0 and a second cyclic shift m1, such that if multiple PSS sequences exist, at least one of the first cyclic shift m0 and the second cyclic shift m1 depends on the PSS sequence index. Furthermore, if the generated SSS sequences are associated with the same PSS sequence index, these SSS sequences are guaranteed to have low cross-correlation even under large residual frequency offsets, because an SSS sequence cannot be obtained by cyclically shifting another SSS sequence associated with the same PSS index by one step.

[0212] According to one embodiment, there are no two definitive cyclic shift pairs (m0, m1) and (m′0, m′1) that simultaneously satisfy m′0 = m0 + 1 and m′1 = m1 + 1. In other words, this can be expressed as any two SSS cyclic shift pairs (m0, m1) and (m′0, m′1) can satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1. This guarantees robustness against large frequency shifts. According to this embodiment, for example, by using the sequence index carried in the PSS, i.e. The design of the cyclic shift pair is implemented by encoding a cyclic shift of one of two binary sequences, for example, for the first cyclic shift m0, and it is required that any two candidate values ​​of the first cyclic shift m0 are separated from each other by more than one (1) cyclic shift step. Therefore, consecutive cyclic shifts of the first binary sequence cannot be selected simultaneously, which also means that non-consecutive cyclic shifts of the first binary sequence can be selected. At this time, the total number of candidate values ​​of the first cyclic shift m0 can be kept to a minimum, so that SSS detection based on low complexity / low cost scrambling-FWHT can be used in the client device 500.

[0213] The sequence index carried by the SSS, i.e. The encoding consists of a first cyclic shift m0 and a second cyclic shift m1, which are first and second binary sequences, respectively. The second cyclic shift m1 is allowed to include all or most of its valid values ​​{0, 1, 2, ..., L-1}. This SSS design avoids the situation where an SSS sequence can be obtained by cyclically shifting another SSS sequence by one cyclic shift step, thus ensuring robustness against large frequency shifts.

[0214] It should be noted that the index of the PSS sequence Encode as the first circular shift m0, and the index of the SSS sequence. The encoding of the first circular shift m0 and the second circular shift m1 can be done in any way; for example, m0 and m1 can be interchanged or replaced in the equation below. Given the value of the first circular shift m0, the number of candidate values ​​for the second circular shift m1 can be the same or different for different values ​​of the first circular shift m0.

[0215] According to the implementation method of this embodiment, the index of the SSS sequence has been... and the index of the PSS sequence Encode to the first cyclic shift m0 and the second cyclic shift m1, that is, determine the first cyclic shift m0 and the second cyclic shift m1 as follows:

[0216]

[0217]

[0218] Where g is the minimum cyclic shift step size among the candidate values ​​of the first cyclic shift m0, and it is an integer greater than 1. L′ is a positive integer less than or equal to the length L of the SSS sequence, i.e., L′≤L; for a given first cyclic shift m0, it is also the maximum number of candidate values ​​for the second cyclic shift m1. Here, and in this document, represents the floor function, and mod represents the modulo operation. Since g > 1, the cyclic shift of any two SSS sequences (m0, m1) and (m′0, m′1) can only satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1.

[0219] As a non-limiting example, it should be mentioned that for the implementation of the new wireless synchronization signal, where L = 127 and For example, setting g=2, With L′=112, a total of 336×3=1008 cell IDs can be carried.

[0220] against L = 15, g = 2, and L′ = 8. Figure 8A schematic and non-limiting illustration of this embodiment is shown. Since g = 2, there are no two cyclic shift pairs (m0, m1) and (m′0, m′1) that both satisfy m′0 = m0 + 1 and m′1 = m1 + 1. This is in Figure 8 As shown, each second position along the diagonal direction is unused; that is, the selectable positions (black dots) are separated diagonally by potentially unselected positions (white dots). In this document, the diagonal direction associated with the attached figure includes all lines / directions satisfying m0 = m1 + c, where c is any integer. Therefore, in Figure 8 The diagram cannot simultaneously satisfy both m′0=m0+1 and m′1=m1+1. Figure 8 In the PSS sequence index The y-axis is defined as follows, where m0 = 0 and m0 = 2 both have the same PSS sequence index. That is, both m0=0 and m0=2 have the same PSS sequence index. Correlated. Accordingly, m0=4 and m0=6 are both associated with the same PSS sequence index. Related. It should be noted that the PSS sequence index... Association with the first cyclic shift m0 and the SSS index The association with m0 and m1 is not limited to Figure 8 The order shown is correct. Conversely, any other order is also possible.

[0221] Additionally, according to the embodiments, the cell IDN can be determined based on the first cyclic shift m0 and the second cyclic shift m1. ID Because there exists a PSS sequence index from the first cyclic shift value m0 and the second cyclic shift value m1. and SSS sequence index A simple inverse mapping, so this is possible, for example, satisfying:

[0222]

[0223]

[0224] The PSS sequence index is determined in a simplified manner based on the first cyclic shift m0 and the second cyclic shift m1. and SSS sequence index This alleviates the need to implement large tables in client devices to determine cell IDs based on a first cyclic shift m0 and a second cyclic shift m1.

[0225] According to one embodiment, there are no two definitive cyclic shift pairs (m0, m1) and (m′0, m′1) that both satisfy m′0 = m0 + 1 and m′1 = m1 + 1. That is, the two cyclic shift pairs (m0, m1) and (m′0, m′1) can satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, while the definitive cyclic shift pairs always satisfy m0 < m1 (or m0 > m1). This ensures robustness against large frequency shifts.

[0226] According to the implementation method of this embodiment, the sequence index carried in the PSS has been... and the sequence index carried in SSS Encode to a first cyclic shift m0 and a second cyclic shift m1, wherein the first cyclic shift m0 and the second cyclic shift m1 satisfy:

[0227]

[0228]

[0229] Where g > 1 is the minimum step size between candidate values ​​of the first cyclic shift m0, and L′ ≤ L is the maximum number of candidate values ​​for the second cyclic shift m1 given the first cyclic shift m0. Since g > 1, for any two cyclic shift pairs of SSS sequences, such as (m0, m1) and (m′0, m′1), at most one of m′0 = m0 + 1 and m′1 = m1 + 1 is satisfied. Furthermore, the generated cyclic shift pairs always satisfy m0 < m1 (or m0 > m1). This is advantageous if the SSS is transmitted twice every 10 ms, i.e., once in each half-frame, because it allows the SSS sequence to indicate 5 ms timing (e.g., done in LTE) by simply swapping the values ​​of m0 and m1 between two half-frames. Alternatively, the implementation provides a future-proof solution, e.g., for future new wireless versions of the system, if it is later deemed helpful to increase the number of assumptions in the SSS.

[0230] As a non-limiting example, it should be mentioned that for the implementation of the new wireless synchronization signal, where L = 127 and One possible implementation is to set g=2. And L′=115, etc., carry 336×3=1008 community identifiers.

[0231] Figure 9 A non-limiting example illustration of this embodiment is shown. Taking L=15, g=2, and L′=8 as examples, Figure 9 In the PSS sequence index The y-axis is defined as follows, where m0 = 0 and m0 = 2 both have the same PSS sequence index. That is, both m0=0 and m0=2 have the same PSS sequence index. Correlated. Accordingly, m0=4 and m0=6 are both associated with the same PSS sequence index. Related. It should be noted that the PSS sequence index... Association with the first cyclic shift m0 and the SSS index The association with the first cyclic shift m0 and the second cyclic shift m1 is not limited to... Figure 9 The order shown is, for example, any other order is also possible.

[0232] Additionally, according to the embodiments, the cell IDN can be determined based on the first cyclic shift m0 and the second cyclic shift m1. ID Because there exists a PSS sequence index from the first cyclic shift value m0 and the second cyclic shift value m1. and SSS sequence index A simple inverse mapping, so this is possible, for example. satisfy:

[0233]

[0234]

[0235] The PSS sequence index is determined in a simple way based on the first circular shift m0 and the second circular shift m1. and SSS sequence index This alleviates the need to implement large tables in client devices to determine cell IDs based on a first cyclic shift m0 and a second cyclic shift m1.

[0236] According to the implementation method of this embodiment, the index of the SSS sequence is... and the index of the PSS sequence Encode to the first cyclic shift m0 and the second cyclic shift m1, the first cyclic shift m0 and the second cyclic shift m1 satisfy:

[0237]

[0238]

[0239] Where g is the minimum cyclic shift step size between candidate values ​​of the first cyclic shift m0, and it is an integer greater than 1, i.e., g > 1. L′ is a positive integer less than or equal to the length L of the SSS sequence, i.e., L′ ≤ L; for a given first cyclic shift m0, it is also the maximum number of candidate values ​​for the second cyclic shift m1. Since g > 1, any two cyclic shift pairs of SSS sequences (m0, m1) and (m′0, m′1) can only satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1.

[0240] As a non-limiting example, it should be mentioned that for the implementation of the synchronization signal in the new wireless system, where L = 127 and In one possible implementation, for example, setting g=2, And L′=112, etc., to carry a total of 336×3=1008 cell IDs.

[0241] Figure 10 The illustrations shown are schematic and non-limiting examples of this embodiment. Taking L=15, g=2, and L′=8 as examples, since g=2, there are no two cyclic shift pairs (m0, m1) and (m′0, m′1) that both satisfy m′0=m0+1 and m′1=m1+1. This is in Figure 10 As shown, each second position along the diagonal is unused; that is, the selectable positions (black dots) are separated on the diagonal by potentially unselected positions (white dots). Therefore, in Figure 10 The diagram cannot simultaneously satisfy both m′0=m0+1 and m′1=m1+1. Figure 10 In the PSS sequence index The y-axis is defined as follows, where m0 = 0 and m0 = 4 both have the same PSS sequence index. That is, m0=0 and m0=4 both have the same PSS sequence index. Correlated. Accordingly, m0=2 and m0=6 are both associated with the same PSS sequence index. Related. It should be noted that the PSS sequence index... Association with the first cyclic shift m0 and the SSS index The association with m0 and m1 is not limited to Figure 10 The order shown is correct. Conversely, any other order is also possible.

[0242] Additionally, according to the embodiments, the cell IDN can be determined based on the first cyclic shift m0 and the second cyclic shift m1. ID Because there exists a PSS sequence index from the first cyclic shift value m0 and the second cyclic shift value m1. and SSS sequence index A simple inverse mapping, so this is possible, for example. satisfy:

[0243]

[0244]

[0245] The PSS sequence index is determined in a simplified manner based on the first cyclic shift m0 and the second cyclic shift m1. and SSS sequence index This alleviates the need to implement large tables in client devices to determine cell IDs based on a first cyclic shift m0 and a second cyclic shift m1.

[0246] According to the implementation method of this embodiment, the sequence index carried in the PSS and the sequence index carried in SSS Encode to the first cyclic shift m0 and the second cyclic shift m1, the first cyclic shift m0 and the second cyclic shift m1 satisfy:

[0247]

[0248]

[0249] Where g > 1 is the minimum step size between candidate values ​​of the second cyclic shift m1, and L′ ≤ L is the maximum number of candidate values ​​of the second cyclic shift m1 given the first cyclic shift m0. Since g > 1, any two SSS sequences, such as (m0, m1) and (m′0, m′1), can only satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1 for their cyclic shift pairs. Meanwhile, the generated / selected cyclic shift pairs always satisfy m0 < m1 (or equivalently, m0 > m1). This is advantageous if the SSS is transmitted twice every 10 ms, i.e., once in each half-frame, because it allows the SSS sequence to indicate 5 ms timing (e.g., done in LTE) by simply swapping the values ​​of m0 and m1 between two half-frames. Alternatively, the implementation provides a future-proof solution, e.g., for future new wireless versions, if it is later deemed helpful to increase the number of assumptions in the SSS.

[0250] As a non-limiting example, it should be mentioned that for the implementation of the new wireless synchronization signal, where L = 127 and In one possible implementation, for example, setting g=2, And L′=115, etc., to implement this embodiment as carrying a total of 336×3=1008 cell IDs.

[0251] Figure 11 A non-limiting example illustration of this embodiment is shown. Taking L=15, g=2, and L′=8 as examples, Figure 11 In the PSS sequence index The y-axis is defined as follows, where m0 = 0 and m0 = 4 both have the same PSS sequence index. That is, m0=0 and m0=4 both have the same PSS sequence index. Correlated. Accordingly, m0=2 and m0=6 are both associated with the same PSS sequence index. Related. It should be noted that the PSS sequence index... Association with the first cyclic shift m0 and the SSS index The association with the first cyclic shift m0 and the second cyclic shift m1 is not limited to... Figure 11 The order shown is, for example, any other order is also possible.

[0252] Additionally, according to the embodiments, the cell IDN can be determined based on the first cyclic shift m0 and the second cyclic shift m1. ID Because there exists a PSS sequence index from the first cyclic shift value m0 and the second cyclic shift value m1. and SSS sequence index A simple inverse mapping, so this is possible, for example. satisfy:

[0253]

[0254]

[0255] The PSS sequence index is determined in a simple way based on the first circular shift m0 and the second circular shift m1. and SSS sequence index This alleviates the need to implement large tables in client devices to determine cell IDs based on a first cyclic shift m0 and a second cyclic shift m1.

[0256] According to one embodiment, if two cyclic shift pairs (m0, m1) and (m′0, m′1) have different PSS sequence indices... If associated, then both cyclic shift pairs (m0, m1) and (m′0, m′1) are allowed to satisfy m′0 = m0 + 1 and m′1 = m1 + 1. This ensures robustness against large frequency shifts.

[0257] According to the cyclic shift pair of this embodiment, for example, it can be achieved by using the sequence index carried in the PSS, i.e. This is achieved by encoding into one of two binary sequences via a non-contiguous cyclic shift, for example, for the first cyclic shift m0, and requiring that any two candidate values ​​of the first cyclic shift m0 associated with the same master synchronization signal PSS sequence index be spaced more than one cyclic shift step apart from each other, while allowing different PSS sequence indices. Encode continuous values ​​to the first cyclic shift m0. The total number of the first cyclic shift m0 can be kept to a minimum, enabling SSS detection based on low-cost / low-complexity scrambling-FWHT in the client device 500.

[0258] The sequence index carried by the SSS, i.e. The encoding is a cyclic shift of two m-sequences m0 and m1, where m1 is allowed to include all or most of its valid values ​​{0, 1, 2, ..., L-1}. This SSS design results in a situation where an SSS sequence can be obtained by cyclically shifting another SSS sequence by one cyclic shift step. However, according to embodiments, such a pair of SSS sequences is always indexed with different PSS sequences. It is associated with PSS and will not be detected simultaneously after PSS detection is successful in client device 500.

[0259] It should be noted that the index of the PSS sequence Encode as the first circular shift m0, and the index of the SSS sequence. The encoding of the first circular shift m0 and the second circular shift m1 can be done in any way; for example, m0 and m1 can be interchanged in the equation below. Given the value of the first circular shift m0, the number of candidate values ​​for the second circular shift m1 can be the same or different for different values ​​of the first circular shift m0.

[0260] According to the implementation of the embodiments, the sequence index can be... and The encoding is a first cyclic shift m0 and a second cyclic shift m1. For example, the first cyclic shift m0 and the second cyclic shift m1 can be determined as m0 and m1 satisfying the following:

[0261]

[0262]

[0263] Equations 18 and 19 can also be understood as restricted / limited versions of the encoding methods in equations (10) and (11) above, where g is exemplified here as having a value of 1, i.e., g = 1. According to the implementation, if two SSS sequences are associated with different PSS indices according to equations (18) and (19), then two SSS sequences are allowed to coexist, where the cyclic shift pairs (m0, m1) and (m′0, m′1) of the two sequences satisfy m′0 = m0 + 1 and m′1 = m1 + 1. This is advantageous because more valid values ​​can be selected for the cyclic shift pairs (m0, m1), making it possible to encode a larger number of cell IDs and potentially other additional information into the SSS sequences without increasing the SSS sequence length.

[0264] As a non-limiting example, it should be mentioned that for the implementation of the new wireless synchronization signal, where L = 127 and For example, by letting And L′=112 etc. are used to carry a total of 336×3=1008 cell IDs in this implementation.

[0265] Figure 12 A diagram of this example is provided. Taking L=15 and L′=8 as examples, Figure 12 In the PSS sequence index The y-axis is defined as follows, where m0 = 0 and m0 = 2 both have the same PSS sequence index. That is, both m0=0 and m0=2 have the same PSS sequence index. Correspondingly, m0=1 and m0=3 are both associated with the same PSS sequence index. Related. It should be noted that the PSS sequence index... The association with the first cyclic shift m0, and the SSS sequence index. The association with the first cyclic shift m0 and the second cyclic shift m1 is not limited to... Figure 12 The order shown. Conversely, as long as it's with the same PSS index... Any two associated cyclic shift pairs of SSS sequences, such as (m0, m1) and (m′0, m′1), satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, and any other order is possible.

[0266] Additionally, according to the embodiments, the cell IDN can be determined based on the first cyclic shift m0 and the second cyclic shift m1. ID Because there exists a PSS sequence index from the first cyclic shift value m0 and the second cyclic shift value m1. and SSS sequence index A simple inverse mapping, so this is possible, for example. satisfy:

[0267]

[0268]

[0269] Equations 20 and 21 can also be understood as restricted / limited versions of the inverse mappings in equations (12) and (13) above, for example, g is taken as 1, i.e. g = 1. This alleviates the need to implement large tables in the client device 500 to determine the cell ID based on the first cyclic shift m0 and the second cyclic shift m1.

[0270] According to one embodiment, if two cyclic shift pairs (m0, m1) and (m′0, m′1) have different PSS sequence indices... If the generated cyclic shift pairs are associated and always satisfy m0 < m1 (or m0 > m1), then it is permissible for two cyclic shift pairs (m0, m1) and (m′0, m′1) to both satisfy m′0 = m0 + 1 and m′1 = m1 + 1.

[0271] According to the implementation of the embodiments, the sequence index can be... and Encoding is a first cyclic shift m0 and a second cyclic shift m1, which can be determined to satisfy the following:

[0272]

[0273]

[0274] Equations 22 and 23 can be understood as restricted / limited versions of the encoding methods in equations (14) and (15) above, for example, g is exemplified here as having a value of 1, i.e., g = 1. According to the implementation, if two SSS sequences are associated with different PSS indices according to equations (22) and (23), and the resulting cyclic shift pairs always satisfy m0 < m1 (or equivalently m0 > m1), then two SSS sequences are allowed to coexist, where the cyclic shift pairs (m0, m1) and (m′0, m′1) of these two sequences both satisfy m′0 = m0 + 1 and m′1 = m1 + 1. As mentioned above, this is advantageous because it allows the use of SSS sequences to indicate 5ms timing by swapping the values ​​of m0 and m1, as used in LTE systems. Alternatively, if it is later deemed helpful to increase the number of assumptions in the SSS, then it constitutes a future-proof solution for future new wireless versions of the system.

[0275] As a non-limiting example, it should be mentioned that for the implementation of the new wireless synchronization signal, where L = 127 and In one possible implementation, set And L′=112, etc., to use this implementation to carry a total of 336×3=1008 cell IDs. Taking L=15 and L′=8 as examples, Figure 13 A non-limiting illustration of this embodiment is shown. Figure 13 In the PSS sequence index The y-axis is defined as follows, where m0 = 0 and m0 = 2 both have the same PSS sequence index. That is, both m0=0 and m0=2 have the same PSS sequence index. Correspondingly, m0=1 and m0=3 are both associated with the same PSS sequence index. Related. It should be noted that the PSS sequence index... The association with the first cyclic shift m0, and the SSS sequence index. The association with the first cyclic shift m0 and the second cyclic shift m1 is not limited to... Figure 13 The order shown. Conversely, as long as it's with the same PSS index... Any two associated cyclic shift pairs of SSS sequences, such as (m0, m1) and (m′0, m′1), satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, and any other order is possible if the resulting cyclic shift pairs always satisfy m0 < m1 (or m0 > m1).

[0276] Additionally, according to the embodiments, the cell IDN can be determined based on the first cyclic shift m0 and the second cyclic shift m1. ID Because there exists a PSS sequence index from the first cyclic shift value m0 and the second cyclic shift value m1. and SSS sequence index A simple inverse mapping, so this is possible, for example. satisfy:

[0277]

[0278]

[0279] Equations 24 and 25 can also be understood as restricted / limited versions of the inverse mapping in equations (16) and (17) above, with g being taken as an example, i.e., g = 1. This alleviates the need to implement a large table in the client device 500 to determine the cell ID based on the first cyclic shift value m0 and the second cyclic shift value m1.

[0280] As described above, the relationship with at least one cell ID N can be determined according to the various embodiments described herein. ID The first cyclic shift m0 and the second cyclic shift m1 are associated, and therefore will have various interrelationships.

[0281] According to some embodiments described herein, for example, Figure 8 , 10 As shown in Figure 12, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that the first cyclic shift m0 and the second cyclic shift m1 are equal, that is, m0 = m1. In other words, there is a usable position on the diagonal through the origin of the coordinate system.

[0282] According to some embodiments described herein, for example, Figure 9 , 11 As shown in Figure 13, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that the first cyclic shift m0 and the second cyclic shift m1 are different, that is, m0 ≠ m1, which means that there is no available position on the diagonal through the origin of the coordinate system.

[0283] According to some embodiments described herein, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that the first cyclic shift m0 is greater than the second cyclic shift m1, i.e., m0 > m1. In other words, there is only a usable position above the diagonal through the origin of the coordinate system.

[0284] According to some embodiments described herein, for example, Figure 9 , 11 As shown in Figure 13, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that the first cyclic shift m0 is less than the second cyclic shift m1, i.e., m0 < m1. In other words, there is only a usable position below the diagonal through the origin of the coordinate system.

[0285] According to some embodiments described herein, for example, Figure 8 , 9 As shown in 10 and 11, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that the two cyclic shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, that is, there is always an unused position between the available positions in the diagonal direction.

[0286] According to some embodiments described herein, a first cyclic shift m0 and a second cyclic shift m1 can be determined such that the two cyclic shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, and the first cyclic shift m0 is greater than the second cyclic shift m1, i.e., m0 > m1. In other words, there are always unused positions between the available positions in the diagonal direction through the origin of the coordinate system, and available positions exist only above the diagonal.

[0287] According to some embodiments described herein, for example, Figure 9 and 11 As shown, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that the two cyclic shift pairs (m0, m1) and (m′0, m′1) satisfy at most one of m′0 = m0 + 1 and m′1 = m1 + 1, and the first cyclic shift m0 is less than the second cyclic shift m1, that is, m0 < m1. In other words, there is always an unused position between the available positions in the diagonal direction through the origin of the coordinate system, and there is only an available position below the diagonal.

[0288] According to some embodiments described herein, for example, Figure 12 and 13As shown, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that the two cyclic shift pairs (m0, m1) and (m'0, m'1) that both satisfy m'0 = m0 + 1 and m'1 = m1 + 1 are associated with different master synchronization signal PSS sequence indices. Related.

[0289] According to some embodiments described herein, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that two cyclic shift pairs (m0, m1) and (m′0, m′1) that both satisfy m′0 = m0 + 1 and m′1 = m1 + 1 are associated with different master synchronization signal PSS indices. The coordinates are related, and the first cyclic shift m0 is greater than the second cyclic shift m1, that is, m0 > m1. In other words, there is only a usable position above the diagonal through the origin.

[0290] According to some embodiments described herein, such as Figure 13 As shown, the first cyclic shift m0 and the second cyclic shift m1 can be determined such that the two cyclic shift pairs (m0, m1) and (m'0, m'1) that both satisfy m'0 = m0 + 1 and m'1 = m1 + 1 are associated with different primary synchronization signal (PSS) sequence indices. The coordinates are related, and the first cyclic shift m0 is less than the second cyclic shift m1, i.e., m0 < m1. In other words, there is only a usable position below the diagonal through the origin of the coordinate system.

[0291] Finally, it should be understood that the present invention is not limited to the above embodiments, but relates to and includes all embodiments within the scope of the appended independent claims.

Claims

1. A processing device, characterized in that, The processing equipment is used for: Receive the master synchronization signal (PSS) and obtain the index of the master synchronization signal sequence of the PSS. ; Receive the secondary synchronization signal (SSS) and obtain the index of the secondary synchronization signal sequence of the SSS. ,in, The auxiliary synchronization signal sequence is based on the first cyclic shift. The first binary sequence and the second cyclic shifted The sequence generated from the second binary sequence, wherein the first binary sequence, the second binary sequence, and the auxiliary synchronization signal sequence have the same length. The index of the master synchronization signal sequence The index of the auxiliary synchronization signal sequence The cyclic shifts m0 and m1 satisfy the following: ， Where g is an integer, and g is greater than or equal to 1; It is 112; ; ； This represents the floor function; mod represents modulo operation; and According to the index of the master synchronization signal sequence and the index of the auxiliary synchronization signal sequence Determine the community signage The cell identifier satisfy: .

2. The processing apparatus as described in claim 1, characterized in that, The The value is 3, and the main synchronization signal sequence is one of three main synchronization signal sequences, wherein the index of the main synchronization signal sequence is... The cell identifier satisfy .

3. The processing apparatus as described in claim 1 or 2, characterized in that, It is 336, of which 。 4. The processing apparatus as described in claim 1 or 2, characterized in that: The processing device is used to detect the auxiliary synchronization signal after the primary synchronization signal has been successfully detected.

5. The processing apparatus as described in claim 1, characterized in that, The first binary sequence and the second binary sequence are m-sequences, or the first binary sequence and the second binary sequence are m-sequences that cause the generated auxiliary synchronization signal sequence to belong to a set of Gold sequences.

6. The processing apparatus as described in claim 1 or 5, characterized in that, The length L of the auxiliary synchronization signal sequence is 127.

7. The processing apparatus as described in claim 1, characterized in that, The generator polynomial of the first binary sequence is: The generator polynomial of the second binary sequence is .

8. The processing apparatus as described in claim 1, characterized in that, One of the first binary sequence or the second binary sequence is the same as the binary sequence of the master synchronization signal sequence used to generate the master synchronization signal.

9. The processing apparatus as described in claim 1, characterized in that, The auxiliary synchronization signal sequence satisfy: ， in S0(k) is the first binary sequence, S1(k) is the second binary sequence, S0(k) has a first cyclic shift m0, S1(k) has a second cyclic shift m1, and the length of both the first binary sequence and the second binary sequence is L.

10. The processing apparatus as described in claim 1, characterized in that, The processing device is used to descramble the first binary sequence using the first cyclic shift m0 assumption, and after descrambling according to the correct first cyclic shift m0 assumption, to detect the second binary sequence using the fast Walsh-Hadamard transform.

11. The processing apparatus as described in claim 1 or 2, characterized in that, The processing device is used to generate a secondary synchronization signal sequence and to perform related operations on the generated secondary synchronization signal sequence.

12. The processing apparatus as described in claim 1 or 2, characterized in that, The processing device is used to determine the cyclic shifts m0 and m1 based on the primary synchronization signal and the secondary synchronization signal, and to determine the cell identifier based on m0 and m1. .

13. The processing apparatus as described in claim 1, characterized in that, The cell identifier is determined based on the following mapping relationship. ， ， ， in The value is 3.

14. A client device, comprising a processing device and a transceiver, characterized in that, The transceiver is used to receive the primary synchronization signal and the secondary synchronization signal, and the processing device is the processing device as described in any one of claims 1 to 13.

15. A method for wireless communication, comprising: Receive the master synchronization signal (PSS) and obtain the index of the master synchronization signal sequence of the PSS. ; Receive the secondary synchronization signal (SSS) and obtain the index of the secondary synchronization signal sequence of the SSS. ,in, The auxiliary synchronization signal sequence is based on the first cyclic shift. The first binary sequence and the second cyclic shifted The sequence generated from the second binary sequence, wherein the first binary sequence, the second binary sequence, and the auxiliary synchronization signal sequence have the same length. The index of the master synchronization signal sequence The index of the auxiliary synchronization signal sequence The cyclic shifts m0 and m1 satisfy the following: ， Where g is an integer, and g is greater than or equal to 1; It is 112; ; ； This represents the floor function; mod represents modulo operation; and According to the index of the master synchronization signal sequence and the index of the auxiliary synchronization signal sequence Determine the community signage The cell identifier satisfy: .

16. The method as described in claim 15, characterized in that: Used to detect the auxiliary synchronization signal after the primary synchronization signal has been successfully detected.

17. The method as described in claim 16, characterized in that, The method further includes: The first binary sequence is descrambled using the first cyclic shift m0 assumption. After descrambling according to the correct first cyclic shift m0 assumption, the second binary sequence is detected using the fast Walsh-Hadamard transform.

18. The method as described in claim 15, characterized in that, Also includes: A secondary synchronization signal sequence is generated, and related operations are performed on the generated secondary synchronization signal sequence.

19. The method as described in claim 15, characterized in that, Also includes: The cyclic shifts m0 and m1 are determined based on the primary synchronization signal and the secondary synchronization signal, and the cell identifier is determined based on m0 and m1. .

20. The method as described in claim 15, characterized in that, The cell identifier is determined based on the following mapping relationship. ， ， ， in The value is 3.

21. The method according to any one of claims 15 to 20, characterized in that, It is 336. , It is 3. .

22. An apparatus comprising a processing device and a memory for storing a computer program, which, when executed by the processing device, causes the method of any one of claims 15-21 to be performed.

23. A communication system, comprising network nodes and client devices, characterized in that, The network node is used to send primary synchronization signals and secondary synchronization signals, and the client device is the client device as described in claim 14.

24. A computer-readable medium storing a computer program, characterized in that, When the computer program is run on a computer, it causes the computer to perform the method according to any one of claims 15 to 21.

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