Display device and driving method thereof

Abstract

The present invention discloses a display device and a driving method thereof. The display device includes: a display panel including pixels connected to a p-type scan line, an n-type scan line and a data line, for displaying an image at a first frequency in a first mode or at a lower second frequency in a second mode; a first scan driver for supplying a p-type signal having a first voltage to the p-type scan line; and a second scan driver for supplying an n-type signal having a larger second voltage to the n-type scan line, wherein the second mode includes a first period corresponding to one frame period and a second period including continuous frame periods, wherein during the first period, the scan driver supplies i corresponding signals to the p-type scan line and the n-type scan line respectively, and during at least one frame of the second period, the first scan driver supplies j p-type signals to the p-type scan line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0068923 filed on June 11, 2019, in the Korean Intellectual Property Office, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to a display device, and more particularly, to a display device supplying a plurality of scan signals to a scan line during one frame and a driving method thereof. Background Art

[0004] The organic light emitting diode display of the display device displays images using organic light emitting diodes, which generate light through the recombination of electrons and holes. This has the advantages of fast response speed and low power consumption.

[0005] The driving transistor included in the pixel has a hysteresis characteristic in which the threshold voltage is shifted and the current changes according to the change of the gate voltage. Due to the hysteresis characteristic of the driving transistor, a current different from the current set in the pixel may flow according to the previous data voltage of the pixel. In this way, the pixel may not generate light of the desired brightness in the current frame.

[0006] In order to improve the hysteresis characteristic, a driving method of supplying a plurality of scan signals (eg, a scan signal having a plurality of scan pulses) corresponding to each pixel row may be applied.

[0007] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore may contain information that does not constitute prior art. Summary of the invention

[0008] A display device and a driving method thereof constructed according to an exemplary embodiment of the present invention can change the number of scan signals while being driven at low power.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0010] A display device according to an exemplary embodiment includes: a display panel including a plurality of pixels connected to a p-type scan line, an n-type scan line, and a data line, and configured to display an image in a first mode driven at a first driving frequency or in a second mode driven at a second driving frequency lower than the first driving frequency; a first scan driver configured to supply a p-type scan signal having a first voltage to the p-type scan line; and a second scan driver configured to supply an n-type scan signal having a second voltage greater than the first voltage to the n-type scan line, wherein the second mode includes a first period corresponding to one frame period and a second period including a plurality of consecutive frame periods, during the first period, the first scan driver is configured to supply i p-type scan signals to the p-type scan line, and the second scan driver is configured to supply i n-type scan signals to the n-type scan line, i being a natural number, and during at least one of the plurality of consecutive frame periods of the second period, the first scan driver is configured to supply j p-type scan signals to the p-type scan line, j being a natural number different from i.

[0011] The first scan driver may be configured to supply j p-type scan signals to the p-type scan lines in each of a plurality of frame periods of the second period.

[0012] The number of p-type scan signals supplied during each of the plurality of frame periods of the second period may be less than the number of p-type scan signals supplied during the first period.

[0013] The first scan driver may be further configured to reduce the number of p-type scan signals output in each of a plurality of frame periods of the second period as the second driving frequency decreases.

[0014] The second scan driver may be further configured not to supply the n-type scan signal during the second period.

[0015] The first scan driver may be further configured to supply i p-type scan signals to the p-type scan lines during one frame period in the first mode, and the second scan driver may be further configured to supply i n-type scan signals to the n-type scan lines during one frame period in the first mode.

[0016] The first scan driver and the second scan driver may be further configured to simultaneously supply the p-type scan signal and the n-type scan signal to the p-type scan line and the n-type scan line, respectively, during the first period.

[0017] The display device may further include a timing controller configured to supply the same number of start signals to the first scan driver and the second scan driver in the first mode and to supply different numbers of start signals to the first scan driver and the second scan driver in the second mode.

[0018] The timing controller may be further configured to supply a first start signal having a first width to the first scan driver and supply a second start signal having a first width to the second scan driver in response to a first period in the second mode.

[0019] The timing controller may be further configured to supply a first start signal having a second width smaller than the first width to the first scan driver in response to a second period of the second mode.

[0020] The timing controller may be further configured to reduce the second width of the first start signal as the second driving frequency decreases.

[0021] The timing controller may be further configured to not supply the second start signal to the second scan driver in response to a second period of the second mode.

[0022] The display device may further include an emission driver configured to supply an emission control signal to an emission control line connected to each of the plurality of pixels to define an emission period and a non-emission period.

[0023] The display device may further include a data driver configured to supply a data signal to the data line.

[0024] Each of the plurality of pixels may include: a light emitting element; a first transistor connected between a first node electrically connected to a first power source and a second node electrically connected to a first electrode of the light emitting element, and configured to control a driving current; a second transistor connected between a data line and the first node, and configured to be turned on by a p-type scanning signal supplied to a k-th p-type scanning line, where k is a natural number greater than 1; a third transistor connected between the second node and a third node connected to a gate electrode of the first transistor, and configured to be turned on by an n-type scanning signal supplied to a k-th n-type scanning line; a fourth transistor connected between the third node and an initialization power supply, and is configured to be turned on by an n-type scan signal supplied to the k-1th n-type scan line; a fifth transistor, connected between the first power supply and the first node, and is configured to be turned on by an emission control signal supplied to the k-th emission control line; a sixth transistor, connected between the second node and the first electrode of the light-emitting element, and is configured to be turned on by the emission control signal; a seventh transistor, connected between the initialization power supply and the first electrode of the light-emitting element, and is configured to be turned on by a p-type scan signal supplied to the k-1th p-type scan line; and a storage capacitor connected between the first power supply and the third node.

[0025] The first transistor and the second transistor may include p-type low temperature polysilicon (LTPS) thin film transistors, and the third transistor and the fourth transistor may include n-type oxide semiconductor thin film transistors.

[0026] According to a driving method of a display device of another exemplary embodiment, the display device includes a plurality of pixels connected to a p-type scan line, an n-type scan line and a data line, and is used to display an image in a first mode driven at a first driving frequency or in a second mode driven at a second driving frequency lower than the first driving frequency, the driving method including the following steps: in a first time period corresponding to one frame period, i p-type scan signals are supplied to the p-type scan line, and i n-type scan signals are supplied to the n-type scan line, i being a natural number greater than 1; and in each frame period of a second time period including a plurality of consecutive frame periods, j p-type scan signals are supplied to the p-type scan line, j being a natural number less than i, wherein the first time period and the second time period are included in the second mode.

[0027] As the second driving frequency decreases, the number of p-type scan signals supplied during each of a plurality of frame periods in the second period may decrease.

[0028] The driving method may further include supplying i p-type scan signals to the p-type scan lines and supplying i n-type scan signals to the n-type scan lines in each frame period included in the first mode.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0031] Figure 1 is a block diagram of a display apparatus according to an exemplary embodiment.

[0032] Figure 2 is included in Figure 1 An exemplary circuit diagram of a pixel in a display device of FIG.

[0033] Figure 3 is an exemplary illustration of driving in the first mode Figure 1 Timing diagram of the display device.

[0034] Figure 4 is an exemplary illustration of driving in the first mode Figure 1 Timing diagram of the display device.

[0035] Figure 5 is an exemplary illustration of driving in the second mode Figure 1 Timing diagram of the display device.

[0036] Figure 6 is an exemplary illustration of driving in the second mode Figure 1 Timing diagram of the display device.

[0037] Fig. 7A It is exemplarily shown in Figure 1 A timing diagram of a start signal output in a first mode and a second mode of a display device.

[0038] Figure 7B is exemplarily shown in Figure 1 A timing diagram of a start signal output in the second mode of a display device.

[0039] Fig. 8A It is exemplarily shown in Figure 1 A timing diagram of a scanning signal output in the second mode of a display device.

[0040] Figure 8B is an exemplary illustration with Fig. 8A Timing diagram of the start signal corresponding to the scan signal.

[0041] Fig. 9 is an exemplary illustration included in Figure 1 Circuit diagram of a pixel in a display device. DETAILED DESCRIPTION

[0042] In the following description, for the purpose of illustration, many specific details are set forth to provide a comprehensive understanding of each exemplary embodiment or implementation of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words for non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be practiced without these specific details or under one or more equivalent arrangements. In other examples, well-known structures and devices are shown in the form of block diagrams to avoid unnecessary ambiguity of each exemplary embodiment. In addition, each exemplary embodiment may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used in another exemplary embodiment or implemented in another exemplary embodiment without departing from the present invention.

[0043] Unless otherwise specified, the illustrated exemplary embodiments should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter referred to as "elements" respectively or collectively) can be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0044] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless specified, the presence or absence of cross hatching or shading does not express or indicate any preference or requirement for a specific material, material property, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or description purposes. When the exemplary embodiments may be implemented differently, a specific process sequence different from the described sequence may be performed. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0045] When an element or layer is referred to as "being located on another element or layer", "being connected to" or "being coupled to" another element or layer, the element or layer may be directly located on another element or layer, directly connected to or coupled to another element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as "being directly located on another element or layer", "being directly connected to" or "being directly coupled to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection using or not using an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes (such as, the x-axis, the y-axis and the z-axis) of a rectangular coordinate system, but may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be mutually perpendicular, or may represent different directions that are not mutually perpendicular. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0047] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall"), etc., may be used herein, and thereby describe the relationship of one element to another element as illustrated in the accompanying drawings. Spatially relative terms are intended to cover different orientations of the device when in use, in operation, and / or in manufacture other than the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will subsequently be "above" the other elements or features. Therefore, the exemplary term "below" can include both above and below orientations. In addition, the device can be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are therefore interpreted accordingly.

[0048] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms of "a" and "the" are intended to also include plural forms, unless the context clearly states otherwise. In addition, the terms "include" and / or "comprise", when used in this specification, specify the existence of the described features, integral bodies, steps, operations, elements, parts and / or their combinations, but do not exclude the existence or increase of one or more other features, integral bodies, steps, operations, elements, parts and / or their combinations. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and are not used as terms of degree, and are therefore used to consider the inherent deviations in the values ​​that will be recognized by those of ordinary skill in the art, measured, calculated and / or provided.

[0049] As is customary in the art, some exemplary embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (e.g., logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs certain functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. In addition, each block, unit and / or module in some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules without departing from the scope of the present invention. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs. Terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0051] Figure 1 is a block diagram of a display apparatus according to an exemplary embodiment.

[0052] refer to Figure 1 , the display device 1000 may include a display panel 100 , a first scan driver 200 , a second scan driver 300 , an emission driver 400 , a data driver 500 , and a timing controller 600 .

[0053] In an exemplary embodiment, the display device 1000 may further include a power supply unit for supplying a first power source VDD, a second power source VSS, and an initialization power source VINT to the display panel 100. However, the inventive concept is not limited thereto, and in some exemplary embodiments, at least one of the first power source VDD, the second power source VSS, and the initialization power source VINT may be supplied from the timing controller 600 or the data driver 500.

[0054] In an exemplary embodiment, the display device 1000 may be operated in at least one of a first mode (e.g., a normal driving mode) and a second mode (e.g., a low power driving mode). The first mode is a driving mode in which the display panel 100 normally displays input image data. For example, in the first mode, a conventional image or animation may be displayed by a user's command input, etc.

[0055] On the other hand, the second mode is a mode in which simple display information is always displayed when the display device 1000 is in a standby state (eg, an AOD mode).

[0056] In the first mode, an image may be displayed at a first driving frequency. In the second mode, an image may be displayed at a second driving frequency lower than the first driving frequency. For example, the first driving frequency may be set to about 60 Hz or higher, and the second driving frequency may be set to about 50 Hz or lower (e.g., about 1 Hz).

[0057] The display panel 100 may include a plurality of p-type scan lines SPL, a plurality of n-type scan lines SNL, a plurality of emission control lines EL, a plurality of data lines DL, and a plurality of pixels PX connected to each of the p-type scan lines SPL, the n-type scan lines SNL, the emission control lines EL, and the data lines DL. Each of the pixels PX may include a driving transistor and a plurality of switching transistors.

[0058] The p-type scan line SPL and the n-type scan line SNL are distinguished to describe the scan lines connected to different elements in the pixel PX, and the functions of the scan lines and the scan signals may not be limited.

[0059] exist Figure 1 , the pixel PX is illustrated as being connected to one p-type scan line SPL, one n-type scan line SNL, one data line DL, and one emission control line EL, however, the inventive concept is not limited thereto. In some exemplary embodiments, the signal line connected to the pixel PX corresponding to the circuit structure of the pixel PX may be variously arranged.

[0060] The first scan driver 200 may sequentially supply a p-type scan signal to the pixel PX through the p-type scan line SPL based on the first control signal SCS1. The first scan driver 200 may receive the first control signal SCS1 from the timing controller 600. The first control signal SCS1 may include a first start signal SSP1 and at least one clock signal. The number of p-type scan signals may be determined by the pulse width of the first start signal SSP1.

[0061] In an exemplary embodiment, a plurality of p-type scan signals (eg, a plurality of scan pulses) may be supplied to one p-type scan line SPL during one frame period. The p-type scan signal may have a first voltage. The first voltage may be a logic low level voltage that turns on a p-type transistor.

[0062] In an exemplary embodiment, the first scan driver 200 may include stages which are dependently connected to each other to sequentially output the p-type scan signal to the p-type scan line SPL.

[0063] The second scan driver 300 may sequentially supply an n-type scan signal to the pixel PX through the n-type scan line SNL based on the second control signal SCS2. The second scan driver 300 may receive the second control signal SCS2 from the timing controller 600. The second control signal SCS2 may include a second start signal SSP2 and at least one clock signal. The number of n-type scan signals may be determined by the pulse width of the second start signal SSP2.

[0064] In an exemplary embodiment, a plurality of n-type scan signals (eg, a plurality of scan pulses) may be supplied to one n-type scan line SNL during one frame period. The n-type scan signal may have a second voltage greater than the first voltage. The second voltage may be a logic high level voltage that turns on the n-type transistor.

[0065] In an exemplary embodiment, the second scan driver 300 may include stages which are dependently connected to each other to sequentially output the n-type scan signals to the n-type scan lines SNL.

[0066] The first scan driver 200 may control the p-type scan signal supplied to the p-type scan line SPL in response to the driving frequency. Likewise, the second scan driver 300 may control the n-type scan signal supplied to the n-type scan line SNL in response to the driving frequency.

[0067] For example, in the first mode, a p-type scan signal supplied to the p-type scan line SPL and an n-type scan signal supplied to the n-type scan line SNL may be repeatedly supplied every predetermined period.

[0068] In the second mode, the p-type scan signal supplied to the p-type scan line SPL may be repeatedly supplied every predetermined period, and the n-type scan signal supplied to the n-type scan line SNL may not be supplied during a predetermined period. In addition, the number of p-type scan signals supplied in the second mode may be different from the number of p-type scan signals supplied in the first mode.

[0069] The emission driver 400 may sequentially supply the emission control signal to the pixels PX through the emission control line EL based on the third control signal ECS. The emission driver 400 receives the third control signal ECS and the clock signal from the timing controller 600. The emission control signal may divide one frame period into an emission period and a non-emission period for pixel rows.

[0070] The data driver 500 may receive a fourth control signal DCS and an image data signal RGB from the timing controller 600. The data driver 500 may supply a data signal (or a data voltage) to the pixel PX through the data line DL based on the fourth control signal DCS and the image data signal RGB. In an exemplary embodiment, the data driver 500 may supply a data signal corresponding to a grayscale of an image to the data line DL, or may supply a predetermined reference voltage according to a driving mode of the display device 1000.

[0071] The timing controller 600 may control the driving of the first scan driver 200, the second scan driver 300, the emission driver 400, and the data driver 500 based on a timing signal supplied from the outside. The timing controller 600 may supply a first control signal SCS1 including a first start signal SSP1 and a scan clock signal to the first scan driver 200, and may supply a second control signal SCS2 including a second start signal SSP2 and a scan clock signal to the second scan driver 300. In addition, the timing controller 600 may supply a third control signal ECS and an emission control clock signal to the emission driver 400. The fourth control signal DCS controlling the data driver 500 may include a source start signal, a source output enable signal, a source sampling clock, and the like.

[0072] like Figure 1 As shown in FIG, the scan drivers 200 and 300 and the emission driver 400 according to the illustrated exemplary embodiment are shown as separate elements, however, the inventive concept is not limited thereto. For example, in some exemplary embodiments, the scan drivers 200 and 300 and the emission driver 400 may be formed by a single driver.

[0073] The scan drivers 200 and 300 and the emission driver 400 may be mounted on a substrate through a thin film process. In addition, the scan drivers 200 and 300 and / or the emission driver 400 may be disposed at both sides of a pixel region including the pixel PX.

[0074] Figure 2 is included in Figure 1 An exemplary circuit diagram of a pixel in a display device of FIG.

[0075] Figure 2The pixel PX1 arranged in the k-th row and the p-th column is exemplarily shown, where “k” and “p” are natural numbers.

[0076] refer to Figure 2 , the pixel PX1 may include a light emitting element LED and a pixel circuit PC1 connected to the light emitting element LED.

[0077] A first electrode of the light emitting element LED may be connected to the pixel circuit PC1, and a second electrode of the light emitting element LED may be connected to a second power supply VSS. The light emitting element LED may generate light of a predetermined brightness corresponding to the amount of current supplied from the pixel circuit PC1. The first electrode may be an anode, and the second electrode may be a cathode. Alternatively, the first electrode may be a cathode, and the second electrode may be an anode.

[0078] The pixel circuit PC1 controls the amount of current flowing from the first power source VDD to the second power source VSS via the light emitting element LED in response to the data voltage DATA. The pixel circuit PC1 according to the illustrated exemplary embodiment may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0079] The first transistor T1 may be connected between a first node N1 electrically connected to a first power source VDD and a second node N2 electrically connected to a first electrode of a light emitting element LED. The first transistor T1 may generate a driving current and provide the driving current to the light emitting element LED. A gate electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may be used as a driving transistor of the pixel PX1.

[0080] The second transistor T2 may be connected between the p-th data line DLp and the first node N1. The second transistor T2 may include a gate electrode receiving the k-th p-type scan signal SPk. The k-th p-type scan signal SPk may be supplied through the k-th p-type scan line SPLk. When the second transistor T2 is turned on, the data voltage DATA may be transferred to the first node N1.

[0081] The third transistor T3 may be connected between the second node N2 and the third node N3. The third transistor T3 may include a gate electrode receiving the kth n-type scan signal SNk. The kth n-type scan signal SNk may be supplied through the kth n-type scan line SNLk. The third transistor T3 may be turned on by the kth n-type scan signal SNk to electrically connect the second electrode of the first transistor T1 and the third node N3. In this way, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode. Specifically, the third transistor T3 may perform writing of the data voltage DATA and compensation of the threshold voltage of the first transistor T1.

[0082] The storage capacitor Cst is connected between the first power source VDD and the third node N3. The storage capacitor Cst may store a voltage corresponding to the data voltage DATA and a threshold voltage of the first transistor T1.

[0083] The fourth transistor T4 may be connected between the third node N3 and the initialization power source VINT. The fourth transistor T4 may include a gate electrode receiving the k-1th n-type scan signal SNk-1. The k-1th n-type scan signal SNk-1 may be supplied through the k-1th n-type scan line SNLk-1.

[0084] The fourth transistor T4 may be turned on by the k-1th n-type scan signal SNk-1 to supply the voltage of the initialization power supply VINT to the third node N3. In this way, the voltage of the third node N3 (i.e., the gate voltage of the first transistor T1) may be initialized to the voltage of the initialization power supply VINT. In an exemplary embodiment, the initialization power supply VINT may be set to a voltage lower than the lowest voltage of the data voltage.

[0085] The fifth transistor T5 may be connected between the first power source VDD and the first node N1. The fifth transistor T5 may include a gate electrode receiving a kth emission control signal Ek. The kth emission control signal Ek may be supplied through the kth emission control line ELk.

[0086] The sixth transistor T6 may be connected between the second node N2 and the first electrode of the light emitting element LED. The sixth transistor T6 may include a gate electrode receiving the kth emission control signal Ek.

[0087] The fifth transistor T5 and the sixth transistor T6 may be turned on during a gate-on period (eg, a period of a logic low level) of the kth emission control signal Ek, and may be turned off during a gate-off period of the kth emission control signal Ek.

[0088] The seventh transistor T7 may be connected between the initialization power supply VINT and the first electrode of the light emitting element LED. The seventh transistor T7 may include a gate electrode receiving the k-1th p-type scan signal SPk-1. The k-1th p-type scan signal SPk-1 may be supplied through the k-1th p-type scan line SPLk-1. However, in some exemplary embodiments, the gate electrode of the seventh transistor T7 may be connected to the kth p-type scan line SPLk or the k+1th p-type scan line.

[0089] The seventh transistor T7 may be turned on to supply the voltage of the initialization power source VINT to the first electrode of the light emitting element LED.

[0090] In an exemplary embodiment, initialization power sources having different voltage levels may be connected to the fourth transistor T4 and the seventh transistor T7, respectively. For example, a first initialization power source may be connected to one electrode of the fourth transistor T4, and a second initialization power source may be connected to one electrode of the seventh transistor T7.

[0091] In an exemplary embodiment, the first transistor T1, the second transistor T2, and the seventh transistor T7 may be p-type low temperature polysilicon (LTPS) thin film transistors, and the third transistor T3 and the fourth transistor T4 may be n-type oxide semiconductor thin film transistors. Since n-type oxide semiconductor thin film transistors are superior to p-type LTPS thin film transistors in terms of current leakage characteristics (or cut-off current characteristics), the third transistor T3 and the fourth transistor T4 as switch transistors may be formed of n-type oxide semiconductor thin film transistors.

[0092] In this way, the leakage current in the third transistor T3 and the fourth transistor T4 can be greatly reduced, so that the pixel can be driven and the image can be displayed at a low frequency of less than 30 Hz. In this way, the power consumption in the first mode can be reduced.

[0093] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 may be p-type LTPS thin film transistors.

[0094] In the following, the following will be described in more detail including Figure 2 1 and 2. A driving method of the display device 1000 of the pixel PX1 shown in FIG.

[0095] Figure 3 is an exemplary illustration of driving in the first mode Figure 1 Timing diagram of the display device.

[0096] refer to Figures 1 to 3 , the display device 1000 may operate in the first mode.

[0097] Figure 3 An example of a signal supplied to a pixel PX1 included in the k-th pixel row in the first mode is shown. In the first mode, scan signals SPk-1, SPk, SNk-1, and SNk and an emission control signal Ek may be supplied to the display panel 100 at the same frequency in each frame period. One frame period 1F may include an emission period EP and a non-emission period NEP.

[0098] exist Figure 3 , the lengths of the emission period EP and the non-emission period NEP included in one frame period 1F are shown to be similar to each other, however, the length of the emission period EP may be longer than that of the non-emission period NEP.

[0099] Since the second transistor T2 and the seventh transistor T7 are p-type LTPS transistors, the p-type scan signals SPk-1 and SPk may be supplied to the second transistor T2 and the seventh transistor T7.

[0100] Since the third transistor T3 and the fourth transistor T4 are n-type oxide semiconductor thin film transistors, the n-type scan signals SNk-1 and SNk may be supplied to the third transistor T3 and the fourth transistor T4.

[0101] In an exemplary embodiment, in the first mode, during the non-emission period NEP, three p-type scan signals SPk-1 and SPk and three n-type scan signals SNk-1 and SNk may be supplied to the pixel PX1. More specifically, each of the p-type scan signals SPk-1 and SPk and each of the n-type scan signals SNk-1 and SNk may be supplied to the pixel PX1 three times during the non-emission period NEP.

[0102] The k-th p-type scan signal SPk may be a signal in which the k-1-th p-type scan signal SPk-1 is shifted by one horizontal period 1 H. The k-1-th p-type scan signal SPk-1 and the k-th p-type scan signal SPk do not overlap with each other.

[0103] In an exemplary embodiment, the kth n-type scan signal SNk may be supplied simultaneously with the kth p-type scan signal SPk in the first mode. In the first mode, the k-1th n-type scan signal SNk-1 may be supplied simultaneously with the k-1th p-type scan signal SPk-1.

[0104] In response to each of the first signal and the second signal of the k-1th n-type scan signal SNk-1, the gate voltage of the first transistor T1 can be initialized, and the first transistor T1 can be in a turn-on bias state. In addition, in response to each of the first signal and the second signal of the kth n-type scan signal SNk and the kth p-type scan signal SPk, the first transistor T1 can be in a turn-off bias state.

[0105] More specifically, the gate voltage (and gate-source voltage) of the first transistor T1 is repeatedly changed so that a hysteresis change of the first transistor T1 according to the difference between the data voltage of the previous frame and the data voltage of the current frame can be reduced.

[0106] Then, the gate voltage of the first transistor T1 can be reinitialized by the third signal of the k-1th n-type scan signal SNk-1, and the data voltage DATA corresponding to the timing of the third signal of the kth p-type scan signal SPk can be stored in the storage capacitor Cst by the third signal of the kth n-type scan signal SNk and the third signal of the kth p-type scan signal SPk.

[0107] Then, the pixel PX1 may emit light at a grayscale corresponding to the data voltage DATA stored in the storage capacitor Cst during the emission period EP.

[0108] The k-1th p-type scan signal SPk-1 is independent of the bias state of the first transistor T1. For example, the anode (eg, the first electrode) of the light emitting element LED may be initialized in response to the k-1th p-type scan signal SPk-1.

[0109] As such, in the first mode, the on bias state and the off bias state of the first transistor T1 may be repeated during one frame period, thereby reducing hysteresis variation of the first transistor T1 and improving a transient residual image when the brightness variation is greater.

[0110] However, since the scan signal is output multiple times during one frame, the operation of the first mode increases power consumption. Therefore, when the display device 1000 displays a standby image, a low grayscale image, a static image, etc., power consumption should be reduced by, for example, reducing the driving frequency.

[0111] Figure 4 is an exemplary illustration of driving in the first mode Figure 1 Timing diagram of the display device.

[0112] Hereinafter, the first driving frequency of the first mode will be exemplarily described as 60 Hz. However, the inventive concept is not limited thereto, and in some exemplary embodiments, the first driving frequency may be variously set, such as 120 Hz.

[0113] refer to Figure 3 and Figure 4 In the first mode, during a predetermined unit period (or unit frame period), p-type scan signals SP1 to SPn ("n" is a natural number greater than 1) may be sequentially supplied, and at the same time, n-type scan signals SN1 to SNn may be sequentially supplied. For a unit time (e.g., about 1 second), the unit period may be repeated a number of times corresponding to the first driving frequency (e.g., 60 times). For example, 60 frames of images may be displayed at the first driving frequency.

[0114] The kth p-type scan signal SPk may overlap the kth n-type scan signal SNk.

[0115] The emission control signals E1 to En may be sequentially supplied, and may be repeatedly supplied with a unit period as a cycle.

[0116] In the first mode, the data voltage DATA may be stored in the pixel PX1 every frame.

[0117] Figure 5is an exemplary illustration of driving in the second mode Figure 1 Timing diagram of the display device.

[0118] refer to Figure 1 , Figure 2 and Figure 5 , the display device 1000 can operate in the second mode.

[0119] Figure 5 Schematically shows how the pixel PX1 included in the k-th pixel row is driven in the second mode. The second mode can be driven at a second driving frequency. The second driving frequency is lower than the first driving frequency. For example, the second driving frequency can be about 1 Hz.

[0120] like Figure 5 As shown in , in the second mode, the display device 1000 can operate with a first cycle C1, the first cycle C1 includes a first period P1 corresponding to one frame period 1F and a second period P2 including a plurality of consecutive frame periods. In the second mode, the supply of the scan signals SPk and SNk can be repeated with the period of the first cycle C1.

[0121] The first period P1 may include a data writing period WP and a first emission period EP1. Each frame period of the second period P2 may include a bias period BP and a second emission period EP2.

[0122] The data write period WP is a period during which the second transistor T2 and the third transistor T3 are turned on and the data voltage DATA is stored in the storage capacitor Cst. The bias period BP is a period during which only the second transistor T2 is turned on and a predetermined voltage is supplied to the source electrode of the first transistor T1 to supply (or maintain) the on bias to the first transistor T1. In this way, the first period P1 may also be referred to as a write period, and the second period P2 may also be referred to as a hold period.

[0123] In the second mode, during the first cycle C1, the pixel PX1 may emit light at a grayscale substantially corresponding to the data voltage DATA written in the data writing period WP. For example, the first cycle C1 may include 60 frame periods. In this case, the second period P2 may have 59 frame periods. More specifically, the pixel PX1 may emit light during 60 frame periods based on the data voltage DATA written in the data writing period WP of one frame period.

[0124] In an exemplary embodiment, during the second period P2, only the p-type scan signal is supplied to supply the conduction bias to the first transistor T1 and initialize the voltage of the anode of the light emitting element LED, and the n-type scan signal is not supplied. Therefore, the power consumption of supplying the scan signal can be reduced. For example, when the p-type scan signal is supplied at 60 Hz, the n-type scan signal can be supplied at 1 Hz in the second mode.

[0125] On the other hand, during the second period P2 in the second mode, there is substantially no writing operation of the data voltage. Therefore, the power consumption in the second mode can be further reduced by controlling the number of p-type scan signals supplied during the bias period BP.

[0126] The display device 1000 according to an exemplary embodiment may change the number of p-type scan signals supplied in the bias period BP of the second period P2 in the second mode to be less than the number of p-type scan signals supplied in one frame in the first mode and the first period P1 in the second mode, thereby improving power consumption.

[0127] Figure 6 is an exemplary illustration of driving in the second mode Figure 1 Timing diagram of the display device.

[0128] refer to Figure 1 , Figure 2 , Figure 5 and Figure 6 , in the second mode, the first period P1 including the data writing period WP and the first emission period EP1 and the second period P2 including the consecutive plurality of frame periods may be repeated.

[0129] exist Figure 6 , the lengths of the emission periods EP1 and EP2, the data write period WP, ​​and the bias period BP included in one frame period may be shown to be similar to each other, however, the length of each of the emission periods EP1 and EP2 may be longer than the length of each of the data write period WP and the bias period BP.

[0130] During the first period P1, "i" (i is a natural number greater than 1) k-1th p-type scan signals SPk-1 and "i"th k-1th p-type scan signals SPk can be supplied to the k-1th p-type scan line SPLk-1 and the k-th p-type scan line SPLk, respectively. In addition, during the first period P1, "i"th k-1th n-type scan signals SNk-1 and "i"th k-th n-type scan signals SNk can be supplied to the k-1th n-type scan line SNLk-1 and the k-th n-type scan line SNLk, respectively. The k-th p-type scan signal SPk and the k-th n-type scan signal SNk can be supplied simultaneously. For example, three p-type scan signals SPk-1 and SPk and three n-type scan signals SNk-1 and SNk can be supplied during the first period P1.

[0131] In this way, the operation of the pixel PX1 during the data writing period WP of the first period P1 can be consistent with the non-emission period NEP in the first mode (see Figure 3 The operation of the pixel PX1 during the data writing period WP of the first cycle C1 is substantially the same. The pixel PX1 may emit light at a brightness corresponding to the data voltage DATA supplied during the data writing period WP of the first cycle C1.

[0132] Each of the frame periods included in the second period P2 may include a bias period BP and a second emission period EP2. The n-type scan signals SNk-1 and SNk are not supplied during the second period P2. Thus, the third transistor T3 and the fourth transistor T4 may maintain a turned-off state during the second period P2.

[0133] During the bias period, "j"th k-1th p-type scan signal SPk-1 and "j"th k-th p-type scan signal SPk may be supplied to the k-1th p-type scan line SPLk-1 and the k-th p-type scan line SPLk, respectively, where j is a natural number of 1 or greater. In an exemplary embodiment, the number of p-type scan signals SPk-1 and SPk supplied during the bias period BP may be less than the number of p-type scan signals SPk-1 and SPk supplied during the data write period WP of the first period P1. For example, one k-1th p-type scan signal SPk-1 and one k-th p-type scan signal SPk may be supplied during the bias period BP.

[0134] During the bias period BP, in response to the k-1th p-type scan signal SPk-1, the seventh transistor T7 may be turned on and the voltage of the anode of the light emitting element LED may be initialized. In addition, during the bias period BP, in response to the k-th p-type scan signal SPk, the second transistor T2 may be turned on and a predetermined data voltage DATA may be supplied to the first node N1 (e.g., the source electrode of the first transistor T1).

[0135] More specifically, the on bias may be supplied to the first transistor T1 during the bias period BP. In this way, in the second mode in which data writing is intermittently performed, image defects such as flickering may be prevented or at least suppressed.

[0136] In an exemplary embodiment, the data voltage DATA supplied during the second period P2 may be the same as the data voltage DATA supplied during the first period P1. In another exemplary embodiment, a predetermined reference voltage may be supplied to each of the data lines DL during the second period P2. Specifically, a predetermined reference voltage may be supplied through the data lines DL during the second period P2 to apply a turn-on bias to the first transistor T1. For example, the reference voltage may be a voltage corresponding to a black grayscale.

[0137] The load on the entire display device 1000 may be generated by the p-type scan signals SPk-1 and SPk supplied during the bias period BP. For example, the load generated by the toggling for generating the p-type scan signals SPk-1 and SPk, the load on the signal line due to the conduction of the transistor by the p-type scan signals SPk-1 and SPk, etc. may consume power.

[0138] As described above, the display device 1000 according to the exemplary embodiment can initialize the anode of the light emitting element LED and apply the on bias to the first transistor T1 during the bias period in the second mode, thereby improving flickering that may otherwise occur due to low-frequency driving of 20 Hz or less (e.g., 1 Hz). In addition, the number of p-type scan signals SPk-1 and SPk supplied during the bias period BP is set to be less than the number of p-type scan signals supplied during one frame in the first mode and / or the data write period WP in the second mode, thereby preventing a load increase caused by conversion for generating the p-type scan signals SPk-1 and SPk, and further reducing power consumption in the second mode.

[0139] Fig. 7A It is exemplarily shown in Figure 1 A timing diagram of a start signal output in a first mode and a second mode of a display device, and Figure 7B It is exemplarily shown in Figure 1 0 is a timing diagram of the start signal output in the second mode of the display device shown in .

[0140] refer to Figure 1 , Fig. 7A and Figure 7B , the timing controller 600 may supply the first start signal SSP1 to the first scan driver 200 , and may supply the second start signal SSP2 to the second scan driver 300 .

[0141] In an exemplary embodiment, the number of p-type scan signals (or the number of transitions) may be determined according to the pulse width of the first start signal SSP1. Similarly, the number of n-type scan signals (or the number of transitions) may be determined according to the pulse width of the second start signal SSP2.

[0142] The first start signal SSP1 corresponds to a logic low level. Specifically, the p-type scan signal may be generated corresponding to a logic low level period of the first start signal SSP1.

[0143] The second start signal SSP2 corresponds to a logic high level. Specifically, the n-type scan signal may be generated corresponding to a logic high level period of the second start signal SSP2.

[0144] In the first mode, the timing controller 600 may supply a first start signal SSP1 having a first width W1 to the first scan driver 200 for each frame period. In addition, in the first mode, the timing controller 600 may supply a second start signal SSP2 having a first width W1 to the second scan driver 300 for each frame period.

[0145] In response to the first period P1 in the second mode, the timing controller 600 may supply the first start signal SSP1 having the first width W1 to the first scan driver 200, and may supply the second start signal SSP2 having the first width W1 to the second scan driver 300. Therefore, the number of p-type scan signals and the number of n-type scan signals (or the number of transitions) supplied in one frame in the first mode and the first period P1 in the second mode may be the same.

[0146] In response to the second period P2 in the second mode, the timing controller 600 may supply the first start signal SSP1 having the second width W2 to the first scan driver 200. In this case, the second width W2 may be smaller than the first width W1. Since the second width W2 is smaller than the first width W1, the number of p-type scan signals supplied to the pixel PX1 during each bias period of the second period P2 may be less than the number of p-type scan signals supplied during the data write period WP of the first period P1.

[0147] On the other hand, the timing controller 600 may stop the supply of the second start signal SSP2 during the second period P2 in the second mode.

[0148] like Figure 7BAs shown in , in the second mode, the first cycle C1 may be repeated. For example, in the second mode, the first start signal SSP1 may be generated at a driving frequency of 60 Hz, and the second start signal SSP2 may be generated at a driving frequency of 1 Hz. Specifically, the first cycle C1 may include 60 frame periods.

[0149] Fig. 8A It is exemplarily shown in Figure 1 A timing diagram of a scanning signal output in a second mode of a display device, and Figure 8B is an exemplary illustration with Fig. 8A Timing diagram of the start signal corresponding to the scan signal.

[0150] Hereinafter, the kth p-type scan signal SPk will be described as the p-type scan signal SPk, and the kth n-type scan signal SNk will be described as the n-type scan signal SNk.

[0151] refer to Figure 1 , Fig. 8A and Figure 8B , the number of the p-type scan signals SPk supplied in the second period P2 may be changed according to the driving frequency of the second mode.

[0152] In an exemplary embodiment, as the second driving frequency DFA2 decreases, the number of p-type scan signals SPk supplied during each of the frame periods of the second period P2 may decrease.

[0153] like Fig. 8A As shown in FIG. 1 , in response to the second driving frequency DFA2, one p-type scan signal SPk may be supplied to the p-type scan line during each frame period of the second period P2, and in response to the third driving frequency DFA3, two p-type scan signals SPk may be supplied to the p-type scan line during each frame period of the second period P2. The third driving frequency DFA3 may be greater than the second driving frequency DFA2. For example, the third driving frequency DFA3 may be 20 Hz, and the second driving frequency DFA2 may be 1 Hz. However, the inventive concept is not limited to a specific number of p-type scan signals SPk output according to the driving frequency.

[0154] like Figure 8BAs shown in , as the second driving frequency DFA2 decreases, the pulse width of the first start signal SSP1 corresponding to each of the frame periods of the second period P2 may be reduced. In the first cycle C1 driven at the second driving frequency DFA2, the first start signal SSP1 corresponding to the bias period BP may have a second width W2. In the second cycle C2 driven at the third driving frequency DFA3, the first start signal SSP1 corresponding to the bias period BP may have a third width W3. Since the third driving frequency DFA3 is greater than the second driving frequency DFA2, the third width W3 may be greater than the second width W2.

[0155] The first scan driver 200 may output the p-type scan signal SPk in synchronization with a predetermined clock signal included in a logic low level period of the first start signal SSP1. The number of the p-type scan signals SPk may be determined by the width of the first start signal SSP1.

[0156] As such, in the second mode, the number of p-type scan signals supplied in the bias period BP is adaptively adjusted according to the change in the driving frequency, thereby improving flicker and power consumption that may otherwise occur in low-frequency driving.

[0157] Fig. 9 is an exemplary illustration included in Figure 1 Circuit diagram of a pixel in a display device.

[0158] Except for a part of the structure of the seventh transistor T7 included in the pixel circuit PC2, Fig. 9 The pixel PX2 is Figure 2 The pixels PX1 have substantially the same structure and operate in a substantially similar manner, and thus repeated description of substantially similar elements will be omitted to avoid redundancy.

[0159] refer to Figure 2 and Fig. 9 , the pixel PX2 may include a light emitting element LED and a pixel circuit PC2 connected thereto.

[0160] The pixel circuit PC2 controls the amount of current flowing from the first power source VDD to the second power source VSS via the light emitting element LED in response to the data voltage DATA.

[0161] The pixel circuit PC2 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0162] The fourth transistor T4 may be connected between the third node N3 and the first initialization power source VINT1. The fourth transistor T4 may include a gate electrode receiving the k-1th n-type scan signal SNk-1.

[0163] The seventh transistor T7 may be connected between the second initialization power source VINT2 and the first electrode (eg, anode) of the light emitting element LED. The seventh transistor T7 may include a gate electrode receiving the k-1th p-type scan signal SPk-1.

[0164] Since the fourth transistor T4 and the seventh transistor T7 are connected to different initialization power supplies VINT1 and VINT2, respectively, the initialization operation of the gate voltage of the first transistor T1 and the initialization operation of the voltage of the anode of the light emitting element LED may be improved.

[0165] As described above, the display device and the driving method thereof according to the exemplary embodiment can initialize the anode of the light-emitting element and apply the conduction bias to the first transistor during the bias period in the second mode. In this way, the flicker caused by the low-frequency driving of 20Hz or lower (e.g., 1Hz) can be reduced or minimized. In addition, the number of p-type scan signals supplied during the bias period is set to be less than the number of p-type scan signals supplied during one frame of the first mode and / or the data writing period of the second mode, thereby preventing the load increase caused by the conversion for generating the p-type scan signal and further reducing the power consumption in the second mode.

[0166] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims, and various obvious modifications and equivalent arrangements will be apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: a display panel including a plurality of pixels connected to a p-type scan line, an n-type scan line, and a data line, and configured to display an image in a first mode driven at a first driving frequency or in a second mode driven at a second driving frequency lower than the first driving frequency; a first scan driver configured to supply a p-type scan signal having a first voltage to the p-type scan line; as well as a second scan driver configured to supply an n-type scan signal having a second voltage greater than the first voltage to the n-type scan line, in: The second mode includes a first period corresponding to one frame period and a second period including a plurality of consecutive frame periods; During the first period, the first scan driver is configured to supply i p-type scan signals to the p-type scan lines, and the second scan driver is configured to supply i n-type scan signals to the n-type scan lines, i being a natural number; and During at least one of the plurality of consecutive frame periods of the second period, the first scan driver is configured to supply j p-type scan signals to the p-type scan lines, j being a natural number different from i.

2. The display device according to claim 1, wherein: The first scan driver is configured to supply the j p-type scan signals to the p-type scan lines in each of the plurality of frame periods of the second period.

3. The display device according to claim 2, wherein: The number of the p-type scan signals supplied during each of the plurality of frame periods of the second period is less than the number of the p-type scan signals supplied during the first period.

4. The display device according to claim 2, wherein: The first scan driver is further configured to reduce the number of the p-type scan signals output in each of the plurality of frame periods of the second period as the second driving frequency decreases.

5. The display device according to claim 1, wherein: The second scan driver is further configured not to supply the n-type scan signal during the second period.

6. The display device according to claim 1, wherein: The first scan driver is further configured to supply i of the p-type scan signals to the p-type scan lines during one frame period in the first mode; and The second scan driver is further configured to supply i of the n-type scan signals to the n-type scan lines during one frame period in the first mode.

7. The display device according to claim 1, wherein: The first scan driver and the second scan driver are further configured to simultaneously supply the p-type scan signal and the n-type scan signal to the p-type scan line and the n-type scan line, respectively, during the first period.

8. The display device according to claim 1 further comprises a timing controller, wherein the timing controller is configured to supply the same number of start signals to the first scan driver and the second scan driver in the first mode, and to supply different numbers of start signals to the first scan driver and the second scan driver in the second mode.

9. The display device according to claim 8, wherein: The timing controller is further configured to supply a first start signal having a first width to the first scan driver and supply a second start signal having the first width to the second scan driver in response to the first period in the second mode.

10. The display device according to claim 9, wherein: The timing controller is further configured to supply the first start signal having a second width smaller than the first width to the first scan driver in response to the second period of the second mode.

11. The display device according to claim 10, wherein: The timing controller is further configured to reduce the second width of the first start signal as the second driving frequency decreases.

12. The display device according to claim 10, wherein: The timing controller is further configured to not supply the second start signal to the second scan driver in response to the second period of the second mode. 13 . The display device of claim 1 , further comprising an emission driver configured to supply an emission control signal to an emission control line connected to each of the plurality of pixels to define an emission period and a non-emission period.

14. The display device according to claim 1, further comprising: A data driver is configured to supply a data signal to the data line.

15. The display device according to claim 1, wherein: Each of the plurality of pixels comprises: Light emitting element; a first transistor connected between a first node electrically connected to a first power source and a second node electrically connected to a first electrode of the light emitting element and configured to control a driving current; a second transistor connected between the data line and the first node and configured to be turned on by the p-type scanning signal supplied to the k-th p-type scanning line, where k is a natural number greater than 1; a third transistor connected between the second node and a third node connected to the gate electrode of the first transistor and configured to be turned on by the n-type scan signal supplied to the k-th n-type scan line; a fourth transistor connected between the third node and an initialization power source and configured to be turned on by the n-type scan signal supplied to the k-1th n-type scan line; a fifth transistor connected between the first power source and the first node and configured to be turned on by an emission control signal supplied to the kth emission control line; a sixth transistor connected between the second node and the first electrode of the light emitting element and configured to be turned on by the emission control signal; a seventh transistor connected between the initialization power source and the first electrode of the light emitting element and configured to be turned on by the p-type scan signal supplied to the (k-1)th p-type scan line; and A storage capacitor is connected between the first power source and the third node.

16. The display device according to claim 15, wherein: The first transistor and the second transistor include p-type low temperature polysilicon thin film transistors; and The third transistor and the fourth transistor include n-type oxide semiconductor thin film transistors.

17. A method for driving a display device, the display device comprising a plurality of pixels connected to a p-type scan line, an n-type scan line and a data line, for displaying an image in a first mode driven at a first drive frequency or in a second mode driven at a second drive frequency lower than the first drive frequency, the method comprising: In a first period corresponding to one frame period, i p-type scan signals having a first voltage are supplied to the p-type scan line, and i n-type scan signals having a second voltage greater than the first voltage are supplied to the n-type scan line, where i is a natural number greater than 1; as well as In each frame period of a second period including a plurality of consecutive frame periods, j p-type scan signals are supplied to the p-type scan line, j being a natural number smaller than i, The first time period and the second time period are included in the second mode.

18. The driving method according to claim 17, wherein: As the second driving frequency decreases, the number of the p-type scan signals supplied during each of the plurality of frame periods of the second period decreases.

19. The driving method according to claim 17, further comprising: In each frame period included in the first mode, i of the p-type scan signals are supplied to the p-type scan line and i of the n-type scan signals are supplied to the n-type scan line.

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