Thin film transistor, manufacturing method thereof, and display device

Abstract

The upper insulating layer of the thin film transistor of the present invention includes: a first edge region, which is located near the first side surface of the gate electrode and has a height from the upper surface of the oxide semiconductor layer less than the height of the upper surface of the gate electrode; and a second edge region, which is located near the second side surface of the gate electrode and has a height from the upper surface of the oxide semiconductor layer less than the height of the upper surface of the gate electrode. The upper insulating layer has a porous insulator layer, and the porous insulator layer includes a first part disposed in the first edge region and a second part disposed in the second edge region. The first part of the porous insulator layer is in contact with at least a part of the first region of the oxide semiconductor layer, and the second part of the porous insulator layer is in contact with at least a part of the second region of the oxide semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a thin film transistor, a method for manufacturing the same, and a display device. Background Art

[0002] An active matrix substrate is used for display devices such as a liquid crystal display device, an organic EL (ElectroLuminescence) display device, and a micro LED (Light Emitting Diode) display device. A micro LED display device is a display device in which a plurality of light emitting diodes (LEDs) made of an inorganic compound are two-dimensionally arranged.

[0003] In each pixel of the active matrix substrate, a circuit including a thin film transistor (hereinafter referred to as "TFT") (referred to as "pixel circuit") is disposed. In a current-driven display device such as a micro LED display device or an organic EL display device, for example, a light emitting element (LED, organic EL element, etc.) whose emission luminance changes according to current is disposed corresponding to each pixel. The current supplied to the light emitting element of each pixel is controlled by the pixel circuit.

[0004] In addition, in the active matrix substrate, there is a case where peripheral circuits such as a driving circuit are formed monolithically. The TFT is also used as a circuit element of the peripheral circuit.

[0005] In the present specification, the TFT used for the pixel circuit is referred to as "pixel circuit TFT", and the TFT constituting the peripheral circuit is referred to as "peripheral circuit TFT".

[0006] As the TFT used in the active matrix substrate, an amorphous silicon TFT using an amorphous silicon film (hereinafter simply referred to as "a-Si film") as an active layer, a polysilicon TFT using a polysilicon film (hereinafter referred to as "poly-Si film") as an active layer, etc. have been widely used in the past. Instead of these silicon TFTs, a TFT using an oxide semiconductor such as an In-Ga-Zn-O-based semiconductor (hereinafter referred to as "oxide semiconductor TFT") is sometimes used.

[0007] For example, Patent Document 1 and Patent Document 2 disclose that an oxide semiconductor TFT having a top gate structure is used as a pixel circuit TFT. In Patent Document 1, it is proposed to reduce the parasitic capacitance of the oxide semiconductor TFT by arranging the gate electrode so as not to overlap with the source electrode and the drain electrode by using a self-alignment technique.

[0008] Prior Art Documents

[0009] Patent Documents

[0010] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-056566

[0011] Patent Document 2: Japanese Patent Application Laid-Open No. 2011-187506 Summary of the Invention

[0012] Technical Problem to be Solved by the Invention

[0013] Sometimes, it is necessary to further reduce the parasitic capacitance of the TFTs used in pixel circuits and peripheral circuits.

[0014] For example, in a current-driven display device, if the parasitic capacitance of the pixel circuit TFT is large, when the pixel circuit TFT switches from on to off, the charge stored in the parasitic capacitance is supplied to the light-emitting element that is about to turn off. As a result, the light-emitting operation of the light-emitting element that is about to turn off continues for a while, which may cause a display defect called "image ghosting failure".

[0015] In addition, if the parasitic capacitance of the peripheral circuit TFTs constituting the peripheral circuit is large, it may cause a decrease in the operating speed of the peripheral circuit, an increase in power consumption, etc.

[0016] However, the inventors have found that it is difficult to further reduce the parasitic capacitance in conventional TFT structures (for example, Patent Documents 1 and 2).

[0017] One embodiment of the present invention has been completed in view of the above circumstances, and an object thereof is to provide an oxide semiconductor TFT capable of reducing parasitic capacitance, a manufacturing method thereof, and a display device including such an oxide semiconductor TFT.

[0018] Solution to the Problem

[0019] [Item 1] A thin film transistor, comprising:

[0020] A substrate;

[0021] An oxide semiconductor layer supported by the substrate and including a first region, a second region, and a channel region located between the first region and the second region;

[0022] A gate electrode disposed over the channel region of the oxide semiconductor layer with a gate insulating layer therebetween;

[0023] A source electrode electrically connected to the first region of the oxide semiconductor layer;

[0024] A drain electrode electrically connected to the second region of the oxide semiconductor layer, and

[0025] An upper insulating layer covering the oxide semiconductor layer, the gate insulating layer, and the gate electrode;

[0026] When viewed in the normal direction of the substrate, the gate electrode overlaps with the channel region of the oxide semiconductor layer and does not overlap with the first region and the second region. When viewed in the normal direction of the substrate, the side surface of the gate electrode has a first side surface portion and a second side surface portion. The first side surface portion is located on the first region side and overlaps with the oxide semiconductor layer, and the second side surface portion is located on the second region side and overlaps with the oxide semiconductor layer.

[0027] The upper insulating layer includes:

[0028] A first edge region, which is located near the first side surface portion of the gate electrode when viewed in the normal direction of the substrate, and the height of the first edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode; and

[0029] A second edge region, which is located near the second side surface portion of the gate electrode when viewed in the normal direction of the substrate, and the height of the second edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode.

[0030] The upper insulating layer has a porous insulator layer, and the porous insulator layer includes a first portion disposed in the first edge region and a second portion disposed in the second edge region.

[0031] The first portion of the porous insulator layer is in contact with at least a part of the first region of the oxide semiconductor layer, and the second portion of the porous insulator layer is in contact with at least a part of the second region of the oxide semiconductor layer.

[0032] [Item 2] In the thin film transistor described in Item 1, the gate insulating layer includes a silicon oxide layer.

[0033] [Item 3] In the thin film transistor described in Item 1 or 2, the relative dielectric constant of the porous insulator layer at a frequency of 1 MHz is 3.0 or less.

[0034] [Item 4] In the thin film transistor described in any one of Items 1 to 3, the first portion of the porous insulator layer is in contact with the first side surface portion of the gate electrode, and the second portion of the porous insulator layer is in contact with the second side surface portion of the gate electrode.

[0035] [Item 5] In the thin film transistor described in any one of Items 1 to 4, when viewed in the normal direction of the substrate, the side surface of the gate insulating layer is aligned with the side surface of the gate electrode.

[0036] [Item 6] In the thin film transistor described in Item 5, the porous insulator layer is in contact with the side surface of the gate insulating layer.

[0037] [Item 7] In the thin film transistor described in any one of Items 1 to 4, when viewed from the normal direction of the substrate, the side surface of the gate insulating layer is located inside the side surface of the gate electrode.

[0038] [Item 8] In the thin film transistor described in Item 7, at least a part of the porous insulator layer is arranged to be in contact with the side surface of the gate insulating layer between the gate electrode and the channel region.

[0039] [Item 9] In the thin film transistor described in Item 7, a gap is formed between the gate electrode and the channel region and between the side surface of the gate insulating layer and the upper insulating layer.

[0040] [Item 10] In the thin film transistor described in any one of Items 1 to 9, the upper insulating layer includes a non-porous insulator layer disposed on the porous insulator layer.

[0041] [Item 11] In the thin film transistor described in Item 10,

[0042] When viewed from the normal direction of the substrate, the upper insulating layer has: a first insulating portion including the first edge region and the second edge region; and a second insulating portion located outside the first insulating portion,

[0043] The first insulating portion includes the porous insulator layer and the non-porous insulator layer, and the second insulating portion includes the non-porous insulator layer but does not include the porous insulator layer,

[0044] A first opening for connecting the source electrode to the first region and a second opening for connecting the drain electrode to the second region are provided in the second insulating portion.

[0045] [Item 12] In the thin film transistor described in any one of Items 1 to 10, the thickness of the porous insulator layer is greater than or equal to the thickness of the gate electrode.

[0046] [Item 13] In the thin film transistor described in any one of Items 1 to 12, the porous insulator layer is formed of an organic SOG film or an inorganic SOG film.

[0047] [Item 14] In the thin film transistor described in any one of Items 1 to 13, the first region of the oxide semiconductor layer has a first low-resistance region on the surface with a resistivity lower than that of the channel region, and the second region of the oxide semiconductor layer has a second low-resistance region on the surface with a resistivity lower than that of the channel region.

[0048] The first portion of the porous insulator layer is in contact with at least a part of the first low-resistance region, and the second portion of the porous insulator layer is in contact with at least a part of the second low-resistance region.

[0049] [Item 15] A display device, comprising:

[0050] The thin film transistor described in any one of Items 1 to 14;

[0051] A display region having a plurality of pixels; and

[0052] A pixel circuit configured corresponding to each of the plurality of pixels,

[0053] wherein the pixel circuit includes the thin film transistor.

[0054] [Item 16] In the display device described in Item 15, the display device further has a current-driven light-emitting element configured corresponding to each of the plurality of pixels, and the pixel circuit drives the light-emitting element.

[0055] [Item 17] A method for manufacturing a thin film transistor, which is a method for manufacturing a thin film transistor supported by a substrate, the manufacturing method including:

[0056] Step (A) of forming an oxide semiconductor layer on the substrate;

[0057] Step (B) of sequentially forming a gate insulating layer and a gate electrode on a part of the oxide semiconductor layer; and

[0058] Step (C) of forming an upper insulating layer including a porous insulator layer so as to cover the oxide semiconductor layer, the gate insulating layer, and the gate electrode.

[0059] Among them, the upper insulating layer includes: a first edge region which is located near a first side surface portion of the gate electrode when viewed from the normal direction of the substrate, and a height of the first edge region from an upper surface of the oxide semiconductor layer is less than a height of an upper surface of the gate electrode; and a second edge region which is located near a second side surface portion of the gate electrode when viewed from the normal direction of the substrate, and a height of the second edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode. The porous insulator layer includes a first portion disposed in the first edge region and a second portion disposed in the second edge region, and the first portion and the second portion of the porous insulator layer are respectively in contact with portions of the oxide semiconductor layer not covered by the gate insulating layer.

[0060] The process (B) includes:

[0061] A process (B1) of sequentially forming an insulating film and a gate conductive film on the oxide semiconductor layer;

[0062] A process (B2) of patterning the gate conductive film using a first mask and forming the gate electrode; and

[0063] After the process (B2), a process (B3) of patterning the insulating film by using the first mask or using the gate electrode as a mask to obtain the gate insulating layer. In this process, when viewed from the normal direction of the substrate, a side surface of the gate insulating layer is located more inward than a side surface of the gate electrode.

[0064] [Item 18] In the thin film transistor described in Item 17, in the process (B3), the gate insulating layer is obtained by isotropically etching the insulating film by using the first mask or using the gate electrode as a mask.

[0065] [Item 19] In the thin film transistor described in Item 17,

[0066] The process (B3) includes:

[0067] A process (B4) of obtaining a gate insulating layer precursor by anisotropically etching the insulating film by using the first mask or using the gate electrode as a mask; and

[0068] A process (B5) of obtaining the gate insulating layer by etching a side surface of the gate insulating layer precursor.

[0069] [Item 20] In the thin film transistor described in any one of Items 17 to 19, the step (C) includes a step of forming the porous insulator layer in contact with the side surface of the gate insulating layer.

[0070] [Item 21] In the thin film transistor described in any one of Items 17 to 20, the step (C) includes a step of forming the porous insulator layer in contact with the side surface of the gate insulating layer.

[0071] Advantageous Effects

[0072] According to an embodiment of the present invention, there is provided an oxide semiconductor TFT capable of reducing parasitic capacitance, a manufacturing method thereof, and a display device including such an oxide semiconductor TFT. Description of the Drawings

[0073] Figure 1A is a schematic cross-sectional view of the TFT 101 of the embodiment.

[0074] Figure 1B is a schematic top view of the TFT 101 of the embodiment.

[0075] Figure 2A is a process cross-sectional view for explaining the manufacturing method of the TFT 101.

[0076] Figure 2B is a process cross-sectional view for explaining the manufacturing method of the TFT 101.

[0077] Figure 2C is a process cross-sectional view for explaining the manufacturing method of the TFT 101.

[0078] Figure 2D is a process cross-sectional view for explaining the manufacturing method of the TFT 101.

[0079] Figure 2E is a process cross-sectional view for explaining the manufacturing method of the TFT 101.

[0080] Figure 3A is a cross-sectional view of the TFT 102 showing Modification 1.

[0081] Figure 3B is a cross-sectional view of another TFT 103 showing Modification 1.

[0082] Figure 4A is a process cross-sectional view for explaining the manufacturing method of the TFT 102.

[0083] Figure 4B is a process cross-sectional view for explaining the manufacturing method of the TFT 102.

[0084] Figure 4C It is a process cross-sectional view for explaining the manufacturing method of TFT102.

[0085] Figure 5A It is a cross-sectional view of TFT104 showing Modification 2.

[0086] Figure 5B It is a cross-sectional view of another TFT105 showing Modification 2.

[0087] Figure 5C It is a cross-sectional view of another TFT106 showing Modification 2.

[0088] Figure 6 It is a schematic cross-sectional view for explaining the manufacturing methods of the first and second edge regions FR1 and FR2.

[0089] Figure 7 It is a cross-sectional view of TFT900 of the reference example. Detailed Description of the Invention

[0090] (Embodiment)

[0091] Hereinafter, with reference to the drawings, an oxide semiconductor TFT having an oxide semiconductor layer as an active layer will be described as an example of the TFT of the embodiment.

[0092] Figure 1A and Figure 1B are a cross-sectional view and a top view showing TFT101 of the present embodiment, respectively. Figure 1A Shows a cross-section taken along the line Ia-Ia' shown in Figure 1B FIG.

[0093] TFT101 includes: a substrate 1 such as a glass substrate; an oxide semiconductor layer 7 supported by the substrate 1; a gate electrode 11; a gate insulating layer 9 disposed between the oxide semiconductor layer 7 and the gate electrode 11; and source and drain electrodes 15s and 15d electrically connected to the oxide semiconductor layer 7. In this example, the gate electrode 11 is disposed on a part of the oxide semiconductor layer 7 with the gate insulating layer 9 interposed therebetween (top gate structure). A lower insulating layer 5 can be formed between the oxide semiconductor layer 7 and the substrate 1 as a base film.

[0094] When viewed from the normal direction of the substrate 1, the oxide semiconductor layer 7 includes a first region 7S, a second region 7D, and a region (channel region) 7C that is located between the first region 7S and the second region 7D and forms the channel of TFT101. The source electrode 15s is electrically connected to the first region 7S. The drain electrode 15d is electrically connected to the second region 7D.

[0095] On the surfaces of the first region 7S and the second region 7D of the oxide semiconductor layer 7, a first low-resistance region 8s and a second low-resistance region 8d having a resistivity lower than that of the surface of the channel region 7C may be formed, respectively. The source electrode 15s may be electrically connected to the first low-resistance region 8s, and the drain electrode 15d may be electrically connected to the second low-resistance region 8d.

[0096] When viewed from the normal direction of the substrate 1, the gate electrode 11 is arranged to overlap with the channel region 7C and not to overlap with the first region 7S and the second region 7D. In this specification, when viewed from the normal direction of the substrate 1, a portion e1 of the side surface of the gate electrode 11 that is on the side closer to the first region 7S and overlaps with the oxide semiconductor layer 7 is referred to as the "first side surface portion", and a portion e2 of the side surface of the gate electrode 11 that is on the side closer to the second region 7D and overlaps with the oxide semiconductor layer 7 is referred to as the "second side surface portion".

[0097] The gate insulating layer 9 may also be formed between the oxide semiconductor layer 7 and the gate electrode 11. For example, the same mask may be used to pattern the gate insulating layer 9 and the gate electrode 11.

[0098] An upper insulating layer 13 is provided on the oxide semiconductor layer 7, the gate insulating layer 9, and the gate electrode 11. The upper insulating layer 13 has a first opening CHs reaching the first region 7S and a second opening CHd reaching the second region 7D. The source electrode 15s is formed on the upper insulating layer 13 and within the first opening CHs, and within the first opening CHs, the source electrode 15s is electrically connected to the first region 7S (here, the first low-resistance region 8s) of the oxide semiconductor layer 7. The drain electrode 15d is formed on the upper insulating layer 13 and within the second opening CHd, and within the second opening CHd, the drain electrode 15d is electrically connected to the second region 7D (here, the second low-resistance region 8d) of the oxide semiconductor layer 7.

[0099] The upper insulating layer 13 includes a porous insulator layer 13a. In this specification, a region of the upper insulating layer 13 that can form the capacitance (fringing capacitance) between the first side surface portion e1 of the gate electrode 11 and the first region 7S (here, the first low-resistance region 8s) of the oxide semiconductor layer 7 is referred to as the "first fringing region". Similarly, a region of the upper insulating layer 13 that can form the fringing capacitance between the second side surface portion e2 of the gate electrode 11 and the second region 7D (here, the second low-resistance region 8d) of the oxide semiconductor layer 7 is referred to as the "second fringing region". The porous insulator layer 13a may be provided in at least a part of the first fringing region and at least a part of the second fringing region. In other words, the porous insulator layer 13a includes a portion (referred to as the "first portion") p1 located in the first fringing region and a portion (referred to as the "second portion") p2 located in the second fringing region.

[0100] Figure 6 It is a schematic cross-sectional view showing an example of the first and second edge regions FR1 and FR2. The first edge region refers to, for example, a region FR1 in the upper insulating layer 13 that is near the first side surface e1 of the gate electrode 11 when viewed from the normal direction of the substrate 1, and the height of this region from the upper surface of the oxide semiconductor layer 7 is less than the height hg of the upper surface of the gate electrode 11. The second edge region refers to, for example, a region FR2 in the upper insulating layer 13 that is near the second side surface e2 of the gate electrode 11 when viewed from the normal direction of the substrate 1, and the height of this region from the upper surface of the oxide semiconductor layer 7 is less than the height hg of the upper surface of the gate electrode 11. In addition, the region located "near the first side surface e1 (or the second side surface e2) of the gate electrode 11 when viewed from the normal direction of the substrate 1" means, for example, in the surface of the substrate 1, the distance from the first side surface e1 or the second side surface e2 of the gate electrode 11 is less than or equal to a specified length wf. The specified length wf can be equal to, for example, the thickness tg of the gate electrode 11. The region where "the height from the upper surface of the oxide semiconductor layer 7 is less than the height hg of the upper surface of the gate electrode 11" is, for example, a region below the plane including the upper surface of the gate electrode 11 (on the substrate 1 side).

[0101] As the porous insulator layer 13a, examples can include inorganic SOG (spin on glass) films such as porous silica films and organic SOG films. The method of forming the porous insulator layer 13a is not limited to the coating method and can be other methods such as CVD methods. The porous insulator layer 13a can be formed of, for example, a porous SiOC film, a porous SiOF film, etc. formed by CVD. The interior of the porous insulator layer 13a has a large number of fine pores (relative dielectric constant: about 1), and thus has a low dielectric constant. The relative dielectric constant of the porous insulator layer 13a is, for example, 3.0 or less, preferably 2.5 or less. In addition, the "relative dielectric constant" described in this specification is the relative dielectric constant at a frequency of 1 MHz.

[0102] In Figure 1A and Figure 1B In the TFT101 shown, the upper insulating layer 13 has a laminated structure including a porous insulator layer 13a and a non-porous insulator layer 13b provided on the porous insulator layer 13a. The porous insulator layer 13a can be formed so as to cover the oxide semiconductor layer 7, the gate insulating layer 9, and the gate electrode 11. In addition, the thickness of the porous insulator layer 13a can be set such that the porous insulator layer 13a can be provided in the entire region of the first and second edge regions.

[0103] Here, the advantages of disposing the porous insulator layer 13a in the first and second edge regions will be described with reference to the accompanying drawings.

[0104] Figure 7 FIG. 4 is a schematic cross-sectional view of a reference example TFT 900 having a top-gate structure. For simplicity, the same reference numerals are given to the same components as those shown in FIG. 1. The difference between the TFT 900 and the TFT 101 is that the upper insulating layer 13 of the TFT 900 does not include the porous insulator layer 13a and is composed only of the non-porous insulator layer 13b.

[0105] The parasitic capacitance Ctotal of the reference example TFT 900 includes the parasitic oxide film capacitance Cct between the gate electrode 11 and the oxide semiconductor layer 7, the capacitance of the portion where the gate electrode 11 overlaps with the first low-resistance region 8s and the second low-resistance region 8d with an insulator therebetween (hereinafter referred to as "overlap capacitance") Cov, and the fringe capacitance Cfr. The fringe capacitance Cfr is the sum of the first capacitance generated between the first side surface portion e1 of the gate electrode 11 and the low-resistance region 8s and the second capacitance generated between the second side surface portion e2 of the gate electrode 11 and the low-resistance region 8d. The parasitic capacitance Ctotal is represented by the following formula (1).

[0106] Ctotal = Cct + 2(Cov + Cfr) + Cov + Cfr (1)

[0107] In addition, in formula (1), Cov + Cfr (Miller capacitance) is added in consideration of the Miller effect. When formula (1) is expressed using the gate capacitance Cg (= Cct + 2Cov), the following formula (2) is obtained.

[0108] Ctotal = Cg + 3Cfr + Cov (2)

[0109] From the above formula (2), it can be seen that by reducing especially the fringe capacitance Cfr, the parasitic capacitance Ctotal can be more effectively reduced (three times the reduction amount of the fringe capacitance Cfr).

[0110] In addition, when the shapes, thicknesses, etc. of the gate electrode 11 and the gate insulating layer 9 are the same, the higher the relative dielectric constant ε of the insulating film (here, the non-porous insulator layer 13b) located in the first and second edge regions FR1, FR2 (see Figure 6 ), the larger the fringe capacitance Cfr. Generally, as the upper insulating layer 13 (non-porous insulator layer 13b), a silicon oxide film (relative dielectric constant: for example, 3.9), a silicon nitride film such as Si3N4 (relative dielectric constant: for example, 7.5), etc. can be used.

[0111] In contrast, in the TFT101 of the present embodiment, a porous insulator layer 13a having a small relative permittivity is disposed in the first and second edge regions. Thereby, the relative permittivity ε of the insulating film forming the edge capacitance can be reduced, and thus the edge capacitance Cfr can be reduced. As can be seen from the above formula (2), when the edge capacitance Cfr is reduced, it is three times the reduction amount of the edge capacitance Cfr reduced from the total parasitic capacitance Ctotal. As an example, when the area of the side surface of the gate electrode 11 and the thickness of the gate insulating layer 9 are the same, by disposing the porous insulator layer 13a (for example, porous silica (relative permittivity: 2.2)) in the first and second edge regions, compared with the case where the non-porous insulator layer 13b (for example, silicon oxide (SiO2) (relative permittivity: for example 4.1)) is provided in the first and second edge regions, the edge capacitance Cfr can be reduced by 46%. As a result, the parasitic capacitance Ctotal can be reduced by an amount three times the reduction amount of the edge capacitance.

[0112] Therefore, when the TFT101 is used as the pixel circuit TFT of the display device, the occurrence of image ghosting failures due to parasitic capacitance can be suppressed. In addition, since the time required to discharge the charge stored in the pixel circuit TFT can be reduced, the refresh rate, gray-scale performance, etc. can be improved. Further, when used as the peripheral circuit TFT, it has advantages such as reducing power consumption and increasing the operating speed of the peripheral circuit.

[0113] As described above, the porous insulator layer 13a includes Figure 6 a first portion p1 located in the first edge region FR1 and a second portion p2 located in the second edge region FR2 as shown. The porous insulator layer 13a can be provided in at least a part of each edge region. Alternatively, the porous insulator layer 13a is configured to bury the entire regions of the first and second edge regions FR1, FR2. Thereby, the edge capacitance can be reduced more effectively.

[0114] As Figure 1A and Figure 1B shown, the upper insulating layer 13 can include a porous insulator layer 13a and a non-porous insulator layer 13b provided on the porous insulator layer 13a. Therefore, the mechanical strength and shielding property of the upper insulating layer 13 can be ensured by the non-porous insulator layer 13b, and at the same time, the edge capacitance can be reduced by the porous insulator layer 13a.

[0115] In each edge region, the porous insulator layer 13a may be configured to contact the side surface of the gate electrode 11. That is, a first portion p1 of the porous insulator layer 13a contacts the first side surface portion e1 of the gate electrode 11, and a second portion p2 of the porous insulator layer 13a contacts the second side surface portion e2 of the gate electrode 11. Alternatively, the first portion p1 and the second portion p2 of the porous insulator layer 13a may be respectively configured to contact the side surface of the gate insulating layer 9. As shown in the figure, the first portion p1 and the second portion p2 of the porous insulator layer 13a respectively contact the first and second side portions e1, e2 of the gate electrode 11, and also contact the side surface of the gate insulating layer 9.

[0116] As shown in the figure, the first portion p1 of the porous insulator layer 13a may be configured to cover the entire first side surface portion e1 of the gate electrode 11, and the second portion p2 of the porous insulator layer 13a may also be configured to cover the entire second side surface portion e2 of the gate electrode 11. Thereby, the edge capacitance can be reduced more effectively. The first portion p1 of the porous insulator layer 13a may contact the entire first side surface portion e1, and the second portion p2 may also contact the entire second side surface portion e2.

[0117] In addition, the first portion p1 of the porous insulator layer 13a may contact at least a part of the first region 7S (the first low-resistance region 8s), and the second portion p2 of the porous insulator layer 13a may also contact at least a part of the second region 7D (the second low-resistance region 8d). Thereby, the edge capacitance can be reduced more effectively. From this viewpoint, a more preferable porous insulating material is an inorganic material (for example, a silica-based material) having high insulation tolerance.

[0118] The pores in the porous insulator layer 13a may be open pores or closed pores. The porosity of the porous insulator layer 13a (the ratio of the volume of the pores to the total volume of the porous insulator layer 13a) may be, for example, 3% or more and 30% or less. If it is 3% or more, the dielectric constant of the porous insulator layer 13a can be further reduced. If it is 30% or less, the porous insulator layer 13a can have higher mechanical strength. The average pore diameter of the porous insulator layer 13a is not particularly limited, and may be, for example, 2 nm or more and 20 nm or less. In addition, when the main component of the porous insulator layer 13a is silica, the density of the porous insulator layer 13a may be 0.05 g / cm 3 above and 0.3 g / cm 3 below.

[0119] The thickness of the porous insulator layer 13a can be, for example, 100 nm or more, or can also be more than one time the thickness of the gate electrode 11. Thereby, the proportion of the porous insulator layer 13a occupied by each edge region increases, and thus the edge capacitance can be more effectively reduced. On the other hand, the thickness of the porous insulator layer 13a can be, for example, 500 nm or less, or can also be 1 / 3 or less of the overall thickness of the upper insulator layer 13. Thereby, the occurrence of cracks or the like in the porous insulator layer 13a can be suppressed.

[0120] On the other hand, the non-porous insulator layer 13b is, for example, an insulating layer that does not have pores with a size of 100 nm or more or an insulating layer with a porosity of less than 3%. The non-porous insulator layer 13b can be a silicon nitride layer, a silicon oxide layer, or a laminated film thereof formed by, for example, CVD method. The thickness of the non-porous insulator layer 13b is not particularly limited, but can be greater than the thickness of the porous insulator layer 13a. Thereby, the mechanical strength of the upper insulator layer 13 can be more reliably ensured. The thickness of the non-porous insulator layer 13b can be, for example, 500 nm or more and 1000 nm or less, or can also be 1 / 2 or more and 4 / 5 or less of the overall thickness of the upper insulator layer 13.

[0121] In the TFT 101, when viewed from the normal direction of the substrate 1, it is preferable that the gate electrode 11, the source electrode 15s, and the drain electrode 15d are arranged so as not to overlap. Or, it is preferable to suppress the overlapping length between the gate electrode 11 and the source electrode 15s and the drain electrode 15d to a small overlapping length. Thereby, the parasitic capacitance between the gate electrode 11 and the source electrode 15s and the drain electrode 15d can be reduced.

[0122] Although not shown, a light-shielding layer can be further provided on the side of the oxide semiconductor layer 7 (channel region 7C) closer to the substrate 1. However, in a display device such as a micro LED display device that does not require a backlight, the light-shielding layer can also not be provided. Or, another gate electrode (lower gate electrode) (double gate structure) can be provided on the side of the oxide semiconductor layer 7 closer to the substrate 1 with another gate insulating layer interposed therebetween. The lower gate electrode can be connected to the gate electrode 11 or can also be connected to a constant potential. In addition, from the viewpoint of reducing parasitic capacitance, it is preferable not to provide the light-shielding layer or the lower gate electrode.

[0123] The oxide semiconductor contained in the oxide semiconductor layer 7 is not particularly limited. As the oxide semiconductor, for example, binary oxides such as In-Zn-based oxides and In-Ga-based oxides can be used; ternary oxides such as In-Ga-Zn-based oxides and In-Sn-Zn-based oxides; and quaternary metal oxides such as In-Sn-Ga-Zn-based oxides. The oxide semiconductor can be amorphous or crystalline. The crystalline oxide semiconductor can be, for example, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the plane, etc. The materials, compositions, structures, film formation methods, etc. of the amorphous or crystalline oxide semiconductor are described, for example, in Japanese Patent No. 6275294. For reference, the entire disclosure of the specification of Japanese Patent No. 6275294 is incorporated herein by reference.

[0124] <Manufacturing Method of TFT Substrate 101>

[0125] Refer to Figures 2A to 2E An example of the manufacturing method of the TFT 101 will be described.

[0126] ·STEP1: Form the lower insulating layer

[0127] First, as Figure 2A shown, the lower insulating layer 5 is formed on the substrate 1. As the substrate 1, for example, a substrate having an insulating surface such as a glass substrate, a silicon substrate, a heat-resistant plastic substrate (resin substrate), etc. can be used.

[0128] As the lower insulating layer 5, a silicon oxide (SiO2) layer, a silicon nitride (SiN x ) layer, a silicon oxynitride (SiO x N y ; x>y) layer, a silicon nitride oxide (SiN x O y ; x>y) layer, etc. can be appropriately used. The lower insulating layer 5 may also have a laminated structure. Here, as the lower insulating layer 5, for example, a laminated film in which a silicon nitride (SiN x ) layer is the lower layer and a silicon oxide (SiO2) layer is the upper layer is formed by the CVD method. When an oxide such as a silicon oxide film is used as the lower insulating layer 5 (the uppermost layer when the lower insulating layer 5 has a laminated structure), the oxygen vacancies generated in the channel region 7C of the subsequently formed oxide semiconductor layer 7 can be reduced by the oxide film, thereby suppressing the low resistance of the channel region 7C. The thickness of the lower insulating layer 5 is not particularly limited, and can also be, for example, 300 nm or more and 600 nm or less.

[0129] ·STEP2: Form the oxide semiconductor layer

[0130] Next, as shown in Figure 2A , an oxide semiconductor layer 7 is formed on the lower insulating layer 5.

[0131] Here, first, an oxide semiconductor (e.g., an In-Ga-Zn-O-based semiconductor film) is formed on the lower insulating layer 5. The oxide semiconductor film is formed using, for example, a sputtering method. As the sputtering gas (gas), a mixed gas of an inert gas such as argon and an oxidizing gas such as O2, CO2, O3, H2O, N2O can be used. The formation conditions such as the sputtering target used and the mixing ratio of the sputtering gas (the ratio of oxygen to the inert gas) can be appropriately selected according to the composition (or composition ratio) of the formed oxide semiconductor film.

[0132] After that, heat treatment (first heat treatment) of the oxide semiconductor film can be performed. Here, the heat treatment is performed at a temperature of 300°C or higher and 500°C or lower in the atmosphere. The time of the first heat treatment is, for example, 30 minutes or longer and 2 hours or shorter. Thereby, oxygen vacancies in the channel region 7C can be reduced, and desired TFT characteristics can be achieved. In addition, the first heat treatment can also be performed together with the heat treatment of the coating film (second heat treatment) after the coating film that becomes the porous insulating layer 13a is formed.

[0133] Next, the oxide semiconductor film is patterned to obtain the oxide semiconductor layer 7. The oxide semiconductor film can be patterned by, for example, wet etching. The thickness of the oxide semiconductor layer 7 can also be, for example, 100 nm or more and 200 nm or less.

[0134] ·STEP3: Forming a gate insulating layer and a gate electrode

[0135] Next, as shown in Figure 2B , a gate insulating layer 9 and a gate electrode 11 are formed on a part of the oxide semiconductor layer 7.

[0136] First, an insulating layer as a gate insulating layer and a gate conductive film as a gate electrode are sequentially formed so as to cover the oxide semiconductor layer 7. The thickness of the insulating film is not particularly limited and can be 100 nm or more and 500 nm or less, for example, 300 nm or more and 400 nm or less. The thickness of the gate conductive film is not particularly limited and can also be, for example, 100 nm or more and 500 nm or less.

[0137] The insulating film that becomes the gate insulating layer can be formed, for example, by CVD. As the insulating film, for example, a silicon oxide (SiO2) film, a silicon nitride (SiN x ) film, a silicon oxynitride (SiO x N y ; x > y) film, a silicon nitride oxide (SiN x Oy ; a film where x > y), or a laminated film of these films, etc. When an oxide such as a silicon oxide film is used as the insulating film (as the lowermost film when using a laminated film), the oxygen vacancies generated in the channel region 7C of the oxide semiconductor layer 7 can be reduced, thereby suppressing the low-resistance of the channel region 7C.

[0138] The gate insulating film can be formed, for example, by sputtering. As the material for the gate conductive film, for example, pure metals including molybdenum (Mo), tungsten (W), copper (Cu), chromium (Cr), tantalum (Ta), aluminum (Al), and titanium (Ti), etc.; materials in which these metals contain nitrogen, oxygen, or other metals; or transparent conductive materials such as indium tin oxide (ITO) can be used.

[0139] Next, a first resist mask (not shown) is formed on a part of the gate conductive film. After that, the gate conductive film is patterned using the first resist mask to form the gate electrode 11. The patterning of the gate conductive film can be performed by wet etching or dry etching.

[0140] Next, the insulating film is patterned using the first resist mask. Alternatively, after removing the first resist mask, the patterned gate electrode 11 can be used as a mask to pattern the insulating film. The patterning of the insulating film can be performed, for example, by dry etching. Thus, the gate insulating layer 9 of the TFT101 is obtained, and the surfaces of the portions of the oxide semiconductor layer 7 that become the first region 7S and the second region 7D are exposed.

[0141] In this process, the insulating film and the gate conductive film are patterned using the same mask (the first resist mask). Therefore, the side surfaces of the gate insulating layer 9 and the gate electrode 11 can be aligned in the thickness direction. That is, when viewed from the normal direction of the substrate 1, the peripheries of the gate insulating layer 9 and the gate electrode 11 can be aligned with each other.

[0142] In addition, the surface layer portion of the oxide semiconductor layer 7 (for example, the surface layer portion of the upper oxide semiconductor layer 72) may sometimes be etched together with the insulating film by the above dry etching.

[0143] ·STEP4: Low-resistance treatment

[0144] Next, as Figure 2CAs shown, a low-resistance treatment is performed to make the resistivity of the portion of the oxide semiconductor layer 7 that does not overlap with the gate electrode 11 when viewed from the normal direction of the substrate 1 lower than that of the portion that overlaps with the gate electrode 11, and low-resistance regions 8s and 8d are formed. Here, the exposed surface of the oxide semiconductor layer 7 (the surfaces of the first region 7S and the second region 7D) is subjected to a low-resistance treatment using the gate electrode 11 as a mask. As the low-resistance treatment, plasma treatment can be performed. Examples of the plasma treatment include argon plasma treatment, ammonia plasma treatment, or hydrogen plasma treatment. Alternatively, nitrogen, phosphorus, etc. can be added to the oxide semiconductor layer 7 by an ion implantation method or the like using the gate electrode 11 as a mask, thereby forming low-resistance regions 8s and 8d on the surfaces of the first region 7S and the second region 7D.

[0145] Alternatively, as the upper insulating layer 13, by using an insulating film for reducing an oxide semiconductor of a nitride film (e.g., a silicon nitride film), etc., the resistance of the region of the oxide semiconductor layer 7 in contact with the nitride film (the surfaces of the first region 7S and the second region 7D) can also be made lower than the resistance of the region of the oxide semiconductor layer 7 in contact with the oxide film (the surface of the channel region 7C).

[0146] ·STEP5: Form the upper insulating layer

[0147] Next, as Figure 2D shown, an upper insulating layer 13 covering the gate electrode 11, the gate insulating layer 9, and the oxide semiconductor layer 7 is formed. In this example, as the upper insulating layer 13, a laminated film including a porous insulator layer 13a and a non-porous insulator layer 13b is formed. The overall thickness of the upper insulating layer 13 is not particularly limited, and it can be, for example, 1000 nm or more and 1500 nm or less.

[0148] Specifically, first, an SOG solution is applied so as to cover the gate electrode 11, the gate insulating layer 9, and the oxide semiconductor layer 7. Here, as the SOG solution, a coating liquid HSG-225 (Hitachi Chemical Co., Ltd.) made of silica-based (siloxane) for forming an insulating film is used. Next, the obtained coating film (SOG film) is dried and heat-treated (second heat treatment). The second heat treatment can be performed, for example, at a temperature within 400 °C to 450 °C for 0.5 to 5 hours. Thereby, a porous insulator layer (e.g., relative dielectric constant: 2.3, elastic modulus: 12 GPa, hardness: 1.3 GPa, porosity 20%) 13a is obtained. The thickness of the porous insulator layer 13a can also be, for example, 500 nm. In addition, the second heat treatment can also be used as the first heat treatment of the oxide semiconductor layer 7.

[0149] Here, the porous insulator layer 13a is formed to be in contact with the exposed surface of the oxide semiconductor layer 7 (the low-resistance regions 8s and 8d of the first region 7S and the second region 7D). The porous insulator layer 13a may also be in contact with the surfaces of the gate electrode 11 and the gate insulating layer 9.

[0150] Next, on the porous insulator layer 13a, an inorganic insulating layer such as a silicon oxide film, a silicon nitride film, a silicon oxynitride layer, or a silicon oxynitride layer may be formed as a non-porous insulator layer 13b, either as a single layer or as a stack. The non-porous insulator layer 13b can be formed, for example, by CVD. The thickness of the non-porous insulator layer 13b can also be, for example, 500 nm.

[0151] After that, as Figure 2E shown, a first opening CHs reaching the surface of the first region 7S (the first low-resistance region 8s) and a second opening CHd reaching the surface of the second region 7D (the second low-resistance region 8d) are formed in the upper insulating layer 13 by, for example, dry etching.

[0152] ·STEP6: Forming the source electrode and the drain electrode

[0153] After that, a source conductive film is formed on the upper insulating layer 13 and within the first opening CHs and the second opening CHd, and the source conductive film is patterned. Thus, the source electrode 15s and the drain electrode 15d are formed from the source conductive film. The TFT101 is manufactured in such a manner. Figure 1A as shown.

[0154] As the source conductive film, the same material as the above-described gate conductive film can be used. The thickness of the source conductive film is not particularly limited and can also be, for example, 400 nm or more and 800 nm or less. The patterning of the source conductive film can be performed by dry etching or wet etching.

[0155] <Variant Example 1>

[0156] Figure 3A is a cross-sectional view showing another TFT102 of the present embodiment.

[0157] In the TFT102, the side surface of the gate insulating layer 9 is located more inward than the side surface of the gate electrode 11, and the porous insulator layer 13a is also disposed between the peripheral portion of the gate electrode 11 and the channel region 7C of the oxide semiconductor layer 7. Other structures may be the same as those of the TFT101.

[0158] The relative dielectric constant of the porous insulator layer 13a is less than the relative dielectric constant of the gate insulating layer 9. The porous insulator layer 13a can be, for example, a porous silicon oxide-based insulating film (relative dielectric constant: 2.3), or can be the above-described other porous insulating films.

[0159] The gate insulating layer 9 includes, for example, silicon oxide (relative dielectric constant: 3.9 for example). The gate insulating layer 9 may be a single-layer silicon oxide or may have a stacked structure containing silicon oxide. For example, the gate insulating layer 9 may be a stacked film including a silicon oxide layer configured to contact the oxide semiconductor layer 7 and a silicon nitride layer (relative dielectric constant: 7.5 for example) disposed on the silicon oxide layer.

[0160] In the TFT102, since the porous insulator layer 13a is disposed not only in the first and second edge regions FR1, FR2 (see Figure 6 ), but also below the peripheral portion of the gate electrode 11, not only the edge capacitance Cfr but also the overlap capacitance Cov can be reduced. Therefore, the parasitic capacitance Ctotal can be reduced more effectively.

[0161] The TFT102 can be manufactured by the same method as the TFT101. However, the difference between this method and the manufacturing method of the TFT101 is that in this method, the side surface of the gate insulating layer 9 is etched so that the side surface of the gate insulating layer 9 is located more inside the side surface of the gate electrode 11.

[0162] For example, as Figure 4A shown, in STEP3, the first resist mask or the gate electrode 11 is used as a mask, and the insulating film that becomes the gate insulating layer 9 is patterned by anisotropic etching. Next, as Figure 4B shown, etching (side etching) is started from the side surface of the patterned insulating film (referred to as "gate insulating layer precursor") 9'. When the gate insulating layer precursor 9' is a SiO2 film, side etching is performed by, for example, hydrofluoric acid treatment to obtain the gate insulating layer 9.

[0163] Instead of the above method, the insulating film may be isotropically etched using the first resist mask or the gate electrode 11 as a mask to form a gate insulating layer 9 having the Figure 4B shown shape.

[0164] Next, as Figure 4C shown, the low-resistance treatment of STEP4 is performed. Subsequently, although not shown, in STEP5, the upper insulating layer 13 is formed so as to be buried between the gate electrode 11 and the oxide semiconductor layer 7. The upper insulating layer 13 may also contact the side surface of the gate insulating layer 9. Thereafter, the TFT102 is manufactured by forming the source electrode 15s and the drain electrode 15d.

[0165] Figure 3B FIG. is a cross-sectional view showing another TFT103 of the present embodiment.

[0166] In the TFT103, the side surface of the gate insulating layer 9 is located more inward than the side surface of the gate electrode 11. Further, a gap 21 is provided between the peripheral portion of the gate electrode 11 and the channel region 7C of the oxide semiconductor layer 7 and between the side surface of the gate insulating layer 9 and the upper insulating layer 13. The relative dielectric constant of the gap 21 is about 1 and is smaller than the relative dielectric constants of the non-porous insulator layer 13b and the gate insulating layer 9.

[0167] In the TFT103, in the first and second edge regions FR1, FR2 (see Figure 6 ), a porous insulator layer 13a is disposed, and a gap 21 is disposed below the peripheral portion of the gate electrode 11. Therefore, similar to the TFT102, not only can the fringe capacitance Cfr be reduced, but also the overlap capacitance Cov can be reduced, so that the parasitic capacitance Ctotal can be reduced more effectively.

[0168] The TFT103 can be manufactured in the same manner as the TFT102 by laterally etching the gate insulating layer 9. However, in STEP5, the upper insulating layer 13 is formed in such a manner that a gap (excluding the holes inside the porous insulator) 21 is generated in at least a part between the side surface of the gate insulating layer 9 and the upper insulating layer 13. Thereafter, the TFT103 is manufactured by forming the source electrode 15s and the drain electrode 15d.

[0169] <Deformation Example 2>

[0170] The porous insulator layer 13a may be disposed in at least a part of each of the first and second edge regions FR1, FR2 (see Figure 6 ), and may not be the lowermost layer of the upper insulating layer 13.

[0171] Figures 5A to 5C Cross-sectional views of other TFTs 104, 105, and 106 of the present embodiment are respectively illustrated.

[0172] For example, as Figure 5A shown, as the lowermost layer of the upper insulating layer 13, a reducing insulating film (for example, SiN x film) 13c capable of reducing the oxide semiconductor in the oxide semiconductor layer 7 is formed, and the porous insulator layer 13a and the non-porous insulator layer 13b are sequentially formed thereon. By disposing the insulating film 13c, the resistivity of the low-resistance regions 8s, 8d can be suppressed to be lower. However, from the viewpoint of reducing the parasitic capacitance of the TFT104, the portion of the insulating film 13c located in the first and second edge regions FR1, FR2 (see Figure 6 ) can be removed.

[0173] In addition, as Figure 5BAs shown, the porous insulator layer 13a can be patterned. The porous insulator layer 13a can be, for example, an island-shaped insulator layer. When viewed from the normal direction of the substrate 1, the upper insulating layer 13 has a portion (referred to as "first insulating portion") r1 including first and second edge regions FR1 and FR2, and a portion (referred to as "second insulating portion") r2 located outside the first insulating portion r1. The first insulating portion r1 has a stacked structure including the porous insulator layer 13a and a non-porous insulator layer 13b provided on the porous insulator layer 13a. The second insulating portion r2 includes the non-porous insulator layer 13b but does not include the porous insulator layer 13a. As shown in the figure, the first opening CHs and the second opening CHd can be formed in the second insulating portion r2 of the upper insulating layer 13. According to this configuration, since the porous insulator is not exposed on the side walls of the first opening CHs and the second opening CHd, there is an advantage that the metal of the electrode can be suppressed from diffusing into the upper insulating layer 13.

[0174] In addition, when a reducing insulating film (for example, SiN x film) capable of reducing the oxide semiconductor in the oxide semiconductor layer 7 is used as the non-porous insulator layer 13b (when the non-porous insulator layer 13b has a stacked structure, as the lowermost layer), the resistivity of the portion in the low-resistance regions 8s and 8d that contacts the second insulating portion r2 can be suppressed to be lower. For example, the non-porous insulator layer 13b can be a stacked film of a reducing insulating film (for example, SiN x film) 13b1 that contacts the low-resistance regions 8s and 8d and an oxidizing insulating film (for example, SiO2 film) 13b2.

[0175] Alternatively, as Figure 5C shown, the upper insulating layer 13 can also be a single-layer structure having the porous insulator layer 13a.

[0176] The TFTs 104 to 106 can be manufactured by the same method as the TFT 101 described with reference to Figures 2A to 2E .

[0177] In addition, in the TFTs 104 to 106, the gate insulating layer 9 is also etched laterally, and a porous insulator layer 13a or a void 21 (refer to Figure 3A , Figure 3B ) can be disposed below the peripheral portion of the gate electrode 11.

[0178] <Display device>

[0179] The thin film transistors of the present embodiment can be applied to circuit boards such as active matrix substrates, various display devices such as liquid crystal display devices, organic EL display devices, and micro LED display devices, image sensors, and electronic devices.

[0180] Hereinafter, the active matrix substrate and the display device using the thin film transistor of the present embodiment will be described.

[0181] The active matrix substrate has a display area including a plurality of pixels and pixel circuits arranged corresponding to each of the plurality of pixels. Each pixel circuit includes at least one thin film transistor (pixel circuit TFT) as a circuit element. In addition, there is a case where peripheral circuits such as drive circuits are monolithically (integrally) provided in an area (peripheral area) other than the display area in the active matrix substrate. The peripheral circuit includes at least one thin film transistor (peripheral circuit TFT) as a circuit element. The thin film transistor of the present embodiment can be used as the pixel circuit TFT and / or the peripheral circuit TFT. Such an active matrix substrate is used not only for voltage-driven display devices such as liquid crystal display devices but also for current-driven display devices.

[0182] The thin film transistor of the present embodiment can be particularly applied to a current-driven display device. In a current-driven display device such as an organic EL display device or a micro LED display device, a plurality of current-driven light-emitting elements (organic EL elements, LED elements, etc.) are arranged corresponding to each pixel. Each pixel circuit (also referred to as a pixel drive circuit.) drives the corresponding light-emitting element. In the thin film transistor according to the present embodiment, since the parasitic resistance can be reduced, the occurrence of image ghosting failures can be suppressed, and higher-quality display can be achieved. The configuration of the pixel drive circuit is disclosed, for example, in International Publication No. 2016 / 035413, International Publication No. 2004 / 107303, etc. For reference, the entire disclosure of the above documents is incorporated herein by reference.

Claims

1. A thin film transistor, characterized in that, Comprising: A substrate; An oxide semiconductor layer, which is supported by the substrate and includes a first region, a second region, and a channel region located between the first region and the second region; A gate electrode, which is disposed over the channel region of the oxide semiconductor layer with a gate insulating layer interposed therebetween; An upper insulating layer, which covers the oxide semiconductor layer, the gate insulating layer, and the gate electrode; A source electrode, which is disposed on the upper insulating layer and is electrically connected to the first region of the oxide semiconductor layer; And A drain electrode, which is disposed on the upper insulating layer and is electrically connected to the second region of the oxide semiconductor layer, When observed from the normal direction of the substrate, the gate electrode overlaps with the channel region of the oxide semiconductor layer and does not overlap with the first region and the second region, When observed from the normal direction of the substrate, the side surface of the gate electrode has a first side surface portion and a second side surface portion. The first side surface portion is located on the first region side and overlaps with the oxide semiconductor layer, and the second side surface portion is located on the second region side and overlaps with the oxide semiconductor layer, The upper insulating layer includes: A first edge region, which is located near the first side surface portion of the gate electrode when observed from the normal direction of the substrate, and the height of the first edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode; And A second edge region, which is located near the second side surface portion of the gate electrode when observed from the normal direction of the substrate, and the height of the second edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode, The first region of the oxide semiconductor layer has a first low-resistance region on the surface with a resistivity less than that of the channel region, and the second region of the oxide semiconductor layer has a second low-resistance region on the surface with a resistivity less than that of the channel region, The upper insulating layer has a reducing insulating film as the lowermost layer, a porous insulator layer, and a non-porous insulator layer disposed on the porous insulator layer. The insulating film is used to reduce the resistivity of the first low-resistance region and the second low-resistance region. The porous insulator layer includes a first portion disposed in the first edge region and a second portion disposed in the second edge region, The portions of the insulating film located in the first edge region and the second edge region are removed. The first portion of the porous insulator layer is in contact with at least a part of the first region of the oxide semiconductor layer, and the second portion of the porous insulator layer is in contact with at least a part of the second region of the oxide semiconductor layer.

2. The thin film transistor according to claim 1, wherein The gate insulating layer includes a silicon oxide layer.

3. The thin film transistor according to claim 1, wherein The relative dielectric constant of the porous insulator layer at a frequency of 1 MHz is 3.0 or less.

4. The thin film transistor according to claim 1, wherein the first part of the porous insulator layer contacts the first side surface of the gate electrode, and the second part of the porous insulator layer contacts the second side surface of the gate electrode.

5. The thin film transistor according to claim 1, wherein when viewed from the normal direction of the substrate, the side surface of the gate insulating layer is aligned with the side surface of the gate electrode.

6. The thin film transistor according to claim 5, wherein the porous insulator layer contacts the side surface of the gate insulating layer.

7. The thin film transistor according to claim 1, wherein when viewed from the normal direction of the substrate, the side surface of the gate insulating layer is located inside the side surface of the gate electrode.

8. The thin film transistor according to claim 7, wherein at least a part of the porous insulator layer is arranged to contact the side surface of the gate insulating layer between the gate electrode and the channel region.

9. The thin film transistor according to claim 7, wherein a gap is formed between the gate electrode and the channel region and between the side surface of the gate insulating layer and the upper insulating layer.

10. A thin film transistor, characterized in that, Comprising: a substrate; an oxide semiconductor layer supported by the substrate and including a first region, a second region, and a channel region located between the first region and the second region; a gate electrode disposed over the channel region of the oxide semiconductor layer with a gate insulating layer therebetween; an upper insulating layer covering the oxide semiconductor layer, the gate insulating layer, and the gate electrode; a source electrode disposed on the upper insulating layer and electrically connected to the first region of the oxide semiconductor layer; and a drain electrode disposed on the upper insulating layer and electrically connected to the second region of the oxide semiconductor layer, when viewed from the normal direction of the substrate, the gate electrode overlaps the channel region of the oxide semiconductor layer and does not overlap the first region and the second region, when viewed from the normal direction of the substrate, the side surface of the gate electrode has a first side surface portion and a second side surface portion, the first side surface portion is located on the first region side and overlaps the oxide semiconductor layer, and the second side surface portion is located on the second region side and overlaps the oxide semiconductor layer, the upper insulating layer includes: a first edge region which, when viewed from the normal direction of the substrate, is located near the first side surface portion of the gate electrode, and the height of the first edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode; and a second edge region which, when viewed from the normal direction of the substrate, is located near the second side surface portion of the gate electrode, and the height of the second edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode, The upper insulating layer has a porous insulator layer and a non-porous insulator layer disposed on the porous insulator layer. The porous insulator layer includes a first portion disposed in the first edge region and a second portion disposed in the second edge region. The first portion of the porous insulator layer is in contact with at least a part of the first region of the oxide semiconductor layer, and the second portion of the porous insulator layer is in contact with at least a part of the second region of the oxide semiconductor layer. When viewed from the normal direction of the substrate, the upper insulating layer has: a first insulating portion including the first edge region and the second edge region; and a second insulating portion located outside the first insulating portion. The first insulating portion includes the porous insulator layer and the non-porous insulator layer, and the second insulating portion includes the non-porous insulator layer but does not include the porous insulator layer. A first opening for connecting the source electrode to the first region is provided in the second insulating portion; and a second opening for connecting the drain electrode to the second region.

11. The thin film transistor according to claim 1 or 10, wherein the thickness of the porous insulator layer is greater than or equal to the thickness of the gate electrode.

12. The thin film transistor according to claim 1 or 10, wherein the porous insulator layer is formed of an organic SOG film or an inorganic SOG film.

13. The thin film transistor according to claim 10, wherein the first region of the oxide semiconductor layer has a first low-resistance region on the surface with a resistivity less than that of the channel region, and the second region of the oxide semiconductor layer has a second low-resistance region on the surface with a resistivity less than that of the channel region. The first portion of the porous insulator layer is in contact with at least a part of the first low-resistance region, and the second portion of the porous insulator layer is in contact with at least a part of the second low-resistance region.

14. A display device, characterized in that, Comprising: the thin film transistor according to claim 1 or 10; a display region having a plurality of pixels; and a pixel circuit configured corresponding to each of the plurality of pixels, wherein the pixel circuit includes the thin film transistor.

15. The display device according to claim 14, wherein the display device further has a current-driven light-emitting element configured corresponding to each of the plurality of pixels, and the pixel circuit drives the light-emitting element.

16. A method for manufacturing a thin film transistor, which is a method for manufacturing a thin film transistor supported by a substrate. The manufacturing method includes: a step (A) of forming an oxide semiconductor layer on the substrate; a step (B) of sequentially forming a gate insulating layer and a gate electrode on a part of the oxide semiconductor layer. Step (C) of forming an upper insulating layer including a first insulating film having a reducing property as the lowermost layer, a porous insulator layer, and a non-porous insulator layer disposed on the porous insulator layer so as to cover the oxide semiconductor layer, the gate insulating layer, and the gate electrode; and Step (D) of forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer on the upper insulating layer, wherein the oxide semiconductor layer is supported by the substrate and includes a first region, a second region, and a channel region located between the first region and the second region; the gate electrode is disposed on the channel region of the oxide semiconductor layer with the gate insulating layer therebetween; the drain electrode is disposed on the upper insulating layer and is electrically connected to the second region of the oxide semiconductor layer, the first region of the oxide semiconductor layer has a first low-resistance region on the surface having a resistivity lower than that of the channel region, and the second region of the oxide semiconductor layer has a second low-resistance region on the surface having a resistivity lower than that of the channel region, the first insulating film is for reducing the resistivity of the first low-resistance region and the second low-resistance region, the upper insulating layer includes: a first edge region, which is located near the first side surface of the gate electrode when viewed from the normal direction of the substrate, and the height of the first edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode; and a second edge region, which is located near the second side surface of the gate electrode when viewed from the normal direction of the substrate, and the height of the second edge region from the upper surface of the oxide semiconductor layer is less than the height of the upper surface of the gate electrode, the porous insulator layer includes a first portion disposed in the first edge region and a second portion disposed in the second edge region, the portions of the first insulating film located in the first edge region and the second edge region are removed, and the first portion and the second portion of the porous insulator layer are respectively in contact with the portions of the oxide semiconductor layer not covered by the gate insulating layer, The step (B) includes: Step (B1) of sequentially forming a second insulating film and a gate conductive film on the oxide semiconductor layer; Step (B2) of patterning the gate conductive film using a first mask and forming the gate electrode; and Step (B3) of patterning the second insulating film after the step (B2) by using the first mask or using the gate electrode as a mask to obtain the gate insulating layer, and in this step, when viewed from the normal direction of the substrate, the side surface of the gate insulating layer is located more inward than the side surface of the gate electrode.

17. The method for manufacturing a thin film transistor according to claim 16, wherein In the step (B3), by using the first mask, or by using the gate electrode as a mask, isotropic etching of the second insulating film is performed to obtain the gate insulating layer.

18. The method for manufacturing a thin film transistor according to claim 16, wherein: The step (B3) includes: A step (B4) of obtaining a gate insulating layer precursor by anisotropically etching the second insulating film by using the first mask, or by using the gate electrode as a mask; And A step (B5) of obtaining the gate insulating layer by etching the side surfaces of the gate insulating layer precursor.

19. The method for manufacturing a thin film transistor according to claim 16, wherein: The step (C) includes a step of forming the porous insulator layer in contact with the side surfaces of the gate insulating layer.

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