Display device

Abstract

A display apparatus according to an aspect of the present invention includes a pixel coupled to a first scan line, a second scan line, an emission control line, and a data line; a first scan driver to supply a scan signal to the first scan line at a first frequency to drive the display apparatus at a first driving frequency and to supply the scan signal to the first scan line at a second frequency to drive the display apparatus at a second driving frequency lower than the first driving frequency; a second scan driver to supply a scan signal to the second scan line at the first frequency to drive the display apparatus at the first driving frequency and to supply the scan signal to the second scan line at the second frequency to drive the display apparatus at the second driving frequency; an emission driver to supply an emission control signal to the emission control line at the first frequency; and a data driver to supply a data signal to the data line in response to the scan signal supplied to the first scan line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0069637, filed on June 12, 2019, the entire contents of which are incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to an electronic device, and more specifically to a display device and a method for driving the display device. Background Technology

[0004] Display devices use control signals applied from external devices to display images on the display panel.

[0005] A display device may include multiple pixels. Each pixel may include multiple transistors, a light-emitting element electrically coupled to the transistors, and a capacitor. The transistors may be turned on in response to various signals provided via lines, thereby generating a drive current. The light-emitting element may emit light in response to the drive current.

[0006] To improve the driving efficiency of display devices, it is necessary to reduce their power consumption. For example, power consumption can be reduced by lowering the driving frequency when displaying static images.

[0007] The information disclosed above in this background section is only for understanding the background technology of the inventive concept, and therefore may include information that does not constitute prior art. Summary of the Invention

[0008] The display device constructed according to an exemplary embodiment of the present invention can reduce power consumption and improve image quality in low-frequency driving mode by partially utilizing various pixel structures included in the display device.

[0009] For example, the switching of the scan signal in low-frequency drive mode can be reduced, and the conduction bias can be applied periodically to the first transistor. Therefore, power consumption can be reduced, and image quality can be improved. Furthermore, the third (and fourth) transistors included in multiple pixel lines can share the scan signal, thereby reducing the number of stages included in the second (and third) scan drivers. This further reduces power consumption. Additionally, the initialization power supplies of the fourth and seventh transistors coupled to the pixels can be separated from each other to further improve image quality.

[0010] Additional features of the inventive concept will be set forth in the following description and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0011] According to an aspect of the present application, a display apparatus includes: pixels coupled to first scan lines, second scan lines, emission control lines, and data lines; a first scan driver that supplies a scan signal to each of the first scan lines at a first frequency to drive the display apparatus at a first driving frequency, and supplies the scan signal to each of the first scan lines at a second frequency to drive the display apparatus at a second driving frequency lower than the first driving frequency; a second scan driver that supplies a scan signal to each of the second scan lines at the first frequency to drive the display apparatus at the first driving frequency, and supplies the scan signal to each of the second scan lines at the second frequency to drive the display apparatus at the second driving frequency; an emission driver that supplies an emission control signal to each of the emission control lines at the first frequency; and a data driver that supplies a data signal to each of the data lines in response to the scan signal supplied to each of the first scan lines.

[0012] The first frequency can be substantially equal to the first driving frequency.

[0013] The second frequency can be substantially equal to the second driving frequency.

[0014] When the display apparatus can be driven at the second driving frequency, the first scan driver and the second scan driver can be configured to supply the scan signal during a first period, and when the display apparatus can be driven at the second driving frequency, the first scan driver and the second scan driver can be configured to not supply the scan signal during a second period.

[0015] The second period can be set to a period longer than the first period.

[0016] The timing controller can supply a first gate start pulse to the first scan driver, can supply a second gate start pulse to the second scan driver, and can supply an emission start pulse to the emission driver.

[0017] When the display apparatus can be driven at the first driving frequency, the timing controller can be configured to output the first gate start pulse and the second gate start pulse at the first frequency, and when the display apparatus can be driven at the second driving frequency, the timing controller can be configured to output the first gate start pulse and the second gate start pulse at the second frequency.

[0018] The timing controller can be configured to output the emission start pulse at the first frequency regardless of the driving frequency.

[0019] The pixel arranged on the i-th horizontal line can include a light emitting element including a first electrode and a second electrode coupled to a second power supply, a first transistor including a first electrode coupled to a first node to control a driving current based on a voltage of a second node, the first node being electrically connected to a first power supply, a second transistor coupled between a corresponding data line and the first node and configured to be activated by a scan signal supplied to the i-th first scan line, a third transistor coupled between the second node and a third node coupled to the second electrode of the first transistor and configured to be activated by a scan signal supplied to the i-th second scan line, a fourth transistor coupled between the second node and a first initialization power supply and configured to be activated by a scan signal supplied to the i-1-th second scan line, a fifth transistor coupled between the first power supply and the first node and configured to be deactivated by an emission control signal supplied to the i-th emission control line, a sixth transistor coupled between the third node and the first electrode of the light emitting element and configured to be deactivated by the emission control signal, and a storage capacitor coupled between the first power supply and the second node, and wherein i is a natural number.

[0020] The pixel arranged on the i-th horizontal line can further include a seventh transistor coupled between the second initialization power supply and the first electrode of the light emitting element, the seventh transistor being configured to be activated by the emission control signal.

[0021] The voltage of the first initialization power supply can be different from the voltage of the second initialization power supply.

[0022] The voltage of the first initialization power supply can be greater than the voltage of the second initialization power supply.

[0023] Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor can include a P-type transistor, and each of the third transistor, the fourth transistor, and the seventh transistor can include an N-type transistor.

[0024] The power supply line arranged under the light emitting element can transmit a voltage of the second power supply to the light emitting element.

[0025] The pixel arranged on the i-th horizontal line can further include a seventh transistor coupled between the power supply line and the first electrode of the light emitting element, the seventh transistor being configured to be activated by the emission control signal.

[0026] The pixel arranged on the i-th horizontal line can have a light emitting element including a first electrode and a second electrode coupled to a second power supply, a first transistor including a first electrode coupled to a first node to control a driving current based on a voltage of a second node, the first node being electrically connected to a first power supply, a second transistor coupled between a corresponding data line and the first node and configured to be activated by a scan signal supplied to the i-th first scan line, a third transistor coupled between the second node and a third node coupled to the second electrode of the first transistor and configured to be activated by a scan signal supplied to the i-th second scan line, a fourth transistor coupled between the second node and a first initialization power supply and configured to be activated by a scan signal supplied to the i-q-th second scan line, q being a natural number, and a fifth transistor coupled between the first power supply and the first node and configured to be deactivated by an emission control signal supplied to the i-th emission control line, and wherein i is a natural number.

[0027] The first scan driver can include n stages coupled in dependence on each other, n being a natural number greater than 1, and the second scan driver can include k stages coupled in dependence on each other, k being a natural number smaller than n.

[0028] A pulse width of the scan signal to be supplied to the second scan line can be greater than a pulse width of the scan signal to be supplied to the first scan line.

[0029] Each of the stages included in the second scan driver can be configured to supply the scan signal to at least two of the second scan lines simultaneously.

[0030] A portion of the scan signal to be supplied to the i-th second scan line can overlap with the scan signal to be supplied to the i-th first scan line and the scan signal to be supplied to the i+1-th first scan line.

[0031] The scan signal to be supplied to the third transistor of the pixel arranged on the i-th horizontal line can be delayed by four or more horizontal periods compared to the scan signal to be supplied to the fourth transistor of the pixel arranged on the i-th horizontal line.

[0032] The pixel arranged on the i-th horizontal line among the pixels can include a light emitting element including a first electrode and a second electrode coupled to a second power source; a first transistor including a first electrode coupled to a first node to control a driving current based on a voltage of a second node, the first node electrically connected to a first power source; a second transistor coupled between a corresponding data line and the first node and configured to be activated by a first scan signal supplied to the i-th first scan line; a third transistor coupled between the second node and a third node coupled to the second electrode of the first transistor and configured to be activated by a second scan signal supplied to the i-th second scan line; a fourth transistor coupled between the second node and a first initialization power source and configured to be activated by a third scan signal supplied to the i-th third scan line; and a fifth transistor coupled between the first power source and the first node and configured to be deactivated by an emission control signal supplied to the i-th emission control line, wherein the first scan driver can be configured to supply the first scan signal to the first scan line, and the second scan driver can be configured to supply the second scan signal to the second scan line, and wherein i is a natural number.

[0033] The third scan driver can supply the third scan signal to the third scan line connected to the pixel at a first frequency when the display apparatus can be driven at a first driving frequency, and supply the third scan signal to the third scan line at a second frequency when the display apparatus can be driven at a second driving frequency.

[0034] The first scan driver can include n stages coupled in dependence on each other, n being a natural number greater than 1, and each of the second scan driver and the third scan driver can include k stages coupled in dependence on each other, k being a natural number smaller than n.

[0035] The third scan driver can be configured to supply the third scan signal to the i-th third scan line, and after a delay of q horizontal periods, the second scan driver can be configured to supply the second scan signal to the i-th second scan line, and a pulse width of the second scan signal can be substantially equal to a pulse width of the third scan signal, and wherein q is a natural number of 4 or more.

[0036] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the application as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description serve to explain the principles of the application.

[0038] Figure 1 is a block diagram illustrating an exemplary embodiment of a display device constructed in accordance with the principles of the application.

[0039] Figure 2 is a circuit diagram illustrating an exemplary embodiment of a representative pixel included in the display device of Figure 1

[0040] Figure 3A is an exemplary timing diagram illustrating an example of the operation of the pixel of Figure 2

[0041] Figure 3B is an exemplary timing diagram illustrating an example of the operation of the pixel of Figure 2

[0042] Figure 4 is an exemplary timing diagram illustrating an example of a method of driving the display device of Figure 1

[0043] Figure 5 is an exemplary timing diagram illustrating an example of a method of driving the display device of Figure 1

[0044] Figure 6 is an exemplary timing diagram illustrating an example of a gate start pulse to be supplied to a scan driver included in the display device of Figure 1

[0045] Figure 7 is a circuit diagram illustrating an exemplary embodiment of a representative pixel included in the display device of Figure 1

[0046] Figure 8A is an exemplary timing diagram illustrating an example of the operation of the pixel of Figure 7

[0047] Figure 8B is an exemplary timing diagram illustrating an example of the operation of the pixel of Figure 7

[0048] Figure 9 is a block diagram illustrating an exemplary embodiment of another display device constructed in accordance with the principles of the application.

[0049] Figure 10A is a circuit diagram illustrating an exemplary embodiment of a representative pixel included in the display device of Figure 9 ​​​​​​​​​circuit diagram of an exemplary embodiment of a representative pixel in a display device of

[0050] Figure 10B is a block diagram illustrating exemplary embodiments of a second scan driver and a third scan driver included in a display device of Figure 9

[0051] Figure 11 is a block diagram illustrating exemplary embodiments of a second scan driver and a third scan driver included in a display device of Figure 1

[0052] Figure 12 is a circuit diagram of an exemplary embodiment of a pixel coupled to a scan driver of Figure 11

[0053] Figure 13A is an exemplary timing diagram illustrating an example of operation of a pixel of Figure 12

[0054] Figure 13B is an exemplary timing diagram illustrating an example of operation of a pixel of Figure 12

[0055] Figure 14A is an exemplary timing diagram illustrating an example of a method of driving a display device including pixels of Figure 12

[0056] Figure 14B is an exemplary timing diagram illustrating an example of a method of driving a display device including pixels of Figure 12

[0057] Figure 15 is a circuit diagram of an exemplary embodiment of a pixel coupled to a scan driver of Figure 11

[0058] Figure 16 is an exemplary timing diagram illustrating an example of operation of a pixel of Figure 15

[0059] Figure 17 is a block diagram illustrating an exemplary embodiment of another display device constructed in accordance with the principles of the present invention.

[0060] Figure 18 is a block diagram illustrating exemplary embodiments of a second scan driver and a third scan driver included in a display device of Figure 17

[0061] Figure 19 is a block diagram illustrating exemplary embodiments of a second scan driver and a third scan driver included in a display device of Figure 17 ​​​​​​​​​​An exemplary timing diagram of an example of a gate start pulse of a scan driver in a display device.

[0062] Figure 20 A circuit diagram illustrating an exemplary embodiment of a representative pixel included in a display device constructed in accordance with the principles of the present application. DETAILED DESCRIPTION

[0063] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present application. As used herein, "embodiment" and "implementation" are interchangeable terms as non-limiting examples of an apparatus or method that utilizes one or more of the inventive concepts disclosed herein. It will be apparent, however, that various exemplary embodiments can be practiced without these specific details or with one or more equivalent settings. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Further, various exemplary embodiments can be different from one another but not necessarily mutually exclusive. For example, a particular feature of an exemplary embodiment can be used in another exemplary embodiment without departing from the inventive concepts.

[0064] Unless otherwise specified, the illustrated exemplary embodiments are to be understood as providing examples of the various ways in which the inventive concepts can be practiced. Accordingly, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects of each embodiment (hereinafter, individually or collectively referred to as "elements") can be combined, separated, interchanged with one another and / or re-arranged without departing from the inventive concepts.

[0065] The use of cross-hatching and / or shading in the drawings is generally used to clarify boundaries between regions of an element. As such, the presence or absence of cross-hatching or shading does not in and of itself indicate or imply any preference or requirement for particular material, material properties, dimensions, proportions, commonality of elements between illustrations, and / or any other characteristic, property, attribute, or the like of the elements being presented. Further, in the drawings, the size and relative sizes of elements can be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be practiced differently, a particular sequence of processes can be performed in a different order than described. For example, two processes described consecutively can be performed at the same time or can be performed in the reverse order as described. Moreover, identical reference numerals have been used to designate identical elements.

[0066] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. In this regard, the term "connected" can refer to physical or electrical and / or fluid connection, with or without intervening elements. Further, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system, such as the x-axis, the y-axis, and the z-axis, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any one of X, Y, Z, or an arbitrary combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0067] Although the terms "first", "second", etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0068] Spatially relative terms such as "beneath", "below", "lower", "bottom", "on", "above", "upper", "over", "higher", "side" (as in "sidewall") and the like can be used herein for descriptive purposes, and by so doing, descriptions can be made by the relative position of one element to another element as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or "contains" or variants thereof are used in either the detailed description and / or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." It is also noted that, as used herein, the terms "substantially," "approximately," and other like terms are used as terms of approximation and not as terms of degree, unless otherwise indicated, and accordingly, are utilized to account for inherent deviations in measurements, calculations and / or other sources.

[0070] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0071] Figure 1 is a block diagram illustrating an exemplary embodiment of a display apparatus 1000 configured according to the principles of the present application.

[0072] Referring to Figure 1 , the display apparatus 1000 can include a pixel unit 100, a first scan driver 200, a second scan driver 300, an emission driver 400, a data driver 500, and a timing controller 600.

[0073] The display apparatus 1000 can display an image using various driving frequencies depending on a driving condition. In an embodiment, the display apparatus 1000 can adjust output frequencies of the first scan driver 200 and the second scan driver 300 and an output frequency of the data driver 500 corresponding to the output frequencies of the first scan driver 200 and the second scan driver 300 depending on a driving condition. For example, the display apparatus 1000 can display an image in response to various driving frequencies ranging from about 1 Hz to about 120 Hz.

[0074] The timing controller 600 can be supplied with input image data IRGB and timing signals Vsync, Hsync, DE, and CLK from a host system such as an application processor (AP) through a predetermined interface.

[0075] The timing controller 600 can generate a data driving control signal DCS based on the input image data IRGB and timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. The data driving control signal DCS can be supplied to the data driver 500. The timing controller 600 can rearrange the input image data IRGB and supply the rearranged input image data IRGB (i.e., image data RGB) to the data driver 500.

[0076] The timing controller 600 can supply the first gate start pulse GSP1 and the second gate start pulse GSP2 and the clock signal CLK to the first scan driver 200 and the second scan driver 300 based on the timing signals.

[0077] The timing controller 600 can supply the emission start pulse ESP and the clock signal CLK to the emission driver 400 based on the timing signals. The emission start pulse ESP can control a first timing of an emission control signal. The clock signal CLK can be used to shift the emission start pulse.

[0078] The first gate start pulse GSP1 can control a first timing of a scan signal to be supplied from the first scan driver 200. The clock signal CLK can be used to shift the first gate start pulse GSP1.

[0079] The second gate start pulse GSP2 can control a first timing of a scan signal to be supplied from the second scan driver 300. The clock signal CLK can be used to shift the second gate start pulse GSP2.

[0080] The data driver 500 can supply a data signal to the data line D in response to the data driving control signal DCS. The data signal supplied to the data line D can be supplied to a pixel PXL selected by a scan signal.

[0081] The data driver 500 can supply a data signal to the data line D during a frame period in response to a driving frequency. For example, the data driver 500 can supply a data signal to the data line D during a frame period when the display apparatus 1000 is driven at a first driving frequency. Here, the data signal to be supplied to the data line D can be synchronized with a scan signal to be supplied to the first scan line S1 and the second scan line S2.

[0082] In an embodiment, when the display apparatus 1000 is driven at a second driving frequency lower than the first driving frequency, the data driver 500 can supply a data signal to the data line D during a first period of each frame period and supply an arbitrary reference voltage to the data line D during a second period except for the first period. During the first period, a scan signal can be supplied to the second scan line S2.

[0083] In some embodiments, the reference voltage can be set to a specific voltage within the voltage range of the data signal. For example, the reference voltage can be set to a data voltage having a black gray scale. Also, the reference voltage can change within the voltage range of the data signal when a horizontal period elapses or a frame elapses.

[0084] Alternatively, in some embodiments, the data driver 500 can not supply the data signal or voltage to the data line D during the second period.

[0085] Also, the first period can refer to a period in which a scan signal is supplied to all of the first scan lines S1 and the second scan lines S2 and an emission control signal is supplied to the emission control line E. The second period can refer to a period in which an emission control signal is supplied to the emission control line E.

[0086] The first scan driver 200 can supply a scan signal to the first scan lines S1 in response to the first gate start pulse GSP1. In one exemplary embodiment, the first scan driver 200 can supply the scan signal at a first frequency, which can be substantially equal to the first driving frequency. For example, the first scan driver 200 can continuously supply the scan signal to the first scan lines S1. Here, the scan signal to be supplied from the first scan driver 200 can be set to a gate-on voltage, so that the transistor included in the pixel PXL can be turned on.

[0087] The second scan driver 300 can supply a scan signal to the second scan lines S2 in response to the second gate start pulse GSP2. In one exemplary embodiment, the second scan driver 300 can supply the scan signal at a second frequency, which can be substantially equal to the second driving frequency. For example, the second scan driver 300 can continuously supply the scan signal to the second scan lines S2. Here, the scan signal to be supplied from the second scan driver 300 can be set to a gate-on voltage, so that the transistor included in the pixel PXL can be turned on.

[0088] The first scan driver 200 and the second scan driver 300 can control scan signals to be supplied to the first scan lines S1 and the second scan lines S2 in response to a driving frequency. For example, when the display apparatus 1000 is driven at a first driving frequency, the first scan driver 200 can sequentially supply one or more scan signals to each of the first scan lines S1 during each frame period. Likewise, when the display apparatus 1000 is driven at the first driving frequency, the second scan driver 300 can sequentially supply one or more scan signals to each of the second scan lines S2 during each frame period. Here, a scan signal to be supplied to the ith (i is a natural number) first scan line S1i can overlap with a scan signal to be supplied to the ith second scan line S2i. In other words, a scan signal to be supplied to the ith first scan line S1i can be supplied in synchronization with a scan signal to be supplied to the ith second scan line S2i.

[0089] In an embodiment, when the display apparatus 1000 is driven at a second driving frequency, the first scan driver 200 supplies a scan signal to the first scan lines S1 during a first period. For example, the first scan driver 200 can supply at least one scan signal to each of the first scan lines S1 during the first period.

[0090] When the display apparatus 1000 is driven at the second driving frequency, the second scan driver 300 supplies a scan signal to the second scan lines S2 during the first period. For example, the second scan driver 300 can supply at least one scan signal to each of the second scan lines S2 during the first period. Here, a scan signal to be supplied to the ith first scan line S1i during the first period can overlap with a scan signal to be supplied to the ith second scan line S2i.

[0091] In an embodiment, when the display apparatus 1000 is driven at the second driving frequency, the first scan driver 200 and the second scan driver 300 can not supply a scan signal to the first scan lines S1 and the second scan lines S2. Here, in a driving mode using a low frequency lower than about 60 Hz, power consumption can be significantly reduced.

[0092] The emission driver 400 can supply an emission control signal to the emission control line E in response to an emission start pulse ESP. For example, the emission driver 400 can sequentially supply the emission control signal to the emission control line E. If the emission control signal is sequentially supplied to the emission control line E, the pixel PXL can not emit based on the horizontal line. For this operation, the emission control signal can be set to a gate cutoff voltage so that the transistor included in the pixel PXL can be cut off. In an embodiment, the emission driver 400 can supply the emission control signal to the ith emission control line Ei so that the emission control signal overlaps with the scan signal to be supplied to the (i-1)th first scan line S1i-1 (and / or the (i-1)th second scan line S2i-1) and the ith first scan line S1i (and / or the ith second scan line S2i).

[0093] In an embodiment, the emission driver 400 can supply the emission control signal to the emission control line E in response to a maximum driving frequency of the display apparatus 1000. For example, the output frequency at which the emission driver 400 outputs the emission control signal can be constant regardless of a change in the driving frequency.

[0094] As the driving frequency decreases, the number of times the emission driver 400 repeatedly performs the operation of supplying the emission control signal to each of the emission control lines E during each frame period can increase.

[0095] The pixel unit 100 can include the pixel PXL coupled with the data line D, the first scan line S1, and the second scan line S2, and the emission control line E. The pixel PXL can be supplied with voltages of the first power supply VDD, the second power supply VSS, and the initialization power supply Vint from an external apparatus.

[0096] When the scan signal is supplied to the corresponding first scan line S1 and the second scan line S2 coupled with the pixel PXL, each pixel PXL can be selected and then supplied with the data signal from the corresponding data line D. The pixel PXL supplied with the data signal can control the amount of current (driving current) flowing from the first power supply VDD to the second power supply VSS via the light emitting element in response to the data signal. The light emitting element can generate light having a predetermined brightness in response to the amount of current. The time during which each pixel PXL emits light can be controlled by the emission control signal supplied from the corresponding emission control line E coupled with the pixel PXL.

[0097] Furthermore, depending on the structure of the pixel circuit, the pixel PXL can be coupled to one or more first scan lines S1, one or more second scan lines S2, and one or more emission control lines E. In other words, in an embodiment, the signal lines S1, S2, E, and D to be coupled to the pixel PXL can be set to various forms depending on the circuit structure of the pixel PXL.

[0098] Figure 2 is a circuit diagram illustrating an exemplary embodiment of a representative pixel PXL included in a display device of FIG. 1. Figure 1

[0099] Referring to Figure 2 , the pixel PXL can include a light emitting element LD, first to seventh transistors M1 to M7, and a storage capacitor Cst.

[0100] The light emitting element LD can include a first electrode (one of an anode electrode and a cathode electrode) coupled to the fourth node N4 and a second electrode (the other of the cathode electrode and the anode electrode) coupled to the second power supply VSS. The light emitting element LD can emit light having a predetermined brightness corresponding to a current supplied from the first transistor M1.

[0101] In an embodiment, the light emitting element LD can be an organic light emitting diode including an organic light emitting layer. In an embodiment, the light emitting element LD can be an inorganic light emitting element formed of an inorganic material. The light emitting element LD can have a shape in which a plurality of inorganic light emitting elements are coupled in parallel and / or in series between the second power supply VSS and the fourth node N4.

[0102] The first transistor (or driving transistor) M1 can include a first electrode coupled to the first node N1 and a second electrode coupled to the third node N3. A gate electrode of the first transistor M1 is coupled to the second node N2. The first transistor M1 can control an amount of current flowing from the first power supply VDD to the second power supply VSS via the light emitting element LD in response to a voltage of the second node N2. To this end, the first power supply VDD can be set to a voltage higher than the second power supply VSS.

[0103] The second transistor M2 can be coupled between the data line Dm and the first node N1. A gate electrode of the second transistor M2 can be coupled to the i-th first scan line S1i. When a scan signal is supplied to the i-th first scan line S1i, the second transistor M2 can be turned on to electrically couple the data line Dm and the first node N1.

[0104] The third transistor M3 can be coupled between the second electrode (i.e., the third node N3) of the first transistor M1 and the second node N2. A gate electrode of the third transistor M3 can be coupled to the i-th second scan line S2i. When a scan signal is supplied to the i-th second scan line S2i, the third transistor M3 can be turned on to electrically connect the second electrode of the first transistor M1 to the second node N2. Accordingly, if the third transistor M3 is turned on, the first transistor M1 can be connected in a diode form.

[0105] ​The fourth transistor M4 is coupled between the second node N2 and the first initialization power source Vint1. A gate electrode of the fourth transistor M4 is coupled to the i-1th second scan line S2i-1. When a scan signal is supplied to the i-1th second scan line S2i-1, the fourth transistor M4 is turned on so that a voltage of the first initialization power source Vint1 can be supplied to the second node N2.

[0106] In an embodiment, the voltage of the first initialization power source Vint1 is set to be lower than a voltage of a data signal to be supplied to the data line Dm. Thus, when the fourth transistor M4 is turned on, a gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power source Vint1, and the first transistor M1 can have an on-bias state (i.e., the first transistor M1 can be initialized to the on-bias state).

[0107] The fifth transistor M5 is coupled between the first power source VDD and the first node N1. A gate electrode of the fifth transistor M5 can be coupled to the emission control line Ei. The fifth transistor M5 can be turned off when an emission control signal is supplied to the emission control line Ei, and can be turned on in other cases.

[0108] The sixth transistor M6 is coupled between the second electrode (i.e., the third node N3) of the first transistor M1 and the first electrode (i.e., the fourth node N4) of the light emitting element LD. A gate electrode of the sixth transistor M6 can be coupled to the emission control line Ei. The sixth transistor M6 can be turned off when an emission control signal is supplied to the emission control line Ei, and can be turned on in other cases.

[0109] The seventh transistor M7 is coupled between the second initialization power source Vint2 and the fourth node N4. In an embodiment, a gate electrode of the seventh transistor M7 can be coupled to the i-th emission control line Ei.

[0110] The seventh transistor M7 can be turned on when an emission control signal is supplied to the emission control line Ei, and can be turned off in other cases. In other words, the seventh transistor M7, which is an N-type transistor, can be turned on or turned off in reverse to the turning on or turning off of the fifth transistor M5 and the sixth transistor M6.

[0111] When an emission control signal is supplied (i.e., during a non-emission period), the seventh transistor M7 is turned on so that a voltage of the second initialization power source Vint2 can be supplied to the first electrode of the light emitting element LD.

[0112] If the voltage of the second initialization power source Vint2 is supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD can be discharged. Because the residual voltage charged in the parasitic capacitor is discharged (removed), the undesired faint emission can be prevented. Thus, the black performance of the pixel PXL can be enhanced.

[0113] The first initialization power source Vint1 and the second initialization power source Vint2 can generate different voltages. In other words, the voltage for initializing the second node N2 and the voltage for initializing the fourth node N4 can be set to different values.

[0114] During the low frequency operation with a relatively long frame period, if the voltage of the first initialization power source Vint1 to be supplied to the second node N2 is too low, the hysteresis of the first transistor M1 can be excessively varied during the corresponding frame period. Such hysteresis can cause a flickering phenomenon in the low frequency driving mode. Thus, in the low frequency driving mode of the display device, the voltage of the first initialization power source Vint1 can be required to be higher than the voltage of the second power source VSS.

[0115] However, if the voltage of the second initialization power source Vint2 to be supplied to the fourth node N4 is higher than a predetermined reference voltage, the voltage of the parasitic capacitor of the light emitting element LD is charged rather than discharged. Thus, the voltage of the second initialization power source Vint2 is required to be lower than the predetermined reference voltage. For example, the voltage of the second initialization power source Vint2 can be similar to the voltage of the second power source VSS. However, this is for illustrative purposes only. For example, depending on the driving conditions of the display device, the voltage of the second initialization power source Vint2 can be higher or lower than the voltage of the second power source VSS.

[0116] In other words, in order to improve the driving performance of the pixel PXL, the voltage to be supplied to the second node N2 through the fourth transistor M4 is required to be different from the voltage to be supplied to the fourth node N4 through the seventh transistor M7.

[0117] In various embodiments, the pixel PXL included in the display device 1000 can be coupled with the first initialization power source Vint1 and the second initialization power source Vint2 that provide different voltages. Thus, because the voltage for initializing the first transistor M1 and the voltage for initializing the light emitting element LD are independently determined, the flickering phenomenon or the emission error can be prevented or mitigated.

[0118] However, this is for illustrative purposes only, and one electrode of the fourth transistor M4 and one electrode of the seventh transistor M7 can be coupled to a common initialization power source.

[0119] The storage capacitor Cst can be coupled between the first power supply VDD and the second node N2. The storage capacitor Cst can store a voltage applied to the second node N2.

[0120] The first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 each can be formed of a polysilicon semiconductor transistor. For example, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 each can include a polysilicon semiconductor layer as an active layer (channel). The polysilicon semiconductor layer can be formed by a low temperature polysilicon (LTPS) process. Further, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 each can be a P-type transistor. Accordingly, a gate-on voltage for turning on the first transistor M1, the second transistor M2, the fifth transistor M5, or the sixth transistor M6 can have a logic low level.

[0121] Since the polysilicon semiconductor transistor has an advantage of high response speed, the polysilicon semiconductor transistor can be applied to a switching element in which a high-speed switching operation is required.

[0122] The third transistor M3, the fourth transistor M4, and the seventh transistor M7 each can be formed of an oxide semiconductor transistor. For example, the third transistor M3, the fourth transistor M4, and the seventh transistor M7 each can be formed of an N-type oxide semiconductor transistor and include an oxide semiconductor layer as an active layer. Accordingly, a gate-on voltage for turning on the third transistor M3, the fourth transistor M4, or the seventh transistor M7 can have a logic high level.

[0123] The oxide semiconductor transistor can be produced by a low temperature process and has a low charge mobility compared to a charge mobility of the polysilicon semiconductor transistor. In other words, the oxide semiconductor transistor can have an excellent off-current characteristic. Accordingly, if each of the third transistor M3 and the fourth transistor M4 is formed of an oxide semiconductor transistor, a leakage current from the second node N2 can be minimized. Thereby, a display quality of the display device can be enhanced. Since the seventh transistor M7 is formed of an oxide semiconductor transistor, a leakage current from the fourth node N4 can be minimized, thereby a display quality of the display device can be enhanced.

[0124] In a case where the seventh transistor M7 is a P-type transistor, a logic low level of a voltage for turning on the seventh transistor M7 is required to be lower than a voltage of the second initialization power supply Vint2. However, as described above, the second initialization power supply Vint2 can have a voltage of 0 V. Accordingly, the logic low level of the voltage for turning on the seventh transistor M7 can be 0 V. Figure 2If the seventh transistor M7 is formed of an N-type transistor, a logic low level of a signal for controlling the seventh transistor M7 can be relatively increased, as illustrated in the middle. Accordingly, the gate electrode of the seventh transistor M7 can be coupled to the emission control line Ei, and the seventh transistor M7 can be controlled by the emission control signal.

[0125] Accordingly, when the seventh transistor M7 is controlled by the emission control signal, power consumption is reduced. Furthermore, because the second initialization power source Vint2 having a relatively low potential is applied to the fourth node N4, black display performance can be further enhanced.

[0126] Figure 3A is an exemplary timing diagram illustrating an example of an operation of the pixel PXL of Figure 2 FIG. 1.

[0127] Referring to Figure 2 and Figure 3A In a case in which the display apparatus 1000 is driven at a first driving frequency, the pixel PXL can be supplied with a signal for displaying an image at the first driving frequency.

[0128] In a case in which the display apparatus 1000 is driven at a second driving frequency lower than the first driving frequency, the pixel PXL can be supplied with a signal for displaying an image at the second driving frequency.

[0129] A gate-on voltage of a scan signal to be supplied to each of the second scan lines S2i and S2i-1 coupled to the third transistor M3, the fourth transistor M4, and the seventh transistor M7, each of which is an N-type transistor, can have a logic high level. A gate-on voltage of a scan signal to be supplied to each of the first scan lines S1i and S1i+1 coupled to the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6, each of which is a P-type transistor, can have a logic low level.

[0130] First, an emission control signal is supplied to the emission control line Ei. If the emission control signal is supplied to the emission control line Ei, the fifth transistor M5 and the sixth transistor M6 are cut off. If the fifth transistor M5 and the sixth transistor M6 are cut off, the pixel PXL is set to a non-emission state.

[0131] Further, if the emission control signal is supplied to the emission control line Ei, the seventh transistor M7 is turned on. If the seventh transistor M7 is turned on, the voltage of the second initialization power source Vint2 can be supplied to the first electrode of the light emitting element LD (i.e., the fourth node N4). Thereby, a residual voltage remaining in the parasitic capacitor of the light emitting element LD can be discharged.

[0132] Although all of the second to fourth transistors M2 to M4 are turned off, if the emission control signal to be supplied to the emission control line Ei is transitioned from a logic low level to a logic high level, the gate voltage of the fifth transistor M5 is increased. Therefore, when the emission control signal is supplied to the emission control line Ei, the voltage of the first electrode of the first transistor M1 (i.e., the first node N1) can be increased by voltage coupling, and an on bias can be applied to the first transistor M1.

[0133] Thereafter, the scan signal is supplied to the i-1th second scan line S2i-1. If the scan signal is supplied to the i-1th second scan line S2i-1, the fourth transistor M4 can be turned on. If the fourth transistor M4 is turned on, the voltage of the first initialization power source Vint1 is supplied to the second node N2.

[0134] Thereafter, the scan signal is supplied to the i-1th second scan line S2i-1. If the scan signal is supplied to the i-1th second scan line S2i-1, the fourth transistor M4 can be turned on. If the fourth transistor M4 is turned on, the voltage of the first initialization power source Vint1 is supplied to the second node N2.

[0135] If the scan signal is supplied to the i-1th second scan line S2i-1, the fourth transistor M4 can be turned on. If the fourth transistor M4 is turned on, the voltage of the first initialization power source Vint1 is supplied to the second node N2.

[0136] When the first transistor M1 is turned on, the data signal DS supplied to the first node N1 can be supplied to the second node N2 via the diode-connected first transistor M1. Here, a voltage corresponding to the data signal DS and the threshold voltage of the first transistor M1 can be applied to the second node N2. Here, the storage capacitor Cst can store the voltage corresponding to the second node N2.

[0137] Thereafter, the supply of the emission control signal to the emission control line Ei can be suspended. If the supply of the emission control signal to the emission control line Ei is suspended, the fifth transistor M5 and the sixth transistor M6 are turned on. Further, the seventh transistor M7 is turned off. Here, the first transistor M1 can control the drive current flowing to the light emitting element LD in response to the voltage of the second node N2. The light emitting element LD can generate light having a luminance corresponding to the amount of current.

[0138] For the purpose of description, although Figure 3A The illustrated scan signal is supplied to each of the first scan line S1 and the second scan line S2, but exemplary embodiments are not limited thereto. For example, a plurality of scan signals can be supplied to each of the first scan line S1 and the second scan line S2. In this case, the operation process is substantially the same as that of Figure 3A ; thus, a detailed description thereof will be omitted to avoid redundancy. In the following description, it is assumed that the scan signal is supplied to each of the first scan line S1 and the second scan line S2.

[0139] Figure 3B is an exemplary timing diagram illustrating an example of the operation of the pixel PXL of Figure 2 .

[0140] Referring to Figure 2 and Figure 3B , when the display apparatus 1000 is driven at the second driving frequency, the pixel PXL can periodically increase the voltage of the first electrode (e.g., the source electrode) of the first transistor M1 during the second period so as to maintain the luminance of the image output during the first period.

[0141] In an embodiment, during the second period, the scan signal is not supplied to either the third transistor M3 or the fourth transistor M4. For example, during the second period, the scan signal to be supplied to the (i-1)th second scan line S2i-1 and the ith second scan line S2i can have a logic low level L.

[0142] Because the third transistor M3 and the fourth transistor M4 remain turned off, the gate voltage of the first transistor M1 (i.e., the voltage of the second node N2) can not be affected by the operation performed during the second period.

[0143] Further, in an embodiment, the scan signal can not be supplied to the second transistor M2 during the second period. For example, during the second period, the scan signal to be supplied to the first scan line S1 can have a logic high level H.

[0144] In other words, during the second period, only the emission control signal can be supplied to the pixel PXL through the emission control line Ei. During the second period (e.g., while the second period is ongoing), the emission control signal can be supplied to the emission control line Ei in a pulse shape. Figure 5When the second transistor M2 is turned on (as indicated by T2), the scan signal is supplied to neither the first scan line S1 nor the second scan line S2.

[0145] When all of the second transistor M2 to the fourth transistor M4 are turned off, the emission control signal to be supplied to the i-th emission control line Ei is transitioned from a logic low level to a logic high level. Thereby, the fifth transistor M5 and the sixth transistor M6 are turned off. Here, when the gate voltage of the fifth transistor M5 is increased, for example, by a parasitic capacitor between the gate electrode of the fifth transistor M5 and the first node N1, the voltage of the first node N1 is coupled with the increased gate voltage of the fifth transistor M5, whereby the voltage of the first node N1 can be increased. Thus, the turn-on bias can be applied to the first transistor M1 each time the emission control signal is supplied to the emission control line Ei during the second period.

[0146] Thus, in the low-frequency driving mode, the second transistor M2 does not need to be turned on for applying the turn-on bias during the second period, and the first scan driver 200 can not output the scan signal during the second period. Thus, the power consumption can be reduced.

[0147] Figure 4 is an example of an example timing chart illustrating a method of driving the display device 1000 when the display device 1000 is driven at a first driving frequency. Figure 1

[0148] For example, the first driving frequency can be set to a value ranging from approximately 60 Hz to approximately 120 Hz. The first driving frequency is a driving frequency used when the display device 1000 displays a normal image.

[0149] Referring to Figure 4 When the display device 1000 is driven at the first driving frequency, the scan signal is sequentially supplied to the first scan lines S11 to S1n and the second scan lines S21 to S2n during each frame period 1F. Here, a representative scan signal to be supplied to the i-th first scan line S1i can overlap with a representative scan signal to be supplied to the i-th second scan line S2i.

[0150] When the display device 1000 is driven at the first driving frequency, the emission control signal can be sequentially supplied to the emission control lines E1 to En during each frame period 1F. Here, a representative emission control signal to be supplied to the i-th emission control line Ei can overlap with scan signals to be supplied to the i-1-th first scan line S1i-1 and the i-th first scan line S1i. The data signal DS is supplied to the data line D in synchronization with the scan signal.

[0151] The pixel PXL can emit light in response to the data signal DS, and an image can be displayed on the pixel unit 100.​

[0152] Figure 5 is an example of an example timing chart illustrating a method of driving the display device 1000 when the display device 1000 is driven at a second driving frequency. Figure 1

[0153] For example, the second driving frequency can be set to a frequency less than about 60 Hz. The second driving frequency is a driving frequency for displaying an image when the display device 1000 is in a standby mode or the like.

[0154] Referring to Figure 5 When the display device 1000 is driven at the second driving frequency, each frame period 1F is divided into a first period T1 and a second period T2. Here, the second period T2 can be set to a period longer than the first period T1.

[0155] The scan signals to be supplied to the i-th scan lines S1i and S2i and the data signal DS corresponding to the scan signals can be supplied at substantially the same period as the second driving frequency.

[0156] During the first period T1, the scan signals are sequentially supplied to the first scan lines S11 to S1n and the second scan lines S21 to S2n. Here, the scan signal to be supplied to the i-th first scan line S1i can overlap the scan signal to be supplied to the i-th second scan line S2i.

[0157] Further, during the first period T1, the emission control signals are sequentially supplied to the emission control lines E1 to En. Here, the emission control signal to be supplied to the i-th emission control line Ei can overlap the scan signals to be supplied to the i-1-th first scan line S1i-1 and the i-th first scan line S1i.

[0158] The data signal DS is supplied to the data lines D in synchronization with the scan signals. The data signal DS to be supplied to the i-th horizontal line can be supplied at substantially the same period as the second driving frequency.

[0159] During the second period T2, the scan signals are not supplied to the first scan lines S11 to S1n and the second scan lines S21 to S2n.

[0160] Further, during the second period T2, the plurality of emission control signals are supplied to each of the emission control lines E1 to En. For example, in a case in which the second driving frequency is about 1 Hz, the emission control signal is supplied to the i-th emission control line Ei once during the first period T1, and the emission control signal is supplied to the i-th emission control line Ei fifty-nine times during the second period T2.

[0161] ​During the second period T2, a voltage of the reference power source Vref can be supplied to each of the data lines D. However, this is for illustrative purposes only, and no voltage can be applied to the data lines D during the second period T2.

[0162] In a low-frequency driving mode using a second driving frequency (e.g., about 1 Hz), an image corresponding to the data signal DS can be displayed for a long time after the data signal DS is applied to each data line D once. Thus, a flickering phenomenon can occur due to the hysteresis of the first transistor M1.

[0163] However, as described with reference to Figure 3B , in the display apparatus 1000 using the pixel PXL according to the exemplary embodiment of the present application, the voltage of the first electrode of the first transistor M1 increases each time the emission control signal is supplied during the second period T2. Thereby, the hysteresis characteristic of the first transistor M1 can be improved.

[0164] Further, because the scan signal is not supplied to either the first scan lines S11 to S1n or the second scan lines S21 to S2n during the second period T2 (i.e., the number of times the scan signal is switched at the second driving frequency is reduced), power consumption in the low-frequency driving mode can be reduced. Here, switching can mean that the voltage level of the scan signal changes from a gate-on level to a gate-off level, and / or from a gate-off level to a gate-on level.

[0165] Figure 6 is an exemplary timing chart illustrating an example of a gate start pulse to be supplied to a scan driver included in Figure 1 the display apparatus 1000.

[0166] Referring to Figure 1 , Figure 4 , Figure 5 and Figure 6 , the output frequency of the first gate start pulse GSP1 and the second gate start pulse GSP2 can vary depending on the driving frequency.

[0167] In an embodiment, the pulse width of the first gate start pulse GSP1 and the second gate start pulse GSP2 can be substantially the same as each other. The pulse width of the emission start pulse ESP can be greater than the pulse width of the first gate start pulse GSP1 and the second gate start pulse GSP2.

[0168] In an embodiment, the timing controller 600 can output the emission start pulse ESP at a constant frequency regardless of the driving frequency. For example, the output frequency of the emission start pulse ESP can be set to be substantially the same as the maximum driving frequency of the display apparatus 1000.

[0169] In a case in which the display apparatus 1000 is driven at the first driving frequency, the same number of scan signals are supplied to the first scan lines S11 to S1n and the second scan lines S21 to S2n. For example, when the display apparatus 1000 is driven at the first driving frequency, the timing controller 600 supplies the first gate start pulse GSP1 to the first scan driver 200 at the first driving frequency. Also, when the display apparatus 1000 is driven at the first driving frequency, the timing controller 600 supplies the second gate start pulse GSP2 to the second scan driver 300 at the first driving frequency. Also, when the display apparatus 1000 is driven at the first driving frequency, the timing controller 600 supplies the emission start pulse ESP to the emission driver 400 at the first driving frequency.

[0170] In a case in which the display apparatus 1000 is driven at the second driving frequency (e.g., in a low-frequency driving mode), the timing controller 600 supplies the first gate start pulse GSP1 to the first scan driver 200 at the second driving frequency. Also, when the display apparatus 1000 is driven at the second driving frequency, the timing controller 600 supplies the second gate start pulse GSP2 to the second scan driver 300 at the second driving frequency. Thus, when the display apparatus 1000 is driven at the second driving frequency, the first scan driver 200 and the second scan driver 300 can output scan signals only during a first time period (indicated by T1 in Figure 5

[0171] Although the display apparatus 1000 is driven at the second driving frequency, the timing controller 600 supplies the emission start pulse ESP to the emission driver 400 at the first driving frequency.

[0172] Figure 7 is a circuit diagram illustrating a representative pixel PXL included in the display apparatus 1000 of Figure 1 is an example embodiment of the pixel PXL of Figure 8A is an example of the operation of the pixel PXL of Figure 7 is an example of the operation of the pixel PXL of Figure 8B Figure 7 In the following description of

[0173] In the following description of Figures 7-8B the same reference numerals are used to refer to the same or like parts as those of Figures 2-3B and repetitive description thereof will be omitted to avoid redundancy.

[0174] Referring to Figures 7-8B , the pixel PXL can include a light emitting element LD, first to seventh transistors M1 to M7, and a storage capacitor Cst.

[0175] ​​Each of the third transistor M3, the fourth transistor M4, and the seventh transistor M7 is formed of an N-type transistor. For example, each of the third transistor M3, the fourth transistor M4, and the seventh transistor M7 can be formed of an N-type oxide semiconductor transistor.

[0176] In an embodiment, the gate electrode of the seventh transistor M7 can be coupled to the (i+1)th second scan line S2i+1. The seventh transistor M7 is turned on after the data write operation and the threshold voltage compensation operation have been performed with respect to the first transistor M1.

[0177] However, this is for illustrative purposes only, and the gate electrode of the seventh transistor M7 can be coupled to the (i-1)th second scan line S2i-1 or the ith second scan line S2i. Thus, the timing at which the light emitting element LD is initialized can be adjusted.

[0178] Figure 8A The method of driving the pixel PXL when the display device 1000 is driven at the first drive frequency is illustrated. Further, during the first period T1, in a case where the display device 1000 is driven at the second drive frequency, the pixel PXL is operated according to the driving method of Figure 8A .

[0179] The seventh transistor M7 is controlled by a control signal supplied to the (i+1)th second scan line S2i+1. Thus, the timing at which the voltage of the second initialization power source Vint2 is supplied to the light emitting element LD can be separated from the data write timing and the gate initialization timing of the first transistor M1.

[0180] The method of driving the pixel PXL is substantially the same as described with reference to Figure 3A the driving method; thus, a repetitive description thereof will be omitted to avoid redundancy.

[0181] Figure 8B The method of driving the pixel PXL during the second period T2 is illustrated. In an embodiment, during a non-emission period of the second period T2 (i.e., a period in which the emission control signal is supplied), a scan signal is supplied to the first scan line S1i, and the second transistor M2 is turned on. Here, the reference voltage Vref is supplied from the data line Dm to the first electrode of the first transistor M1. Thus, during the second period T2, if the scan signal is supplied to the first scan line S1i, the turn-on bias can be applied to the first transistor M1.

[0182] Figure 9 is a block diagram illustrating an exemplary embodiment of another display device 1001 configured according to the principles of the present invention, Figure 10A is a block diagram illustrating a display device 1001 including a display panel 1000 configured according to the principles of the present invention, Figure 9a circuit diagram of an exemplary embodiment of a representative pixel PXL in the display apparatus 1001, and Figure 10B is a circuit diagram illustrating an exemplary embodiment of a representative pixel PXL included in Figure 9 a circuit diagram of an exemplary embodiment of a representative pixel PXL in the display apparatus 1001.

[0183] In the following description of Figure 9 the same reference numerals are used to represent the same or similar components as those of Figure 1 and repetitive description thereof will be omitted to avoid redundancy. In the following description of Figure 10A and Figure 10B the same reference numerals are used to represent the same or similar components as those of Figure 2 and Figure 7 and repetitive description thereof will be omitted to avoid redundancy.

[0184] Referring to Figures 9-10B the display apparatus 1001 can include a pixel unit 100, a first scan driver 200, a second scan driver 300, an emission driver 400, a data driver 500, and a timing controller 600.

[0185] In general, a second electrode (e.g., a cathode electrode) of the light emitting element LD is coupled to a common electrode disposed on the second electrode. The common electrode can be a conductive layer integrally formed on the light emitting element LD of the pixel unit 100. A voltage of the second power supply VSS can be supplied to the conductive layer.

[0186] In an embodiment, a power supply line L_VSS for transmitting the second power supply VSS can be further disposed in the pixel unit 100 on which the pixel PXL is disposed. The power supply line L_VSS is disposed under the light emitting element LD and between the light emitting element LD and a predetermined substrate. For example, the power supply line L_VSS can be disposed on the same layer as the first scan line S1, the second scan line S2, the data line D, or the emission control line E. The power supply line L_VSS can include a plurality of lines extending in one direction in the pixel unit 100, or can be disposed in a mesh pattern.

[0187] The power supply line L_VSS is electrically coupled to the common electrode. In addition, a voltage of the second power supply VSS can be supplied to the power supply line L_VSS.

[0188] A voltage drop due to line resistance can occur in the power supply line L_VSS. Accordingly, the voltage of the power supply line L_VSS can be different from the voltage of the common electrode directly coupled to the second electrode of the light emitting element LD.

[0189] In an embodiment, the seventh transistor M7 can be coupled between the fourth node N4 and a power supply line L_VSS for transmitting a voltage of the second power supply VSS. For example, as shown in FIG. 2, the seventh transistor M7 can be coupled between the fourth node N4 and the power supply line L_VSS.Figure 10A and Figure 10B As illustrated, the second initialization power supply coupled to the seventh transistor M7 can be replaced by the power line L_VSS. If the seventh transistor M7 is turned on, the voltage of the power line L_VSS is supplied to the fourth node N4, and the residual voltage charged in the parasitic capacitor can be discharged (removed).

[0190] Therefore, the structure for forming a separate second initialization power supply and the line for transmitting the voltage of the second initialization power supply can be omitted, thereby reducing production costs.

[0191] Figure 11 The illustration includes Figure 1 A block diagram of an exemplary embodiment of a scan driver in a display device 1000.

[0192] Reference Figure 1 , Figure 2 and Figure 11 The first scan driver 200 is coupled to the first scan line S1, and the second scan driver 300 is coupled to the second scan line S2.

[0193] Pixel unit 100 includes multiple pixel lines PL. For example, pixel unit 100 may include n pixel lines PL (n is a natural number greater than 1). Each of the pixel lines PL includes a pixel PXL coupled to the same scan line. Furthermore, each of the pixel lines PL is coupled to at least one of the first scan lines S1 and at least one of the second scan lines S2.

[0194] The first scan driver 200 can output a first scan signal to a first scan line S1. Each first scan signal can have a gate on-voltage, which has a logic low level. The first scan driver 200 includes n first-stage P_STs configured to shift and output the first scan signal. The i-th first-stage P_STi is coupled to the i-th first scan line S1i. The i-th first scan line S1i is coupled to the i-th pixel line PLi.

[0195] Similarly, the (i+1)th first-level P_STi+1 is coupled to the (i+1)th first scan line S1i+1. Each of the first scan signals to be supplied to the first scan line S1 has a pulse width corresponding to a horizontal time period (1H). Therefore, the number of first-level P_STs included in the first scan driver 200 can correspond to the number of pixel lines PL. For example, the first scan driver 200 may include n first-level P_STs subordinately coupled to each other.

[0196] However, this is for illustrative purposes only. For example, in the case where the first scan driver 200 outputs a scan signal for controlling the N-type transistor, the first scan driver 200 may include a second stage.

[0197] The second scan driver 300 can output a second scan signal to a second scan line S2. Each second scan signal can have a gate on-voltage, which has a logic high level. The second scan driver 300 includes j second-stage N_STs (where j is a natural number less than n) configured to shift and output the second scan signal.

[0198] In an embodiment, each of the second-level N_ST can be coupled to multiple second scan lines S2. For example, as Figure 11 As illustrated in the diagram, each of the second-level N_STs can be coupled to two consecutive second scan lines S2. The k-th second-level N_STk can be coupled to the i-th second scan line S2i and the (i+1)-th second scan line S2i+1.

[0199] In this case, the number of second-level N_STs can be half the number of first-level P_STs, that is, n / 2. For example, n / 2 second-level N_STs can be subordinately coupled to each other.

[0200] Each of the second scan signals to be supplied to the second scan line S2 has a pulse width corresponding to three or more horizontal time periods (3H).

[0201] exist Figure 2 In the case of pixel PXL, a period in which the second transistor M2 and the third transistor M3 are simultaneously turned on is required. Therefore, if the first scan signal supplied to the four first scan lines S1 overlaps with the second scan signal, the four second scan lines S2 can be coupled to the k-th second stage N_STk. Thus, the four pixel lines can share the output of the k-th second stage N_STk.

[0202] In this embodiment, a second scan signal is supplied to a third transistor M3 and a fourth transistor M4. For proper driving of pixel PXL, the second scan signal is first supplied to the third transistor M3, and then to the fourth transistor M4. The second scan signal supplied to the third transistor M3 does not overlap with the second scan signal supplied to the fourth transistor M4.

[0203] In an embodiment, the ipth second scan line S2i-p (where p is a natural number) (e.g., the (i-4th)th second scan line S2i-4) can be coupled to the ith pixel line PLi. Therefore, the ipth second scan line S2i-p can be coupled together to the ipth pixel line PLi-p and the ith pixel line PLi.

[0204] Thus, the second scan driver 300 outputting the second scan signal having a pulse width corresponding to three or more horizontal periods (3H) can collectively output the second scan signal to the third transistors M3 included in the pixels of the plurality of pixel lines, respectively. Accordingly, the number of the second stages N_ST included in the second scan driver 300 can be reduced, and power consumption of the second scan driver 300 and the display apparatus 1000 including the second scan driver 300 can be reduced.

[0205] Figure 12 is a circuit diagram of an exemplary embodiment of a pixel PXL coupled to a scan driver of Figure 11 .

[0206] In the following description of Figure 12 , the same reference numbers are used for the components that are the same or similar to those of Figure 2 , and repetitive description thereof will be omitted to avoid redundancy.

[0207] Referring to Figure 2 , Figure 11 and Figure 12 , the k-th second stage N_STk can be shared by the i-th second scan line S2i and the i+1-th second scan line S2i+1.

[0208] Although Figure 12 one second stage is illustrated as being commonly coupled to two consecutive second scan lines, exemplary embodiments are not limited thereto. For example, one second stage can be commonly coupled to three or more second scan lines.

[0209] The i-th pixel PXLi is arranged on the i-th pixel line PLi, and the i+1-th pixel PXLi+1 is arranged on the i+1-th pixel line PLi+1. The i-th pixel PXLi and the i+1-th pixel PXLi+1 have substantially the same configuration.

[0210] The k-th second stage N_STk can simultaneously supply the k-th second scan signal SC(k) to the i-th second scan line S2i and the i+1-th second scan line S2i+1. Accordingly, the k-th second scan signal SC(k) is supplied to both the third transistor M3 of the i-th pixel PXLi and the third transistor M3 of the i+1-th pixel PXLi+1.

[0211] Hereinafter, the k-th second scan signal SC(k) can be interpreted as a scan signal output from the k-th second stage N_STk.

[0212] Likewise, the k-pth second-stage N_STk-p can supply the k-pth second scan signal SC(k-p) to the i-4th second scan line S2i-4 and the i-3th second scan line S2i-3 at the same time. The gate electrode of the fourth transistor M4 of the i-th pixel PXLi is coupled to the i-4th second scan line S2i-4. The gate electrode of the fourth transistor M4 of the i+1-th pixel PXLi+1 is coupled to the i-3th second scan line S2i-3. Thus, the k-pth second scan signal SC(k-p) is supplied to both the fourth transistor M4 of the i-th pixel PXLi and the fourth transistor M4 of the i+1-th pixel PXLi+1.

[0213] Figure 13A is an example of an exemplary timing chart illustrating an example of the operation of the pixel PXL of Figure 12 FIG. 1.

[0214] Referring to Figure 12 and Figure 13A In a case in which the display apparatus 1000 is driven at the first driving frequency, the kth second scan signal SC(k) is commonly supplied to the i-th pixel PXLi and the i+1-th pixel PXLi+1.

[0215] In an embodiment, the second scan signal can have a pulse width corresponding to four horizontal periods (4H). In this case, the second scan signal overlaps with two consecutive first scan signals. Thus, two consecutive second scan lines are commonly coupled to one second stage.

[0216] The third transistor M3 of the i-th pixel PXLi and the third transistor M3 of the i+1-th pixel PXLi+1 are simultaneously controlled by the kth second scan signal SC(k). Also, the fourth transistor M4 of the i-th pixel PXLi and the fourth transistor M4 of the i+1-th pixel PXLi+1 are simultaneously controlled by the k-pth second scan signal SC(k-p).

[0217] First, the emission control signals are sequentially supplied to the i-th emission control line Ei and the i+1-th emission control line Ei+1. The emission control signals are supplied to the i-th emission control line Ei and the i+1-th emission control line Ei+1 at intervals of one horizontal period (1H).

[0218] Thereafter, the second scan signal (e.g., the k-pth second scan signal SC(k-p)) is simultaneously supplied to the i-4th second scan line S2i-4 and the i-3th second scan line S2i-3. Thus, the fourth transistor M4 of the i-th pixel PXLi and the fourth transistor M4 of the i+1-th pixel PXLi+1 are simultaneously turned on, and the voltage of the first initialization power source Vint1 is simultaneously supplied to the second node N2.

[0219] Subsequently, a second scan signal (e.g., the kth second scan signal SC(k)) is supplied to the ith second scan line S2i and the i+1th second scan line S2i+1 at the same time. Thereby, the third transistor M3 of the ith pixel PXLi and the third transistor M3 of the i+1th pixel PXLi+1 are turned on at the same time.

[0220] While the third transistor M3 of the ith pixel PXLi and the third transistor M3 of the i+1th pixel PXLi+1 are turned on, the first scan signal is sequentially supplied to the ith pixel PXLi and the i+1th pixel PXLi+1. Accordingly, the data signal DS is sequentially written in the ith pixel PXLi and the i+1th pixel PXLi+1.

[0221] Since the third transistor M3 remains turned on even after the supply of the first scan signal has been completed, the time required for threshold voltage compensation can be reliably ensured.

[0222] Thereafter, the supply of the emission control signal to the ith emission control line Ei and the i+1th emission control line Ei+1 is sequentially discontinued, and the ith pixel PXLi and the i+1th pixel PXLi+1 sequentially emit light.

[0223] Thus, since the third transistors M3 included in the plurality of pixel lines share the second scan signal, the power consumption of the second scan driver 300 and the display apparatus 1000 including the second scan driver 300 can be reduced.

[0224] Figure 13B is an exemplary timing chart illustrating an example of the operation of the pixel PXL of Figure 12 .

[0225] In the following description of Figure 13B , like reference numerals are used to denote like parts throughout Figure 13A , and repetitive description thereof will be omitted to avoid redundancy.

[0226] Referring to Figure 13B , the output of the kth second scan signal SC(k) can be delayed by q horizontal periods (qH, q is a natural number greater than 1) compared to the k-pth second scan signal SC(k-p).

[0227] Here, the k-th second scan signal SC(k) does not overlap with the k-p-th second scan signal SC(k-p). Also, in a case where a supply interval between the k-th second scan signal SC(k) and the k-p-th second scan signal SC(k-p) corresponds to q horizontal periods (qH), the fourth transistor M4 of the i-th pixel PXLi is coupled to the i-q-th second scan line S2i-q and the fourth transistor M4 of the i+1-th pixel PXLi+1 is coupled to the i-q+1-th second scan line S2i-q+1.

[0228] However, in a case where i is smaller than q, a second scan signal output from a separate stage or a gate start pulse can be supplied to the fourth transistor M4 of the i-th pixel PXLi. For example, in a case where q is 6, a second scan signal that leads the second scan signal supplied to the third transistors M3 of the first to sixth pixels PXL1 to PXL6 by six horizontal periods can be generated from a separate stage or the like, and can be supplied to the first to sixth pixels PXL1 to PXL6.

[0229] Figure 14A is an example of an example timing diagram illustrating a method of driving the display apparatus 1000 when the display apparatus 1000 is driven at a first driving frequency. Figure 12 is an example of an example timing diagram illustrating a method of driving the display apparatus 1000 when the display apparatus 1000 is driven at a first driving frequency.

[0230] In the following description of Figure 14A , the same reference numbers are used for components that are the same or similar to those of Figure 4 , and a repeated description thereof will be omitted to avoid redundancy.

[0231] Referring to Figure 14A , in a case where the display apparatus 1000 is driven at a first driving frequency, the pixels PXL can be supplied with signals for displaying an image at the first driving frequency.

[0232] In an embodiment, the second scan signals are commonly supplied to two consecutive second scan lines S2. Accordingly, the number of second scan signals sequentially output from the second scan driver 300 during each frame period 1F can be half the number of first scan signals supplied to the first scan line S1. Accordingly, the number of second stages included in the second scan driver 300 can be reduced, and the power consumption of the second scan driver 300 and the display apparatus 1000 can be reduced.

[0233] Also, at least two first scan signals overlap with each second scan signal.

[0234] The second scan signal having a pulse width of three or more horizontal periods (3H) is supplied to each pixel twice during each frame period 1F. The pulse width of the emission control signal can cover the time during which the second scan signal is supplied twice. For example, in the case in which the second scan signal has a pulse width corresponding to four horizontal periods (4H), the emission control signal can have a pulse width corresponding to nine or more horizontal periods (9H).

[0235] The operation of driving the pixels using the first driving frequency has been described with reference to Figure 3A 、 Figure 13A and Figure 13B ; thus, a repeated description thereof will be omitted to avoid redundancy.

[0236] Figure 14B is an example of an example timing chart illustrating a method of driving the display apparatus 1000 including the pixel PXL when the display apparatus 1000 is driven at the second driving frequency. Figure 12

[0237] In the following description of Figure 14B , the same reference numerals are used to designate components that are the same or similar to those of Figure 3B , and a repeated description thereof will be omitted to avoid redundancy.

[0238] Referring to Figure 14B , when the display apparatus 1000 is driven at the second driving frequency, each frame period 1F is divided into a first period T1 and a second period T2. Here, the second period T2 can be set as a period longer than the first period T1.

[0239] The driving operation of the display apparatus 1000 in the first period T1 is substantially the same as the driving operation of Figure 14A .

[0240] In an embodiment, the second scan signal is commonly supplied to two consecutive second scan lines S2. Thus, the number of the second scan signals sequentially output from the second scan driver 300 during each frame period 1F can be half of the number of the first scan signals supplied to the first scan line S1.

[0241] During the second period T2, the supply of the first scan signal and the second scan signal can be suspended, and only the emission control signal can be periodically supplied. Since the parasitic capacitor is coupled between the first node N1 and the gate electrode of the fifth transistor M5 by the switching of the emission control signal, the turn-on bias can be periodically applied to the first transistor M1. Thus, the power consumption in the second period T2 can be reduced, so that the image quality in the low-frequency driving mode can be improved.

[0242] Figure 15 ​It is a diagram showing the coupling to Figure 11 A circuit diagram of an exemplary embodiment of the pixel PXL of the scan driver. Figure 16 It is a diagram. Figure 15 An exemplary timing diagram of the operation of pixel PXL.

[0243] In addition to the third transistor M3, the fourth transistor M4, and the seventh transistor M7, and the scan signal for controlling the transistors, the pixels and the method for driving the pixels according to this embodiment are similar to... Figure 7 and Figure 12 The methods for determining and driving pixels are essentially the same; therefore, the same reference numerals are used to indicate the same pixels. Figure 7 and Figure 12 Components that are identical or similar to each other will be omitted from repeated descriptions to avoid redundancy.

[0244] Reference Figure 15 and Figure 16 Each of the pixels PXLi and PLXi+1 includes a light-emitting element LD, a storage capacitor Cst, and a first transistor M1 to a seventh transistor M7.

[0245] In this embodiment, each of the first transistors M1 to the seventh transistor M7 is formed of a polysilicon semiconductor transistor. For example, each of the first transistors M1 to the seventh transistor M7 may be formed of a P-type LTPS transistor. Therefore, each of the scan signals to be supplied to the first transistors M1 to the seventh transistor M7 has a gate on-state voltage, which has a logic low level.

[0246] The gate electrode of the seventh transistor M7 of the i-th pixel PXLi is coupled to the i-th first scan line S1i. Therefore, the second transistor M2 and the seventh transistor M7 can be controlled simultaneously. However, this is only for illustrative purposes, and the gate electrode of the seventh transistor M7 of the i-th pixel PXLi can be coupled to either the (i-1)-th first scan line S1i-1 or the (i+1)-th first scan line S1i+1.

[0247] In an embodiment, such as Figure 16 As illustrated in the diagram, the output of the kth second scan signal SC(k) can be delayed by six horizontal time intervals (6H) compared to the kpth second scan signal SC(kp). Therefore, the gate electrode of the fourth transistor M4 of the i-th pixel PXLi is coupled to the (i-6)th second scan line S2i-6. Similarly, the gate electrode of the fourth transistor M4 of the (i+1)th pixel PXLi+1 is coupled to the (i-5)th second scan line S2i-5.

[0248] In addition to the fact that the gate on-voltage of each of the scan signals is at a logic low level, Figure 15 Methods for driving pixel PXL andFigure 13A or Figure 13B the driving method of the display apparatus 1000 of FIG. 1 is substantially the same. Thus, repetitive description thereof will be omitted to avoid redundancy.

[0249] Figure 17 is a block diagram illustrating an exemplary embodiment of another display apparatus configured according to the principles of the present application.

[0250] In the following description of the display apparatus 1002 of FIG. 10, Figure 17 the same reference numerals are used to represent the same or similar components as those of the display apparatus 1000 of FIG. 1, and repetitive description thereof will be omitted to avoid redundancy. Figure 1 Referring to FIG. 10,

[0251] Figure 17 The display apparatus 1002 can include a pixel unit 100, a first scan driver 200, a second scan driver 300, a third scan driver 350, an emission driver 400, a data driver 500, and a timing controller 600A.

[0252] The pixel unit 100 includes a plurality of pixels PXL. Each pixel PXL can have the same configuration as that of any one of the pixels described above.

[0253] The timing controller 600A can supply the first gate start pulse GSP1, the second gate start pulse GSP2, and the third gate start pulse GSP3, and the clock signal CLK to the first scan driver 200, the second scan driver 300, and the third scan driver 350 based on the timing signals Vsync, Hsync, DE, and CLK.

[0254] The first gate start pulse GSP1 can control a first timing of a scan signal to be supplied from the first scan driver 200. The second gate start pulse GSP2 can control a first timing of a scan signal to be supplied from the second scan driver 300.

[0255] The third gate start pulse GSP3 can control a first timing of a scan signal to be supplied from the third scan driver 350.

[0256] The data driver 500 can supply a data signal to the data line D in response to a data driving control signal DCS. The data signal supplied to the data line D can be supplied to the pixel PXL selected by the scan signal.

[0257] The first scan driver 200 can supply a scan signal to the first scan line S1 in response to the first gate start pulse GSP1. The first scan line S1 is coupled to a gate electrode of the second transistor M2 of the pixel PXL. For example, a data signal can be written by the scan signal supplied to the first scan line S1. In an embodiment, the first scan line S1 can also be coupled to a gate electrode of the seventh transistor M7 of the pixel PXL.​

[0258] The third scan driver 350 can supply a scan signal to the third scan line S3 in response to the third gate start pulse GSP3. The third scan line S3 is coupled to a gate electrode of the fourth transistor M4 of the pixel PXL. For example, a voltage of the initialization power source Vint can be supplied to the gate electrode of the first transistor M1 by the scan signal supplied to the third scan line S3.

[0259] The second scan driver 300 can supply a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. The second scan line S2 is coupled to a gate electrode of the third transistor M3 of the pixel PXL. For example, a threshold voltage of the first transistor M1 of each pixel PXL can be compensated for by the scan signal supplied to the corresponding second scan line S2.

[0260] Thus, the scan signals to be supplied to the third transistor M3 and the fourth transistor M4 can be separately controlled. Thus, RC delay in the scan line due to a connection relationship of the scan line can be mitigated, and image quality can be improved. Figure 11

[0261] Figure 18 is a block diagram illustrating exemplary embodiments of a second scan driver and a third scan driver included in a display apparatus of Figure 17 Figure 19 is an exemplary timing chart illustrating an example of a gate start pulse to be supplied to a scan driver included in a display apparatus of Figure 17

[0262] Referring to Figure 17 , Figure 18 and Figure 19 , the second scan driver 300 can output second scan signals LSC1 to LSC(n / 4) through the second scan lines S2. The third scan driver 350 can output third scan signals RSC1 to RSC(n / 4) through the third scan lines S3.

[0263] The pixel unit 100 includes n pixel lines PL1 to PLn.

[0264] The second scan driver 300 includes k first stages 301 to 30k (k is a natural number smaller than n) coupled to each other in dependence. The second scan driver 300 can shift and supply the second gate start pulse GSP2 to the second scan lines S2. Each of the first stages 301 to 30k is coupled to a plurality of the second scan lines S2. For example, as Figure 18 ​​​As illustrated in the drawing, each of the first stages 301 to 30k can be coupled to four second scan lines S2. The second scan signal LSC1 output from the first first stage 301 can be supplied to the first to fourth pixel lines PL1 to PL4 at the same time. Accordingly, the number of the first stages 301 to 30k included in the second scan driver 300 can be reduced to 1 / 4.

[0265] The third scan driver 350 includes k second stages 351 to 35k coupled to each other in a slave relationship. The third scan driver 350 can shift and supply the third gate start pulse GSP3 to the third scan lines S3. Each of the second stages 351 to 35k is coupled to a plurality of the third scan lines S3. For example, the third scan signal RSC1 output from the first second stage 351 can be supplied to the first to fourth pixel lines PL1 to PL4 at the same time. Accordingly, the number of the second stages 351 to 35k included in the third scan driver 350 can be reduced to 1 / 4.

[0266] As described above, the third scan signals RSC1 to RSC(n / 4) to be supplied to the fourth transistors M4 of the pixels PXL must be supplied earlier than the second scan signals LSC1 to LSC(n / 4) to be supplied to the third transistors M3 of the pixels PXL. Accordingly, the supply timing of the second gate start pulse GSP2 and the third gate start pulse GSP3 can be different from each other. For example, the supply of the first second scan signal LSC1 can be delayed by about q horizontal periods (qH) compared to the supply of the first third scan signal RSC1.

[0267] Accordingly, the second gate start pulse GSP2 can be delayed by q horizontal periods (qH) from the output of the timing controller 600A compared to the third gate start pulse GSP3. Here, the first gate start pulse GSP1 can overlap a part of the second gate start pulse GSP2.

[0268] Thus, since the scan signals to be supplied to the third transistors M3 and the fourth transistors M4 are separately controlled, the RC delay in the scan lines S1, S2, and S3 can be mitigated, and the image quality can be improved.

[0269] Figure 20 is a circuit diagram illustrating a representative pixel PXL included in a display apparatus constructed according to the principles of the present application.

[0270] The pixel and the method of driving the pixel according to this embodiment are substantially the same as those of Figure 7 except for the seventh transistor M7 and the scan signal for controlling the seventh transistor M7; accordingly, the same reference numerals are used to denote the same elements as those of Figure 7components of the same or similar components, and repetitive description thereof will be omitted to avoid redundancy.

[0271] Referring to Figure 20 The pixel PXL can include a light emitting element LD, first to seventh transistors M1 to M7, and a storage capacitor Cst.

[0272] Each of the third transistor M3 and the fourth transistor M4 is formed of an N-type transistor. For example, each of the third transistor M3 and the fourth transistor M4 can be formed of an N-type oxide semiconductor transistor.

[0273] The seventh transistor M7 is formed of a P-type transistor. For example, the seventh transistor M7 is formed of a P-type polysilicon semiconductor transistor.

[0274] In an embodiment, the gate electrode of the seventh transistor M7 can be coupled to the i-th first scan line S1i. The seventh transistor M7 can be turned on at the same time as the second transistor M2.

[0275] However, this is for illustrative purposes only, and the gate electrode of the seventh transistor M7 can be coupled to the i-1-th first scan line S1i-1 or the i+1-th first scan line S1i+1. Thus, the timing of initializing the light emitting element LD can be adjusted.

[0276] While certain example embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to these embodiments, but is intended to cover any modifications and equivalents within the scope of the appended claims as well as various obvious modifications and equivalent arrangements as would be apparent to one of ordinary skill in the art having the benefit of this description.

Claims

1. A display device comprising: pixels coupled to first scan lines, second scan lines, emission control lines, and data lines; a first scan driver supplying a scan signal to each of the first scan lines at a first frequency to drive the display device at a first drive frequency, and supplying the scan signal to each of the first scan lines at a second frequency to drive the display device at a second drive frequency lower than the first drive frequency, wherein the first frequency is equal to the first drive frequency and the second frequency is equal to the second drive frequency; a second scan driver supplying a scan signal to each of the second scan lines at the first frequency to drive the display device at the first drive frequency, and supplying the scan signal to each of the second scan lines at the second frequency to drive the display device at the second drive frequency; an emission driver supplying an emission control signal to each of the emission control lines at the first frequency during a first period and a second period; and a data driver supplying a data signal to each of the data lines in response to the scan signal supplied to each of the first scan lines, wherein, when the display device is driven at the second drive frequency, the first scan driver and the second scan driver are configured to supply the scan signal during the first period, and wherein, when the display device is driven at the second drive frequency, the first scan driver and the second scan driver are configured to not supply the scan signal during the second period.

2. The display device of claim 1, wherein, The second period is set to a period longer than the first period.

3. The display device according to claim 1, further comprising: a timing controller supplying a first gate start pulse to the first scan driver, a second gate start pulse to the second scan driver, and an emission start pulse to the emission driver.

4. The display device according to claim 3, wherein when the display device is driven at the first drive frequency, the timing controller is configured to output the first gate start pulse and the second gate start pulse at the first frequency, and wherein, when the display device is driven at the second drive frequency, the timing controller is configured to output the first gate start pulse and the second gate start pulse at the second frequency.

5. The display device of claim 4, wherein, The timing controller is configured to output the emission start pulse at the first frequency regardless of a drive frequency.

6. The display device of claim 1, wherein, pixels arranged on an i-th horizontal line among the pixels include: a light emitting element including a first electrode and a second electrode coupled to a second power supply; a first transistor including a first electrode coupled to a first node to control a drive current based on a voltage of a second node, the first node electrically connected to a first power supply; a second transistor coupled between a corresponding data line and the first node and configured to be activated by the scan signal supplied to an i-th first scan line; a third transistor coupled between the second node and a third node coupled to a second electrode of the first transistor and configured to be activated by the scan signal supplied to an i-th second scan line; a fourth transistor coupled between the second node and a first initialization power supply and configured to be activated by the scan signal supplied to an i-1-th second scan line; a fifth transistor coupled between the first power supply and the first node and configured to be deactivated by the emission control signal supplied to an i-th emission control line; a sixth transistor coupled between the third node and the first electrode of the light emitting element and configured to be deactivated by the emission control signal; and a storage capacitor coupled between the first power supply and the second node, and wherein i is a natural number.

7. The display device of claim 6, wherein, The pixel arranged on the i-th horizontal line further includes a seventh transistor coupled between a second initialization power supply and the first electrode of the light emitting element, the seventh transistor configured to be activated by the emission control signal.

8. The display device of claim 7, wherein, The voltage of the first initialization power supply is different from the voltage of the second initialization power supply.

9. The display device of claim 8, wherein, The voltage of the first initialization power supply is greater than the voltage of the second initialization power supply.

10. The display apparatus of claim 8, wherein: each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor includes a P-type transistor, and each of the third transistor, the fourth transistor, and the seventh transistor includes an N-type transistor.

11. The display apparatus of claim 6, further comprising a power supply line arranged below the light emitting element to transmit the voltage of the second power supply to the light emitting element.

12. The display device of claim 11, wherein, The pixel arranged on the i-th horizontal line further includes a seventh transistor coupled between the power supply line and the first electrode of the light emitting element, the seventh transistor configured to be activated by the emission control signal.

13. The display device of claim 1, wherein, The pixel arranged on the i-th horizontal line includes: a light emitting element including a first electrode and a second electrode coupled to a second power supply; a first transistor including a first electrode coupled to a first node to control a drive current based on a voltage of a second node, the first node electrically connected to a first power supply; a second transistor coupled between a corresponding data line and the first node and configured to be activated by the scan signal supplied to an i-th first scan line; a third transistor coupled between the second node and a third node coupled to a second electrode of the first transistor and configured to be activated by the scan signal supplied to an i-th second scan line; a third transistor coupled between the second node and a third node coupled to a second electrode of the first transistor, and configured to be activated by the scan signal supplied to the i-th second scan line; a fourth transistor coupled between the second node and a first initialization power supply, and configured to be activated by the scan signal supplied to the i-q-th second scan line, where q is a natural number and i is a natural number equal to or greater than q, and in a case where i is smaller than q, the fourth transistor is configured to receive the scan signal output from a separate stage or a gate start pulse; and a fifth transistor coupled between the first power supply and the first node, and configured to be deactivated by the emission control signal supplied to the i-th emission control line.

14. The display device according to claim 13, wherein: the first scan driver includes n stages coupled in dependence on each other, n being a natural number greater than 1, and the second scan driver includes k stages coupled in dependence on each other, k being a natural number smaller than n.

15. The display device of claim 14, wherein, A pulse width of the scan signal to be supplied to the second scan lines is greater than a pulse width of the scan signal to be supplied to the first scan lines.

16. The display device of claim 15, wherein, Each of the stages included in the second scan driver is configured to supply the scan signal to at least two of the second scan lines simultaneously.

17. The display device of claim 15, wherein, A portion of the scan signal to be supplied to the i-th second scan line overlaps with the scan signal to be supplied to the i-th first scan line and the scan signal to be supplied to the i+1-th first scan line.

18. The display device of claim 14, wherein, The scan signal to be supplied to the third transistor of the pixel arranged on the i-th horizontal line is delayed by four or more horizontal periods compared to the scan signal to be supplied to the fourth transistor of the pixel arranged on the i-th horizontal line.

19. The display device of claim 1, wherein, The pixel arranged on the i-th horizontal line among the pixels includes: a light emitting element including a first electrode and a second electrode coupled to a second power supply; a first transistor including a first electrode coupled to a first node to control a drive current based on a voltage of a second node, the first node being electrically connected to a first power supply; a second transistor coupled between a corresponding data line and the first node, and configured to be activated by a first scan signal supplied to the i-th first scan line; a third transistor coupled between the second node and a third node coupled to a second electrode of the first transistor, and configured to be activated by a second scan signal supplied to the i-th second scan line; a fourth transistor coupled between the second node and a first initialization power supply, and configured to be activated by a third scan signal supplied to the i-th third scan line; and a fifth transistor coupled between the first power supply and the first node, and configured to be deactivated by the emission control signal supplied to the i-th emission control line. a fifth transistor coupled between the first power supply and the first node and configured to be deactivated by the emission control signal supplied to an i-th emission control line, wherein the first scan driver is configured to supply the first scan signal to the first scan lines and the second scan driver is configured to supply the second scan signal to the second scan lines, and wherein i is a natural number.

20. The display device according to claim 19, further comprising: a third scan driver that supplies the third scan signal to third scan lines connected to the pixels at the first frequency when the display device is driven at the first driving frequency and at the second frequency when the display device is driven at the second driving frequency.

21. The display device according to claim 20, wherein: the first scan driver includes n stages coupled in dependence on each other, n being a natural number greater than 1, and each of the second scan driver and the third scan driver includes k stages coupled in dependence on each other, k being a natural number smaller than n.

22. The display device of claim 21, wherein, the third scan driver is configured to supply the third scan signal to the i-th third scan line and, after a delay of q horizontal periods, the second scan driver is configured to supply the second scan signal to the i-th second scan line, and a pulse width of the second scan signal is equal to a pulse width of the third scan signal, and wherein q is a natural number of 4 or more.

Images