Display device

Abstract

The display device includes: a substrate; a driving thin-film transistor disposed on the substrate and including a driving semiconductor layer and a driving gate electrode; a first scan line disposed on the substrate and extending in a first direction; a data line extending in a second direction intersecting the first direction; a node connection line disposed in the same layer as the first scan line; and a shielding conductive layer disposed between the data line and the node connection line and disposed in the same layer as the driving gate electrode, wherein one end of the node connection line is connected to the driving gate electrode through a first node contact hole.

Description

[0001] This application claims priority and all rights to Korean Patent Application No. 10-2019-0074199, filed on June 21, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more exemplary embodiments relate to a display device, and more specifically, to a display device for achieving high quality. Background Technology

[0003] A display device is a device for visually expressing data. A display device includes a substrate divided into a display area and a peripheral area. The display area includes scan lines and data lines insulated from each other, as well as multiple pixels. The display area further includes thin-film transistors and pixel electrodes electrically connected to the thin-film transistors corresponding to the respective pixels. The display area may also include counter electrodes commonly provided in the pixels. The peripheral area may include various wiring for delivering electrical signals to the display area, scan drivers, data drivers, controllers, etc.

[0004] Display devices are used for a variety of purposes. Furthermore, their thinness and light weight have led to their wider application. Pixel circuitry, including within the pixels, has been designed in various forms to achieve high quality and high resolution in display devices. Summary of the Invention

[0005] One or more exemplary embodiments provide a display apparatus for implementing high-quality images. However, the purpose is merely exemplary, and the scope of the exemplary embodiments is not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practice of the proposed exemplary embodiments.

[0007] According to one or more exemplary embodiments, a display device includes: a substrate; a driving thin-film transistor disposed on the substrate and including a driving semiconductor layer and a driving gate electrode; a first scan line disposed on the substrate and extending in a first direction; a data line extending in a second direction intersecting the first direction; a node connection line disposed in the same layer as the first scan line; and a shielding conductive layer disposed between the data line and the node connection line and disposed in the same layer as the driving gate electrode, wherein one end of the node connection line is connected to the driving gate electrode through a first node contact hole.

[0008] In an exemplary embodiment, the display device may further include a first gate electrode layer connected to the first scan line through a third contact hole, wherein a shielding conductive layer extends from the first gate electrode layer.

[0009] In an exemplary embodiment, the shielding conductive layer and the node connection line may extend in a second direction.

[0010] In an exemplary embodiment, the first gate electrode layer may include a compensation gate electrode of a compensation thin-film transistor and a switching gate electrode of a switching thin-film transistor, and a shielding conductive layer may be disposed between the compensation gate electrode and the switching gate electrode.

[0011] In an exemplary embodiment, the display device may further include a driving voltage line extending in a second direction and disposed in the same layer as the data line, and a shielding conductive layer may be disposed between the data line and the driving voltage line.

[0012] In an exemplary embodiment, the display device may further include a compensation thin-film transistor connected to the first scan line and including a compensation semiconductor layer and a compensation gate electrode, and the other end of the node connection line may be connected to the compensation semiconductor layer through a second node contact hole.

[0013] In an exemplary embodiment, the resistance value of the first scan line may be less than the resistance value of the driving gate electrode.

[0014] In an exemplary embodiment, the display device may further include: a storage capacitor including a driving gate electrode as a lower electrode and an upper electrode overlapping the lower electrode and defining a storage opening having a closed shape, and a first node contact hole may be arranged in the storage opening.

[0015] In an exemplary embodiment, the size of the storage opening may be larger than the size of the first node contact hole.

[0016] In an exemplary embodiment, the display device may further include: an emission control thin-film transistor disposed on a substrate and including an emission control semiconductor layer and an emission control gate electrode; and an emission control line for delivering an emission control signal to the emission control gate electrode, wherein the emission control gate electrode may be provided as part of the emission control line.

[0017] In an exemplary embodiment, the display device may further include: a second scan line separate from the first scan line and extending in a first direction; and a second gate electrode layer connected to the second scan line through a fourth contact hole, wherein a shielding conductive layer may extend from the second gate electrode layer.

[0018] In an exemplary embodiment, the second gate electrode layer may be part of the first initialization gate electrode of the first initialization thin-film transistor.

[0019] In an exemplary embodiment, the first initialization gate electrode may have a curved shape.

[0020] In an exemplary embodiment, the shielding conductive layer may extend in the second direction.

[0021] According to one or more exemplary embodiments, a display device includes: a substrate; a driving thin-film transistor disposed on the substrate and including a driving gate electrode and a driving semiconductor layer, wherein a first gate insulating layer is disposed between the driving gate electrode and the driving semiconductor layer; a shielding conductive layer disposed in the same layer as the driving gate electrode; a second gate insulating layer and an interlayer insulating layer disposed on the shielding conductive layer; a node connection line disposed on the interlayer insulating layer and connected to the driving gate electrode through a first node contact hole penetrating the interlayer insulating layer and the second gate insulating layer; a first scan line disposed in the same layer as the node connection line and extending in a first direction; a via layer covering the first scan line and the node connection line; and a data line disposed on the via layer and extending in a second direction intersecting the first direction, wherein the shielding conductive layer may extend in the second direction between the data line and the node connection line.

[0022] In an exemplary embodiment, the display device may further include a first gate electrode layer connected to the first scan line through a third contact hole, and a shielding conductive layer may extend from the first gate electrode layer.

[0023] In an exemplary embodiment, the display device may further include: a second scan line extending in a first direction; and a second gate electrode layer connected to the second scan line through a fourth contact hole, wherein a shielding conductive layer may extend from the second gate electrode layer.

[0024] In an exemplary embodiment, the driving semiconductor layer may be curved.

[0025] In an exemplary embodiment, the display device may further include a driving voltage line extending in a second direction and disposed in the same layer as the data line, and the node connection line may overlap with the driving voltage line.

[0026] In an exemplary embodiment, the shielding conductive layer can receive a scanning signal. Attached Figure Description

[0027] The above and other aspects, features and advantages of specific exemplary embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 This is a schematic top plan view of a display device according to an exemplary embodiment;

[0029] Figure 2 This is a schematic block diagram of a display device according to an exemplary embodiment;

[0030] Figure 3 Is included Figure 1 An exemplary embodiment of the equivalent circuit diagram of the pixels in the display device shown;

[0031] Figure 4A This is a schematic plan view illustrating the positions of a plurality of thin-film transistors and capacitors included in a pixel circuit according to an exemplary embodiment;

[0032] Figures 4B to 4E These are shown separately according to the layers. Figure 4A A schematic layout diagram of the configuration shown;

[0033] Figure 5 It is shown Figure 4A A schematic layout diagram of a portion of the configuration of the shielding conductive layer shown;

[0034] Figure 6 It shows the section intercepted along line I-I'. Figure 4A The local configuration of the cross-sectional view;

[0035] Figure 7 It is intercepted along lines II-II' and III-III'. Figure 4A A cross-sectional view showing the configuration in which organic light-emitting devices are arranged;

[0036] Figure 8 Is included Figure 1 Another exemplary embodiment of the equivalent circuit diagram of the pixels in the display device shown; and

[0037] Figure 9 This is a schematic diagram illustrating the layout of the locations of a plurality of thin-film transistors and capacitors included in a pixel circuit according to an exemplary embodiment. Detailed Implementation

[0038] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings, in which the same reference numerals always refer to the same elements. In this regard, these exemplary embodiments may have different forms and should not be construed as limited to the description set forth herein. Therefore, the exemplary embodiments described below with reference to the accompanying drawings are only intended to explain aspects of this specification. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms that include “at least one” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0039] In an exemplary embodiment, when a layer, region, or component is referred to as being "on" another layer, region, or component, the layer, region, or component may be directly on the other layer, region, or component, or there may be an intermediate layer, region, or component between the layer, region, or component and the other layer, region, or component.

[0040] For ease of explanation, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the exemplary embodiments described below are not limited thereto. It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part without departing from the teachings herein.

[0041] In the exemplary embodiments described below, when a layer, region, or component is connected to another layer, region, or component, the layer, region, or component may be directly connected to the other layer, region, or component, or may be indirectly connected to the other layer, region, or component, while other layers, regions, or components exist between the layer, region, or component and the other layer, region, or component. For example, in this specification, when a layer, region, or component is electrically connected to another layer, region, or component, the layer, region, or component may be directly electrically connected to the other layer, region, or component, or may be indirectly electrically connected to the other layer, region, or component, while other layers, regions, or components exist between the layer, region, or component and the other layer, region, or component.

[0042] Display devices used for displaying images may include liquid crystal displays, electrophoretic displays, organic light-emitting displays, inorganic light-emitting displays, field emission displays, surface conduction electron emission displays, plasma displays, cathode ray displays, etc.

[0043] In the following description, the organic light-emitting display device is described as an example of a display device according to an exemplary embodiment, but the display device according to the present invention is not limited thereto, and the display device can be of various types.

[0044] Figure 1 This is a schematic top plan view of a display device according to an exemplary embodiment.

[0045] refer to Figure 1The display device includes a display area DA and a peripheral area PA surrounding the display area DA. Pixels PX, each including an organic light-emitting device (“OLED”), can be arranged in the display area DA to provide an image. The peripheral area PA, which is an area in which no image is provided and is referred to as a non-display area, may include scan drivers and data drivers for providing electrical signals to be applied to the pixels PX, and power lines for providing power such as drive voltage and common voltage.

[0046] Figure 2 This is a schematic block diagram of a display device according to an exemplary embodiment.

[0047] The display device according to an exemplary embodiment includes a display unit 10 comprising a plurality of pixels PX, a scan driver 20, a data driver 30, an emission control driver 40, and a controller 50.

[0048] The display unit 10 is arranged in the display area DA and is located at the intersection of multiple scan lines SL1 to SLn+1, multiple data lines DL1 to DLm, and multiple emission control lines EL1 to ELn, and includes multiple pixels PX arranged approximately in a matrix. The multiple scan lines SL1 to SLn+1 and the multiple emission control lines EL1 to ELn extend in a first direction as the row direction, and the multiple data lines DL1 to DLm and the drive voltage line ELVDDL extend in a second direction as the column direction. In a pixel line, the n value of the multiple scan lines SL1 to SLn+1 may be different from the n value of the multiple emission control lines EL1 to ELn.

[0049] Each pixel PX is connected to three of the multiple scan lines SL1 to SLn+1 provided to the display unit 10. The scan driver 20 generates three scan signals and transmits the scan signals to each pixel PX through the multiple scan lines SL1 to SLn+1. That is, the scan driver 20 sequentially provides the current scan signal to scan lines SL2 to SLn, previous scan lines SL1 to SLn-1, or subsequent scan lines SL3 to SLn+1.

[0050] The initialization voltage line IL can receive the initialization voltage from the external power supply VINT and provide the initialization voltage to each pixel PX.

[0051] In addition, each pixel PX is connected to the data lines DL1 to DLm of the multiple data lines connected to the display unit 10 and the emission control lines EL1 to ELn of the multiple emission control lines connected to the display unit 10.

[0052] The data driver 30 delivers data signals to the pixel PX via multiple data lines DL1 to DLm. Each time a scan signal is provided to scan lines SL2 to SLn, a data signal is provided to the pixel PX selected in response to the scan signal.

[0053] The transmit control driver 40 generates a transmit control signal and delivers it to pixel PX via multiple transmit control lines EL1 to ELn. The transmit control signal controls the transmit timing of pixel PX. Depending on the internal structure of pixel PX, the transmit control driver 40 can be omitted.

[0054] The controller 50 converts multiple externally delivered image signals IR, IG, and IB into multiple image data signals DR, DG, and DB, and delivers the image data signals DR, DG, and DB to the data driver 30. Additionally, the controller 50 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, generates control signals for controlling the scan driver 20, the data driver 30, and the transmit control driver 40, and delivers these control signals to the scan driver 20, data driver 30, and transmit control driver 40, respectively. That is, the controller 50 generates a scan drive control signal SCS for controlling the scan driver 20, a data drive control signal DCS for controlling the data driver 30, and a transmit drive control signal ECS for controlling the transmit control driver 40, and delivers the signals described above.

[0055] Each pixel PX receives a driving voltage ELVDD and a common power voltage ELVSS from an external source. The driving voltage ELVDD can be a high-level voltage, and the common power voltage ELVSS can be a voltage lower than the driving voltage ELVDD or a ground voltage. The driving voltage ELVDD is supplied to each pixel PX through the driving voltage line ELVDDL.

[0056] Each of the multiple pixels PX responds to the data signals delivered via multiple data lines DL1 to DLm by emitting light with a specific brightness by providing a driving current to the organic light-emitting device of the pixel PX.

[0057] Figure 3 Is included Figure 1 An exemplary embodiment of the equivalent circuit diagram of the pixels in the display device shown.

[0058] refer to Figure 3 The pixel PX includes signal lines 121, 131, 132, 133 and 151, multiple thin-film transistors T1, T2, T3, T4, T5, T6 and T7 connected to the signal lines, capacitor Cst, initialization voltage line 103, driving voltage line 152 and organic light-emitting device OLED.

[0059] Figure 3 The illustration shows a case where each pixel PX includes signal lines 121, 131, 132, 133, and 151, an initialization voltage line 103, and a drive voltage line 152; however, the invention is not limited thereto. As another exemplary embodiment, at least one of the signal lines 121, 131, 132, 133, and 151, or / and the initialization voltage line 103, may be shared by neighboring pixels PX.

[0060] The thin-film transistor may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0061] The signal lines include a current scan line 131 that delivers a scan signal Sn, a previous scan line 132 that delivers a previous scan signal Sn-1 to a first initialization thin-film transistor T4, a subsequent scan line 133 that delivers a subsequent scan signal Sn+1 to a second initialization thin-film transistor T7, an emission control line 121 that delivers an emission control signal En to an operation control thin-film transistor T5 and an emission control thin-film transistor T6, and a data line 151 that intersects the current scan line 131 and delivers a data signal Dm. A drive voltage line 152 delivers a drive voltage ELVDD to a drive thin-film transistor T1, and an initialization voltage line 103 delivers an initialization voltage Vint that initializes the drive thin-film transistor T1 and the pixel electrodes of the organic light-emitting device (OLED).

[0062] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the lower electrode Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin-film transistor T1 is connected to the driving voltage line 152 via the operation control thin-film transistor T5. Furthermore, the driving drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting device (OLED) via the emission control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin-film transistor T2 and transmits the driving current I... OLED It is provided to organic light-emitting devices (OLEDs).

[0063] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the current scan line 131, the switching source electrode S2 of the switching thin-film transistor T2 is connected to the data line 151, and the switching drain electrode D2 of the switching thin-film transistor T2 is connected to the driving source electrode S1 of the driving thin-film transistor T1. Furthermore, the operating control thin-film transistor T5 is also connected to the driving voltage line 152. The switching thin-film transistor T2 is turned on in response to the scan signal Sn delivered through the current scan line 131 and performs a switching operation that delivers the data signal Dm delivered through the data line 151 to the driving source electrode S1 of the driving thin-film transistor T1.

[0064] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the current scan line 131. The compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the driving drain electrode D1 of the driving thin-film transistor T1 and is also connected to the pixel electrode of the organic light-emitting device OLED via the emission control thin-film transistor T6. Furthermore, the compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to the lower electrode Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn received through the current scan line 131, and electrically connects the driving gate electrode G1 and the driving drain electrode D1 of the driving thin-film transistor T1 to each other, thereby diode-connecting the driving thin-film transistor T1.

[0065] The first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the previous scan line 132. The first initialization source electrode S4 of the first initialization thin-film transistor T4 is connected to the second initialization source electrode S7 of the second initialization thin-film transistor T7 and the initialization voltage line 103. The first initialization drain electrode D4 of the first initialization thin-film transistor T4 is connected to the lower electrode Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin-film transistor T3, and the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on in response to the previous scan signal Sn-1 delivered through the previous scan line 132 and delivers the initialization voltage Vint to the driving gate electrode G1 of the driving thin-film transistor T1, thereby performing an initialization operation to initialize the voltage of the driving gate electrode G1 of the driving thin-film transistor T1.

[0066] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emitter control line 121, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the drive voltage line 152, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the drive source electrode S1 of the drive thin film transistor T1 and the switch drain electrode D2 of the switch thin film transistor T2.

[0067] The emission control gate electrode G6 of the emission control thin-film transistor T6 is connected to the emission control line 121. The emission control source electrode S6 of the emission control thin-film transistor T6 is connected to the driving drain electrode D1 of the driving thin-film transistor T1 and the compensation source electrode S3 of the compensation thin-film transistor T3. Furthermore, the emission control drain electrode D6 of the emission control thin-film transistor T6 is electrically connected to the second initialization drain electrode D7 of the second initialization thin-film transistor T7 and the pixel electrode of the organic light-emitting device (OLED). The emission control gate electrode G6 can be provided as part of the emission control line 121.

[0068] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are simultaneously turned on in response to the emission control signal En delivered through the emission control line 121, so that the driving voltage ELVDD is delivered to the organic light-emitting device OLED and the driving current I... OLED It flows through an organic light-emitting device (OLED).

[0069] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 is connected to the subsequent scan line 133. The second initialization drain electrode D7 of the second initialization thin-film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting device (OLED). The second initialization source electrode S7 of the second initialization thin-film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin-film transistor T4 and the initialization voltage line 103. The second initialization thin-film transistor T7 is turned on in response to the subsequent scan signal Sn+1 delivered through the subsequent scan line 133, and initializes the pixel electrode of the organic light-emitting device (OLED).

[0070] although Figure 3 The illustration shows a configuration where the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are respectively connected to the previous scan line 132 and the subsequent scan line 133, but the invention is not limited thereto. As another exemplary embodiment, both the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be connected to the previous scan line 132 and can be driven in response to the previous scan signal Sn-1. Furthermore, Figure 3 The positions of the source electrodes S1 to S7 and the drain electrodes D1 to D4 shown can be changed relative to each other depending on whether the thin-film transistor is p-type or n-type.

[0071] The detailed operation of each pixel PX according to the exemplary embodiment is as follows.

[0072] During the initialization period, when a previous scan signal Sn-1 is provided through the previous scan line 132, the first initialization thin-film transistor T4 is turned on in response to the previous scan signal Sn-1, and the driving thin-film transistor T1 is initialized by the initialization voltage Vint provided from the initialization voltage line 103.

[0073] During the data programming period, when a scan signal Sn is provided through the current scan line 131, the switching thin-film transistor T2 and the compensation thin-film transistor T3 are turned on in response to the scan signal Sn. In this case, the driving thin-film transistor T1 is connected to the turned-on compensation thin-film transistor T3 diode and biased in the positive direction.

[0074] By doing so, a compensation voltage Dm+Vth, which is the value of the data signal Dm provided from the data line 151 minus the threshold voltage (Vth) of the driving thin film transistor T1 (Vth is negative), is applied to the driving gate electrode G1 of the driving thin film transistor T1.

[0075] The driving voltage ELVDD and the compensation voltage Dm+Vth are applied to the two ends of the storage capacitor Cst, respectively, and the charge corresponding to the difference between the voltages at the two ends of the storage capacitor Cst is stored in the storage capacitor Cst.

[0076] During the emission period, the operation control thin-film transistor T5 and the emission control thin-film transistor T6 are turned on in response to the emission control signal En provided from the emission control line 121. The drive current I is determined based on the difference between the voltage at the drive gate electrode G1 of the driving thin-film transistor T1 and the drive voltage ELVDD. OLED It is generated and drives current I. OLED The emission control thin-film transistor T6 is provided to the organic light-emitting device OLED.

[0077] The display device according to this exemplary embodiment includes a shielding conductive layer 141 connected to the current scan line 131 and receiving a scan signal Sn. The shielding conductive layer 141 can block parasitic capacitance that may occur between the portion A where the data line 151 is arranged and the portion B that connects the driving thin-film transistor T1 to the compensating thin-film transistor T3. Since the scan signal, which is not a constant voltage but a pulse signal, is applied to the shielding conductive layer 141, the voltage applied to the pixel circuit can be kept low.

[0078] In the following text, reference will be made to Figures 4A to 7 The layout and cross-sectional views of the display device according to the exemplary embodiments are described in more detail.

[0079] Figure 4A This is a schematic diagram illustrating the layout of the positions of a plurality of thin-film transistors and capacitors in a pixel circuit according to an exemplary embodiment. Figures 4B to 4E They are shown according to the layers respectively. Figure 4A The diagram shows a schematic layout of the configuration.

[0080] Figure 5 It is shown Figure 4AA schematic layout diagram of a portion of the configuration of the shielding conductive layer shown. Figure 6 The cut-off along line I-I' is shown Figure 4A The local configuration of the cross-sectional view. Figure 7 It is intercepted along lines II-II' and III-III'. Figure 4A A cross-sectional view showing the configuration in which organic light-emitting devices are arranged.

[0081] like Figures 4A to 5 As shown, the display device according to an exemplary embodiment includes a current scan line 131, a previous scan line 132, an emission control line 121, and an initialization voltage line 103 extending in a first direction, and includes a data line 151 and a drive voltage line 152 extending in a second direction intersecting the first direction.

[0082] In an exemplary embodiment, the current scan line 131 and the previous scan line 132 may comprise the same material and be disposed in the same layer. The previous scan line 132 may be connected to the subsequent scan line 133 (see [link]). Figure 3 The current scan line 131 and the previous scan line 132 are arranged in a different layer than the layer in which the gate electrodes G1 to G7 of the thin-film transistors T1 to T7 are arranged, and each can have a resistance smaller than that of the gate electrodes G1 to G7. That is, the specific resistance value of the current scan line 131 can be smaller than that of the gate electrodes G1 to G7. Therefore, RC delay caused by the application of the scan signal Sn can be effectively prevented or minimized.

[0083] For example, the current scan line 131 and the previous scan line 132 can be arranged in layers directly on the interlayer insulating layer 114, including conductive materials such as aluminum (Al), copper (Cu), and titanium (Ti), and can include multilayers or single layers containing the aforementioned materials. For example, the current scan line 131 and the previous scan line 132 can each have a Ti / Al / Ti multilayer structure.

[0084] Gate electrodes G1 to G7 may be disposed on the first gate insulating layer 112 (e.g., disposed between the first gate insulating layer 112 and the second gate insulating layer 113), including molybdenum (Mo), titanium (Ti), etc., and may comprise a single layer or multiple layers. For example, gate electrodes G1 to G7 may be a single Mo layer.

[0085] The second gate insulating layer 113 and the interlayer insulating layer 114 can be arranged between the current scan line 131 and the gate electrodes G1 to G7. That is, the current scan line 131 and the previous scan line 132 are arranged on a different layer than the layer on which the gate electrodes G1 to G7 are arranged, and the current scan line 131 and the previous scan line 132 can be connected to the gate electrodes G1 to G7 through contact holes.

[0086] Furthermore, the transmit control line 121 may comprise the same material as the gate electrodes G1 to G7 and is disposed on the first gate insulating layer 112, which is the same layer on which the gate electrodes G1 to G7 are disposed. In other words, the transmit control line 121 may be in the same layer as the gate electrodes G1 to G7.

[0087] Data line 151 and drive voltage line 152 can be arranged between the current scan line 131 and the planarization layer 116. The resistivity of data line 151 and drive voltage line 152 can be similar to that of the current scan line 131. For example, data line 151 and drive voltage line 152 can include conductive materials comprising Al, Cu, or Ti, and can include multilayers or single layers comprising the aforementioned materials. For example, data line 151 and drive voltage line 152 can have a Ti / Al / Ti multilayer structure.

[0088] Additionally, the display device according to the exemplary embodiment includes a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, a second initialization thin-film transistor T7, and a storage capacitor Cst.

[0089] The driving semiconductor layer A1 of the driving thin-film transistor T1, the switching semiconductor layer A2 of the switching thin-film transistor T2, the compensation semiconductor layer A3 of the compensation thin-film transistor T3, the first initialization semiconductor layer A4 of the first initialization thin-film transistor T4, the operation control semiconductor layer A5 of the operation control thin-film transistor T5, the emission control semiconductor layer A6 of the emission control thin-film transistor T6, and the second initialization semiconductor layer A7 of the second initialization thin-film transistor T7 are arranged in the same layer and comprise the same material. For example, semiconductor layers A1 to A7 may comprise polycrystalline silicon. Furthermore, semiconductor layers A1 to A7 may be interconnected and bent into various shapes.

[0090] Semiconductor layers A1 to A7 may each include a channel region and source and drain regions on either side of the channel region. For example, the source and drain regions may be doped with impurities, and the impurities may include N-type or P-type impurities. The source and drain regions correspond to the source electrode and drain electrode, respectively. In the following text, the terms "source region" and "drain region" will be used instead of the terms "source electrode" and "drain electrode".

[0091] The driving thin-film transistor T1 includes a driving semiconductor layer A1, a driving gate electrode G1, a driving source region S1, and a driving drain region D1. The driving semiconductor layer A1 is curved. A storage capacitor Cst is formed on the driving thin-film transistor T1 to overlap with it.

[0092] The driving semiconductor layer A1 includes a driving channel region and driving source regions S1 and driving drain regions D1 on both sides of the driving channel region. The driving semiconductor layer A1 has a curved shape and can therefore be longer than the other semiconductor layers A2 to A7. For example, because the driving semiconductor layer A1 has a curved shape at several locations, like an omega "Ω" or the letter "S", it can have a large channel length in a narrow space (see...). Figure 4B Because the driving semiconductor layer A1 is long, the driving range of the gate voltage applied to the driving gate electrode G1 is increased. Therefore, the grayscale of the light emitted from the organic light-emitting device OLED can be controlled more precisely, and the display quality can be improved.

[0093] The storage capacitor Cst includes a lower electrode Cst1 and an upper electrode Cst2, and a second gate insulating layer 113 is disposed between the lower electrode Cst1 and the upper electrode Cst2. Here, the driving gate electrode G1 also serves as the lower electrode Cst1. That is, the driving gate electrode G1 is integrally formed with the lower electrode Cst1. The second gate insulating layer 113 serves as the dielectric layer of the storage capacitor Cst, and the storage capacitance is determined by the charge stored in the storage capacitor Cst and the voltage between the lower electrode Cst1 and the upper electrode Cst2.

[0094] The lower electrode Cst1 is a floating electrode in the form of an island, and includes a transmit control line 121, a switching gate electrode G2, a compensation gate electrode G3, a first initialization gate electrode G4, an operation control gate electrode G5, a transmit control gate electrode G6, and a second initialization gate electrode G7 (see [link to relevant documentation]). Figure 4C The same material as the transmit control line 121, switch gate electrode G2, compensation gate electrode G3, first initialization gate electrode G4, operation control gate electrode G5, transmit control gate electrode G6, and second initialization gate electrode G7 (see...). Figure 4C They are arranged on the same floor.

[0095] The upper electrode Cst2 is disposed on the second gate insulating layer 113. The upper electrode Cst2 defines a storage opening SOP. The upper electrode Cst2 overlaps entirely with the lower electrode Cst1. The storage opening SOP may have the form of a closed curve penetrating the upper electrode Cst2. Here, a simple closed curve indicates a closed shape where the start and end points are the same when points are drawn on a straight line or curve (e.g., a polygon or a circle). The upper electrode Cst2 is connected to the drive voltage line 152 through a contact hole and receives the drive voltage ELVDD.

[0096] The switching thin-film transistor T2 includes a switching semiconductor layer A2 and a switching gate electrode G2. The switching semiconductor layer A2 includes a switching source region S2 and a switching drain region D2 on both sides of the switching channel region. The switching drain region D2 is connected to the driving source region S1.

[0097] The compensated thin-film transistor T3 includes a compensated semiconductor layer A3 and a compensated gate electrode G3. The compensated semiconductor layer A3 includes a compensated source region S3 and a compensated drain region D3 on either side of the compensated channel region. The compensated thin-film transistor T3 formed by the compensated semiconductor layer A3 is a dual thin-film transistor comprising two compensated channel regions. The region between the compensated channel regions is a doped region and partially constitutes the source region of one channel region and the drain region of the other channel region of the dual thin-film transistor. The compensated drain region D3 can be connected to the lower electrode Cst1 via node connection line 135. The compensated gate electrode G3 can form an additional dual gate electrode to prevent leakage current.

[0098] The first initialization thin-film transistor T4 includes a first initialization semiconductor layer A4 and a first initialization gate electrode G4. The first initialization semiconductor layer A4 includes a first initialization source region S4 and a first initialization drain region D4 on both sides of the first initialization channel region. The first initialization thin-film transistor T4 formed by the first initialization semiconductor layer A4 is a dual thin-film transistor including two first initialization channel regions. The region between the first initialization channel regions is a doped region and partially constitutes the source region of one channel region of the dual thin-film transistor and the drain region of the other channel region of the dual thin-film transistor. The first initialization drain region D4 can be connected to the lower electrode Cst1 via node connection line 135. The first initialization source region S4 can be connected to the initialization voltage line 103.

[0099] The operation control thin-film transistor T5 includes an operation control semiconductor layer A5 and an operation control gate electrode G5. The operation control semiconductor layer A5 includes an operation control source region S5 and an operation control drain region D5 on both sides of the operation control channel region. The operation control drain region D5 can be connected to the drive source region S1.

[0100] The emitter control thin-film transistor T6 includes an emitter control semiconductor layer A6 and an emitter control gate electrode G6. The emitter control semiconductor layer A6 includes an emitter control source region S6 and an emitter control drain region D6 on both sides of the emitter control channel region. The emitter control source region S6 can be connected to the drive drain region D1.

[0101] The second initialization thin-film transistor T7 includes a second initialization semiconductor layer A7 and a second initialization gate electrode G7. The second initialization semiconductor layer A7 includes a second initialization source region S7 and a second initialization drain region D7 on both sides of the second initialization channel region.

[0102] Initialization voltage line 103 may include the same material as semiconductor layers A1 to A7 and is disposed in the same layer as semiconductor layers A1 to A7 (see [link]). Figure 4B The initialization voltage line 103 can be connected to the first initialization source region S4 of the first initialization thin-film transistor T4 and the second initialization source region S7 of the second initialization thin-film transistor T7.

[0103] One end of the driving semiconductor layer A1 of the driving thin-film transistor T1 is connected to the switching semiconductor layer A2 and the operation control semiconductor layer A5, and the other end of the driving semiconductor layer A1 is connected to the compensation semiconductor layer A3 and the emission control semiconductor layer A6. Therefore, the driving source region S1 is connected to the switching drain region D2 and the operation control drain region D5, and the driving drain region D1 is connected to the compensation source region S3 and the emission control source region S6.

[0104] The lower electrode Cst1 of the storage capacitor Cst is connected to the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 via node connection line 135. Node connection line 135 is disposed in the same layer as the current scan line 131 (see [link]). Figure 4D One end of the node connection line 135 is connected to the lower electrode Cst1 via a first node contact hole CNT1 defined in the second gate insulating layer 113 and the interlayer insulating layer 114. Here, the first node contact hole CNT1 is arranged in the storage opening SOP defined by the upper electrode Cst2. Since the size of the storage opening SOP is larger than the size of the first node contact hole CNT1, the first node contact hole CNT1 can contact the lower electrode Cst1 without contacting the upper electrode Cst2.

[0105] The other end of the node connection line 135 is connected to the compensation drain region D3 and the first initialization drain region D4 through the second node contact hole CNT2 defined in the first gate insulation layer 112, the second gate insulation layer 113 and the interlayer insulation layer 114.

[0106] The upper electrode Cst2 of the storage capacitor Cst is connected to the drive voltage line 152 through a contact hole defined in the interlayer insulating layer 114 and the via layer 115, and receives the drive voltage ELVDD from the drive voltage line 152.

[0107] Additionally, the switching thin-film transistor T2 is used as a switching device for selecting the pixel PX for emitting light. The switching gate electrode G2 is connected via a contact hole to the current scan line 131, which is disposed on a different layer than the layer on which the switching gate electrode G2 is disposed. The switching source region S2 is connected via a contact hole to the data line 151. The switching drain region D2 is connected to the driving thin-film transistor T1 and the operation control thin-film transistor T5.

[0108] The emission control drain region D6 of the emission control thin film transistor T6 can be directly connected to the pixel electrode 210 of the organic light-emitting device OLED through a via defined in the via layer 115 and the planarization layer 116.

[0109] The display device according to this exemplary embodiment includes a shielding conductive layer 141 for reducing parasitic capacitance. The shielding conductive layer 141 can be accessed through a third contact hole CNT3 (see...). Figure 5 The first gate electrode layer 123 extends to connect to the current scan line 131. In other words, it can be understood that the shielding conductive layer 141 is integrally formed with the first gate electrode layer 123.

[0110] The first gate electrode layer 123 may include the compensation gate electrode G3 of the compensation thin-film transistor T3 and the switching gate electrode G2 of the switching thin-film transistor T2. A shielding conductive layer 141 may be disposed between the switching gate electrode G2 and the compensation gate electrode G3. In other words, since the first gate electrode layer 123 is connected to the current scan line 131 through the third contact hole CNT3, the scan signal Sn (see [link to relevant documentation]) is a pulse signal. Figure 3 It can be provided to the shielding conductive layer 141.

[0111] Refer to the schematic diagram and the cross-sectional view of the outer periphery of the shielding conductive layer 141, respectively. Figure 5 and Figure 6 In the plan view, a shielding conductive layer 141 is arranged between the data line 151 and the node connection line 135. The shielding conductive layer 141, the data line 151, and the node connection line 135 all extend in the second direction.

[0112] The shielding conductive layer 141 can be disposed on the first gate insulating layer 112 and in the same layer as the gate electrodes G1 to G7. The shielding conductive layer 141 can be disposed between the switching thin-film transistor T2 and the compensation thin-film transistor T3. In addition, the data line 151 can be connected to the switching semiconductor layer A2 of the switching thin-film transistor T2 through the first connection electrode 134.

[0113] When the display device does not include the shielding conductive layer 141, parasitic capacitance may be generated between the data line 151 and the node connection line 135, and therefore, the characteristics of driving the thin film transistor T1, etc., may change depending on the signal provided by the data line 151.

[0114] However, since the display device according to this exemplary embodiment includes a shielding conductive layer 141, the generation of parasitic capacitance can be effectively prevented. Furthermore, since the shielding conductive layer 141 receives and is linked to the scan signal Sn as a pulse signal, the coupling effects caused by the signal from the data line 151 can be minimized.

[0115] In the following, the configuration included in the display device of the exemplary embodiments will be described in accordance with the stacking order. Figure 7 It shows that an organic light-emitting device (OLED) is arranged in it. Figure 4A The configuration on the sections taken along lines II-II' and III-III'.

[0116] The substrate 110 may comprise glass, ceramic, metallic, or flexible or bendable materials. When the substrate 110 is flexible or bendable, it may comprise, for example, polymeric resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 110 may have a single-layer or multi-layer structure comprising the materials mentioned above, and in the case of a multi-layer structure, the substrate 110 may further comprise an inorganic layer. In some exemplary embodiments, the substrate 110 may have a structure comprising organic / inorganic / organic materials.

[0117] The buffer layer 111 on the substrate 110 can reduce or prevent the penetration of foreign matter, moisture or external air from the bottom of the substrate 110 and provide a planarized surface on the substrate 110. For example, the buffer layer 111 may include inorganic materials such as oxides or nitrides, organic materials or organic-inorganic composite materials, and may include a single-layer or multi-layer structure comprising inorganic and organic materials.

[0118] A barrier layer (not shown) may be further included between the substrate 110 and the buffer layer 111. The barrier layer can prevent or minimize the penetration of impurities from the substrate 110 into the semiconductor layers A1 to A7. The barrier layer may include inorganic materials such as oxides or nitrides, organic materials, or organic-inorganic composite materials, and may include a single-layer or multi-layer structure comprising inorganic and organic materials.

[0119] Semiconductor layers A1, A3, and A6 may be disposed on buffer layer 111. Semiconductor layers A1, A3, and A6 may comprise amorphous silicon or polycrystalline silicon. In another exemplary embodiment, semiconductor layer A1 may comprise an oxide of at least one of indium (In), gallium (Ga), tin (Sn), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In some exemplary embodiments, semiconductor layer A1 may comprise a Zn oxide-based material, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In another exemplary embodiment, semiconductor layer A1 may comprise an In-Ga-Zn-O (“IGZO”) semiconductor, an In-Sn-Zn-O (“ITZO”) semiconductor, or an In-Ga-Sn-Zn-O (“IGTZO”) semiconductor comprising a metal such as In, Ga, or Sn in ZnO. Semiconductor layers A1, A3, and A6 may include a channel region and source and drain regions disposed on both sides of the channel region. Each of semiconductor layers A1, A3, and A6 may include a single layer or multiple layers.

[0120] On semiconductor layers A1, A3, and A6, gate electrodes G1, G3, and G6 are arranged to at least partially overlap with semiconductor layers A1, A3, and A6, respectively, while a first gate insulating layer 112 lies between semiconductor layers A1, A3, and A6 and gate electrodes G1, G3, and G6. Gate electrodes G1, G3, and G6 may comprise Mo, Al, Cu, Ti, etc., and may comprise a single layer or multiple layers. For example, gate electrodes G1, G3, and G6 may each comprise a single Mo layer.

[0121] The first gate insulating layer 112 may include silicon oxide (SiO2) or silicon nitride (SiN). x Silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), etc.

[0122] The second gate insulating layer 113 can be provided to cover the gate electrodes G1, G3, and G6. The second gate insulating layer 113 may include SiO2 or SiN. x , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO2, etc.

[0123] The lower electrode Cst1 of the storage capacitor Cst can overlap with the driving thin-film transistor T1. For example, the driving gate electrode G1 of the driving thin-film transistor T1 can be used as the lower electrode Cst1 of the storage capacitor Cst.

[0124] The upper electrode Cst2 of the storage capacitor Cst overlaps with the lower electrode Cst1, and the second gate insulating layer 113 is located between the upper electrode Cst2 and the lower electrode Cst1. In this case, the second gate insulating layer 113 can serve as the dielectric layer of the storage capacitor Cst. The upper electrode Cst2 can include a conductive material comprising Mo, Al, Cu, Ti, etc., and can include multiple layers or a single layer comprising the aforementioned materials.

[0125] Interlayer insulating layer 114 can be provided to cover the upper electrode Cst2 of the storage capacitor Cst. Interlayer insulating layer 114 may include SiO2, SiN... x , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO2, etc.

[0126] Node connection lines 135 are disposed on interlayer insulating layer 114. Node connection lines 135 may include conductive materials comprising aluminum (Al), copper (Cu), titanium (Ti), etc., and may comprise multiple layers or a single layer comprising the aforementioned materials. For example, node connection lines 135 may have a Ti / Al / Ti multilayer structure.

[0127] One end of the node connection line 135 can be connected to the driving gate electrode G1 through the first node contact hole CNT1 penetrating the interlayer insulating layer 114 and the second gate insulating layer 113, and the other end of the node connection line 135 can be connected to the compensation semiconductor layer A3 through the second node contact hole CNT2 penetrating the interlayer insulating layer 114, the second gate insulating layer 113 and the first gate insulating layer 112.

[0128] The via layer 115 can be on the node connection line 135 and the second connection electrode 136, and the data line 151 and the drive voltage line 152 can be on the via layer 115.

[0129] For example, the through-hole layer 115 may include common commercial polymers such as benzocyclobutene (“BCB”), polyimide, hexamethyldisilane (“HMDSO”), polymethyl methacrylate (“PMMA”), and polystyrene (“PS”), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, blends thereof, etc. The through-hole layer 115 may include inorganic materials. For example, the through-hole layer 115 may include SiO2, SiN... x Materials such as SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2 can be used. When the via layer 115 includes inorganic materials, chemical planarization polishing can be performed. Alternatively, the via layer 115 can include both organic and inorganic materials.

[0130] Data line 151 and drive voltage line 152 are disposed on via layer 115. Data line 151 and drive voltage line 152 may each comprise a conductive material comprising Al, Cu, Ti, etc., and may comprise multiple layers or a single layer comprising the aforementioned materials.

[0131] A planarization layer 116 is located on the data line 151 and the drive voltage line 152. The planarization layer 116 may comprise an organic material such as acrylic, BCB, polyimide (“PI”), or HMDSO. Alternatively, the planarization layer 116 may comprise an inorganic material. The planarization layer 116 typically planarizes the upper portion of the protective layer covering the thin-film transistors T1 through T7. The planarization layer 116 may comprise a single layer or multiple layers.

[0132] An organic light-emitting device (OLED) including a pixel electrode 210, a counter electrode 230, and an intermediate layer 220 located between the pixel electrode 210 and the counter electrode 230 and including an emission layer can be arranged on a planarization layer 116.

[0133] The pixel electrode 210 is connected to the second connection electrode 136 through a via, penetrates the planarization layer 116 and the via layer 115, and is connected to the emission control drain region D6 of the emission control thin film transistor T6 through the second connection electrode 136.

[0134] A pixel defining layer 117 can be disposed on a planarization layer 116. The pixel defining layer 117 defines pixels PX through openings corresponding to each pixel PX. That is, the openings expose at least the central portion of the pixel electrode 210. The pixel defining layer 117 also prevents the generation of electric arcs or the like at the edges of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210. The pixel defining layer 117 may include organic materials, such as PI, HMDSO, etc.

[0135] The intermediate layer 220 of an organic light-emitting OLED can include low molecular weight materials or polymer materials. For example, when the intermediate layer 220 includes low molecular weight materials, the hole injection layer (“HIL”), emitter layer (“EML”), electron transport layer (“ETL”), electron injection layer (“EIL”), etc., can have a single-layer structure or a multi-layer stacked structure, and the low molecular weight materials can include various organic materials such as copper phthalocyanine (“CuPc”), N,N'-bis(naphthyl-1-yl)-N,N'-diphenyl-benzidine (“NPB”), and tri-8-hydroxyquinoline aluminum (“Alq3”). This layer can be formed by a vacuum deposition method.

[0136] When the interlayer 220 comprises a polymer material, it can typically have a structure including an HTL and an EML. In this case, for example, the HTL may comprise poly(3,4-ethylenedioxythiophene) (“PEDOT”), and the EML may comprise polymer materials such as polyphenylacetylene (“PPV”) and polyfluorene. The interlayer 220 can be formed using screen printing, inkjet printing, laser-induced thermal imaging (“LITI”), and the like.

[0137] However, the intermediate layer 220 is not limited to this and can have various structures. In addition, the intermediate layer 220 may include a layer integrally formed on the plurality of pixel electrodes 210, and may also include a layer patterned to correspond to each of the plurality of pixel electrodes 210.

[0138] The counter electrode 230 can be arranged in the display area DA to cover the display area DA. That is, the counter electrode 230 can be integrally formed above multiple organic light-emitting devices (OLEDs) to correspond to multiple pixel electrodes 210.

[0139] Since OLEDs (Organic Light Emitting Devices) can be easily damaged by external moisture or oxygen, a thin-film encapsulation layer 300 can cover the OLED for protection. The thin-film encapsulation layer 300 can cover the display area DA and extend to the outer region of the display area DA. The thin-film encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0140] For example, the first inorganic encapsulation layer 310 may cover the counter electrode 230 and includes ceramics, metal oxides, metal nitrides, metal carbides, metal oxide nitrides, indium oxide (In₂O₃), tin oxide (SnO₂), indium tin oxide (“ITO”), silicon oxide, silicon nitride, and / or silicon oxynitride, etc. Other layers, such as a capping layer (not shown), may be located between the first inorganic encapsulation layer 310 and the counter electrode 230 as needed. When the first inorganic encapsulation layer 310 is provided along the structure located beneath it, the upper surface of the first inorganic encapsulation layer 310 is not flat.

[0141] The organic encapsulation layer 320 covers the first inorganic encapsulation layer 310, and unlike the first inorganic encapsulation layer 310, the organic encapsulation layer 320 may have an approximately flat upper surface. More specifically, the upper surface of the organic encapsulation layer 320 may be approximately flat in the portion corresponding to the display area DA. For example, the organic encapsulation layer 320 may comprise at least one material selected from the group consisting of acrylic, methacrylic acid, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisilane.

[0142] For example, the second inorganic encapsulation layer 330 may cover the organic encapsulation layer 320 and includes ceramics, metal oxides, metal nitrides, metal carbides, metal oxynitrides, In2O3, SnO2, ITO, silicon oxide, silicon nitride and / or silicon oxynitride, etc.

[0143] As described above, the thin-film encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330. By using this multilayer structure, even if cracks occur in the thin-film encapsulation layer 300, the connection of such cracks between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320, or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330, can be prevented. In doing so, the formation of pathways for external moisture or oxygen to permeate into the display area DA can be prevented or minimized.

[0144] Although not shown, spacers for preventing mask embossing can be further provided on pixel defining layer 117, and various functional layers such as polarizing layer, black matrix, color filter and / or touch screen including touch electrodes for reducing external light reflection can be provided on thin film encapsulation layer 300.

[0145] Figure 8 This is an equivalent circuit diagram of a pixel according to another exemplary embodiment, and Figure 9 It is a schematic illustration including Figure 8 A plan view showing the locations of multiple thin-film transistors and capacitors in the pixel circuitry. Figure 8 and Figure 9 In, with Figure 3 and Figure 4A The same reference numerals in the attached figures refer to the same reference numerals as those in the attached figures. Figure 3 and Figure 4A The components are the same as the components, and therefore repeated descriptions will be omitted.

[0146] refer to Figure 8 The pixel PX includes signal lines 121, 131, 132 and 151, multiple thin-film transistors T1, T2, T3, T4, T5, T6 and T7 connected to signal lines 121, 131, 132 and 151, capacitor Cst, initialization voltage line 103, driving voltage line 152 and organic light-emitting device OLED.

[0147] In this exemplary embodiment, a shielding conductive layer 142 connected to the previous scan line 132 may be disposed between portion A, where the data line 151 is disposed, and portion B, where the driving thin-film transistor T1 is connected to the compensation thin-film transistor T3. The shielding conductive layer 142 is connected to the previous scan line 132 and can receive the previous scan signal Sn-1.

[0148] The shielding conductive layer 142 can be used to prevent parasitic capacitance that may occur between part A and part B.

[0149] refer to Figure 9 The shielding conductive layer 142 extends in the second direction, and in the top plan view, the shielding conductive layer 142 is arranged between the data line 151 and the node connection line 135. Since the node connection line 135 overlaps with the drive voltage line 152, the shielding conductive layer 142 can be understood as being arranged between the data line 151 and the drive voltage line 152.

[0150] In this exemplary embodiment, the shielding conductive layer 142 can extend from the second gate electrode layer 125, which is connected to the previous scan line 132 through the fourth contact hole CNT4. The second gate electrode layer 125 can be the first initialization gate electrode G4 of the first initialization thin-film transistor T4. The first initialization gate electrode G4 can be bent twice and overlapped twice with the first initialization semiconductor layer A4. For example, the first initialization gate electrode G4 can be in the form of the letter "C". The first initialization gate electrode G4 can be a dual-gate electrode, and the first initialization thin-film transistor T4 can be a dual thin-film transistor.

[0151] A conductive shielding layer 142 can be disposed between the data line 151 and the node connection line 135 to prevent the occurrence of parasitic capacitance. Additionally, the conductive shielding layer 142 receives and links to the previous scan signal Sn-1, which is a pulse signal. Therefore, the coupling effects caused by the signal from the data line 151 can be minimized.

[0152] As described above, in an exemplary embodiment, a shielding conductive layer 141 or 142 disposed in the same layer as the gate electrodes G1 to G7 is arranged between the node connection line 135 connecting the driving thin-film transistor T1 and the compensation thin-film transistor T3 and the data line 151. Therefore, crosstalk caused by parasitic capacitance can be reduced.

[0153] In addition, since the scan line 131 has a lower resistance than the gate electrodes G1 to G7 of the thin-film transistors T1 to T7, RC delay can be prevented.

[0154] It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each exemplary embodiment should typically be considered as other similar features or aspects that can be used in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications of form and detail may be made in one or more embodiments without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: substrate; A driving thin-film transistor is disposed on the substrate and includes a driving semiconductor layer and a driving gate electrode; A first scan line is disposed on the substrate and extends in a first direction; The data cable extends in a second direction that intersects the first direction; The node connection lines are arranged in the same layer as the first scan lines; A shielding conductive layer is disposed between the data line and the node connection line, and is disposed in the same layer as the driving gate electrode; as well as The first gate electrode layer is connected to the first scan line through the third contact hole. One end of the node connection line is connected to the driving gate electrode through the first node contact hole, and The shielding conductive layer extends from the first gate electrode layer.

2. The display device according to claim 1, wherein, The shielding conductive layer and the node connection line extend in the second direction.

3. The display device according to claim 1, wherein, The first gate electrode layer includes a compensation gate electrode for a compensation thin-film transistor and a switching gate electrode for a switching thin-film transistor, and The shielding conductive layer is disposed between the compensation gate electrode and the switching gate electrode.

4. The display device according to claim 1, further comprising: A driving voltage line extends in the second direction and is arranged in the same layer as the data line, and The shielding conductive layer is disposed between the data line and the drive voltage line.

5. The display device according to claim 1, further comprising: A compensation thin-film transistor is connected to the first scan line and includes a compensation semiconductor layer and a compensation gate electrode. The other end of the node connection line is connected to the compensation semiconductor layer through the second node contact hole.

6. The display device according to claim 1, wherein, The resistance value of the first scan line is less than the resistance value of the driving gate electrode.

7. The display device according to claim 1, further comprising: The storage capacitor includes a drive gate electrode as a lower electrode and an upper electrode that overlaps with the lower electrode and defines a storage opening with a closed shape. The first node contact hole is arranged in the storage opening.

8. The display device according to claim 7, wherein, The size of the storage opening is larger than the size of the first node contact hole.

9. The display device according to claim 1, further comprising: An emission control thin-film transistor is disposed on the substrate and includes an emission control semiconductor layer and an emission control gate electrode; as well as The transmit control line delivers the transmit control signal to the transmit control gate electrode. The emission control gate electrode is provided as part of the emission control line.

10. A display device, comprising: substrate; A driving thin-film transistor is disposed on the substrate and includes a driving semiconductor layer and a driving gate electrode; A first scan line is disposed on the substrate and extends in a first direction; The data cable extends in a second direction that intersects the first direction; The node connection lines are arranged in the same layer as the first scan lines; A shielding conductive layer is disposed between the data line and the node connection line, and is disposed in the same layer as the driving gate electrode; The second scan line is separate from the first scan line and extends in the first direction; as well as The second gate electrode layer is connected to the second scan line through the fourth contact hole. One end of the node connection line is connected to the driving gate electrode through the first node contact hole, and The shielding conductive layer extends from the second gate electrode layer.

11. The display device according to claim 10, wherein, The second gate electrode layer is part of the first initialization gate electrode of the first initialization thin-film transistor.

12. The display device according to claim 11, wherein, The first initialization gate electrode has a curved shape.

13. The display device according to claim 10, wherein, The shielding conductive layer extends in the second direction.

14. A display device, comprising: substrate; A driving thin-film transistor is disposed on the substrate and includes a driving gate electrode and a driving semiconductor layer, wherein a first gate insulating layer is disposed between the driving gate electrode and the driving semiconductor layer; A shielding conductive layer is arranged in the same layer as the driving gate electrode; A second gate insulating layer and an interlayer insulating layer are disposed on the shielding conductive layer; A node connection line is arranged on the interlayer insulating layer and connected to the drive gate electrode through a first node contact hole that penetrates the interlayer insulating layer and the second gate insulating layer; The first scan line is arranged in the same layer as the node connection line and extends in a first direction; A via layer covers the first scan line and the node connection line; as well as The data line is arranged on the via layer and extends in a second direction intersecting the first direction. The shielding conductive layer extends in the second direction between the data line and the node connection line.

15. The display device according to claim 14, further comprising: The first gate electrode layer is connected to the first scan line through the third contact hole, and The shielding conductive layer extends from the first gate electrode layer.

16. The display device according to claim 14, further comprising: The second scan line extends in the first direction; as well as The second gate electrode layer is connected to the second scan line through the fourth contact hole, and The shielding conductive layer extends from the second gate electrode layer.

17. The display device according to claim 14, wherein, The driving semiconductor layer is curved.

18. The display device according to claim 14, further comprising: A driving voltage line extends in the second direction and is arranged in the same layer as the data line, and The node connection line overlaps with the driving voltage line.

19. The display device according to claim 14, wherein, The shielding conductive layer receives the scanning signal.

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