Method, apparatus, electronic device, and computer storage medium for supporting communication between multiple chips

Abstract

Embodiments of the present disclosure relate to a method, apparatus, electronic device, and computer-readable storage medium for determining a connection relationship between multiple chips. The method may include determining identity information of multiple chips managed by a host, where the multiple chips are connected through their respective inter-chip communication interfaces for inter-chip communication. The method may further include causing one or more of the multiple chips to obtain identity information of other chips connected to the inter-chip communication interfaces of the one or more chips. The method may further include reading the identity information of the other chips via a management interface of the one or more chips for communicating with the host to determine the connection relationship between the multiple chips. The technical solution of the present disclosure determines the chips connected thereto through the inter-chip communication interfaces of the respective chips, so as to create and maintain a physical connection matrix of the chip network on the host side, thereby facilitating fault detection of chip network connections and dynamic configuration of chip network topologies.

Description

Technical Field

[0001] Embodiments of the present disclosure mainly relate to the field of computers, and more specifically, to methods, devices, electronic devices, computer-readable storage media, and computer program products for supporting communication between multiple chips. Background Art

[0002] With the development of computer technology, the demand for computing power in artificial intelligence applications is increasing. However, due to limitations such as process and power consumption, the computing power of a single chip (such as an artificial intelligence chip, GPU, etc.) can no longer meet the demand for processing speed. Therefore, it is necessary to connect multiple chips to form a chip network to meet the needs of artificial intelligence applications. Therefore, there is a need to optimize the communication between chips (i.e., inter-chip communication) to achieve high bandwidth and low latency.

[0003] In addition, different operators and algorithms of artificial intelligence applications also have different bandwidth and latency requirements. Different network topologies have different bandwidths and latencies. How to support different network topologies, especially dynamic topology changes, is another challenge for inter-chip communication. Summary of the Invention

[0004] According to an exemplary embodiment of the present disclosure, a solution for supporting communication between multiple chips is provided.

[0005] In a first aspect of the present disclosure, a method for supporting communication between multiple chips is provided. The method may include determining identity information of a plurality of chips managed by a host, the plurality of chips being connected through their respective inter-chip communication interfaces for inter-chip communication. The method may further include causing one or more of the plurality of chips to obtain identity information of other chips connected to the inter-chip communication interfaces of the one or more chips. The method may further include obtaining identity information of other chips via a management interface of one or more chips for communicating with the host to determine the connection relationship between the plurality of chips.

[0006] In a second aspect of the present disclosure, a device for supporting communication between multiple chips is provided, including: an identity information determination module configured to determine identity information of a plurality of chips managed by a host, the plurality of chips being connected through their respective inter-chip communication interfaces for inter-chip communication; a chip instruction module configured to cause one or more of the plurality of chips to obtain identity information of other chips connected to the inter-chip communication interfaces of the one or more chips; and a connection relationship determination module configured to obtain identity information of other chips via a management interface of one or more chips for communicating with the host to determine the connection relationship between the plurality of chips.

[0007] In a third aspect of the present disclosure, a device is provided, including one or more processors; and a storage device for storing one or more programs, which when executed by the one or more processors, cause the one or more processors to implement the method according to the first aspect of the present disclosure.

[0008] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, having stored thereon a computer program, which when executed by a processor, implements the method according to the first aspect of the present disclosure.

[0009] In a fifth aspect of the present disclosure, a computer program product is provided, including a computer program, which when executed by a processor, implements the method according to the first aspect of the present disclosure.

[0010] It should be understood that the content described in the Summary of the Invention section is not intended to limit the key or important features of the embodiments of the present disclosure, nor to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where:

[0012] Figure 1A A schematic diagram showing the interface configuration of an example chip according to multiple embodiments of the present disclosure;

[0013] Figure 1B A schematic diagram showing an example chip network in which multiple embodiments of the present disclosure can be implemented;

[0014] Figure 2 A flowchart showing a process for supporting communication between multiple chips according to an embodiment of the present disclosure;

[0015] Figure 3 A flowchart showing a process for obtaining identity information of other connected chips according to an embodiment of the present disclosure;

[0016] Figure 4 A schematic block diagram showing a device for supporting communication between multiple chips according to an embodiment of the present disclosure; and

[0017] Figure 5 A block diagram showing a computing device capable of implementing multiple embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only and are not intended to limit the scope of protection of the present disclosure.

[0019] In the description of the embodiments of the present disclosure, the term "including" and its like shall be understood as an open inclusion, that is, "including but not limited to". The term "based on" shall be understood as "at least partially based on". The term "one embodiment" or "the embodiment" shall be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0020] As mentioned above, there is an urgent need for a method to support communication between multiple chips to quickly, efficiently and low-costly obtain the connection relationship of the chip network, so as to support the dynamic change of the topology structure of the chip network, and then change the topology structure according to requirements to increase bandwidth and reduce latency. The traditional inter-chip communication technology in the chip network is mainly used to solve the fixed topology structure of the chip network. Therefore, the topology structure of the chip network is not flexible and often faces the problem of insufficient bandwidth.

[0021] According to an embodiment of the present disclosure, a solution to support communication between multiple chips is proposed. In this solution, a host such as a central processing unit (CPU) can enumerate multiple chips it manages, such as artificial intelligence chips, and number these chips. Then, the CPU commands each chip to perform a connection awareness operation respectively. As an example, the chip can read the status information of its respective ports. When the status information is active, it configures a predetermined address range, sends test data to a specific address within this address range, and waits for the returned response data. After receiving the response data, it obtains the numbers of other chips communicating with this port from the response data. The CPU aggregates the connection information collected by each chip, so that the physical connection information of any chip network can be obtained. After obtaining the physical connection information of the chip network, the logical connection relationship between each chip can be dynamically configured according to the service requirements, so as to construct the required topology structure.

[0022] To more elaborately describe the topology structure of the chip network and its construction process in multiple embodiments of the present disclosure, it is first necessary to briefly describe the chip network. Figure 1A A schematic diagram showing the interface configuration of an exemplary chip 100 according to multiple embodiments of the present disclosure is shown. As Figure 1AAs shown, chip 100 includes multiple interfaces. For example, management interface 110 and inter-chip communication interfaces C0, C1, C2, and C3. Management interface 110 is used to communicate with a host such as a CPU that manages chip 100, and is typically used to receive configuration information from the host and send connection information of chip 100. As an example, management interface 110 can be a PCIe interface. In addition, inter-chip communication interfaces C0, C1, C2, and C3 are all used to perform inter-chip communication with other chips under the management of the host. As an example, inter-chip communication interfaces C0, C1, C2, and C3 can be CCIX (Cache Coherent Interconnect eXtension) interfaces.

[0023] A so-called chip network refers to a network formed by direct physical connections between multiple chips through inter-chip communication interfaces. Figure 1B The figure shows a schematic diagram of an example chip network 100' in which multiple embodiments of the present disclosure can be implemented. As Figure 1B shown, each box represents a chip. Each chip has a unique chip identity information in chip network 100'. For example, the reference numbers 101, 102, 103, 104, 105, 106, 107, and 108 of each chip can be used to represent the identity information of each chip. It should be understood that the specific examples of the identity information are all illustrative and not for the purpose of limitation, and the identity information of each chip is not limited to being represented by numbers.

[0024] Any chip in chip network 100' can have a direct physical connection with one or more other chips. It should be noted that chip network 100' can be composed of multiple chips integrated on a circuit board, or can be composed of chips in multiple devices controlled by chips connected through data transmission lines. Therefore, the pins of two chips integrated on a circuit board (such as Figure 1A the inter-chip communication interfaces C0, C1, C2, and C3 therein) are directly connected, or the interfaces of the chips in two devices (such as Figure 1A the inter-chip communication interfaces C0, C1, C2, and C3 therein) are connected through data transmission lines. That is to say, the connection between two chips can be understood as the two chips being interconnected through the corresponding interfaces. For example, when chip 101 transmits information to chip 102, specifically, chip 101 sends information to chip 102 through its own interface C1 connected to chip 102.

[0025] In addition, it should be understood that in order to focus on describing the details of inter-chip communication technology, the present disclosure is in Figure 1BThe communication process between the management interface 110 of each chip and a host such as a CPU is not shown. As an example, chips 101, 102, 103, and 104 may communicate with a PCIe switch module (not shown) via a management interface 110 such as a PCIe interface, and then the PCIe switch module communicates with the host. Similarly, chips 105, 106, 107, and 108 may also communicate with another PCIe switch module (not shown) via a management interface 110 such as a PCIe interface, and then the other PCIe switch module communicates with the host. Alternatively or additionally, chips 101, 102, 103, 104, 105, 106, 107, and 108 may also directly communicate with the host through their respective management interfaces 110.

[0026] The chips 100 and the chip network 100' in the technical solutions described above are only for illustration and do not limit the present invention. It should be understood that the configuration of the chips, especially the configuration of the chip interfaces, can be diverse, so the topology interfaces of the chip network can be more complex. Therefore, various modifications can be made to the chips 100 and the chip network 100' without departing from the protection scope of the present disclosure. To more clearly explain the principle of the above solutions, the following will refer to Figure 2 to describe in more detail the process of determining the connection relationship between multiple chips.

[0027] Figure 2 FIG. shows a flowchart of a process 200 supporting communication between multiple chips according to an embodiment of the present disclosure. For the convenience of discussion, the process 200 will be described in conjunction with Figure 1A and Figure 1B to describe the process 200.

[0028] At 210, the identity information of multiple chips managed by the host can be determined, and the multiple chips are connected through their respective inter-chip communication interfaces for inter-chip communication. As an example, the host can enumerate all the chips it manages to determine the identity information of these chips. For example, Figure 1B chips 101, 102, 103, 104, 105, 106, 107, and 108 in, and these chips can be connected through their respective inter-chip communication interfaces C0, C1, C2, and C3 to form a chip network 100'.

[0029] At 220, sensing instructions can be sent to each chip so that one or more of these chips can obtain the identity information of other chips connected to the inter-chip communication interface of the one or more chips. As an example, the host can send instructions to all the chips it manages so that all the chips perform the operation of obtaining the identity information of other chips connected to them. Alternatively or additionally, the host can also send the above sensing instructions only to the chips in the working state it manages. Due to the particularity of the chip network such as the artificial intelligence chip, the connection relationship between each chip is usually extremely complex. By each chip starting from its inter-chip communication interface and sending test signals and receiving response signals, the detailed connection relationship of the chip network can be efficiently obtained. And since this sensing operation is initiated from the inter-chip communication interface of each chip, there is no need to detect the specific interface of the chip connected to this inter-chip communication interface (because this interface will also perform the same sensing operation).

[0030] In some embodiments, a more complete and automated information transmission process can be adopted to obtain the identity information of other connected chips. Figure 3 FIG. shows a flowchart of a process 300 for obtaining the identity information of other connected chips according to an embodiment of the present disclosure.

[0031] At 310, one or more chips can obtain the status information of their inter-chip communication interfaces. As an example, the micro control unit (MCU) in each chip can read the status of the inter-chip communication interfaces C0, C1, C2, and C3.

[0032] At 320, it can be determined whether the status information is active. It should be noted that if the inter-chip communication interface is in the active state, it indicates that this inter-chip communication interface has a physical connection with the inter-chip communication interface of other chips; while if the inter-chip communication interface is in the inactive state, it indicates that this inter-chip communication interface does not have a physical connection with the inter-chip communication interface of other chips. If this inter-chip communication interface is in the inactive state, no operation is performed on this interface. If this inter-chip communication interface is in the active state, proceed to 330.

[0033] At 330, the inter-chip communication interface sends test data to other chips connected to this inter-chip communication interface. In some embodiments, a predetermined address range (for example, the BAR0 address) can be configured for this inter-chip communication interface first, and then test data is sent to the addresses of other chips within this predetermined address range. As an example, a Hello data packet can be sent to this address, that is, a write storage instruction is sent first, and the data written is specific data, for example, 0xa1a1, and then a read storage instruction is sent to this address.

[0034] At 340, since a read memory instruction is sent to a specific address, the chip at this time will wait for a reply and then receive the response data of the above test data. As an example, the response data is usually an ACK packet, and the identity information of other chips with a connection relationship is included in the response data.

[0035] After describing in detail the process 300 in which a chip obtains the identity information of other chips connected thereto, return to Figure 2 , and continue to discuss the process 200 of determining the connection relationship between multiple chips. After instructing each chip to obtain the identity information of other chips connected thereto, the process 200 proceeds to 230.

[0036] At 230, the identity information of the above other chips can be obtained via the management interface 110 for communicating with the host of the one or more chips to determine the connection relationship between the multiple chips. As an example, after each chip completes the connection sensing operation, it can send an interrupt message to the host to inform the host that the sensing operation is completed. Then, the host can read the connection information obtained by each chip through the management interface 110 such as PCIe of each chip. Furthermore, the host can determine the physical connection relationship between the chips it manages. In this way, a host such as a CPU can determine the physical connection relationship between the chips it manages.

[0037] In some embodiments, the host can store the determined connection relationship between the chips in a connection matrix. As an example, as Figure 1B shown, through the connection sensing operation, chip 101 can determine that its inter-chip communication interface C0 is connected to chip 106, its inter-chip communication interface C1 is connected to chip 102, its inter-chip communication interface C2 is connected to chip 104, and its inter-chip communication interface C3 is connected to chip 103. Similarly, through the connection sensing operation, chip 102 can determine that its inter-chip communication interface C0 is connected to chip 104, its inter-chip communication interface C1 is connected to chip 105, its inter-chip communication interface C2 is connected to chip 103, and its inter-chip communication interface C3 is connected to chip 101. Through the connection sensing operation, chip 103 can determine that its inter-chip communication interface C0 is connected to chip 102, its inter-chip communication interface C1 is connected to chip 108, its inter-chip communication interface C2 is connected to chip 101, and its inter-chip communication interface C3 is connected to chip 104. And so on, a connection matrix as shown in Table 1 can be constructed.

[0038]

[0039] Table 1

[0040] In Table 1, the top row is the numbers of the four inter-chip communication interfaces of each chip, the leftmost column is the identity information (ID) of each chip, and the other data are the identity information of the corresponding chips connected to the respective interfaces of each chip. By constructing a connection matrix such as Table 1, the host can easily learn the physical connection relationships of the chips. Alternatively or additionally, the connection matrix further includes at least one of the status information and bandwidth information of the respective inter-chip communication interfaces of these chips. A host such as a CPU can, by determining and maintaining a connection matrix containing various information, more comprehensively master the connection conditions among the chips it manages, thus facilitating subsequent dynamic configuration of the chip network topology.

[0041] In some embodiments, connection faults can also be detected by the inter-chip communication interfaces of the one or more chips. As an example, when the detected connection fault is repairable, the connection fault is repaired and the result of the repair is reported. When the detected connection fault is not repairable, the traffic transmitted via the inter-chip communication interfaces of the one or more chips is switched to another inter-chip communication interface, and the connection fault is reported. In this way, even if connection faults occur among the chips, the chip network can continue to operate by repairing or directly transferring traffic, and it can facilitate the host to update the connection matrix it maintains by reporting to the host.

[0042] In some embodiments, the connection relationships of multiple chips can also be enumerated according to the determined number of chips, and these chips can be configured according to the user-specified connection relationship among the enumerated connection relationships. As an example, all possible logical connection modes that can be realized can be enumerated according to the physical connection relationships among the chips recorded in the above connection matrix. For example, according to the physical connection relationships in Table 1 above, at least two logical connection modes of the chips can be enumerated: 101 <—> 104 <—> 103 <—> 102 <—> 105 <—> 108 <—> 107 <—> 106 <—> 101; and 101 <—> 102 <—> 104 <—> 107 <—> 105 <—> 106 <—> 108 <—> 103 <—> 101. Then, a logical connection mode can be selected from them to execute specific computing services.

[0043] In the above embodiments of the present disclosure, the host can be a central processing unit CPU, and the chip can be a system-on-chip SoC.

[0044] Compared with the traditional technology, the solution of the present disclosure determines the chips connected thereto through the inter-chip communication interfaces of each chip, so that a physical connection matrix of the chip network can be created and maintained on the CPU side. This can facilitate the fault detection of the chip network connection and the dynamic configuration of the chip network topology. In addition, since the flexible configuration of the logical connection topology of each chip can be achieved, the number of chips and the connection manner in the topology structure can be changed according to requirements, thereby improving the bandwidth of the chip network and reducing the latency.

[0045] The above discusses examples of the connection relationships between chips in some example scenarios. However, it should be understood that the description of these scenarios is only for explaining the embodiments of the present disclosure by way of example. Depending on actual needs, different strategies can also be selected in different or similar scenarios. It should also be noted that the technical solution of the present disclosure is not limited in essence to the field of artificial intelligence chips, and the technical solution of the present disclosure can also have the various advantages mentioned above when applied to other fields that require multi-chip collaborative processing of a large amount of services.

[0046] Figure 4 FIG. shows a schematic block diagram of a device 400 supporting communication between multiple chips according to an embodiment of the present disclosure. As Figure 4 shown, the device 400 includes an identity information determination module 410 configured to determine the identity information of multiple chips managed by a host, the multiple chips being connected through their respective inter-chip communication interfaces for inter-chip communication; a chip instruction module 420 configured to cause one or more of the multiple chips to obtain the identity information of other chips connected to the inter-chip communication interfaces of the one or more chips; and a connection relationship determination module 430 configured to obtain the identity information of the other chips via a management interface 110 for communicating with the host of the one or more chips to determine the connection relationship between the multiple chips.

[0047] In some embodiments, the chip instruction module 420 may further include: a status information reading module configured to obtain the status information of the inter-chip communication interfaces of the one or more chips; a test data sending module configured to, in response to the status information being active, send test data from the inter-chip communication interfaces of the one or more chips to other chips connected to the inter-chip communication interfaces among the multiple chips; and a response data receiving module configured to receive the response data of the test data, the response data including the identity information of the other chips.

[0048] In some embodiments, the test data sending module may further include: an address range configuration module configured to configure a predetermined address range for the inter-chip communication interfaces of the one or more chips; and a sending sub-module configured to send test data to addresses within the predetermined address range of other chips.

[0049] In some embodiments, the apparatus 400 may further include: a connection relationship storage module configured to store the determined connection relationships between the multiple chips into a connection matrix, where the connection matrix may further include at least one of the following: status information of the respective inter-chip communication interfaces of the multiple chips; and bandwidth information.

[0050] In some embodiments, the apparatus 400 may further include: a first fault detection module configured to detect a connection fault by the inter-chip communication interfaces of the one or more chips; a repair module configured to repair the connection fault in response to the detected connection fault being repairable; and a repair result reporting module configured to report the result of the repair.

[0051] In some embodiments, the apparatus 400 may further include: a second fault detection module configured to detect a connection fault by the inter-chip communication interfaces of the one or more chips; a service switching module configured to switch the service transmitted via the inter-chip communication interfaces of the one or more chips to an additional inter-chip communication interface in response to the detected connection fault being unrepairable; and a connection fault reporting module configured to report the connection fault.

[0052] In some embodiments, the apparatus 400 may further include: a connection relationship enumeration module configured to enumerate the connection relationships of the multiple chips according to the number of the determined multiple chips; and a chip configuration module configured to configure the multiple chips according to the user-specified connection relationships among the enumerated connection relationships.

[0053] In some embodiments, the above host may be a central processing unit CPU, and the above multiple chips may be system-on-chip SoCs.

[0054] Figure 5 A schematic block diagram of an example device 500 that may be used to implement the embodiments of the present disclosure is shown. As shown, the device 500 includes a central processing unit (CPU) 501, which may execute various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 502 or computer program instructions loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 may also be stored. The CPU 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0055] Multiple components in device 500 are connected to I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, an optical disc, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0056] The processing unit 501 executes the various methods and processes described above, such as process 200 or 300. For example, in some embodiments, process 200 or 300 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed onto device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by CPU 501, one or more steps of process 300 described above may be performed. Alternatively, in other embodiments, CPU 501 may be configured to execute process 200 or 300 by any other suitable means (e.g., by means of firmware).

[0057] The functions described above herein may be performed at least in part by one or more hardware logic components. By way of example and not limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0058] The program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, a special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0059] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0060] Moreover, although the operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the foregoing discussion, these should not be construed as limitations on the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented separately or in any suitable subcombination in multiple implementations.

[0061] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A method for supporting communication between multiple chips, comprising: Determining, by a host, identity information of the multiple chips managed by the host, wherein the multiple chips are connected through respective inter-chip communication interfaces for inter-chip communication, and each chip of the multiple chips includes an inter-chip communication interface for inter-chip communication with other chips managed by the host and a management interface for communicating with the host, receiving configuration information from the host and sending connection information of each chip; Issuing, by the host, a sensing instruction to enable one or more of the multiple chips to obtain identity information of other chips connected to the inter-chip communication interfaces of the one or more chips based on the sensing instruction, wherein enabling one or more of the multiple chips to obtain identity information of other chips connected to the inter-chip communication interfaces of the one or more chips includes: sending, by the host, an instruction to all chips it manages, so that all chips perform an operation of obtaining identity information of other chips connected to them; And Obtaining, by the host via the management interfaces of the one or more chips for communicating with the host, the identity information of the other chips to determine the connection relationship between the multiple chips, wherein the host reads the connection information obtained by each chip through the management interface of each chip.

2. The method according to claim 1, wherein enabling the one or more of the multiple chips to obtain the identity information of the other chips includes: Obtaining status information of the inter-chip communication interfaces of the one or more chips; In response to the status information being active, sending, by the inter-chip communication interfaces of the one or more chips, test data to other chips connected to the inter-chip communication interfaces among the multiple chips; And Receiving response data of the test data, the response data including the identity information of the other chips.

3. The method according to claim 2, wherein sending the test data to the other chips includes: Configuring a predetermined address range for the inter-chip communication interfaces of the one or more chips; And Sending the test data to addresses within the predetermined address range of the other chips.

4. The method according to claim 1, further comprising: Storing the determined connection relationship between the multiple chips in a connection matrix, the connection matrix further including at least one of the following: Status information of the respective inter-chip communication interfaces of the multiple chips; and Bandwidth information.

5. The method according to claim 1, further comprising: Detecting, by the inter-chip communication interfaces of the one or more chips, a connection fault; In response to the detected connection fault being repairable, repairing the connection fault; And Reporting the result of the repair.

6. The method according to claim 1, further comprising: Detecting, by the inter-chip communication interfaces of the one or more chips, a connection fault; In response to the detected connection fault being irreparable, switching services transmitted via the inter-chip communication interfaces of the one or more chips to an additional inter-chip communication interface; And Reporting the connection fault.

7. The method according to claim 1, further comprising: Enumerate the connection relationships of the multiple chips according to the determined number of the multiple chips; and Configure the multiple chips according to the user-specified connection relationships among the enumerated connection relationships.

8. The method according to claim 1, wherein the host is a central processing unit (CPU), and the multiple chips are system-on-chip (SoC).

9. An apparatus for supporting communication between multiple chips, comprising: An identity information determination module, configured to determine the identity information of the multiple chips managed by a host, the multiple chips being connected through respective inter-chip communication interfaces for inter-chip communication, wherein each chip of the multiple chips includes an inter-chip communication interface for inter-chip communication with other chips managed by the host, and a management interface for communicating with the host, receiving configuration information from the host and sending connection information of each chip; A chip instruction module, configured to issue sensing instructions, so that one or more of the multiple chips obtain the identity information of other chips connected to the inter-chip communication interfaces of the one or more chips based on the sensing instructions, wherein enabling one or more of the multiple chips to obtain the identity information of other chips connected to the inter-chip communication interfaces of the one or more chips includes: the host sending instructions to all chips it manages, so that all chips perform operations to obtain the identity information of other chips connected to them; and A connection relationship determination module, configured to obtain the identity information of the other chips via the management interfaces of the one or more chips for communicating with the host, so as to determine the connection relationships among the multiple chips, wherein the host reads the connection information obtained by each chip through the management interface of each chip.

10. The apparatus according to claim 9, wherein the chip instruction module further comprises: A status information reading module, configured to obtain the status information of the inter-chip communication interfaces of the one or more chips; A test data sending module, configured to, in response to the status information being active, send test data from the inter-chip communication interfaces of the one or more chips to other chips among the multiple chips connected to the inter-chip communication interfaces; and A response data receiving module, configured to receive response data of the test data, the response data including the identity information of the other chips.

11. The apparatus according to claim 10, wherein the test data sending module further comprises: An address range configuration module, configured to configure a predetermined address range for the inter-chip communication interfaces of the one or more chips; and A sending sub-module, configured to send the test data to addresses within the predetermined address range of the other chips.

12. The apparatus according to claim 9, further comprising: A connection relationship storage module, configured to store the determined connection relationships among the multiple chips into a connection matrix, the connection matrix further including at least one of the following: The status information of the respective inter-chip communication interfaces of the multiple chips; and Bandwidth information.

13. The apparatus according to claim 9, further comprising: A first fault detection module, configured to detect a connection fault by an inter-chip communication interface of the one or more chips; A repair module, configured to repair the connection fault in response to the detected connection fault being repairable; And A repair result reporting module, configured to report the result of the repair.

14. The apparatus according to claim 9, further comprising: A second fault detection module, configured to detect a connection fault by an inter-chip communication interface of the one or more chips; A service switching module, configured to switch a service transmitted via the inter-chip communication interface of the one or more chips to an additional inter-chip communication interface in response to the detected connection fault being irreparable; And A connection fault reporting module, configured to report the connection fault.

15. The apparatus according to claim 9, further comprising: A connection relationship enumeration module, configured to enumerate connection relationships of the multiple chips according to the determined number of the multiple chips; And A chip configuration module, configured to configure the multiple chips according to a user-specified connection relationship among the enumerated connection relationships.

16. The apparatus according to claim 9, wherein the host is a central processing unit CPU, and the multiple chips are system-on-chip SoCs.

17. An electronic device, the electronic device comprising: One or more processors; And A storage device, configured to store one or more programs, which when executed by the one or more processors cause the one or more processors to implement the method according to any one of claims 1-8.

18. A computer-readable storage medium, having stored thereon a computer program, which when executed by a processor implements the method according to any one of claims 1-8.

Images